Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/e1000phy.c
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1 /*- 2 * Principal Author: Parag Patel 3 * Copyright (c) 2001 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Additional Copyright (c) 2001 by Traakan Software under same licence. 29 * Secondary Author: Matthew Jacob 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. 37 */ 38 39 /* 40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and 41 * 1000baseSX PHY. 42 * Nathan Binkert <nate@openbsd.org> 43 * Jung-uk Kim <jkim@niksun.com> 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/bus.h> 52 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 #include "miidevs.h" 60 61 #include <dev/mii/e1000phyreg.h> 62 63 #include "miibus_if.h" 64 65 static int e1000phy_probe(device_t); 66 static int e1000phy_attach(device_t); 67 68 static device_method_t e1000phy_methods[] = { 69 /* device interface */ 70 DEVMETHOD(device_probe, e1000phy_probe), 71 DEVMETHOD(device_attach, e1000phy_attach), 72 DEVMETHOD(device_detach, mii_phy_detach), 73 DEVMETHOD(device_shutdown, bus_generic_shutdown), 74 DEVMETHOD_END 75 }; 76 77 static devclass_t e1000phy_devclass; 78 static driver_t e1000phy_driver = { 79 "e1000phy", 80 e1000phy_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0); 85 86 static int e1000phy_service(struct mii_softc *, struct mii_data *, int); 87 static void e1000phy_status(struct mii_softc *); 88 static void e1000phy_reset(struct mii_softc *); 89 static int e1000phy_mii_phy_auto(struct mii_softc *, int); 90 91 static const struct mii_phydesc e1000phys[] = { 92 MII_PHY_DESC(MARVELL, E1000), 93 MII_PHY_DESC(MARVELL, E1011), 94 MII_PHY_DESC(MARVELL, E1000_3), 95 MII_PHY_DESC(MARVELL, E1000_5), 96 MII_PHY_DESC(MARVELL, E1111), 97 MII_PHY_DESC(xxMARVELL, E1000), 98 MII_PHY_DESC(xxMARVELL, E1011), 99 MII_PHY_DESC(xxMARVELL, E1000_3), 100 MII_PHY_DESC(xxMARVELL, E1000S), 101 MII_PHY_DESC(xxMARVELL, E1000_5), 102 MII_PHY_DESC(xxMARVELL, E1101), 103 MII_PHY_DESC(xxMARVELL, E3082), 104 MII_PHY_DESC(xxMARVELL, E1112), 105 MII_PHY_DESC(xxMARVELL, E1149), 106 MII_PHY_DESC(xxMARVELL, E1111), 107 MII_PHY_DESC(xxMARVELL, E1116), 108 MII_PHY_DESC(xxMARVELL, E1116R), 109 MII_PHY_DESC(xxMARVELL, E1116R_29), 110 MII_PHY_DESC(xxMARVELL, E1118), 111 MII_PHY_DESC(xxMARVELL, E1145), 112 MII_PHY_DESC(xxMARVELL, E1149R), 113 MII_PHY_DESC(xxMARVELL, E3016), 114 MII_PHY_DESC(xxMARVELL, PHYG65G), 115 MII_PHY_END 116 }; 117 118 static const struct mii_phy_funcs e1000phy_funcs = { 119 e1000phy_service, 120 e1000phy_status, 121 e1000phy_reset 122 }; 123 124 static int 125 e1000phy_probe(device_t dev) 126 { 127 128 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT)); 129 } 130 131 static int 132 e1000phy_attach(device_t dev) 133 { 134 struct mii_softc *sc; 135 struct ifnet *ifp; 136 137 sc = device_get_softc(dev); 138 139 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0); 140 141 ifp = sc->mii_pdata->mii_ifp; 142 if (strcmp(ifp->if_dname, "msk") == 0 && 143 (sc->mii_flags & MIIF_MACPRIV0) != 0) 144 sc->mii_flags |= MIIF_PHYPRIV0; 145 146 switch (sc->mii_mpd_model) { 147 case MII_MODEL_xxMARVELL_E1011: 148 case MII_MODEL_xxMARVELL_E1112: 149 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) 150 sc->mii_flags |= MIIF_HAVEFIBER; 151 break; 152 case MII_MODEL_xxMARVELL_E1149: 153 case MII_MODEL_xxMARVELL_E1149R: 154 /* 155 * Some 88E1149 PHY's page select is initialized to 156 * point to other bank instead of copper/fiber bank 157 * which in turn resulted in wrong registers were 158 * accessed during PHY operation. It is believed that 159 * page 0 should be used for copper PHY so reinitialize 160 * E1000_EADR to select default copper PHY. If parent 161 * device know the type of PHY(either copper or fiber), 162 * that information should be used to select default 163 * type of PHY. 164 */ 165 PHY_WRITE(sc, E1000_EADR, 0); 166 break; 167 } 168 169 PHY_RESET(sc); 170 171 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 172 if (sc->mii_capabilities & BMSR_EXTSTAT) { 173 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 174 if ((sc->mii_extcapabilities & 175 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 176 sc->mii_flags |= MIIF_HAVE_GTCR; 177 } 178 device_printf(dev, " "); 179 mii_phy_add_media(sc); 180 printf("\n"); 181 182 MIIBUS_MEDIAINIT(sc->mii_dev); 183 return (0); 184 } 185 186 static void 187 e1000phy_reset(struct mii_softc *sc) 188 { 189 uint16_t reg, page; 190 191 reg = PHY_READ(sc, E1000_SCR); 192 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) { 193 reg &= ~E1000_SCR_AUTO_X_MODE; 194 PHY_WRITE(sc, E1000_SCR, reg); 195 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) { 196 /* Select 1000BASE-X only mode. */ 197 page = PHY_READ(sc, E1000_EADR); 198 PHY_WRITE(sc, E1000_EADR, 2); 199 reg = PHY_READ(sc, E1000_SCR); 200 reg &= ~E1000_SCR_MODE_MASK; 201 reg |= E1000_SCR_MODE_1000BX; 202 PHY_WRITE(sc, E1000_SCR, reg); 203 if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) { 204 /* Set SIGDET polarity low for SFP module. */ 205 PHY_WRITE(sc, E1000_EADR, 1); 206 reg = PHY_READ(sc, E1000_SCR); 207 reg |= E1000_SCR_FIB_SIGDET_POLARITY; 208 PHY_WRITE(sc, E1000_SCR, reg); 209 } 210 PHY_WRITE(sc, E1000_EADR, page); 211 } 212 } else { 213 switch (sc->mii_mpd_model) { 214 case MII_MODEL_xxMARVELL_E1111: 215 case MII_MODEL_xxMARVELL_E1112: 216 case MII_MODEL_xxMARVELL_E1116: 217 case MII_MODEL_xxMARVELL_E1116R_29: 218 case MII_MODEL_xxMARVELL_E1118: 219 case MII_MODEL_xxMARVELL_E1149: 220 case MII_MODEL_xxMARVELL_E1149R: 221 case MII_MODEL_xxMARVELL_PHYG65G: 222 /* Disable energy detect mode. */ 223 reg &= ~E1000_SCR_EN_DETECT_MASK; 224 reg |= E1000_SCR_AUTO_X_MODE; 225 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 || 226 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29) 227 reg &= ~E1000_SCR_POWER_DOWN; 228 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 229 break; 230 case MII_MODEL_xxMARVELL_E3082: 231 reg |= (E1000_SCR_AUTO_X_MODE >> 1); 232 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 233 break; 234 case MII_MODEL_xxMARVELL_E3016: 235 reg |= E1000_SCR_AUTO_MDIX; 236 reg &= ~(E1000_SCR_EN_DETECT | 237 E1000_SCR_SCRAMBLER_DISABLE); 238 reg |= E1000_SCR_LPNP; 239 /* XXX Enable class A driver for Yukon FE+ A0. */ 240 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); 241 break; 242 default: 243 reg &= ~E1000_SCR_AUTO_X_MODE; 244 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 245 break; 246 } 247 if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) { 248 /* Auto correction for reversed cable polarity. */ 249 reg &= ~E1000_SCR_POLARITY_REVERSAL; 250 } 251 PHY_WRITE(sc, E1000_SCR, reg); 252 253 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 || 254 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29 || 255 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 || 256 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) { 257 PHY_WRITE(sc, E1000_EADR, 2); 258 reg = PHY_READ(sc, E1000_SCR); 259 reg |= E1000_SCR_RGMII_POWER_UP; 260 PHY_WRITE(sc, E1000_SCR, reg); 261 PHY_WRITE(sc, E1000_EADR, 0); 262 } 263 } 264 265 switch (sc->mii_mpd_model) { 266 case MII_MODEL_xxMARVELL_E3082: 267 case MII_MODEL_xxMARVELL_E1112: 268 case MII_MODEL_xxMARVELL_E1118: 269 break; 270 case MII_MODEL_xxMARVELL_E1116: 271 case MII_MODEL_xxMARVELL_E1116R_29: 272 page = PHY_READ(sc, E1000_EADR); 273 /* Select page 3, LED control register. */ 274 PHY_WRITE(sc, E1000_EADR, 3); 275 PHY_WRITE(sc, E1000_SCR, 276 E1000_SCR_LED_LOS(1) | /* Link/Act */ 277 E1000_SCR_LED_INIT(8) | /* 10Mbps */ 278 E1000_SCR_LED_STAT1(7) | /* 100Mbps */ 279 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */ 280 /* Set blink rate. */ 281 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) | 282 E1000_BLINK_RATE(E1000_BLINK_84MS)); 283 PHY_WRITE(sc, E1000_EADR, page); 284 break; 285 case MII_MODEL_xxMARVELL_E3016: 286 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ 287 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); 288 /* Integrated register calibration workaround. */ 289 PHY_WRITE(sc, 0x1D, 17); 290 PHY_WRITE(sc, 0x1E, 0x3F60); 291 break; 292 default: 293 /* Force TX_CLK to 25MHz clock. */ 294 reg = PHY_READ(sc, E1000_ESCR); 295 reg |= E1000_ESCR_TX_CLK_25; 296 PHY_WRITE(sc, E1000_ESCR, reg); 297 break; 298 } 299 300 /* Reset the PHY so all changes take effect. */ 301 reg = PHY_READ(sc, E1000_CR); 302 reg |= E1000_CR_RESET; 303 PHY_WRITE(sc, E1000_CR, reg); 304 } 305 306 static int 307 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 308 { 309 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 310 uint16_t speed, gig; 311 int reg; 312 313 switch (cmd) { 314 case MII_POLLSTAT: 315 break; 316 317 case MII_MEDIACHG: 318 /* 319 * If the interface is not up, don't do anything. 320 */ 321 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 322 break; 323 324 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 325 e1000phy_mii_phy_auto(sc, ife->ifm_media); 326 break; 327 } 328 329 speed = 0; 330 switch (IFM_SUBTYPE(ife->ifm_media)) { 331 case IFM_1000_T: 332 if ((sc->mii_flags & MIIF_HAVE_GTCR) == 0) 333 return (EINVAL); 334 speed = E1000_CR_SPEED_1000; 335 break; 336 case IFM_1000_SX: 337 if ((sc->mii_extcapabilities & 338 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) 339 return (EINVAL); 340 speed = E1000_CR_SPEED_1000; 341 break; 342 case IFM_100_TX: 343 speed = E1000_CR_SPEED_100; 344 break; 345 case IFM_10_T: 346 speed = E1000_CR_SPEED_10; 347 break; 348 case IFM_NONE: 349 reg = PHY_READ(sc, E1000_CR); 350 PHY_WRITE(sc, E1000_CR, 351 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 352 goto done; 353 default: 354 return (EINVAL); 355 } 356 357 if ((ife->ifm_media & IFM_FDX) != 0) { 358 speed |= E1000_CR_FULL_DUPLEX; 359 gig = E1000_1GCR_1000T_FD; 360 } else 361 gig = E1000_1GCR_1000T; 362 363 reg = PHY_READ(sc, E1000_CR); 364 reg &= ~E1000_CR_AUTO_NEG_ENABLE; 365 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET); 366 367 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 368 gig |= E1000_1GCR_MS_ENABLE; 369 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 370 gig |= E1000_1GCR_MS_VALUE; 371 } else if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) 372 gig = 0; 373 PHY_WRITE(sc, E1000_1GCR, gig); 374 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); 375 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET); 376 done: 377 break; 378 case MII_TICK: 379 /* 380 * Is the interface even up? 381 */ 382 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 383 return (0); 384 385 /* 386 * Only used for autonegotiation. 387 */ 388 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 389 sc->mii_ticks = 0; 390 break; 391 } 392 393 /* 394 * check for link. 395 * Read the status register twice; BMSR_LINK is latch-low. 396 */ 397 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 398 if (reg & BMSR_LINK) { 399 sc->mii_ticks = 0; 400 break; 401 } 402 403 /* Announce link loss right after it happens. */ 404 if (sc->mii_ticks++ == 0) 405 break; 406 if (sc->mii_ticks <= sc->mii_anegticks) 407 break; 408 409 sc->mii_ticks = 0; 410 PHY_RESET(sc); 411 e1000phy_mii_phy_auto(sc, ife->ifm_media); 412 break; 413 } 414 415 /* Update the media status. */ 416 PHY_STATUS(sc); 417 418 /* Callback if something changed. */ 419 mii_phy_update(sc, cmd); 420 return (0); 421 } 422 423 static void 424 e1000phy_status(struct mii_softc *sc) 425 { 426 struct mii_data *mii = sc->mii_pdata; 427 int bmcr, bmsr, ssr; 428 429 mii->mii_media_status = IFM_AVALID; 430 mii->mii_media_active = IFM_ETHER; 431 432 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 433 bmcr = PHY_READ(sc, E1000_CR); 434 ssr = PHY_READ(sc, E1000_SSR); 435 436 if (bmsr & E1000_SR_LINK_STATUS) 437 mii->mii_media_status |= IFM_ACTIVE; 438 439 if (bmcr & E1000_CR_LOOPBACK) 440 mii->mii_media_active |= IFM_LOOP; 441 442 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && 443 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { 444 /* Erg, still trying, I guess... */ 445 mii->mii_media_active |= IFM_NONE; 446 return; 447 } 448 449 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 450 switch (ssr & E1000_SSR_SPEED) { 451 case E1000_SSR_1000MBS: 452 mii->mii_media_active |= IFM_1000_T; 453 break; 454 case E1000_SSR_100MBS: 455 mii->mii_media_active |= IFM_100_TX; 456 break; 457 case E1000_SSR_10MBS: 458 mii->mii_media_active |= IFM_10_T; 459 break; 460 default: 461 mii->mii_media_active |= IFM_NONE; 462 return; 463 } 464 } else { 465 /* 466 * Some fiber PHY(88E1112) does not seem to set resolved 467 * speed so always assume we've got IFM_1000_SX. 468 */ 469 mii->mii_media_active |= IFM_1000_SX; 470 } 471 472 if (ssr & E1000_SSR_DUPLEX) { 473 mii->mii_media_active |= IFM_FDX; 474 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) 475 mii->mii_media_active |= mii_phy_flowstatus(sc); 476 } else 477 mii->mii_media_active |= IFM_HDX; 478 479 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 480 if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) & 481 E1000_1GSR_MS_CONFIG_RES) != 0) 482 mii->mii_media_active |= IFM_ETH_MASTER; 483 } 484 } 485 486 static int 487 e1000phy_mii_phy_auto(struct mii_softc *sc, int media) 488 { 489 uint16_t reg; 490 491 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 492 reg = PHY_READ(sc, E1000_AR); 493 reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR); 494 reg |= E1000_AR_10T | E1000_AR_10T_FD | 495 E1000_AR_100TX | E1000_AR_100TX_FD; 496 if ((media & IFM_FLOW) != 0 || 497 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 498 reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR; 499 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); 500 } else 501 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X); 502 if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) { 503 reg = 0; 504 if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0) 505 reg |= E1000_1GCR_1000T_FD; 506 if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0) 507 reg |= E1000_1GCR_1000T; 508 PHY_WRITE(sc, E1000_1GCR, reg); 509 } 510 PHY_WRITE(sc, E1000_CR, 511 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); 512 513 return (EJUSTRETURN); 514 }
Cache object: 04c47a8b2e680c18474286151e21d625
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