Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/e1000phy.c
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1 /*- 2 * Principal Author: Parag Patel 3 * Copyright (c) 2001 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Additional Copyright (c) 2001 by Traakan Software under same licence. 29 * Secondary Author: Matthew Jacob 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. 37 */ 38 39 /* 40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and 41 * 1000baseSX PHY. 42 * Nathan Binkert <nate@openbsd.org> 43 * Jung-uk Kim <jkim@niksun.com> 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/bus.h> 52 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 #include "miidevs.h" 60 61 #include <dev/mii/e1000phyreg.h> 62 63 #include "miibus_if.h" 64 65 static int e1000phy_probe(device_t); 66 static int e1000phy_attach(device_t); 67 68 struct e1000phy_softc { 69 struct mii_softc mii_sc; 70 int mii_model; 71 }; 72 73 static device_method_t e1000phy_methods[] = { 74 /* device interface */ 75 DEVMETHOD(device_probe, e1000phy_probe), 76 DEVMETHOD(device_attach, e1000phy_attach), 77 DEVMETHOD(device_detach, mii_phy_detach), 78 DEVMETHOD(device_shutdown, bus_generic_shutdown), 79 DEVMETHOD_END 80 }; 81 82 static devclass_t e1000phy_devclass; 83 static driver_t e1000phy_driver = { 84 "e1000phy", 85 e1000phy_methods, 86 sizeof(struct e1000phy_softc) 87 }; 88 89 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0); 90 91 static int e1000phy_service(struct mii_softc *, struct mii_data *, int); 92 static void e1000phy_status(struct mii_softc *); 93 static void e1000phy_reset(struct mii_softc *); 94 static int e1000phy_mii_phy_auto(struct mii_softc *, int); 95 96 static const struct mii_phydesc e1000phys[] = { 97 MII_PHY_DESC(MARVELL, E1000), 98 MII_PHY_DESC(MARVELL, E1011), 99 MII_PHY_DESC(MARVELL, E1000_3), 100 MII_PHY_DESC(MARVELL, E1000S), 101 MII_PHY_DESC(MARVELL, E1000_5), 102 MII_PHY_DESC(MARVELL, E1101), 103 MII_PHY_DESC(MARVELL, E3082), 104 MII_PHY_DESC(MARVELL, E1112), 105 MII_PHY_DESC(MARVELL, E1149), 106 MII_PHY_DESC(MARVELL, E1111), 107 MII_PHY_DESC(MARVELL, E1116), 108 MII_PHY_DESC(MARVELL, E1116R), 109 MII_PHY_DESC(MARVELL, E1118), 110 MII_PHY_DESC(MARVELL, E1149R), 111 MII_PHY_DESC(MARVELL, E3016), 112 MII_PHY_DESC(MARVELL, PHYG65G), 113 MII_PHY_DESC(xxMARVELL, E1000), 114 MII_PHY_DESC(xxMARVELL, E1011), 115 MII_PHY_DESC(xxMARVELL, E1000_3), 116 MII_PHY_DESC(xxMARVELL, E1000_5), 117 MII_PHY_DESC(xxMARVELL, E1111), 118 MII_PHY_END 119 }; 120 121 static int 122 e1000phy_probe(device_t dev) 123 { 124 125 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT)); 126 } 127 128 static int 129 e1000phy_attach(device_t dev) 130 { 131 struct e1000phy_softc *esc; 132 struct mii_softc *sc; 133 struct mii_attach_args *ma; 134 struct mii_data *mii; 135 struct ifnet *ifp; 136 137 esc = device_get_softc(dev); 138 sc = &esc->mii_sc; 139 ma = device_get_ivars(dev); 140 sc->mii_dev = device_get_parent(dev); 141 mii = ma->mii_data; 142 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list); 143 144 sc->mii_flags = miibus_get_flags(dev); 145 sc->mii_inst = mii->mii_instance++; 146 sc->mii_phy = ma->mii_phyno; 147 sc->mii_service = e1000phy_service; 148 sc->mii_pdata = mii; 149 150 sc->mii_flags |= MIIF_NOMANPAUSE; 151 152 esc->mii_model = MII_MODEL(ma->mii_id2); 153 ifp = sc->mii_pdata->mii_ifp; 154 if (strcmp(ifp->if_dname, "msk") == 0 && 155 (sc->mii_flags & MIIF_MACPRIV0) != 0) 156 sc->mii_flags |= MIIF_PHYPRIV0; 157 158 switch (esc->mii_model) { 159 case MII_MODEL_MARVELL_E1011: 160 case MII_MODEL_MARVELL_E1112: 161 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) 162 sc->mii_flags |= MIIF_HAVEFIBER; 163 break; 164 case MII_MODEL_MARVELL_E1149: 165 case MII_MODEL_MARVELL_E1149R: 166 /* 167 * Some 88E1149 PHY's page select is initialized to 168 * point to other bank instead of copper/fiber bank 169 * which in turn resulted in wrong registers were 170 * accessed during PHY operation. It is believed that 171 * page 0 should be used for copper PHY so reinitialize 172 * E1000_EADR to select default copper PHY. If parent 173 * device know the type of PHY(either copper or fiber), 174 * that information should be used to select default 175 * type of PHY. 176 */ 177 PHY_WRITE(sc, E1000_EADR, 0); 178 break; 179 } 180 181 e1000phy_reset(sc); 182 183 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask; 184 if (sc->mii_capabilities & BMSR_EXTSTAT) 185 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 186 device_printf(dev, " "); 187 mii_phy_add_media(sc); 188 printf("\n"); 189 190 MIIBUS_MEDIAINIT(sc->mii_dev); 191 return (0); 192 } 193 194 static void 195 e1000phy_reset(struct mii_softc *sc) 196 { 197 struct e1000phy_softc *esc; 198 uint16_t reg, page; 199 200 esc = (struct e1000phy_softc *)sc; 201 reg = PHY_READ(sc, E1000_SCR); 202 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) { 203 reg &= ~E1000_SCR_AUTO_X_MODE; 204 PHY_WRITE(sc, E1000_SCR, reg); 205 if (esc->mii_model == MII_MODEL_MARVELL_E1112) { 206 /* Select 1000BASE-X only mode. */ 207 page = PHY_READ(sc, E1000_EADR); 208 PHY_WRITE(sc, E1000_EADR, 2); 209 reg = PHY_READ(sc, E1000_SCR); 210 reg &= ~E1000_SCR_MODE_MASK; 211 reg |= E1000_SCR_MODE_1000BX; 212 PHY_WRITE(sc, E1000_SCR, reg); 213 if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) { 214 /* Set SIGDET polarity low for SFP module. */ 215 PHY_WRITE(sc, E1000_EADR, 1); 216 reg = PHY_READ(sc, E1000_SCR); 217 reg |= E1000_SCR_FIB_SIGDET_POLARITY; 218 PHY_WRITE(sc, E1000_SCR, reg); 219 } 220 PHY_WRITE(sc, E1000_EADR, page); 221 } 222 } else { 223 switch (esc->mii_model) { 224 case MII_MODEL_MARVELL_E1111: 225 case MII_MODEL_MARVELL_E1112: 226 case MII_MODEL_MARVELL_E1116: 227 case MII_MODEL_MARVELL_E1118: 228 case MII_MODEL_MARVELL_E1149: 229 case MII_MODEL_MARVELL_E1149R: 230 case MII_MODEL_MARVELL_PHYG65G: 231 /* Disable energy detect mode. */ 232 reg &= ~E1000_SCR_EN_DETECT_MASK; 233 reg |= E1000_SCR_AUTO_X_MODE; 234 if (esc->mii_model == MII_MODEL_MARVELL_E1116) 235 reg &= ~E1000_SCR_POWER_DOWN; 236 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 237 break; 238 case MII_MODEL_MARVELL_E3082: 239 reg |= (E1000_SCR_AUTO_X_MODE >> 1); 240 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 241 break; 242 case MII_MODEL_MARVELL_E3016: 243 reg |= E1000_SCR_AUTO_MDIX; 244 reg &= ~(E1000_SCR_EN_DETECT | 245 E1000_SCR_SCRAMBLER_DISABLE); 246 reg |= E1000_SCR_LPNP; 247 /* XXX Enable class A driver for Yukon FE+ A0. */ 248 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); 249 break; 250 default: 251 reg &= ~E1000_SCR_AUTO_X_MODE; 252 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 253 break; 254 } 255 if (esc->mii_model != MII_MODEL_MARVELL_E3016) { 256 /* Auto correction for reversed cable polarity. */ 257 reg &= ~E1000_SCR_POLARITY_REVERSAL; 258 } 259 PHY_WRITE(sc, E1000_SCR, reg); 260 261 if (esc->mii_model == MII_MODEL_MARVELL_E1116 || 262 esc->mii_model == MII_MODEL_MARVELL_E1149 || 263 esc->mii_model == MII_MODEL_MARVELL_E1149R) { 264 PHY_WRITE(sc, E1000_EADR, 2); 265 reg = PHY_READ(sc, E1000_SCR); 266 reg |= E1000_SCR_RGMII_POWER_UP; 267 PHY_WRITE(sc, E1000_SCR, reg); 268 PHY_WRITE(sc, E1000_EADR, 0); 269 } 270 } 271 272 switch (esc->mii_model) { 273 case MII_MODEL_MARVELL_E3082: 274 case MII_MODEL_MARVELL_E1112: 275 case MII_MODEL_MARVELL_E1118: 276 break; 277 case MII_MODEL_MARVELL_E1116: 278 page = PHY_READ(sc, E1000_EADR); 279 /* Select page 3, LED control register. */ 280 PHY_WRITE(sc, E1000_EADR, 3); 281 PHY_WRITE(sc, E1000_SCR, 282 E1000_SCR_LED_LOS(1) | /* Link/Act */ 283 E1000_SCR_LED_INIT(8) | /* 10Mbps */ 284 E1000_SCR_LED_STAT1(7) | /* 100Mbps */ 285 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */ 286 /* Set blink rate. */ 287 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) | 288 E1000_BLINK_RATE(E1000_BLINK_84MS)); 289 PHY_WRITE(sc, E1000_EADR, page); 290 break; 291 case MII_MODEL_MARVELL_E3016: 292 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ 293 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); 294 /* Integrated register calibration workaround. */ 295 PHY_WRITE(sc, 0x1D, 17); 296 PHY_WRITE(sc, 0x1E, 0x3F60); 297 break; 298 default: 299 /* Force TX_CLK to 25MHz clock. */ 300 reg = PHY_READ(sc, E1000_ESCR); 301 reg |= E1000_ESCR_TX_CLK_25; 302 PHY_WRITE(sc, E1000_ESCR, reg); 303 break; 304 } 305 306 /* Reset the PHY so all changes take effect. */ 307 reg = PHY_READ(sc, E1000_CR); 308 reg |= E1000_CR_RESET; 309 PHY_WRITE(sc, E1000_CR, reg); 310 } 311 312 static int 313 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 314 { 315 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 316 uint16_t speed, gig; 317 int reg; 318 319 switch (cmd) { 320 case MII_POLLSTAT: 321 break; 322 323 case MII_MEDIACHG: 324 /* 325 * If the interface is not up, don't do anything. 326 */ 327 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 328 break; 329 330 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 331 e1000phy_mii_phy_auto(sc, ife->ifm_media); 332 break; 333 } 334 335 speed = 0; 336 switch (IFM_SUBTYPE(ife->ifm_media)) { 337 case IFM_1000_T: 338 if ((sc->mii_extcapabilities & 339 (EXTSR_1000TFDX | EXTSR_1000THDX)) == 0) 340 return (EINVAL); 341 speed = E1000_CR_SPEED_1000; 342 break; 343 case IFM_1000_SX: 344 if ((sc->mii_extcapabilities & 345 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) 346 return (EINVAL); 347 speed = E1000_CR_SPEED_1000; 348 break; 349 case IFM_100_TX: 350 speed = E1000_CR_SPEED_100; 351 break; 352 case IFM_10_T: 353 speed = E1000_CR_SPEED_10; 354 break; 355 case IFM_NONE: 356 reg = PHY_READ(sc, E1000_CR); 357 PHY_WRITE(sc, E1000_CR, 358 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 359 goto done; 360 default: 361 return (EINVAL); 362 } 363 364 if ((ife->ifm_media & IFM_FDX) != 0) { 365 speed |= E1000_CR_FULL_DUPLEX; 366 gig = E1000_1GCR_1000T_FD; 367 } else 368 gig = E1000_1GCR_1000T; 369 370 reg = PHY_READ(sc, E1000_CR); 371 reg &= ~E1000_CR_AUTO_NEG_ENABLE; 372 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET); 373 374 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 375 gig |= E1000_1GCR_MS_ENABLE; 376 if ((ife->ifm_media & IFM_ETH_MASTER) != 0 || 377 (mii->mii_ifp->if_flags & IFF_LINK0) != 0) 378 gig |= E1000_1GCR_MS_VALUE; 379 } else if ((sc->mii_extcapabilities & 380 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 381 gig = 0; 382 PHY_WRITE(sc, E1000_1GCR, gig); 383 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); 384 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET); 385 done: 386 break; 387 case MII_TICK: 388 /* 389 * Is the interface even up? 390 */ 391 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 392 return (0); 393 394 /* 395 * Only used for autonegotiation. 396 */ 397 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 398 sc->mii_ticks = 0; 399 break; 400 } 401 402 /* 403 * check for link. 404 * Read the status register twice; BMSR_LINK is latch-low. 405 */ 406 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 407 if (reg & BMSR_LINK) { 408 sc->mii_ticks = 0; 409 break; 410 } 411 412 /* Announce link loss right after it happens. */ 413 if (sc->mii_ticks++ == 0) 414 break; 415 if (sc->mii_ticks <= sc->mii_anegticks) 416 break; 417 418 sc->mii_ticks = 0; 419 e1000phy_reset(sc); 420 e1000phy_mii_phy_auto(sc, ife->ifm_media); 421 break; 422 } 423 424 /* Update the media status. */ 425 e1000phy_status(sc); 426 427 /* Callback if something changed. */ 428 mii_phy_update(sc, cmd); 429 return (0); 430 } 431 432 static void 433 e1000phy_status(struct mii_softc *sc) 434 { 435 struct mii_data *mii = sc->mii_pdata; 436 int bmcr, bmsr, ssr; 437 438 mii->mii_media_status = IFM_AVALID; 439 mii->mii_media_active = IFM_ETHER; 440 441 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 442 bmcr = PHY_READ(sc, E1000_CR); 443 ssr = PHY_READ(sc, E1000_SSR); 444 445 if (bmsr & E1000_SR_LINK_STATUS) 446 mii->mii_media_status |= IFM_ACTIVE; 447 448 if (bmcr & E1000_CR_LOOPBACK) 449 mii->mii_media_active |= IFM_LOOP; 450 451 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && 452 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { 453 /* Erg, still trying, I guess... */ 454 mii->mii_media_active |= IFM_NONE; 455 return; 456 } 457 458 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 459 switch (ssr & E1000_SSR_SPEED) { 460 case E1000_SSR_1000MBS: 461 mii->mii_media_active |= IFM_1000_T; 462 break; 463 case E1000_SSR_100MBS: 464 mii->mii_media_active |= IFM_100_TX; 465 break; 466 case E1000_SSR_10MBS: 467 mii->mii_media_active |= IFM_10_T; 468 break; 469 default: 470 mii->mii_media_active |= IFM_NONE; 471 return; 472 } 473 } else { 474 /* 475 * Some fiber PHY(88E1112) does not seem to set resolved 476 * speed so always assume we've got IFM_1000_SX. 477 */ 478 mii->mii_media_active |= IFM_1000_SX; 479 } 480 481 if (ssr & E1000_SSR_DUPLEX) { 482 mii->mii_media_active |= IFM_FDX; 483 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) 484 mii->mii_media_active |= mii_phy_flowstatus(sc); 485 } else 486 mii->mii_media_active |= IFM_HDX; 487 488 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 489 if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) & 490 E1000_1GSR_MS_CONFIG_RES) != 0) 491 mii->mii_media_active |= IFM_ETH_MASTER; 492 } 493 } 494 495 static int 496 e1000phy_mii_phy_auto(struct mii_softc *sc, int media) 497 { 498 uint16_t reg; 499 500 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 501 reg = PHY_READ(sc, E1000_AR); 502 reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR); 503 reg |= E1000_AR_10T | E1000_AR_10T_FD | 504 E1000_AR_100TX | E1000_AR_100TX_FD; 505 if ((media & IFM_FLOW) != 0 || 506 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 507 reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR; 508 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); 509 } else 510 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X); 511 if ((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 512 PHY_WRITE(sc, E1000_1GCR, 513 E1000_1GCR_1000T_FD | E1000_1GCR_1000T); 514 PHY_WRITE(sc, E1000_CR, 515 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); 516 517 return (EJUSTRETURN); 518 }
Cache object: 33be54fe6a69b724210c61aec8cb4693
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