Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/e1000phy.c
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1 /*- 2 * Principal Author: Parag Patel 3 * Copyright (c) 2001 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Additional Copyright (c) 2001 by Traakan Software under same licence. 29 * Secondary Author: Matthew Jacob 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY. 37 */ 38 39 /* 40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and 41 * 1000baseSX PHY. 42 * Nathan Binkert <nate@openbsd.org> 43 * Jung-uk Kim <jkim@niksun.com> 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/module.h> 50 #include <sys/socket.h> 51 #include <sys/bus.h> 52 53 54 #include <net/if.h> 55 #include <net/if_media.h> 56 57 #include <dev/mii/mii.h> 58 #include <dev/mii/miivar.h> 59 #include "miidevs.h" 60 61 #include <dev/mii/e1000phyreg.h> 62 63 #include "miibus_if.h" 64 65 static int e1000phy_probe(device_t); 66 static int e1000phy_attach(device_t); 67 68 static device_method_t e1000phy_methods[] = { 69 /* device interface */ 70 DEVMETHOD(device_probe, e1000phy_probe), 71 DEVMETHOD(device_attach, e1000phy_attach), 72 DEVMETHOD(device_detach, mii_phy_detach), 73 DEVMETHOD(device_shutdown, bus_generic_shutdown), 74 DEVMETHOD_END 75 }; 76 77 static devclass_t e1000phy_devclass; 78 static driver_t e1000phy_driver = { 79 "e1000phy", 80 e1000phy_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0); 85 86 static int e1000phy_service(struct mii_softc *, struct mii_data *, int); 87 static void e1000phy_status(struct mii_softc *); 88 static void e1000phy_reset(struct mii_softc *); 89 static int e1000phy_mii_phy_auto(struct mii_softc *, int); 90 91 static const struct mii_phydesc e1000phys[] = { 92 MII_PHY_DESC(MARVELL, E1000), 93 MII_PHY_DESC(MARVELL, E1011), 94 MII_PHY_DESC(MARVELL, E1000_3), 95 MII_PHY_DESC(MARVELL, E1000_5), 96 MII_PHY_DESC(MARVELL, E1111), 97 MII_PHY_DESC(xxMARVELL, E1000), 98 MII_PHY_DESC(xxMARVELL, E1011), 99 MII_PHY_DESC(xxMARVELL, E1000_3), 100 MII_PHY_DESC(xxMARVELL, E1000S), 101 MII_PHY_DESC(xxMARVELL, E1000_5), 102 MII_PHY_DESC(xxMARVELL, E1101), 103 MII_PHY_DESC(xxMARVELL, E3082), 104 MII_PHY_DESC(xxMARVELL, E1112), 105 MII_PHY_DESC(xxMARVELL, E1149), 106 MII_PHY_DESC(xxMARVELL, E1111), 107 MII_PHY_DESC(xxMARVELL, E1116), 108 MII_PHY_DESC(xxMARVELL, E1116R), 109 MII_PHY_DESC(xxMARVELL, E1118), 110 MII_PHY_DESC(xxMARVELL, E1149R), 111 MII_PHY_DESC(xxMARVELL, E3016), 112 MII_PHY_DESC(xxMARVELL, PHYG65G), 113 MII_PHY_END 114 }; 115 116 static const struct mii_phy_funcs e1000phy_funcs = { 117 e1000phy_service, 118 e1000phy_status, 119 e1000phy_reset 120 }; 121 122 static int 123 e1000phy_probe(device_t dev) 124 { 125 126 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT)); 127 } 128 129 static int 130 e1000phy_attach(device_t dev) 131 { 132 struct mii_softc *sc; 133 struct ifnet *ifp; 134 135 sc = device_get_softc(dev); 136 137 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0); 138 139 ifp = sc->mii_pdata->mii_ifp; 140 if (strcmp(ifp->if_dname, "msk") == 0 && 141 (sc->mii_flags & MIIF_MACPRIV0) != 0) 142 sc->mii_flags |= MIIF_PHYPRIV0; 143 144 switch (sc->mii_mpd_model) { 145 case MII_MODEL_xxMARVELL_E1011: 146 case MII_MODEL_xxMARVELL_E1112: 147 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK) 148 sc->mii_flags |= MIIF_HAVEFIBER; 149 break; 150 case MII_MODEL_xxMARVELL_E1149: 151 case MII_MODEL_xxMARVELL_E1149R: 152 /* 153 * Some 88E1149 PHY's page select is initialized to 154 * point to other bank instead of copper/fiber bank 155 * which in turn resulted in wrong registers were 156 * accessed during PHY operation. It is believed that 157 * page 0 should be used for copper PHY so reinitialize 158 * E1000_EADR to select default copper PHY. If parent 159 * device know the type of PHY(either copper or fiber), 160 * that information should be used to select default 161 * type of PHY. 162 */ 163 PHY_WRITE(sc, E1000_EADR, 0); 164 break; 165 } 166 167 PHY_RESET(sc); 168 169 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask; 170 if (sc->mii_capabilities & BMSR_EXTSTAT) { 171 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 172 if ((sc->mii_extcapabilities & 173 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0) 174 sc->mii_flags |= MIIF_HAVE_GTCR; 175 } 176 device_printf(dev, " "); 177 mii_phy_add_media(sc); 178 printf("\n"); 179 180 MIIBUS_MEDIAINIT(sc->mii_dev); 181 return (0); 182 } 183 184 static void 185 e1000phy_reset(struct mii_softc *sc) 186 { 187 uint16_t reg, page; 188 189 reg = PHY_READ(sc, E1000_SCR); 190 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) { 191 reg &= ~E1000_SCR_AUTO_X_MODE; 192 PHY_WRITE(sc, E1000_SCR, reg); 193 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) { 194 /* Select 1000BASE-X only mode. */ 195 page = PHY_READ(sc, E1000_EADR); 196 PHY_WRITE(sc, E1000_EADR, 2); 197 reg = PHY_READ(sc, E1000_SCR); 198 reg &= ~E1000_SCR_MODE_MASK; 199 reg |= E1000_SCR_MODE_1000BX; 200 PHY_WRITE(sc, E1000_SCR, reg); 201 if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) { 202 /* Set SIGDET polarity low for SFP module. */ 203 PHY_WRITE(sc, E1000_EADR, 1); 204 reg = PHY_READ(sc, E1000_SCR); 205 reg |= E1000_SCR_FIB_SIGDET_POLARITY; 206 PHY_WRITE(sc, E1000_SCR, reg); 207 } 208 PHY_WRITE(sc, E1000_EADR, page); 209 } 210 } else { 211 switch (sc->mii_mpd_model) { 212 case MII_MODEL_xxMARVELL_E1111: 213 case MII_MODEL_xxMARVELL_E1112: 214 case MII_MODEL_xxMARVELL_E1116: 215 case MII_MODEL_xxMARVELL_E1118: 216 case MII_MODEL_xxMARVELL_E1149: 217 case MII_MODEL_xxMARVELL_E1149R: 218 case MII_MODEL_xxMARVELL_PHYG65G: 219 /* Disable energy detect mode. */ 220 reg &= ~E1000_SCR_EN_DETECT_MASK; 221 reg |= E1000_SCR_AUTO_X_MODE; 222 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116) 223 reg &= ~E1000_SCR_POWER_DOWN; 224 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 225 break; 226 case MII_MODEL_xxMARVELL_E3082: 227 reg |= (E1000_SCR_AUTO_X_MODE >> 1); 228 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 229 break; 230 case MII_MODEL_xxMARVELL_E3016: 231 reg |= E1000_SCR_AUTO_MDIX; 232 reg &= ~(E1000_SCR_EN_DETECT | 233 E1000_SCR_SCRAMBLER_DISABLE); 234 reg |= E1000_SCR_LPNP; 235 /* XXX Enable class A driver for Yukon FE+ A0. */ 236 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001); 237 break; 238 default: 239 reg &= ~E1000_SCR_AUTO_X_MODE; 240 reg |= E1000_SCR_ASSERT_CRS_ON_TX; 241 break; 242 } 243 if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) { 244 /* Auto correction for reversed cable polarity. */ 245 reg &= ~E1000_SCR_POLARITY_REVERSAL; 246 } 247 PHY_WRITE(sc, E1000_SCR, reg); 248 249 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 || 250 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 || 251 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) { 252 PHY_WRITE(sc, E1000_EADR, 2); 253 reg = PHY_READ(sc, E1000_SCR); 254 reg |= E1000_SCR_RGMII_POWER_UP; 255 PHY_WRITE(sc, E1000_SCR, reg); 256 PHY_WRITE(sc, E1000_EADR, 0); 257 } 258 } 259 260 switch (sc->mii_mpd_model) { 261 case MII_MODEL_xxMARVELL_E3082: 262 case MII_MODEL_xxMARVELL_E1112: 263 case MII_MODEL_xxMARVELL_E1118: 264 break; 265 case MII_MODEL_xxMARVELL_E1116: 266 page = PHY_READ(sc, E1000_EADR); 267 /* Select page 3, LED control register. */ 268 PHY_WRITE(sc, E1000_EADR, 3); 269 PHY_WRITE(sc, E1000_SCR, 270 E1000_SCR_LED_LOS(1) | /* Link/Act */ 271 E1000_SCR_LED_INIT(8) | /* 10Mbps */ 272 E1000_SCR_LED_STAT1(7) | /* 100Mbps */ 273 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */ 274 /* Set blink rate. */ 275 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) | 276 E1000_BLINK_RATE(E1000_BLINK_84MS)); 277 PHY_WRITE(sc, E1000_EADR, page); 278 break; 279 case MII_MODEL_xxMARVELL_E3016: 280 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */ 281 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04); 282 /* Integrated register calibration workaround. */ 283 PHY_WRITE(sc, 0x1D, 17); 284 PHY_WRITE(sc, 0x1E, 0x3F60); 285 break; 286 default: 287 /* Force TX_CLK to 25MHz clock. */ 288 reg = PHY_READ(sc, E1000_ESCR); 289 reg |= E1000_ESCR_TX_CLK_25; 290 PHY_WRITE(sc, E1000_ESCR, reg); 291 break; 292 } 293 294 /* Reset the PHY so all changes take effect. */ 295 reg = PHY_READ(sc, E1000_CR); 296 reg |= E1000_CR_RESET; 297 PHY_WRITE(sc, E1000_CR, reg); 298 } 299 300 static int 301 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 302 { 303 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 304 uint16_t speed, gig; 305 int reg; 306 307 switch (cmd) { 308 case MII_POLLSTAT: 309 break; 310 311 case MII_MEDIACHG: 312 /* 313 * If the interface is not up, don't do anything. 314 */ 315 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 316 break; 317 318 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 319 e1000phy_mii_phy_auto(sc, ife->ifm_media); 320 break; 321 } 322 323 speed = 0; 324 switch (IFM_SUBTYPE(ife->ifm_media)) { 325 case IFM_1000_T: 326 if ((sc->mii_flags & MIIF_HAVE_GTCR) == 0) 327 return (EINVAL); 328 speed = E1000_CR_SPEED_1000; 329 break; 330 case IFM_1000_SX: 331 if ((sc->mii_extcapabilities & 332 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0) 333 return (EINVAL); 334 speed = E1000_CR_SPEED_1000; 335 break; 336 case IFM_100_TX: 337 speed = E1000_CR_SPEED_100; 338 break; 339 case IFM_10_T: 340 speed = E1000_CR_SPEED_10; 341 break; 342 case IFM_NONE: 343 reg = PHY_READ(sc, E1000_CR); 344 PHY_WRITE(sc, E1000_CR, 345 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN); 346 goto done; 347 default: 348 return (EINVAL); 349 } 350 351 if ((ife->ifm_media & IFM_FDX) != 0) { 352 speed |= E1000_CR_FULL_DUPLEX; 353 gig = E1000_1GCR_1000T_FD; 354 } else 355 gig = E1000_1GCR_1000T; 356 357 reg = PHY_READ(sc, E1000_CR); 358 reg &= ~E1000_CR_AUTO_NEG_ENABLE; 359 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET); 360 361 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 362 gig |= E1000_1GCR_MS_ENABLE; 363 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 364 gig |= E1000_1GCR_MS_VALUE; 365 } else if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) 366 gig = 0; 367 PHY_WRITE(sc, E1000_1GCR, gig); 368 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD); 369 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET); 370 done: 371 break; 372 case MII_TICK: 373 /* 374 * Is the interface even up? 375 */ 376 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) 377 return (0); 378 379 /* 380 * Only used for autonegotiation. 381 */ 382 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 383 sc->mii_ticks = 0; 384 break; 385 } 386 387 /* 388 * check for link. 389 * Read the status register twice; BMSR_LINK is latch-low. 390 */ 391 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR); 392 if (reg & BMSR_LINK) { 393 sc->mii_ticks = 0; 394 break; 395 } 396 397 /* Announce link loss right after it happens. */ 398 if (sc->mii_ticks++ == 0) 399 break; 400 if (sc->mii_ticks <= sc->mii_anegticks) 401 break; 402 403 sc->mii_ticks = 0; 404 PHY_RESET(sc); 405 e1000phy_mii_phy_auto(sc, ife->ifm_media); 406 break; 407 } 408 409 /* Update the media status. */ 410 PHY_STATUS(sc); 411 412 /* Callback if something changed. */ 413 mii_phy_update(sc, cmd); 414 return (0); 415 } 416 417 static void 418 e1000phy_status(struct mii_softc *sc) 419 { 420 struct mii_data *mii = sc->mii_pdata; 421 int bmcr, bmsr, ssr; 422 423 mii->mii_media_status = IFM_AVALID; 424 mii->mii_media_active = IFM_ETHER; 425 426 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR); 427 bmcr = PHY_READ(sc, E1000_CR); 428 ssr = PHY_READ(sc, E1000_SSR); 429 430 if (bmsr & E1000_SR_LINK_STATUS) 431 mii->mii_media_status |= IFM_ACTIVE; 432 433 if (bmcr & E1000_CR_LOOPBACK) 434 mii->mii_media_active |= IFM_LOOP; 435 436 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 && 437 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) { 438 /* Erg, still trying, I guess... */ 439 mii->mii_media_active |= IFM_NONE; 440 return; 441 } 442 443 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 444 switch (ssr & E1000_SSR_SPEED) { 445 case E1000_SSR_1000MBS: 446 mii->mii_media_active |= IFM_1000_T; 447 break; 448 case E1000_SSR_100MBS: 449 mii->mii_media_active |= IFM_100_TX; 450 break; 451 case E1000_SSR_10MBS: 452 mii->mii_media_active |= IFM_10_T; 453 break; 454 default: 455 mii->mii_media_active |= IFM_NONE; 456 return; 457 } 458 } else { 459 /* 460 * Some fiber PHY(88E1112) does not seem to set resolved 461 * speed so always assume we've got IFM_1000_SX. 462 */ 463 mii->mii_media_active |= IFM_1000_SX; 464 } 465 466 if (ssr & E1000_SSR_DUPLEX) { 467 mii->mii_media_active |= IFM_FDX; 468 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) 469 mii->mii_media_active |= mii_phy_flowstatus(sc); 470 } else 471 mii->mii_media_active |= IFM_HDX; 472 473 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 474 if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) & 475 E1000_1GSR_MS_CONFIG_RES) != 0) 476 mii->mii_media_active |= IFM_ETH_MASTER; 477 } 478 } 479 480 static int 481 e1000phy_mii_phy_auto(struct mii_softc *sc, int media) 482 { 483 uint16_t reg; 484 485 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) { 486 reg = PHY_READ(sc, E1000_AR); 487 reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR); 488 reg |= E1000_AR_10T | E1000_AR_10T_FD | 489 E1000_AR_100TX | E1000_AR_100TX_FD; 490 if ((media & IFM_FLOW) != 0 || 491 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 492 reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR; 493 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD); 494 } else 495 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X); 496 if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) { 497 reg = 0; 498 if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0) 499 reg |= E1000_1GCR_1000T_FD; 500 if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0) 501 reg |= E1000_1GCR_1000T; 502 PHY_WRITE(sc, E1000_1GCR, reg); 503 } 504 PHY_WRITE(sc, E1000_CR, 505 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG); 506 507 return (EJUSTRETURN); 508 }
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