The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/inphy.c

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    1 /*-
    2  * Copyright (c) 2001 Jonathan Lemon
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. Neither the name of the author nor the names of any co-contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  *      $FreeBSD: releng/5.0/sys/dev/mii/inphy.c 106107 2002-10-29 00:20:47Z semenu $
   30  */
   31 
   32 /*
   33  * driver for Intel 82553 and 82555 PHYs
   34  */
   35 
   36 #include <sys/param.h>
   37 #include <sys/systm.h>
   38 #include <sys/kernel.h>
   39 #include <sys/socket.h>
   40 #include <sys/bus.h>
   41 
   42 #include <net/if.h>
   43 #include <net/if_media.h>
   44 
   45 #include <dev/mii/mii.h>
   46 #include <dev/mii/miivar.h>
   47 #include <dev/mii/miidevs.h>
   48 
   49 #include <dev/mii/inphyreg.h>
   50 
   51 #include "miibus_if.h"
   52 
   53 static int      inphy_probe(device_t dev);
   54 static int      inphy_attach(device_t dev);
   55 
   56 static device_method_t inphy_methods[] = {
   57         /* device interface */
   58         DEVMETHOD(device_probe,         inphy_probe),
   59         DEVMETHOD(device_attach,        inphy_attach),
   60         DEVMETHOD(device_detach,        mii_phy_detach),
   61         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
   62         { 0, 0 }
   63 };
   64 
   65 static devclass_t inphy_devclass;
   66 
   67 static driver_t inphy_driver = {
   68         "inphy",
   69         inphy_methods,
   70         sizeof(struct mii_softc)
   71 };
   72 
   73 DRIVER_MODULE(inphy, miibus, inphy_driver, inphy_devclass, 0, 0);
   74 
   75 static int      inphy_service(struct mii_softc *, struct mii_data *, int);
   76 static void     inphy_status(struct mii_softc *);
   77 
   78 static int
   79 inphy_probe(device_t dev)
   80 {
   81         struct mii_attach_args *ma;
   82         device_t parent;
   83 
   84         ma = device_get_ivars(dev);
   85         parent = device_get_parent(device_get_parent(dev));
   86 
   87         /* Intel 82553 A/B steppings */
   88         if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxINTEL &&
   89             MII_MODEL(ma->mii_id2) == MII_MODEL_xxINTEL_I82553AB) {
   90                 device_set_desc(dev, MII_STR_xxINTEL_I82553AB);
   91                 return (0);
   92         }
   93 
   94         if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_INTEL) {
   95                 switch (MII_MODEL(ma->mii_id2)) {
   96                 case MII_MODEL_INTEL_I82555:
   97                         device_set_desc(dev, MII_STR_INTEL_I82555);
   98                         return (0);
   99                 case MII_MODEL_INTEL_I82553C:
  100                         device_set_desc(dev, MII_STR_INTEL_I82553C);
  101                         return (0);
  102                 case MII_MODEL_INTEL_I82562EM:
  103                         device_set_desc(dev, MII_STR_INTEL_I82562EM);
  104                         return (0);
  105                 case MII_MODEL_INTEL_I82562ET:
  106                         device_set_desc(dev, MII_STR_INTEL_I82562ET);
  107                         return (0);
  108                 }
  109         }
  110 
  111         return (ENXIO);
  112 }
  113 
  114 static int
  115 inphy_attach(device_t dev)
  116 {
  117         struct mii_softc *sc;
  118         struct mii_attach_args *ma;
  119         struct mii_data *mii;
  120 
  121         sc = device_get_softc(dev);
  122         ma = device_get_ivars(dev);
  123         sc->mii_dev = device_get_parent(dev);
  124         mii = device_get_softc(sc->mii_dev);
  125         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
  126 
  127         sc->mii_inst = mii->mii_instance;
  128         sc->mii_phy = ma->mii_phyno;
  129         sc->mii_service = inphy_service;
  130         sc->mii_pdata = mii;
  131         mii->mii_instance++;
  132 
  133 #if 0
  134         sc->mii_flags |= MIIF_NOISOLATE;
  135 #endif
  136 
  137         ifmedia_add(&mii->mii_media,
  138             IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
  139             BMCR_LOOP|BMCR_S100, NULL);
  140 
  141         mii_phy_reset(sc);
  142 
  143         sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
  144         device_printf(dev, " ");
  145         mii_phy_add_media(sc);
  146         printf("\n");
  147 
  148         MIIBUS_MEDIAINIT(sc->mii_dev);
  149 
  150         return (0);
  151 }
  152 
  153 static int
  154 inphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
  155 {
  156         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
  157         int reg;
  158 
  159         switch (cmd) {
  160         case MII_POLLSTAT:
  161                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
  162                         return (0);
  163                 break;
  164 
  165         case MII_MEDIACHG:
  166                 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
  167                         reg = PHY_READ(sc, MII_BMCR);
  168                         PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
  169                         return (0);
  170                 }
  171 
  172                 /*
  173                  * If the interface is not up, don't do anything.
  174                  */
  175                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  176                         break;
  177 
  178                 mii_phy_setmedia(sc);
  179                 break;
  180 
  181         case MII_TICK:
  182                 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
  183                         return (0);
  184                 if (mii_phy_tick(sc) == EJUSTRETURN)
  185                         return (0);
  186                 break;
  187         }
  188 
  189         /* Update the media status. */
  190         inphy_status(sc);
  191 
  192         /* Callback if something changed. */
  193         mii_phy_update(sc, cmd);
  194         return (0);
  195 }
  196 
  197 static void
  198 inphy_status(struct mii_softc *sc)
  199 {
  200         struct mii_data *mii = sc->mii_pdata;
  201         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
  202         int bmsr, bmcr, scr;
  203 
  204         mii->mii_media_status = IFM_AVALID;
  205         mii->mii_media_active = IFM_ETHER;
  206 
  207         bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
  208         if (bmsr & BMSR_LINK)
  209                 mii->mii_media_status |= IFM_ACTIVE;
  210 
  211         bmcr = PHY_READ(sc, MII_BMCR);
  212         if (bmcr & BMCR_ISO) {
  213                 mii->mii_media_active |= IFM_NONE;
  214                 mii->mii_media_status = 0;
  215                 return;
  216         }
  217 
  218         if (bmcr & BMCR_LOOP)
  219                 mii->mii_media_active |= IFM_LOOP;
  220 
  221         if (bmcr & BMCR_AUTOEN) {
  222                 if ((bmsr & BMSR_ACOMP) == 0) {
  223                         mii->mii_media_active |= IFM_NONE;
  224                         return;
  225                 }
  226 
  227                 scr = PHY_READ(sc, MII_INPHY_SCR);
  228                 if (scr & SCR_S100)
  229                         mii->mii_media_active |= IFM_100_TX;
  230                 else
  231                         mii->mii_media_active |= IFM_10_T;
  232                 if (scr & SCR_FDX)
  233                         mii->mii_media_active |= IFM_FDX;
  234         } else
  235                 mii->mii_media_active = ife->ifm_media;
  236 }

Cache object: f5dc482cd1753fe9fad1f0d4f406a9ba


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