The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/inphyreg.h

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    1 /*      $NetBSD: inphyreg.h,v 1.3 2003/11/02 11:10:36 wiz Exp $ */
    2 
    3 /*-
    4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
    9  * NASA Ames Research Center.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   39 
   40 #ifndef _DEV_MII_INPHYREG_H_
   41 #define _DEV_MII_INPHYREG_H_
   42 
   43 /*
   44  * Intel 82555 registers.
   45  */
   46 
   47 #define MII_INPHY_SCR           0x10    /* Status and Control */
   48 #define SCR_FLOWCTL             0x8000  /* PHY Base flow control enabled */
   49 #define SCR_CSDC                0x2000  /* Carrier sense disconnect control */
   50 #define SCR_TFCD                0x1000  /* Transmit flow control disable */
   51 #define SCR_RDSI                0x0800  /* Receive deserializer in-sync */
   52 #define SCR_100TXPD             0x0400  /* 100baseTX is powered down */
   53 #define SCR_10TPD               0x0200  /* 10baseT is powered down */
   54 #define SCR_POLARITY            0x0100  /* reverse 10baseT polarity */
   55 #define SCR_T4                  0x0004  /* autoneg resulted in 100baseT4 */
   56 #define SCR_S100                0x0002  /* autoneg resulted in 100baseTX */
   57 #define SCR_FDX                 0x0001  /* autoneg resulted in full-duplex */
   58 
   59 #define MII_INPHY_SCTRL         0x11    /* Special Control Bit */
   60 #define SCTRL_SCRBYPASS         0x8000  /* scrambler bypass */
   61 #define SCTRL_4B5BNYPASS        0x4000  /* 4bit to 5bit bypass */
   62 #define SCTRL_FTHP              0x2000  /* force transmit H-pattern */
   63 #define SCTRL_F34TP             0x1000  /* force 34 transmit patter */
   64 #define SCTRL_GOODLINK          0x0800  /* 100baseTX link good */
   65 #define SCTRL_TCSD              0x0200  /* transmit carrier sense disable */
   66 #define SCTRL_DDPD              0x0100  /* disable dynamic power-down */
   67 #define SCTRL_ANEGLOOP          0x0080  /* autonegotiation loopback */
   68 #define SCTRL_MDITRISTATE       0x0040  /* MDI Tri-state */
   69 #define SCTRL_FILTERBYPASS      0x0020  /* Filter bypass */
   70 #define SCTRL_AUTOPOLDIS        0x0010  /* auto-polarity disable */
   71 #define SCTRL_SQUELCHDIS        0x0008  /* squlch test disable */
   72 #define SCTRL_EXTSQUELCH        0x0004  /* extended sequelch enable */
   73 #define SCTRL_LINKINTDIS        0x0002  /* link integrity disable */
   74 #define SCTRL_JABBERDIS         0x0001  /* jabber disabled */
   75 
   76 #define MII_INPHY_100TXRDC      0x14    /* 100baseTX Receive Disconnect Cntr */
   77 
   78 #define MII_INPHY_100TXREFC     0x15    /* 100baseTX Receive Error Frame Ctr */
   79 
   80 #define MII_INPHY_RSEC          0x16    /* Receive Symbol Error Counter */
   81 
   82 #define MII_INPHY_100TXRPEOFC   0x17    /* 100baseTX Rcv Premature EOF Ctr */
   83 
   84 #define MII_INPHY_10TREOFC      0x18    /* 10baseT Rcv EOF Ctr */
   85 
   86 #define MII_INPHY_10TTJDC       0x19    /* 10baseT Tx Jabber Detect Ctr */
   87 
   88 #define MII_INPHY_SCTRL2        0x1b    /* 82555 Special Control */
   89 #define SCTRL2_LEDMASK          0x0007  /* mask of LEDs control: see below */
   90 
   91 #define LEDMASK_ACTLINK         0x0000  /* A = Activity, L = Link */
   92 #define LEDMASK_SPDCOLL         0x0001  /* A = Speed, L = Collision */
   93 #define LEDMASK_SPDLINK         0x0002  /* A = Speed, L = Link */
   94 #define LEDMASK_ACTCOLL         0x0003  /* A = Activity, L = Collision */
   95 #define LEDMASK_OFFOFF          0x0004  /* A = off, L = off */
   96 #define LEDMASK_OFFON           0x0005  /* A = off, L = on */
   97 #define LEDMASK_ONOFF           0x0006  /* A = on, L = off */
   98 #define LESMASK_ONON            0x0007  /* A = on, L = on */
   99 
  100 #endif /* _DEV_MII_INPHYREG_H_ */

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