1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2006, Pyun YongHyeon
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 #ifndef _DEV_MII_IP1000PHYREG_H_
33 #define _DEV_MII_IP1000PHYREG_H_
34
35 /*
36 * Registers for the IC Plus IP1000A internal PHY.
37 */
38
39 /* Control register */
40 #define IP1000PHY_MII_BMCR 0x00
41 #define IP1000PHY_BMCR_FDX 0x0100
42 #define IP1000PHY_BMCR_STARTNEG 0x0200
43 #define IP1000PHY_BMCR_ISO 0x0400
44 #define IP1000PHY_BMCR_PDOWN 0x0800
45 #define IP1000PHY_BMCR_AUTOEN 0x1000
46 #define IP1000PHY_BMCR_LOOP 0x4000
47 #define IP1000PHY_BMCR_RESET 0x8000
48
49 #define IP1000PHY_BMCR_10 0x0000
50 #define IP1000PHY_BMCR_100 0x2000
51 #define IP1000PHY_BMCR_1000 0x0040
52
53 /* Status register */
54 #define IP1000PHY_MII_BMSR 0x01
55 #define IP1000PHY_BMSR_EXT 0x0001
56 #define IP1000PHY_BMSR_LINK 0x0004
57 #define IP1000PHY_BMSR_ANEG 0x0008
58 #define IP1000PHY_BMSR_RFAULT 0x0010
59 #define IP1000PHY_BMSR_ANEGCOMP 0x0020
60 #define IP1000PHY_BMSR_EXTSTS 0x0100
61
62 #define IP1000PHY_MII_ID1 0x02
63
64 /* Autonegotiation advertisement register */
65 #define IP1000PHY_MII_ANAR 0x04
66 #define IP1000PHY_ANAR_CSMA 0x0001
67 #define IP1000PHY_ANAR_10T 0x0020
68 #define IP1000PHY_ANAR_10T_FDX 0x0040
69 #define IP1000PHY_ANAR_100TX 0x0080
70 #define IP1000PHY_ANAR_100TX_FDX 0x0100
71 #define IP1000PHY_ANAR_100T4 0x0200
72 #define IP1000PHY_ANAR_PAUSE 0x0400
73 #define IP1000PHY_ANAR_APAUSE 0x0800
74 #define IP1000PHY_ANAR_RFAULT 0x2000
75 #define IP1000PHY_ANAR_NP 0x8000
76
77 /* Autonegotiation link parnet ability register */
78 #define IP1000PHY_MII_ANLPAR 0x05
79 #define IP1000PHY_ANLPAR_10T 0x0020
80 #define IP1000PHY_ANLPAR_10T_FDX 0x0040
81 #define IP1000PHY_ANLPAR_100TX 0x0080
82 #define IP1000PHY_ANLPAR_100TX_FDX 0x0100
83 #define IP1000PHY_ANLPAR_100T4 0x0200
84 #define IP1000PHY_ANLPAR_PAUSE 0x0400
85 #define IP1000PHY_ANLPAR_APAUSE 0x0800
86 #define IP1000PHY_ANLPAR_RFAULT 0x2000
87 #define IP1000PHY_ANLPAR_ACK 0x4000
88 #define IP1000PHY_ANLPAR_NP 0x8000
89
90 /* Autonegotiation expansion register */
91 #define IP1000PHY_MII_ANER 0x06
92 #define IP1000PHY_ANER_LPNWAY 0x0001
93 #define IP1000PHY_ANER_PRCVD 0x0002
94 #define IP1000PHY_ANER_NEXTP 0x0004
95 #define IP1000PHY_ANER_LPNEXTP 0x0008
96 #define IP1000PHY_ANER_PDF 0x0100
97
98 /* Autonegotiation next page transmit register */
99 #define IP1000PHY_MII_NEXTP 0x07
100 #define IP1000PHY_NEXTP_MSGC 0x0001
101 #define IP1000PHY_NEXTP_TOGGLE 0x0800
102 #define IP1000PHY_NEXTP_ACK2 0x1000
103 #define IP1000PHY_NEXTP_MSGP 0x2000
104 #define IP1000PHY_NEXTP_NEXTP 0x8000
105
106 /* Autonegotiation link partner next page register */
107 #define IP1000PHY_MII_NEXTPLP 0x08
108 #define IP1000PHY_NEXTPLP_MSGC 0x0001
109 #define IP1000PHY_NEXTPLP_TOGGLE 0x0800
110 #define IP1000PHY_NEXTPLP_ACK2 0x1000
111 #define IP1000PHY_NEXTPLP_MSGP 0x2000
112 #define IP1000PHY_NEXTPLP_ACK 0x4000
113 #define IP1000PHY_NEXTPLP_NEXTP 0x8000
114
115 /* 1000baseT control register */
116 #define IP1000PHY_MII_1000CR 0x09
117 #define IP1000PHY_1000CR_1000T 0x0100
118 #define IP1000PHY_1000CR_1000T_FDX 0x0200
119 #define IP1000PHY_1000CR_MASTER 0x0400
120 #define IP1000PHY_1000CR_MMASTER 0x0800
121 #define IP1000PHY_1000CR_MANUAL 0x1000
122 #define IP1000PHY_1000CR_TMNORMAL 0x0000
123 #define IP1000PHY_1000CR_TM1 0x2000
124 #define IP1000PHY_1000CR_TM2 0x4000
125 #define IP1000PHY_1000CR_TM3 0x6000
126 #define IP1000PHY_1000CR_TM4 0x8000
127
128 /* 1000baseT status register */
129 #define IP1000PHY_MII_1000SR 0x0A
130 #define IP1000PHY_1000SR_LP 0x0400
131 #define IP1000PHY_1000SR_LP_FDX 0x0800
132 #define IP1000PHY_1000SR_RXSTAT 0x1000
133 #define IP1000PHY_1000SR_LRXSTAT 0x2000
134 #define IP1000PHY_1000SR_MASTER 0x4000
135 #define IP1000PHY_1000SR_MASTERF 0x8000
136
137 /* Extended status register */
138 #define IP1000PHY_MII_EXTSTS 0x0F
139 #define IP1000PHY_EXTSTS_1000T 0x1000
140 #define IP1000PHY_EXTSTS_1000T_FDX 0x2000
141 #define IP1000PHY_EXTSTS_1000X 0x4000
142 #define IP1000PHY_EXTSTS_1000X_FDX 0x8000
143
144 /* PHY specific control & status register. IP1001 only. */
145 #define IP1000PHY_SCSR 0x10
146 #define IP1000PHY_SCSR_RXPHASE_SEL 0x0001
147 #define IP1000PHY_SCSR_TXPHASE_SEL 0x0002
148 #define IP1000PHY_SCSR_REPEATOR_MODE 0x0004
149 #define IP1000PHY_SCSR_RESERVED1_DEF 0x0008
150 #define IP1000PHY_SCSR_RXCLK_DRV_MASK 0x0060
151 #define IP1000PHY_SCSR_RXCLK_DRV_DEF 0x0040
152 #define IP1000PHY_SCSR_RXD_DRV_MASK 0x0180
153 #define IP1000PHY_SCSR_RXD_DRV_DEF 0x0100
154 #define IP1000PHY_SCSR_JABBER_ENB 0x0200
155 #define IP1000PHY_SCSR_HEART_BEAT_ENB 0x0400
156 #define IP1000PHY_SCSR_DOWNSHIFT_ENB 0x0800
157 #define IP1000PHY_SCSR_RESERVED2_DEF 0x1000
158 #define IP1000PHY_SCSR_LED_DRV_4MA 0x0000
159 #define IP1000PHY_SCSR_LED_DRV_8MA 0x2000
160 #define IP1000PHY_SCSR_LED_MODE_MASK 0xC000
161 #define IP1000PHY_SCSR_LED_MODE_DEF 0x0000
162
163 /* PHY link status register. IP1001 only. */
164 #define IP1000PHY_LSR 0x11
165 #define IP1000PHY_LSR_JABBER_DET 0x0200
166 #define IP1000PHY_LSR_APS_SLEEP 0x0400
167 #define IP1000PHY_LSR_MDIX 0x0800
168 #define IP1000PHY_LSR_FULL_DUPLEX 0x1000
169 #define IP1000PHY_LSR_SPEED_10 0x0000
170 #define IP1000PHY_LSR_SPEED_100 0x2000
171 #define IP1000PHY_LSR_SPEED_1000 0x4000
172 #define IP1000PHY_LSR_SPEED_MASK 0x6000
173 #define IP1000PHY_LSR_LINKUP 0x8000
174
175 /* PHY specific control register 2. IP1001 only. */
176 #define IP1000PHY_SCR
177 #define IP1000PHY_SCR_SEW_RATE_MASK 0x0003
178 #define IP1000PHY_SCR_SEW_RATE_DEF 0x0003
179 #define IP1000PHY_SCR_AUTO_XOVER 0x0004
180 #define IP1000PHY_SCR_SPEED_10_100_ENB 0x0040
181 #define IP1000PHY_SCR_FIFO_LATENCY_2 0x0000
182 #define IP1000PHY_SCR_FIFO_LATENCY_3 0x0080
183 #define IP1000PHY_SCR_FIFO_LATENCY_4 0x0100
184 #define IP1000PHY_SCR_FIFO_LATENCY_5 0x0180
185 #define IP1000PHY_SCR_MDIX_ENB 0x0200
186 #define IP1000PHY_SCR_RESERVED_DEF 0x0400
187 #define IP1000PHY_SCR_APS_ON 0x0800
188
189 #endif /* _DEV_MII_IP1000PHYREG_H_ */
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