Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/ip1000phyreg.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
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1 /*- 2 * Copyright (c) 2006, Pyun YongHyeon 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: releng/8.4/sys/dev/mii/ip1000phyreg.h 189567 2009-03-09 08:17:46Z yongari $ 28 */ 29 30 #ifndef _DEV_MII_IP1000PHYREG_H_ 31 #define _DEV_MII_IP1000PHYREG_H_ 32 33 /* 34 * Registers for the IC Plus IP1000A internal PHY. 35 */ 36 37 /* Control register */ 38 #define IP1000PHY_MII_BMCR 0x00 39 #define IP1000PHY_BMCR_FDX 0x0100 40 #define IP1000PHY_BMCR_STARTNEG 0x0200 41 #define IP1000PHY_BMCR_ISO 0x0400 42 #define IP1000PHY_BMCR_PDOWN 0x0800 43 #define IP1000PHY_BMCR_AUTOEN 0x1000 44 #define IP1000PHY_BMCR_LOOP 0x4000 45 #define IP1000PHY_BMCR_RESET 0x8000 46 47 #define IP1000PHY_BMCR_10 0x0000 48 #define IP1000PHY_BMCR_100 0x2000 49 #define IP1000PHY_BMCR_1000 0x0040 50 51 /* Status register */ 52 #define IP1000PHY_MII_BMSR 0x01 53 #define IP1000PHY_BMSR_EXT 0x0001 54 #define IP1000PHY_BMSR_LINK 0x0004 55 #define IP1000PHY_BMSR_ANEG 0x0008 56 #define IP1000PHY_BMSR_RFAULT 0x0010 57 #define IP1000PHY_BMSR_ANEGCOMP 0x0020 58 #define IP1000PHY_BMSR_EXTSTS 0x0100 59 60 #define IP1000PHY_MII_ID1 0x02 61 62 /* Autonegotiation advertisement register */ 63 #define IP1000PHY_MII_ANAR 0x04 64 #define IP1000PHY_ANAR_CSMA 0x0001 65 #define IP1000PHY_ANAR_10T 0x0020 66 #define IP1000PHY_ANAR_10T_FDX 0x0040 67 #define IP1000PHY_ANAR_100TX 0x0080 68 #define IP1000PHY_ANAR_100TX_FDX 0x0100 69 #define IP1000PHY_ANAR_100T4 0x0200 70 #define IP1000PHY_ANAR_PAUSE 0x0400 71 #define IP1000PHY_ANAR_APAUSE 0x0800 72 #define IP1000PHY_ANAR_RFAULT 0x2000 73 #define IP1000PHY_ANAR_NP 0x8000 74 75 /* Autonegotiation link parnet ability register */ 76 #define IP1000PHY_MII_ANLPAR 0x05 77 #define IP1000PHY_ANLPAR_10T 0x0020 78 #define IP1000PHY_ANLPAR_10T_FDX 0x0040 79 #define IP1000PHY_ANLPAR_100TX 0x0080 80 #define IP1000PHY_ANLPAR_100TX_FDX 0x0100 81 #define IP1000PHY_ANLPAR_100T4 0x0200 82 #define IP1000PHY_ANLPAR_PAUSE 0x0400 83 #define IP1000PHY_ANLPAR_APAUSE 0x0800 84 #define IP1000PHY_ANLPAR_RFAULT 0x2000 85 #define IP1000PHY_ANLPAR_ACK 0x4000 86 #define IP1000PHY_ANLPAR_NP 0x8000 87 88 /* Autonegotiation expansion register */ 89 #define IP1000PHY_MII_ANER 0x06 90 #define IP1000PHY_ANER_LPNWAY 0x0001 91 #define IP1000PHY_ANER_PRCVD 0x0002 92 #define IP1000PHY_ANER_NEXTP 0x0004 93 #define IP1000PHY_ANER_LPNEXTP 0x0008 94 #define IP1000PHY_ANER_PDF 0x0100 95 96 /* Autonegotiation next page transmit register */ 97 #define IP1000PHY_MII_NEXTP 0x07 98 #define IP1000PHY_NEXTP_MSGC 0x0001 99 #define IP1000PHY_NEXTP_TOGGLE 0x0800 100 #define IP1000PHY_NEXTP_ACK2 0x1000 101 #define IP1000PHY_NEXTP_MSGP 0x2000 102 #define IP1000PHY_NEXTP_NEXTP 0x8000 103 104 /* Autonegotiation link partner next page register */ 105 #define IP1000PHY_MII_NEXTPLP 0x08 106 #define IP1000PHY_NEXTPLP_MSGC 0x0001 107 #define IP1000PHY_NEXTPLP_TOGGLE 0x0800 108 #define IP1000PHY_NEXTPLP_ACK2 0x1000 109 #define IP1000PHY_NEXTPLP_MSGP 0x2000 110 #define IP1000PHY_NEXTPLP_ACK 0x4000 111 #define IP1000PHY_NEXTPLP_NEXTP 0x8000 112 113 /* 1000baseT control register */ 114 #define IP1000PHY_MII_1000CR 0x09 115 #define IP1000PHY_1000CR_1000T 0x0100 116 #define IP1000PHY_1000CR_1000T_FDX 0x0200 117 #define IP1000PHY_1000CR_MASTER 0x0400 118 #define IP1000PHY_1000CR_MMASTER 0x0800 119 #define IP1000PHY_1000CR_MANUAL 0x1000 120 #define IP1000PHY_1000CR_TMNORMAL 0x0000 121 #define IP1000PHY_1000CR_TM1 0x2000 122 #define IP1000PHY_1000CR_TM2 0x4000 123 #define IP1000PHY_1000CR_TM3 0x6000 124 #define IP1000PHY_1000CR_TM4 0x8000 125 126 /* 1000baseT status register */ 127 #define IP1000PHY_MII_1000SR 0x0A 128 #define IP1000PHY_1000SR_LP 0x0400 129 #define IP1000PHY_1000SR_LP_FDX 0x0800 130 #define IP1000PHY_1000SR_RXSTAT 0x1000 131 #define IP1000PHY_1000SR_LRXSTAT 0x2000 132 #define IP1000PHY_1000SR_MASTER 0x4000 133 #define IP1000PHY_1000SR_MASTERF 0x8000 134 135 /* Extended status register */ 136 #define IP1000PHY_MII_EXTSTS 0x0F 137 #define IP1000PHY_EXTSTS_1000T 0x1000 138 #define IP1000PHY_EXTSTS_1000T_FDX 0x2000 139 #define IP1000PHY_EXTSTS_1000X 0x4000 140 #define IP1000PHY_EXTSTS_1000X_FDX 0x8000 141 142 /* PHY specific control & status register. IP1001 only. */ 143 #define IP1000PHY_SCSR 0x10 144 #define IP1000PHY_SCSR_RXPHASE_SEL 0x0001 145 #define IP1000PHY_SCSR_TXPHASE_SEL 0x0002 146 #define IP1000PHY_SCSR_REPEATOR_MODE 0x0004 147 #define IP1000PHY_SCSR_RESERVED1_DEF 0x0008 148 #define IP1000PHY_SCSR_RXCLK_DRV_MASK 0x0060 149 #define IP1000PHY_SCSR_RXCLK_DRV_DEF 0x0040 150 #define IP1000PHY_SCSR_RXD_DRV_MASK 0x0180 151 #define IP1000PHY_SCSR_RXD_DRV_DEF 0x0100 152 #define IP1000PHY_SCSR_JABBER_ENB 0x0200 153 #define IP1000PHY_SCSR_HEART_BEAT_ENB 0x0400 154 #define IP1000PHY_SCSR_DOWNSHIFT_ENB 0x0800 155 #define IP1000PHY_SCSR_RESERVED2_DEF 0x1000 156 #define IP1000PHY_SCSR_LED_DRV_4MA 0x0000 157 #define IP1000PHY_SCSR_LED_DRV_8MA 0x2000 158 #define IP1000PHY_SCSR_LED_MODE_MASK 0xC000 159 #define IP1000PHY_SCSR_LED_MODE_DEF 0x0000 160 161 /* PHY link status register. IP1001 only. */ 162 #define IP1000PHY_LSR 0x11 163 #define IP1000PHY_LSR_JABBER_DET 0x0200 164 #define IP1000PHY_LSR_APS_SLEEP 0x0400 165 #define IP1000PHY_LSR_MDIX 0x0800 166 #define IP1000PHY_LSR_FULL_DUPLEX 0x1000 167 #define IP1000PHY_LSR_SPEED_10 0x0000 168 #define IP1000PHY_LSR_SPEED_100 0x2000 169 #define IP1000PHY_LSR_SPEED_1000 0x4000 170 #define IP1000PHY_LSR_SPEED_MASK 0x6000 171 #define IP1000PHY_LSR_LINKUP 0x8000 172 173 /* PHY specific control register 2. IP1001 only. */ 174 #define IP1000PHY_SCR 175 #define IP1000PHY_SCR_SEW_RATE_MASK 0x0003 176 #define IP1000PHY_SCR_SEW_RATE_DEF 0x0003 177 #define IP1000PHY_SCR_AUTO_XOVER 0x0004 178 #define IP1000PHY_SCR_SPEED_10_100_ENB 0x0040 179 #define IP1000PHY_SCR_FIFO_LATENCY_2 0x0000 180 #define IP1000PHY_SCR_FIFO_LATENCY_3 0x0080 181 #define IP1000PHY_SCR_FIFO_LATENCY_4 0x0100 182 #define IP1000PHY_SCR_FIFO_LATENCY_5 0x0180 183 #define IP1000PHY_SCR_MDIX_ENB 0x0200 184 #define IP1000PHY_SCR_RESERVED_DEF 0x0400 185 #define IP1000PHY_SCR_APS_ON 0x0800 186 187 #endif /* _DEV_MII_IP1000PHYREG_H_ */
Cache object: f4930201c93d58176c2284fb33bfaa3a
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