The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/lxtphyreg.h

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    1 /*      OpenBSD: lxtphyreg.h,v 1.1 1998/11/11 19:34:47 jason Exp        */
    2 /*      NetBSD: lxtphyreg.h,v 1.1 1998/10/24 00:33:17 thorpej Exp       */
    3 /*      $FreeBSD$       */
    4 
    5 /*-
    6  * Copyright (c) 1998 The NetBSD Foundation, Inc.
    7  * All rights reserved.
    8  *
    9  * This code is derived from software contributed to The NetBSD Foundation
   10  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   11  * NASA Ames Research Center.
   12  *
   13  * Redistribution and use in source and binary forms, with or without
   14  * modification, are permitted provided that the following conditions
   15  * are met:
   16  * 1. Redistributions of source code must retain the above copyright
   17  *    notice, this list of conditions and the following disclaimer.
   18  * 2. Redistributions in binary form must reproduce the above copyright
   19  *    notice, this list of conditions and the following disclaimer in the
   20  *    documentation and/or other materials provided with the distribution.
   21  * 3. All advertising materials mentioning features or use of this software
   22  *    must display the following acknowledgement:
   23  *      This product includes software developed by the NetBSD
   24  *      Foundation, Inc. and its contributors.
   25  * 4. Neither the name of The NetBSD Foundation nor the names of its
   26  *    contributors may be used to endorse or promote products derived
   27  *    from this software without specific prior written permission.
   28  *
   29  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   31  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   32  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   33  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   34  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   37  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   39  * POSSIBILITY OF SUCH DAMAGE.
   40  */
   41 
   42 #ifndef _DEV_MII_LXTPHYREG_H_
   43 #define _DEV_MII_LXTPHYREG_H_
   44 
   45 /*
   46  * LXT970 registers.
   47  */
   48 
   49 #define MII_LXTPHY_MIRROR       0x10    /* Mirror register */
   50         /* All bits user-defined */
   51 
   52 #define MII_LXTPHY_IER          0x11    /* Interrupt Enable Register */
   53 #define IER_MIIDRVLVL           0x0008  /* Rediced MII driver levels */
   54 #define IER_LNK_CRITERIA        0x0004  /* Enhanced Link Loss Criteria */
   55 #define IER_INTEN               0x0002  /* Interrupt Enable */
   56 #define IER_TINT                0x0001  /* Force Interrupt */
   57 
   58 #define MII_LXTPHY_ISR          0x12    /* Interrupt Status Register */
   59 #define ISR_MINT                0x8000  /* MII Interrupt Pending */
   60 #define ISR_XTALOK              0x4000  /* Clocks OK */
   61 
   62 #define MII_LXTPHY_CONFIG       0x13    /* Configuration Register */
   63 #define CONFIG_TXMIT_TEST       0x4000  /* 100base-T Transmit Test */
   64 #define CONFIG_REPEATER         0x2000  /* Repeater Mode */
   65 #define CONFIG_MDIO_INT         0x1000  /* Enable intr signalling on MDIO */
   66 #define CONFIG_TPLOOP           0x0800  /* Disable 10base-T Loopback */
   67 #define CONFIG_SQE              0x0400  /* Enable SQE */
   68 #define CONFIG_DISJABBER        0x0200  /* Disable Jabber */
   69 #define CONFIG_DISLINKTEST      0x0100  /* Disable Link Test */
   70 #define CONFIG_LEDC1            0x0080  /* LEDC configuration */
   71 #define CONFIG_LEDC0            0x0040  /* ... */
   72                                         /* 0 0 LEDC indicates collision */
   73                                         /* 0 1 LEDC is off */
   74                                         /* 1 0 LEDC indicates activity */
   75                                         /* 1 1 LEDC is on */
   76 #define CONFIG_ADVTXCLK         0x0020  /* Advance TX clock */
   77 #define CONFIG_5BSYMBOL         0x0010  /* 5-bit Symbol mode */
   78 #define CONFIG_SCRAMBLER        0x0008  /* Bypass scrambler */
   79 #define CONFIG_100BASEFX        0x0004  /* 100base-FX */
   80 #define CONFIG_TXDISCON         0x0001  /* Disconnect TP transmitter */
   81 
   82 #define MII_LXTPHY_CSR          0x14    /* Chip Status Register */
   83 #define CSR_LINK                0x2000  /* Link is up */
   84 #define CSR_DUPLEX              0x1000  /* Full-duplex */
   85 #define CSR_SPEED               0x0800  /* 100Mbps */
   86 #define CSR_ACOMP               0x0400  /* Autonegotiation complete */
   87 #define CSR_PAGERCVD            0x0200  /* Link page received */
   88 #define CSR_LOWVCC              0x0004  /* Low Voltage Fault */
   89 
   90 #endif /* _DEV_MII_LXTPHYREG_H_ */

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