The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/miidevs.h

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    1 /*      $FreeBSD: releng/5.0/sys/dev/mii/miidevs.h 103103 2002-09-08 19:12:02Z jdp $    */
    2 
    3 /*
    4  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
    5  *
    6  * generated from:
    7  *      FreeBSD: src/sys/dev/mii/miidevs,v 1.20 2002/07/05 11:07:24 benno Exp 
    8  */
    9 /*$NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp $*/
   10 
   11 /*-
   12  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
   13  * All rights reserved.
   14  *
   15  * This code is derived from software contributed to The NetBSD Foundation
   16  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   17  * NASA Ames Research Center.
   18  *
   19  * Redistribution and use in source and binary forms, with or without
   20  * modification, are permitted provided that the following conditions
   21  * are met:
   22  * 1. Redistributions of source code must retain the above copyright
   23  *    notice, this list of conditions and the following disclaimer.
   24  * 2. Redistributions in binary form must reproduce the above copyright
   25  *    notice, this list of conditions and the following disclaimer in the
   26  *    documentation and/or other materials provided with the distribution.
   27  * 3. All advertising materials mentioning features or use of this software
   28  *    must display the following acknowledgement:
   29  *      This product includes software developed by the NetBSD
   30  *      Foundation, Inc. and its contributors.
   31  * 4. Neither the name of The NetBSD Foundation nor the names of its
   32  *    contributors may be used to endorse or promote products derived
   33  *    from this software without specific prior written permission.
   34  *
   35  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   36  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   37  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   38  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   39  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   40  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   41  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   42  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   43  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   44  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   45  * POSSIBILITY OF SUCH DAMAGE.
   46  */
   47 
   48 /*
   49  * List of known MII OUIs.
   50  * For a complete list see http://standards.ieee.org/regauth/oui/
   51  *
   52  * XXX Vendors do obviously not agree how OUIs (18 bit) are mapped
   53  * to the 16 bits available in the id registers. The MII_OUI() macro
   54  * in "mii.h" reflects the most obvious way. If a vendor uses a
   55  * different mapping, an "xx" prefixed OUI is defined here which is
   56  * mangled accordingly to compensate.
   57  */
   58 
   59 #define MII_OUI_ALTIMA  0x0010a9        /* Altima Communications */
   60 #define MII_OUI_AMD     0x00001a        /* Advanced Micro Devices */
   61 #define MII_OUI_BROADCOM        0x001018        /* Broadcom Corporation */
   62 #define MII_OUI_DAVICOM 0x00606e        /* Davicom Semiconductor */
   63 #define MII_OUI_ICS     0x00a0be        /* Integrated Circuit Systems */
   64 #define MII_OUI_INTEL   0x00aa00        /* Intel */
   65 #define MII_OUI_JATO    0x00e083        /* Jato Technologies */
   66 #define MII_OUI_LEVEL1  0x00207b        /* Level 1 */
   67 #define MII_OUI_NATSEMI 0x080017        /* National Semiconductor */
   68 #define MII_OUI_QUALSEMI        0x006051        /* Quality Semiconductor */
   69 #define MII_OUI_REALTEK 0x000020        /* RealTek Semicondctor */
   70 #define MII_OUI_SEEQ    0x00a07d        /* Seeq */
   71 #define MII_OUI_SIS     0x00e006        /* Silicon Integrated Systems */
   72 #define MII_OUI_TDK     0x00c039        /* TDK */
   73 #define MII_OUI_TI      0x080028        /* Texas Instruments */
   74 #define MII_OUI_XAQTI   0x00e0ae        /* XaQti Corp. */
   75 #define MII_OUI_MARVELL 0x005043        /* Marvell Semiconductor */
   76 #define MII_OUI_xxMARVELL       0x000ac2        /* Marvell Semiconductor */
   77 
   78 /* in the 79c873, AMD uses another OUI (which matches Davicom!) */
   79 #define MII_OUI_xxAMD   0x00606e        /* Advanced Micro Devices */
   80 
   81 /* Intel 82553 A/B steppings */
   82 #define MII_OUI_xxINTEL 0x00f800        /* Intel */
   83 
   84 /* some vendors have the bits swapped within bytes
   85         (ie, ordered as on the wire) */
   86 #define MII_OUI_xxALTIMA        0x000895        /* Altima Communications */
   87 #define MII_OUI_xxBROADCOM      0x000818        /* Broadcom Corporation */
   88 #define MII_OUI_xxICS   0x00057d        /* Integrated Circuit Systems */
   89 #define MII_OUI_xxSEEQ  0x0005be        /* Seeq */
   90 #define MII_OUI_xxSIS   0x000760        /* Silicon Integrated Systems */
   91 #define MII_OUI_xxTI    0x100014        /* Texas Instruments */
   92 #define MII_OUI_xxXAQTI 0x350700        /* XaQti Corp. */
   93 
   94 /* Level 1 is completely different - from right to left.
   95         (Two bits get lost in the third OUI byte.) */
   96 #define MII_OUI_xxLEVEL1        0x1e0400        /* Level 1 */
   97 
   98 /* Don't know what's going on here. */
   99 #define MII_OUI_xxDAVICOM       0x006040        /* Davicom Semiconductor */
  100 
  101 
  102 /*
  103  * List of known models.  Grouped by oui.
  104  */
  105 
  106 /* Altima Communications PHYs */
  107 #define MII_MODEL_xxALTIMA_AC101        0x0021
  108 #define MII_STR_xxALTIMA_AC101  "AC101 10/100 media interface"
  109 
  110 /* Advanced Micro Devices PHYs */
  111 #define MII_MODEL_xxAMD_79C873  0x0000
  112 #define MII_STR_xxAMD_79C873    "Am79C873 10/100 media interface"
  113 #define MII_MODEL_AMD_79c973phy 0x0036
  114 #define MII_STR_AMD_79c973phy   "Am79c973 internal PHY"
  115 #define MII_MODEL_AMD_79c978    0x0039
  116 #define MII_STR_AMD_79c978      "Am79c978 HomePNA PHY"
  117 
  118 /* Broadcom Corp. PHYs. */
  119 #define MII_MODEL_BROADCOM_3C905B       0x0012
  120 #define MII_STR_BROADCOM_3C905B "3c905B 10/100 internal PHY"
  121 #define MII_MODEL_BROADCOM_3C905C       0x0017
  122 #define MII_STR_BROADCOM_3C905C "3c905C 10/100 internal PHY"
  123 #define MII_MODEL_BROADCOM_BCM5201      0x0021
  124 #define MII_STR_BROADCOM_BCM5201        "BCM5201 10/100baseTX PHY"
  125 #define MII_MODEL_BROADCOM_BCM5221      0x001e
  126 #define MII_STR_BROADCOM_BCM5221        "BCM5221 10/100baseTX PHY"
  127 #define MII_MODEL_xxBROADCOM_BCM5400    0x0004
  128 #define MII_STR_xxBROADCOM_BCM5400      "Broadcom 1000baseTX PHY"
  129 #define MII_MODEL_xxBROADCOM_BCM5401    0x0005
  130 #define MII_STR_xxBROADCOM_BCM5401      "BCM5401 10/100/1000baseTX PHY"
  131 #define MII_MODEL_xxBROADCOM_BCM5411    0x0007
  132 #define MII_STR_xxBROADCOM_BCM5411      "BCM5411 10/100/1000baseTX PHY"
  133 #define MII_MODEL_xxBROADCOM_BCM5701    0x0011
  134 #define MII_STR_xxBROADCOM_BCM5701      "BCM5701 10/100/1000baseTX PHY"
  135 #define MII_MODEL_xxBROADCOM_BCM5703    0x0016
  136 #define MII_STR_xxBROADCOM_BCM5703      "BCM5703 10/100/1000baseTX PHY"
  137 
  138 /* Davicom Semiconductor PHYs */
  139 #define MII_MODEL_xxDAVICOM_DM9101      0x0000
  140 #define MII_STR_xxDAVICOM_DM9101        "DM9101 10/100 media interface"
  141 
  142 /* Integrated Circuit Systems PHYs */
  143 #define MII_MODEL_xxICS_1890    0x0002
  144 #define MII_STR_xxICS_1890      "ICS1890 10/100 media interface"
  145 
  146 /* Intel PHYs */
  147 #define MII_MODEL_xxINTEL_I82553AB      0x0000
  148 #define MII_STR_xxINTEL_I82553AB        "i83553 10/100 media interface"
  149 #define MII_MODEL_INTEL_I82555  0x0015
  150 #define MII_STR_INTEL_I82555    "i82555 10/100 media interface"
  151 #define MII_MODEL_INTEL_I82562EM        0x0032
  152 #define MII_STR_INTEL_I82562EM  "i82562EM 10/100 media interface"
  153 #define MII_MODEL_INTEL_I82562ET        0x0033
  154 #define MII_STR_INTEL_I82562ET  "i82562ET 10/100 media interface"
  155 #define MII_MODEL_INTEL_I82553C 0x0035
  156 #define MII_STR_INTEL_I82553C   "i82553 10/100 media interface"
  157 
  158 /* Jato Technologies PHYs */
  159 #define MII_MODEL_JATO_BASEX    0x0000
  160 #define MII_STR_JATO_BASEX      "Jato 1000baseX media interface"
  161 
  162 /* Level 1 PHYs */
  163 #define MII_MODEL_xxLEVEL1_LXT970       0x0000
  164 #define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
  165 
  166 /* National Semiconductor PHYs */
  167 #define MII_MODEL_NATSEMI_DP83840       0x0000
  168 #define MII_STR_NATSEMI_DP83840 "DP83840 10/100 media interface"
  169 #define MII_MODEL_NATSEMI_DP83843       0x0001
  170 #define MII_STR_NATSEMI_DP83843 "DP83843 10/100 media interface"
  171 #define MII_MODEL_NATSEMI_DP83891       0x0005
  172 #define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 media interface"
  173 #define MII_MODEL_NATSEMI_DP83861       0x0006
  174 #define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 media interface"
  175 
  176 /* Quality Semiconductor PHYs */
  177 #define MII_MODEL_QUALSEMI_QS6612       0x0000
  178 #define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 media interface"
  179 
  180 /* RealTek Semiconductor PHYs */
  181 #define MII_MODEL_REALTEK_RTL8201L      0x0020
  182 #define MII_STR_REALTEK_RTL8201L        "RTL8201L 10/100 media interface"
  183 
  184 /* Seeq PHYs */
  185 #define MII_MODEL_xxSEEQ_80220  0x0003
  186 #define MII_STR_xxSEEQ_80220    "Seeq 80220 10/100 media interface"
  187 #define MII_MODEL_xxSEEQ_84220  0x0004
  188 #define MII_STR_xxSEEQ_84220    "Seeq 84220 10/100 media interface"
  189 
  190 /* Silicon Integrated Systems PHYs */
  191 #define MII_MODEL_xxSIS_900     0x0000
  192 #define MII_STR_xxSIS_900       "SiS 900 10/100 media interface"
  193 
  194 /* TDK */
  195 #define MII_MODEL_TDK_78Q2120   0x0014
  196 #define MII_STR_TDK_78Q2120     "TDK 78Q2120 media interface"
  197 
  198 /* Texas Instruments PHYs */
  199 #define MII_MODEL_xxTI_TLAN10T  0x0001
  200 #define MII_STR_xxTI_TLAN10T    "ThunderLAN 10baseT media interface"
  201 #define MII_MODEL_xxTI_100VGPMI 0x0002
  202 #define MII_STR_xxTI_100VGPMI   "ThunderLAN 100VG-AnyLan media interface"
  203 
  204 /* XaQti Corp. PHYs. */
  205 #define MII_MODEL_XAQTI_XMACII  0x0000
  206 #define MII_STR_XAQTI_XMACII    "XaQti Corp. XMAC II gigabit interface"
  207 
  208 /* Marvell Semiconductor PHYs */
  209 #define MII_MODEL_MARVELL_E1000 0x0000
  210 #define MII_STR_MARVELL_E1000   "Marvell 88E1000 Gigabit PHY"
  211 #define MII_MODEL_xxMARVELL_E1000       0x0005
  212 #define MII_STR_xxMARVELL_E1000 "Marvell 88E1000 Gigabit PHY"
  213

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