The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/qsphyreg.h

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    1 /*      OpenBSD: qsphyreg.h,v 1.2 1999/03/09 00:02:45 jason Exp         */
    2 /*      NetBSD: qsphyreg.h,v 1.1 1998/08/11 00:01:03 thorpej Exp        */
    3 /*      $FreeBSD$       */
    4 
    5 /*-
    6  * Copyright (c) 1998 The NetBSD Foundation, Inc.
    7  * All rights reserved.
    8  *
    9  * This code is derived from software contributed to The NetBSD Foundation
   10  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   11  * NASA Ames Research Center.
   12  *
   13  * Redistribution and use in source and binary forms, with or without
   14  * modification, are permitted provided that the following conditions
   15  * are met:
   16  * 1. Redistributions of source code must retain the above copyright
   17  *    notice, this list of conditions and the following disclaimer.
   18  * 2. Redistributions in binary form must reproduce the above copyright
   19  *    notice, this list of conditions and the following disclaimer in the
   20  *    documentation and/or other materials provided with the distribution.
   21  * 3. All advertising materials mentioning features or use of this software
   22  *    must display the following acknowledgement:
   23  *      This product includes software developed by the NetBSD
   24  *      Foundation, Inc. and its contributors.
   25  * 4. Neither the name of The NetBSD Foundation nor the names of its
   26  *    contributors may be used to endorse or promote products derived
   27  *    from this software without specific prior written permission.
   28  *
   29  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   31  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   32  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   33  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   34  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   37  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   39  * POSSIBILITY OF SUCH DAMAGE.
   40  */
   41 
   42 #ifndef _DEV_MII_QSPHYREG_H_
   43 #define _DEV_MII_QSPHYREG_H_
   44 
   45 /*
   46  * Register definitions for the Quality Semiconductor QS6612
   47  * Further documentation can be found at:
   48  *      http://www.qualitysemi.com/products/network.html
   49  */
   50 
   51 #define MII_QSPHY_MCTL          0x11    /* Mode control */
   52 #define MCTL_T4PRE              0x1000  /* 100baseT4 interface present */
   53 #define MCTL_BTEXT              0x0800  /* reduce 10baseT squelch level */
   54 #define MCTL_FACTTEST           0x0100  /* factory test mode */
   55 #define MCTL_PHYADDRMASK        0x00f8  /* PHY address */
   56 #define MCTL_FACTTEST2          0x0004  /* another factory test mode */
   57 #define MCTL_NLPDIS             0x0002  /* disable link pulse tx */
   58 #define MCTL_SQEDIS             0x0001  /* disable SQE */
   59 
   60 #define MII_QSPHY_ISRC          0x1d    /* Interrupt source */
   61 #define MII_QSPHY_IMASK         0x1e    /* Interrupt mask */
   62 #define IMASK_TLINTR            0x8000  /* ThunderLAN interrupt mode */
   63 #define IMASK_ANCPL             0x0040  /* autonegotiation complete */
   64 #define IMASK_RFD               0x0020  /* remote fault detected */
   65 #define IMASK_LD                0x0010  /* link down */
   66 #define IMASK_ANLPA             0x0008  /* autonegotiation LP ACK */
   67 #define IMASK_PDT               0x0004  /* parallel detection fault */
   68 #define IMASK_ANPR              0x0002  /* autonegotiation page received */
   69 #define IMASK_REF               0x0001  /* receive error counter full */
   70 
   71 #define MII_QSPHY_PCTL          0x1f    /* PHY control */
   72 #define PCTL_RXERDIS            0x2000  /* receive error counter disable */
   73 #define PCTL_ANC                0x1000  /* autonegotiation complete */
   74 #define PCTL_RLBEN              0x0200  /* remote coopback enable */
   75 #define PCTL_DCREN              0x0100  /* DC restoration enable */
   76 #define PCTL_4B5BEN             0x0040  /* 4b/5b encoding */
   77 #define PCTL_PHYISO             0x0020  /* isolate PHY */
   78 #define PCTL_OPMASK             0x001c  /* operation mode mask */
   79 #define PCTL_AN                 0x0000  /* autonegotiation in-progress */
   80 #define PCTL_10_T               0x0004  /* 10baseT */
   81 #define PCTL_100_TX             0x0008  /* 100baseTX */
   82 #define PCTL_100_T4             0x0010  /* 100baseT4 */
   83 #define PCTL_10_T_FDX           0x0014  /* 10baseT-FDX */
   84 #define PCTL_100_TX_FDX         0x0018  /* 100baseTX-FDX */
   85 #define PCTL_MLT3DIS            0x0002  /* disable MLT3 */
   86 #define PCTL_SRCDIS             0x0001  /* disable scrambling */
   87 
   88 #endif /* _DEV_MII_QSPHYREG_H_ */

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