Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/mii/rgephy.c
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1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY. 40 */ 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/socket.h> 47 #include <sys/taskqueue.h> 48 #include <sys/bus.h> 49 50 #include <net/if.h> 51 #include <net/if_var.h> 52 #include <net/if_arp.h> 53 #include <net/if_media.h> 54 55 #include <dev/mii/mii.h> 56 #include <dev/mii/miivar.h> 57 #include "miidevs.h" 58 59 #include <dev/mii/rgephyreg.h> 60 61 #include "miibus_if.h" 62 63 #include <machine/bus.h> 64 #include <dev/rl/if_rlreg.h> 65 66 static int rgephy_probe(device_t); 67 static int rgephy_attach(device_t); 68 69 static device_method_t rgephy_methods[] = { 70 /* device interface */ 71 DEVMETHOD(device_probe, rgephy_probe), 72 DEVMETHOD(device_attach, rgephy_attach), 73 DEVMETHOD(device_detach, mii_phy_detach), 74 DEVMETHOD(device_shutdown, bus_generic_shutdown), 75 DEVMETHOD_END 76 }; 77 78 static driver_t rgephy_driver = { 79 "rgephy", 80 rgephy_methods, 81 sizeof(struct mii_softc) 82 }; 83 84 DRIVER_MODULE(rgephy, miibus, rgephy_driver, 0, 0); 85 86 static int rgephy_service(struct mii_softc *, struct mii_data *, int); 87 static void rgephy_status(struct mii_softc *); 88 static int rgephy_mii_phy_auto(struct mii_softc *, int); 89 static void rgephy_reset(struct mii_softc *); 90 static int rgephy_linkup(struct mii_softc *); 91 static void rgephy_loop(struct mii_softc *); 92 static void rgephy_load_dspcode(struct mii_softc *); 93 static void rgephy_disable_eee(struct mii_softc *); 94 95 static const struct mii_phydesc rgephys[] = { 96 MII_PHY_DESC(REALTEK, RTL8169S), 97 MII_PHY_DESC(REALTEK, RTL8251), 98 MII_PHY_END 99 }; 100 101 static const struct mii_phy_funcs rgephy_funcs = { 102 rgephy_service, 103 rgephy_status, 104 rgephy_reset 105 }; 106 107 static int 108 rgephy_probe(device_t dev) 109 { 110 111 return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT)); 112 } 113 114 static int 115 rgephy_attach(device_t dev) 116 { 117 struct mii_softc *sc; 118 u_int flags; 119 120 sc = device_get_softc(dev); 121 flags = 0; 122 if (mii_dev_mac_match(dev, "re")) 123 flags |= MIIF_PHYPRIV0; 124 else if (mii_dev_mac_match(dev, "ure")) 125 flags |= MIIF_PHYPRIV1; 126 mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0); 127 128 /* RTL8169S do not report auto-sense; add manually. */ 129 sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) & 130 sc->mii_capmask; 131 if (sc->mii_capabilities & BMSR_EXTSTAT) 132 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR); 133 device_printf(dev, " "); 134 mii_phy_add_media(sc); 135 printf("\n"); 136 /* 137 * Allow IFM_FLAG0 to be set indicating that auto-negotiation with 138 * manual configuration, which is used to work around issues with 139 * certain setups by default, should not be triggered as it may in 140 * turn cause harm in some edge cases. 141 */ 142 sc->mii_pdata->mii_media.ifm_mask |= IFM_FLAG0; 143 144 PHY_RESET(sc); 145 146 MIIBUS_MEDIAINIT(sc->mii_dev); 147 return (0); 148 } 149 150 static int 151 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd) 152 { 153 struct ifmedia_entry *ife = mii->mii_media.ifm_cur; 154 int speed, gig, anar; 155 156 switch (cmd) { 157 case MII_POLLSTAT: 158 break; 159 160 case MII_MEDIACHG: 161 PHY_RESET(sc); /* XXX hardware bug work-around */ 162 163 anar = PHY_READ(sc, RGEPHY_MII_ANAR); 164 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP | 165 RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX | 166 RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10); 167 168 switch (IFM_SUBTYPE(ife->ifm_media)) { 169 case IFM_AUTO: 170 #ifdef foo 171 /* 172 * If we're already in auto mode, just return. 173 */ 174 if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN) 175 return (0); 176 #endif 177 (void)rgephy_mii_phy_auto(sc, ife->ifm_media); 178 break; 179 case IFM_1000_T: 180 speed = RGEPHY_S1000; 181 goto setit; 182 case IFM_100_TX: 183 speed = RGEPHY_S100; 184 anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX; 185 goto setit; 186 case IFM_10_T: 187 speed = RGEPHY_S10; 188 anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10; 189 setit: 190 if ((ife->ifm_media & IFM_FLOW) != 0 && 191 (mii->mii_media.ifm_media & IFM_FLAG0) != 0) 192 return (EINVAL); 193 194 if ((ife->ifm_media & IFM_FDX) != 0) { 195 speed |= RGEPHY_BMCR_FDX; 196 gig = RGEPHY_1000CTL_AFD; 197 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10); 198 if ((ife->ifm_media & IFM_FLOW) != 0 || 199 (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 200 anar |= 201 RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 202 } else { 203 gig = RGEPHY_1000CTL_AHD; 204 anar &= 205 ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD); 206 } 207 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) { 208 gig |= RGEPHY_1000CTL_MSE; 209 if ((ife->ifm_media & IFM_ETH_MASTER) != 0) 210 gig |= RGEPHY_1000CTL_MSC; 211 } else { 212 gig = 0; 213 anar &= ~RGEPHY_ANAR_ASP; 214 } 215 if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0) 216 speed |= 217 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG; 218 rgephy_loop(sc); 219 PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig); 220 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 221 PHY_WRITE(sc, RGEPHY_MII_BMCR, speed); 222 break; 223 case IFM_NONE: 224 PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN); 225 break; 226 default: 227 return (EINVAL); 228 } 229 break; 230 231 case MII_TICK: 232 /* 233 * Only used for autonegotiation. 234 */ 235 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) { 236 sc->mii_ticks = 0; 237 break; 238 } 239 240 /* 241 * Check to see if we have link. If we do, we don't 242 * need to restart the autonegotiation process. 243 */ 244 if (rgephy_linkup(sc) != 0) { 245 sc->mii_ticks = 0; 246 break; 247 } 248 249 /* Announce link loss right after it happens. */ 250 if (sc->mii_ticks++ == 0) 251 break; 252 253 /* Only retry autonegotiation every mii_anegticks seconds. */ 254 if (sc->mii_ticks <= sc->mii_anegticks) 255 return (0); 256 257 sc->mii_ticks = 0; 258 rgephy_mii_phy_auto(sc, ife->ifm_media); 259 break; 260 } 261 262 /* Update the media status. */ 263 PHY_STATUS(sc); 264 265 /* 266 * Callback if something changed. Note that we need to poke 267 * the DSP on the RealTek PHYs if the media changes. 268 * 269 */ 270 if (sc->mii_media_active != mii->mii_media_active || 271 sc->mii_media_status != mii->mii_media_status || 272 cmd == MII_MEDIACHG) { 273 rgephy_load_dspcode(sc); 274 } 275 mii_phy_update(sc, cmd); 276 return (0); 277 } 278 279 static int 280 rgephy_linkup(struct mii_softc *sc) 281 { 282 int linkup; 283 uint16_t reg; 284 285 linkup = 0; 286 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && 287 sc->mii_mpd_rev >= RGEPHY_8211B) { 288 if (sc->mii_mpd_rev == RGEPHY_8211F) { 289 reg = PHY_READ(sc, RGEPHY_F_MII_SSR); 290 if (reg & RGEPHY_F_SSR_LINK) 291 linkup++; 292 } else { 293 reg = PHY_READ(sc, RGEPHY_MII_SSR); 294 if (reg & RGEPHY_SSR_LINK) 295 linkup++; 296 } 297 } else { 298 if (sc->mii_flags & MIIF_PHYPRIV1) 299 reg = PHY_READ(sc, URE_GMEDIASTAT); 300 else 301 reg = PHY_READ(sc, RL_GMEDIASTAT); 302 if (reg & RL_GMEDIASTAT_LINK) 303 linkup++; 304 } 305 306 return (linkup); 307 } 308 309 static void 310 rgephy_status(struct mii_softc *sc) 311 { 312 struct mii_data *mii = sc->mii_pdata; 313 int bmsr, bmcr; 314 uint16_t ssr; 315 316 mii->mii_media_status = IFM_AVALID; 317 mii->mii_media_active = IFM_ETHER; 318 319 if (rgephy_linkup(sc) != 0) 320 mii->mii_media_status |= IFM_ACTIVE; 321 322 bmsr = PHY_READ(sc, RGEPHY_MII_BMSR); 323 bmcr = PHY_READ(sc, RGEPHY_MII_BMCR); 324 if (bmcr & RGEPHY_BMCR_ISO) { 325 mii->mii_media_active |= IFM_NONE; 326 mii->mii_media_status = 0; 327 return; 328 } 329 330 if (bmcr & RGEPHY_BMCR_LOOP) 331 mii->mii_media_active |= IFM_LOOP; 332 333 if (bmcr & RGEPHY_BMCR_AUTOEN) { 334 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) { 335 /* Erg, still trying, I guess... */ 336 mii->mii_media_active |= IFM_NONE; 337 return; 338 } 339 } 340 341 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && 342 sc->mii_mpd_rev >= RGEPHY_8211B) { 343 if (sc->mii_mpd_rev == RGEPHY_8211F) { 344 ssr = PHY_READ(sc, RGEPHY_F_MII_SSR); 345 switch (ssr & RGEPHY_F_SSR_SPD_MASK) { 346 case RGEPHY_F_SSR_S1000: 347 mii->mii_media_active |= IFM_1000_T; 348 break; 349 case RGEPHY_F_SSR_S100: 350 mii->mii_media_active |= IFM_100_TX; 351 break; 352 case RGEPHY_F_SSR_S10: 353 mii->mii_media_active |= IFM_10_T; 354 break; 355 default: 356 mii->mii_media_active |= IFM_NONE; 357 break; 358 } 359 if (ssr & RGEPHY_F_SSR_FDX) 360 mii->mii_media_active |= IFM_FDX; 361 else 362 mii->mii_media_active |= IFM_HDX; 363 364 } else { 365 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 366 switch (ssr & RGEPHY_SSR_SPD_MASK) { 367 case RGEPHY_SSR_S1000: 368 mii->mii_media_active |= IFM_1000_T; 369 break; 370 case RGEPHY_SSR_S100: 371 mii->mii_media_active |= IFM_100_TX; 372 break; 373 case RGEPHY_SSR_S10: 374 mii->mii_media_active |= IFM_10_T; 375 break; 376 default: 377 mii->mii_media_active |= IFM_NONE; 378 break; 379 } 380 if (ssr & RGEPHY_SSR_FDX) 381 mii->mii_media_active |= IFM_FDX; 382 else 383 mii->mii_media_active |= IFM_HDX; 384 } 385 } else { 386 if (sc->mii_flags & MIIF_PHYPRIV1) 387 bmsr = PHY_READ(sc, URE_GMEDIASTAT); 388 else 389 bmsr = PHY_READ(sc, RL_GMEDIASTAT); 390 if (bmsr & RL_GMEDIASTAT_1000MBPS) 391 mii->mii_media_active |= IFM_1000_T; 392 else if (bmsr & RL_GMEDIASTAT_100MBPS) 393 mii->mii_media_active |= IFM_100_TX; 394 else if (bmsr & RL_GMEDIASTAT_10MBPS) 395 mii->mii_media_active |= IFM_10_T; 396 else 397 mii->mii_media_active |= IFM_NONE; 398 if (bmsr & RL_GMEDIASTAT_FDX) 399 mii->mii_media_active |= IFM_FDX; 400 else 401 mii->mii_media_active |= IFM_HDX; 402 } 403 404 if ((mii->mii_media_active & IFM_FDX) != 0) 405 mii->mii_media_active |= mii_phy_flowstatus(sc); 406 407 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) && 408 (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0) 409 mii->mii_media_active |= IFM_ETH_MASTER; 410 } 411 412 static int 413 rgephy_mii_phy_auto(struct mii_softc *sc, int media) 414 { 415 int anar; 416 417 rgephy_loop(sc); 418 PHY_RESET(sc); 419 420 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 421 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0) 422 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP; 423 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 424 DELAY(1000); 425 PHY_WRITE(sc, RGEPHY_MII_1000CTL, 426 RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD); 427 DELAY(1000); 428 PHY_WRITE(sc, RGEPHY_MII_BMCR, 429 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 430 DELAY(100); 431 432 return (EJUSTRETURN); 433 } 434 435 static void 436 rgephy_loop(struct mii_softc *sc) 437 { 438 int i; 439 440 if (sc->mii_mpd_model != MII_MODEL_REALTEK_RTL8251 && 441 sc->mii_mpd_rev < RGEPHY_8211B) { 442 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN); 443 DELAY(1000); 444 } 445 446 for (i = 0; i < 15000; i++) { 447 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) { 448 #if 0 449 device_printf(sc->mii_dev, "looped %d\n", i); 450 #endif 451 break; 452 } 453 DELAY(10); 454 } 455 } 456 457 #define PHY_SETBIT(x, y, z) \ 458 PHY_WRITE(x, y, (PHY_READ(x, y) | (z))) 459 #define PHY_CLRBIT(x, y, z) \ 460 PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z))) 461 462 /* 463 * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of 464 * existing revisions of the 8169S/8110S chips need to be tuned in 465 * order to reliably negotiate a 1000Mbps link. This is only needed 466 * for rev 0 and rev 1 of the PHY. Later versions work without 467 * any fixups. 468 */ 469 static void 470 rgephy_load_dspcode(struct mii_softc *sc) 471 { 472 int val; 473 474 if (sc->mii_mpd_model == MII_MODEL_REALTEK_RTL8251 || 475 sc->mii_mpd_rev >= RGEPHY_8211B) 476 return; 477 478 PHY_WRITE(sc, 31, 0x0001); 479 PHY_WRITE(sc, 21, 0x1000); 480 PHY_WRITE(sc, 24, 0x65C7); 481 PHY_CLRBIT(sc, 4, 0x0800); 482 val = PHY_READ(sc, 4) & 0xFFF; 483 PHY_WRITE(sc, 4, val); 484 PHY_WRITE(sc, 3, 0x00A1); 485 PHY_WRITE(sc, 2, 0x0008); 486 PHY_WRITE(sc, 1, 0x1020); 487 PHY_WRITE(sc, 0, 0x1000); 488 PHY_SETBIT(sc, 4, 0x0800); 489 PHY_CLRBIT(sc, 4, 0x0800); 490 val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000; 491 PHY_WRITE(sc, 4, val); 492 PHY_WRITE(sc, 3, 0xFF41); 493 PHY_WRITE(sc, 2, 0xDE60); 494 PHY_WRITE(sc, 1, 0x0140); 495 PHY_WRITE(sc, 0, 0x0077); 496 val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000; 497 PHY_WRITE(sc, 4, val); 498 PHY_WRITE(sc, 3, 0xDF01); 499 PHY_WRITE(sc, 2, 0xDF20); 500 PHY_WRITE(sc, 1, 0xFF95); 501 PHY_WRITE(sc, 0, 0xFA00); 502 val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000; 503 PHY_WRITE(sc, 4, val); 504 PHY_WRITE(sc, 3, 0xFF41); 505 PHY_WRITE(sc, 2, 0xDE20); 506 PHY_WRITE(sc, 1, 0x0140); 507 PHY_WRITE(sc, 0, 0x00BB); 508 val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000; 509 PHY_WRITE(sc, 4, val); 510 PHY_WRITE(sc, 3, 0xDF01); 511 PHY_WRITE(sc, 2, 0xDF20); 512 PHY_WRITE(sc, 1, 0xFF95); 513 PHY_WRITE(sc, 0, 0xBF00); 514 PHY_SETBIT(sc, 4, 0x0800); 515 PHY_CLRBIT(sc, 4, 0x0800); 516 PHY_WRITE(sc, 31, 0x0000); 517 518 DELAY(40); 519 } 520 521 static void 522 rgephy_reset(struct mii_softc *sc) 523 { 524 uint16_t pcr, ssr; 525 526 switch (sc->mii_mpd_rev) { 527 case RGEPHY_8211F: 528 pcr = PHY_READ(sc, RGEPHY_F_MII_PCR1); 529 pcr &= ~(RGEPHY_F_PCR1_MDI_MM | RGEPHY_F_PCR1_ALDPS_EN); 530 PHY_WRITE(sc, RGEPHY_F_MII_PCR1, pcr); 531 rgephy_disable_eee(sc); 532 break; 533 case RGEPHY_8211C: 534 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0) { 535 /* RTL8211C(L) */ 536 ssr = PHY_READ(sc, RGEPHY_MII_SSR); 537 if ((ssr & RGEPHY_SSR_ALDPS) != 0) { 538 ssr &= ~RGEPHY_SSR_ALDPS; 539 PHY_WRITE(sc, RGEPHY_MII_SSR, ssr); 540 } 541 } 542 /* FALLTHROUGH */ 543 default: 544 if (sc->mii_mpd_rev >= RGEPHY_8211B) { 545 pcr = PHY_READ(sc, RGEPHY_MII_PCR); 546 if ((pcr & RGEPHY_PCR_MDIX_AUTO) == 0) { 547 pcr &= ~RGEPHY_PCR_MDI_MASK; 548 pcr |= RGEPHY_PCR_MDIX_AUTO; 549 PHY_WRITE(sc, RGEPHY_MII_PCR, pcr); 550 } 551 } 552 break; 553 } 554 555 mii_phy_reset(sc); 556 DELAY(1000); 557 rgephy_load_dspcode(sc); 558 } 559 560 static void 561 rgephy_disable_eee(struct mii_softc *sc) 562 { 563 uint16_t anar; 564 565 PHY_WRITE(sc, RGEPHY_F_EPAGSR, 0x0000); 566 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_ADDRESS | 567 (MMDACR_DADDRMASK & RGEPHY_F_MMD_DEV_7)); 568 PHY_WRITE(sc, MII_MMDAADR, RGEPHY_F_MMD_EEEAR); 569 PHY_WRITE(sc, MII_MMDACR, MMDACR_FN_DATANPI | 570 (MMDACR_DADDRMASK & RGEPHY_F_MMD_DEV_7)); 571 PHY_WRITE(sc, MII_MMDAADR, 0x0000); 572 PHY_WRITE(sc, MII_MMDACR, 0x0000); 573 /* 574 * XXX 575 * Restart auto-negotiation to take changes effect. 576 * This may result in link establishment. 577 */ 578 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA; 579 PHY_WRITE(sc, RGEPHY_MII_ANAR, anar); 580 PHY_WRITE(sc, RGEPHY_MII_1000CTL, RGEPHY_1000CTL_AHD | 581 RGEPHY_1000CTL_AFD); 582 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_RESET | 583 RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG); 584 }
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