The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/rgephy.c

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    1 /*-
    2  * Copyright (c) 2003
    3  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by Bill Paul.
   16  * 4. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/8.4/sys/dev/mii/rgephy.c 233493 2012-03-26 04:29:06Z yongari $");
   35 
   36 /*
   37  * Driver for the RealTek 8169S/8110S/8211B/8211C internal 10/100/1000 PHY.
   38  */
   39 
   40 #include <sys/param.h>
   41 #include <sys/systm.h>
   42 #include <sys/kernel.h>
   43 #include <sys/module.h>
   44 #include <sys/socket.h>
   45 #include <sys/bus.h>
   46 
   47 #include <net/if.h>
   48 #include <net/if_arp.h>
   49 #include <net/if_media.h>
   50 
   51 #include <dev/mii/mii.h>
   52 #include <dev/mii/miivar.h>
   53 #include "miidevs.h"
   54 
   55 #include <dev/mii/rgephyreg.h>
   56 
   57 #include "miibus_if.h"
   58 
   59 #include <machine/bus.h>
   60 #include <pci/if_rlreg.h>
   61 
   62 static int rgephy_probe(device_t);
   63 static int rgephy_attach(device_t);
   64 
   65 struct rgephy_softc {
   66         struct mii_softc mii_sc;
   67         int mii_model;
   68         int mii_revision;
   69 };
   70 
   71 static device_method_t rgephy_methods[] = {
   72         /* device interface */
   73         DEVMETHOD(device_probe,         rgephy_probe),
   74         DEVMETHOD(device_attach,        rgephy_attach),
   75         DEVMETHOD(device_detach,        mii_phy_detach),
   76         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
   77         DEVMETHOD_END
   78 };
   79 
   80 static devclass_t rgephy_devclass;
   81 
   82 static driver_t rgephy_driver = {
   83         "rgephy",
   84         rgephy_methods,
   85         sizeof(struct rgephy_softc)
   86 };
   87 
   88 DRIVER_MODULE(rgephy, miibus, rgephy_driver, rgephy_devclass, 0, 0);
   89 
   90 static int      rgephy_service(struct mii_softc *, struct mii_data *, int);
   91 static void     rgephy_status(struct mii_softc *);
   92 static int      rgephy_mii_phy_auto(struct mii_softc *, int);
   93 static void     rgephy_reset(struct mii_softc *);
   94 static void     rgephy_loop(struct mii_softc *);
   95 static void     rgephy_load_dspcode(struct mii_softc *);
   96 
   97 static const struct mii_phydesc rgephys[] = {
   98         MII_PHY_DESC(xxREALTEK, RTL8169S),
   99         MII_PHY_END
  100 };
  101 
  102 static int
  103 rgephy_probe(device_t dev)
  104 {
  105 
  106         return (mii_phy_dev_probe(dev, rgephys, BUS_PROBE_DEFAULT));
  107 }
  108 
  109 static int
  110 rgephy_attach(device_t dev)
  111 {
  112         struct rgephy_softc *rsc;
  113         struct mii_softc *sc;
  114         struct mii_attach_args *ma;
  115         struct mii_data *mii;
  116 
  117         rsc = device_get_softc(dev);
  118         sc = &rsc->mii_sc;
  119         ma = device_get_ivars(dev);
  120         sc->mii_dev = device_get_parent(dev);
  121         mii = ma->mii_data;
  122         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
  123 
  124         sc->mii_flags = miibus_get_flags(dev);
  125         if (strcmp(ma->mii_data->mii_ifp->if_dname, "re") == 0)
  126                 sc->mii_flags |= MIIF_PHYPRIV0;
  127         sc->mii_inst = mii->mii_instance++;
  128         sc->mii_phy = ma->mii_phyno;
  129         sc->mii_service = rgephy_service;
  130         sc->mii_pdata = mii;
  131 
  132         rsc->mii_model = MII_MODEL(ma->mii_id2);
  133         rsc->mii_revision = MII_REV(ma->mii_id2);
  134 
  135 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
  136 
  137 #if 0
  138         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
  139             MII_MEDIA_100_TX);
  140 #endif
  141 
  142         /* RTL8169S do not report auto-sense; add manually. */
  143         sc->mii_capabilities = (PHY_READ(sc, MII_BMSR) | BMSR_ANEG) &
  144             ma->mii_capmask;
  145         if (sc->mii_capabilities & BMSR_EXTSTAT)
  146                 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
  147         device_printf(dev, " ");
  148         mii_phy_add_media(sc);
  149         printf("\n");
  150 #undef ADD
  151         /*
  152          * Allow IFM_FLAG0 to be set indicating that auto-negotiation with
  153          * manual configuration, which is used to work around issues with
  154          * certain setups by default, should not be triggered as it may in
  155          * turn cause harm in some edge cases.
  156          */
  157         mii->mii_media.ifm_mask |= IFM_FLAG0;
  158 
  159         rgephy_reset(sc);
  160         MIIBUS_MEDIAINIT(sc->mii_dev);
  161         return (0);
  162 }
  163 
  164 static int
  165 rgephy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
  166 {
  167         struct rgephy_softc *rsc;
  168         struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
  169         int reg, speed, gig, anar;
  170 
  171         rsc = (struct rgephy_softc *)sc;
  172 
  173         switch (cmd) {
  174         case MII_POLLSTAT:
  175                 break;
  176 
  177         case MII_MEDIACHG:
  178                 /*
  179                  * If the interface is not up, don't do anything.
  180                  */
  181                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  182                         break;
  183 
  184                 rgephy_reset(sc);       /* XXX hardware bug work-around */
  185 
  186                 anar = PHY_READ(sc, RGEPHY_MII_ANAR);
  187                 anar &= ~(RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP |
  188                     RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX |
  189                     RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10);
  190 
  191                 switch (IFM_SUBTYPE(ife->ifm_media)) {
  192                 case IFM_AUTO:
  193 #ifdef foo
  194                         /*
  195                          * If we're already in auto mode, just return.
  196                          */
  197                         if (PHY_READ(sc, RGEPHY_MII_BMCR) & RGEPHY_BMCR_AUTOEN)
  198                                 return (0);
  199 #endif
  200                         (void)rgephy_mii_phy_auto(sc, ife->ifm_media);
  201                         break;
  202                 case IFM_1000_T:
  203                         speed = RGEPHY_S1000;
  204                         goto setit;
  205                 case IFM_100_TX:
  206                         speed = RGEPHY_S100;
  207                         anar |= RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_TX;
  208                         goto setit;
  209                 case IFM_10_T:
  210                         speed = RGEPHY_S10;
  211                         anar |= RGEPHY_ANAR_10_FD | RGEPHY_ANAR_10;
  212 setit:
  213                         if ((ife->ifm_media & IFM_FLOW) != 0 &&
  214                             (mii->mii_media.ifm_media & IFM_FLAG0) != 0)
  215                                 return (EINVAL);
  216 
  217                         if ((ife->ifm_media & IFM_FDX) != 0) {
  218                                 speed |= RGEPHY_BMCR_FDX;
  219                                 gig = RGEPHY_1000CTL_AFD;
  220                                 anar &= ~(RGEPHY_ANAR_TX | RGEPHY_ANAR_10);
  221                                 if ((ife->ifm_media & IFM_FLOW) != 0 ||
  222                                     (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
  223                                         anar |=
  224                                             RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
  225                         } else {
  226                                 gig = RGEPHY_1000CTL_AHD;
  227                                 anar &=
  228                                     ~(RGEPHY_ANAR_TX_FD | RGEPHY_ANAR_10_FD);
  229                         }
  230                         if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
  231                                 gig |= RGEPHY_1000CTL_MSE;
  232                                 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
  233                                     gig |= RGEPHY_1000CTL_MSC;
  234                         } else {
  235                                 gig = 0;
  236                                 anar &= ~RGEPHY_ANAR_ASP;
  237                         }
  238                         if ((mii->mii_media.ifm_media & IFM_FLAG0) == 0)
  239                                 speed |=
  240                                     RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG;
  241                         rgephy_loop(sc);
  242                         PHY_WRITE(sc, RGEPHY_MII_1000CTL, gig);
  243                         PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
  244                         PHY_WRITE(sc, RGEPHY_MII_BMCR, speed);
  245                         break;
  246                 case IFM_NONE:
  247                         PHY_WRITE(sc, MII_BMCR, BMCR_ISO | BMCR_PDOWN);
  248                         break;
  249                 default:
  250                         return (EINVAL);
  251                 }
  252                 break;
  253 
  254         case MII_TICK:
  255                 /*
  256                  * Is the interface even up?
  257                  */
  258                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  259                         return (0);
  260 
  261                 /*
  262                  * Only used for autonegotiation.
  263                  */
  264                 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
  265                         sc->mii_ticks = 0;
  266                         break;
  267                 }
  268 
  269                 /*
  270                  * Check to see if we have link.  If we do, we don't
  271                  * need to restart the autonegotiation process.
  272                  */
  273                 if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 &&
  274                     rsc->mii_revision >= 2) {
  275                         /* RTL8211B(L) */
  276                         reg = PHY_READ(sc, RGEPHY_MII_SSR);
  277                         if (reg & RGEPHY_SSR_LINK) {
  278                                 sc->mii_ticks = 0;
  279                                 break;
  280                         }
  281                 } else {
  282                         reg = PHY_READ(sc, RL_GMEDIASTAT);
  283                         if (reg & RL_GMEDIASTAT_LINK) {
  284                                 sc->mii_ticks = 0;
  285                                 break;
  286                         }
  287                 }
  288 
  289                 /* Announce link loss right after it happens. */
  290                 if (sc->mii_ticks++ == 0)
  291                         break;
  292 
  293                 /* Only retry autonegotiation every mii_anegticks seconds. */
  294                 if (sc->mii_ticks <= sc->mii_anegticks)
  295                         return (0);
  296 
  297                 sc->mii_ticks = 0;
  298                 rgephy_mii_phy_auto(sc, ife->ifm_media);
  299                 break;
  300         }
  301 
  302         /* Update the media status. */
  303         rgephy_status(sc);
  304 
  305         /*
  306          * Callback if something changed. Note that we need to poke
  307          * the DSP on the RealTek PHYs if the media changes.
  308          *
  309          */
  310         if (sc->mii_media_active != mii->mii_media_active ||
  311             sc->mii_media_status != mii->mii_media_status ||
  312             cmd == MII_MEDIACHG) {
  313                 rgephy_load_dspcode(sc);
  314         }
  315         mii_phy_update(sc, cmd);
  316         return (0);
  317 }
  318 
  319 static void
  320 rgephy_status(struct mii_softc *sc)
  321 {
  322         struct rgephy_softc *rsc;
  323         struct mii_data *mii = sc->mii_pdata;
  324         int bmsr, bmcr;
  325         uint16_t ssr;
  326 
  327         mii->mii_media_status = IFM_AVALID;
  328         mii->mii_media_active = IFM_ETHER;
  329 
  330         rsc = (struct rgephy_softc *)sc;
  331         if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && rsc->mii_revision >= 2) {
  332                 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
  333                 if (ssr & RGEPHY_SSR_LINK)
  334                         mii->mii_media_status |= IFM_ACTIVE;
  335         } else {
  336                 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
  337                 if (bmsr & RL_GMEDIASTAT_LINK)
  338                         mii->mii_media_status |= IFM_ACTIVE;
  339         }
  340 
  341         bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
  342 
  343         bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);
  344         if (bmcr & RGEPHY_BMCR_ISO) {
  345                 mii->mii_media_active |= IFM_NONE;
  346                 mii->mii_media_status = 0;
  347                 return;
  348         }
  349 
  350         if (bmcr & RGEPHY_BMCR_LOOP)
  351                 mii->mii_media_active |= IFM_LOOP;
  352 
  353         if (bmcr & RGEPHY_BMCR_AUTOEN) {
  354                 if ((bmsr & RGEPHY_BMSR_ACOMP) == 0) {
  355                         /* Erg, still trying, I guess... */
  356                         mii->mii_media_active |= IFM_NONE;
  357                         return;
  358                 }
  359         }
  360 
  361         if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && rsc->mii_revision >= 2) {
  362                 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
  363                 switch (ssr & RGEPHY_SSR_SPD_MASK) {
  364                 case RGEPHY_SSR_S1000:
  365                         mii->mii_media_active |= IFM_1000_T;
  366                         break;
  367                 case RGEPHY_SSR_S100:
  368                         mii->mii_media_active |= IFM_100_TX;
  369                         break;
  370                 case RGEPHY_SSR_S10:
  371                         mii->mii_media_active |= IFM_10_T;
  372                         break;
  373                 default:
  374                         mii->mii_media_active |= IFM_NONE;
  375                         break;
  376                 }
  377                 if (ssr & RGEPHY_SSR_FDX)
  378                         mii->mii_media_active |= IFM_FDX;
  379                 else
  380                         mii->mii_media_active |= IFM_HDX;
  381         } else {
  382                 bmsr = PHY_READ(sc, RL_GMEDIASTAT);
  383                 if (bmsr & RL_GMEDIASTAT_1000MBPS)
  384                         mii->mii_media_active |= IFM_1000_T;
  385                 else if (bmsr & RL_GMEDIASTAT_100MBPS)
  386                         mii->mii_media_active |= IFM_100_TX;
  387                 else if (bmsr & RL_GMEDIASTAT_10MBPS)
  388                         mii->mii_media_active |= IFM_10_T;
  389                 else
  390                         mii->mii_media_active |= IFM_NONE;
  391                 if (bmsr & RL_GMEDIASTAT_FDX)
  392                         mii->mii_media_active |= IFM_FDX;
  393                 else
  394                         mii->mii_media_active |= IFM_HDX;
  395         }
  396 
  397         if ((mii->mii_media_active & IFM_FDX) != 0)
  398                 mii->mii_media_active |= mii_phy_flowstatus(sc);
  399 
  400         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
  401             (PHY_READ(sc, RGEPHY_MII_1000STS) & RGEPHY_1000STS_MSR) != 0)
  402                 mii->mii_media_active |= IFM_ETH_MASTER;
  403 }
  404 
  405 static int
  406 rgephy_mii_phy_auto(struct mii_softc *sc, int media)
  407 {
  408         int anar;
  409 
  410         rgephy_loop(sc);
  411         rgephy_reset(sc);
  412 
  413         anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
  414         if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
  415                 anar |= RGEPHY_ANAR_PC | RGEPHY_ANAR_ASP;
  416         PHY_WRITE(sc, RGEPHY_MII_ANAR, anar);
  417         DELAY(1000);
  418         PHY_WRITE(sc, RGEPHY_MII_1000CTL,
  419             RGEPHY_1000CTL_AHD | RGEPHY_1000CTL_AFD);
  420         DELAY(1000);
  421         PHY_WRITE(sc, RGEPHY_MII_BMCR,
  422             RGEPHY_BMCR_AUTOEN | RGEPHY_BMCR_STARTNEG);
  423         DELAY(100);
  424 
  425         return (EJUSTRETURN);
  426 }
  427 
  428 static void
  429 rgephy_loop(struct mii_softc *sc)
  430 {
  431         struct rgephy_softc *rsc;
  432         int i;
  433 
  434         rsc = (struct rgephy_softc *)sc;
  435         if (rsc->mii_revision < 2) {
  436                 PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
  437                 DELAY(1000);
  438         }
  439 
  440         for (i = 0; i < 15000; i++) {
  441                 if (!(PHY_READ(sc, RGEPHY_MII_BMSR) & RGEPHY_BMSR_LINK)) {
  442 #if 0
  443                         device_printf(sc->mii_dev, "looped %d\n", i);
  444 #endif
  445                         break;
  446                 }
  447                 DELAY(10);
  448         }
  449 }
  450 
  451 #define PHY_SETBIT(x, y, z) \
  452         PHY_WRITE(x, y, (PHY_READ(x, y) | (z)))
  453 #define PHY_CLRBIT(x, y, z) \
  454         PHY_WRITE(x, y, (PHY_READ(x, y) & ~(z)))
  455 
  456 /*
  457  * Initialize RealTek PHY per the datasheet. The DSP in the PHYs of
  458  * existing revisions of the 8169S/8110S chips need to be tuned in
  459  * order to reliably negotiate a 1000Mbps link. This is only needed
  460  * for rev 0 and rev 1 of the PHY. Later versions work without
  461  * any fixups.
  462  */
  463 static void
  464 rgephy_load_dspcode(struct mii_softc *sc)
  465 {
  466         struct rgephy_softc *rsc;
  467         int val;
  468 
  469         rsc = (struct rgephy_softc *)sc;
  470         if (rsc->mii_revision >= 2)
  471                 return;
  472 
  473         PHY_WRITE(sc, 31, 0x0001);
  474         PHY_WRITE(sc, 21, 0x1000);
  475         PHY_WRITE(sc, 24, 0x65C7);
  476         PHY_CLRBIT(sc, 4, 0x0800);
  477         val = PHY_READ(sc, 4) & 0xFFF;
  478         PHY_WRITE(sc, 4, val);
  479         PHY_WRITE(sc, 3, 0x00A1);
  480         PHY_WRITE(sc, 2, 0x0008);
  481         PHY_WRITE(sc, 1, 0x1020);
  482         PHY_WRITE(sc, 0, 0x1000);
  483         PHY_SETBIT(sc, 4, 0x0800);
  484         PHY_CLRBIT(sc, 4, 0x0800);
  485         val = (PHY_READ(sc, 4) & 0xFFF) | 0x7000;
  486         PHY_WRITE(sc, 4, val);
  487         PHY_WRITE(sc, 3, 0xFF41);
  488         PHY_WRITE(sc, 2, 0xDE60);
  489         PHY_WRITE(sc, 1, 0x0140);
  490         PHY_WRITE(sc, 0, 0x0077);
  491         val = (PHY_READ(sc, 4) & 0xFFF) | 0xA000;
  492         PHY_WRITE(sc, 4, val);
  493         PHY_WRITE(sc, 3, 0xDF01);
  494         PHY_WRITE(sc, 2, 0xDF20);
  495         PHY_WRITE(sc, 1, 0xFF95);
  496         PHY_WRITE(sc, 0, 0xFA00);
  497         val = (PHY_READ(sc, 4) & 0xFFF) | 0xB000;
  498         PHY_WRITE(sc, 4, val);
  499         PHY_WRITE(sc, 3, 0xFF41);
  500         PHY_WRITE(sc, 2, 0xDE20);
  501         PHY_WRITE(sc, 1, 0x0140);
  502         PHY_WRITE(sc, 0, 0x00BB);
  503         val = (PHY_READ(sc, 4) & 0xFFF) | 0xF000;
  504         PHY_WRITE(sc, 4, val);
  505         PHY_WRITE(sc, 3, 0xDF01);
  506         PHY_WRITE(sc, 2, 0xDF20);
  507         PHY_WRITE(sc, 1, 0xFF95);
  508         PHY_WRITE(sc, 0, 0xBF00);
  509         PHY_SETBIT(sc, 4, 0x0800);
  510         PHY_CLRBIT(sc, 4, 0x0800);
  511         PHY_WRITE(sc, 31, 0x0000);
  512 
  513         DELAY(40);
  514 }
  515 
  516 static void
  517 rgephy_reset(struct mii_softc *sc)
  518 {
  519         struct rgephy_softc *rsc;
  520         uint16_t ssr;
  521 
  522         rsc = (struct rgephy_softc *)sc;
  523         if ((sc->mii_flags & MIIF_PHYPRIV0) == 0 && rsc->mii_revision == 3) {
  524                 /* RTL8211C(L) */
  525                 ssr = PHY_READ(sc, RGEPHY_MII_SSR);
  526                 if ((ssr & RGEPHY_SSR_ALDPS) != 0) {
  527                         ssr &= ~RGEPHY_SSR_ALDPS;
  528                         PHY_WRITE(sc, RGEPHY_MII_SSR, ssr);
  529                 }
  530         }
  531 
  532         mii_phy_reset(sc);
  533         DELAY(1000);
  534         rgephy_load_dspcode(sc);
  535 }

Cache object: 57d37f0a37d10224c4d2542163689c82


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