The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/rlswitch.c

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    1 /*-
    2  * Copyright (c) 1997, 1998, 1999
    3  *      Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
    4  * Copyright (c) 2006 Bernd Walter.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. All advertising materials mentioning features or use of this software
   15  *    must display the following acknowledgement:
   16  *      This product includes software developed by Bill Paul.
   17  * 4. Neither the name of the author nor the names of any co-contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   31  * THE POSSIBILITY OF SUCH DAMAGE.
   32  */
   33 
   34 #include <sys/cdefs.h>
   35 __FBSDID("$FreeBSD$");
   36 
   37 /*
   38  * driver for RealTek 8305 pseudo PHYs
   39  */
   40 
   41 #include <sys/param.h>
   42 #include <sys/systm.h>
   43 #include <sys/kernel.h>
   44 #include <sys/module.h>
   45 #include <sys/socket.h>
   46 #include <sys/bus.h>
   47 
   48 #include <net/if.h>
   49 #include <net/if_arp.h>
   50 #include <net/if_media.h>
   51 
   52 #include <dev/mii/mii.h>
   53 #include <dev/mii/miivar.h>
   54 #include "miidevs.h"
   55 
   56 #include <machine/bus.h>
   57 #include <pci/if_rlreg.h>
   58 
   59 #include "miibus_if.h"
   60 
   61 //#define RL_DEBUG
   62 #define RL_VLAN
   63 
   64 static int rlswitch_probe(device_t);
   65 static int rlswitch_attach(device_t);
   66 
   67 static device_method_t rlswitch_methods[] = {
   68         /* device interface */
   69         DEVMETHOD(device_probe,         rlswitch_probe),
   70         DEVMETHOD(device_attach,        rlswitch_attach),
   71         DEVMETHOD(device_detach,        mii_phy_detach),
   72         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
   73         { 0, 0 }
   74 };
   75 
   76 static devclass_t rlswitch_devclass;
   77 
   78 static driver_t rlswitch_driver = {
   79         "rlswitch",
   80         rlswitch_methods,
   81         sizeof(struct mii_softc)
   82 };
   83 
   84 DRIVER_MODULE(rlswitch, miibus, rlswitch_driver, rlswitch_devclass, 0, 0);
   85 
   86 static int      rlswitch_service(struct mii_softc *, struct mii_data *, int);
   87 static void     rlswitch_status(struct mii_softc *);
   88 
   89 #ifdef RL_DEBUG
   90 static void     rlswitch_phydump(device_t dev);
   91 #endif
   92 
   93 static const struct mii_phydesc rlswitches[] = {
   94         MII_PHY_DESC(xxREALTEK, RTL8305SC),
   95         MII_PHY_END
   96 };
   97 
   98 static int
   99 rlswitch_probe(device_t dev)
  100 {
  101         int rv;
  102 
  103         rv = mii_phy_dev_probe(dev, rlswitches, BUS_PROBE_DEFAULT);
  104         if (rv <= 0)
  105                 return (rv);
  106 
  107         return (ENXIO);
  108 }
  109 
  110 static int
  111 rlswitch_attach(device_t dev)
  112 {
  113         struct mii_softc        *sc;
  114         struct mii_attach_args  *ma;
  115         struct mii_data         *mii;
  116 
  117         sc = device_get_softc(dev);
  118         ma = device_get_ivars(dev);
  119         sc->mii_dev = device_get_parent(dev);
  120         mii = device_get_softc(sc->mii_dev);
  121 
  122         /*
  123          * We handle all pseudo PHY in a single instance, so never allow
  124          * non-zero * instances!
  125          */
  126         if (mii->mii_instance != 0) {
  127                 device_printf(dev, "ignoring this PHY, non-zero instance\n");
  128                 return (ENXIO);
  129         }
  130 
  131         LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
  132 
  133         sc->mii_inst = mii->mii_instance;
  134         sc->mii_phy = ma->mii_phyno;
  135         sc->mii_service = rlswitch_service;
  136         sc->mii_pdata = mii;
  137         mii->mii_instance++;
  138 
  139         sc->mii_flags |= MIIF_NOISOLATE;
  140 
  141 #define ADD(m, c)       ifmedia_add(&mii->mii_media, (m), (c), NULL)
  142 
  143 #if 0 /* See above. */
  144         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
  145             BMCR_ISO);
  146 #endif
  147 
  148 #if 0
  149         ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
  150             BMCR_LOOP|BMCR_S100);
  151 #endif
  152 
  153         sc->mii_capabilities = BMSR_100TXFDX & ma->mii_capmask;
  154         device_printf(dev, " ");
  155         mii_phy_add_media(sc);
  156         printf("\n");
  157 #undef ADD
  158 #ifdef RL_DEBUG
  159         rlswitch_phydump(dev);
  160 #endif
  161         
  162 #ifdef RL_VLAN
  163         int val;
  164 
  165         /* Global Control 0 */
  166         val = 0;
  167         val |= 0 << 10;         /* enable 802.1q VLAN Tag support */
  168         val |= 0 << 9;          /* enable VLAN ingress filtering */
  169         val |= 1 << 8;          /* disable VLAN tag admit control */
  170         val |= 1 << 6;          /* internal use */
  171         val |= 1 << 5;          /* internal use */
  172         val |= 1 << 4;          /* internal use */
  173         val |= 1 << 3;          /* internal use */
  174         val |= 1 << 1;          /* reserved */
  175         MIIBUS_WRITEREG(sc->mii_dev, 0, 16, val);
  176 
  177         /* Global Control 2 */
  178         val = 0;
  179         val |= 1 << 15;         /* reserved */
  180         val |= 0 << 14;         /* enable 1552 Bytes support */
  181         val |= 1 << 13;         /* enable broadcast input drop */
  182         val |= 1 << 12;         /* forward reserved control frames */
  183         val |= 1 << 11;         /* disable forwarding unicast frames to other VLAN's */
  184         val |= 1 << 10;         /* disable forwarding ARP broadcasts to other VLAN's */
  185         val |= 1 << 9;          /* enable 48 pass 1 */
  186         val |= 0 << 8;          /* enable VLAN */
  187         val |= 1 << 7;          /* reserved */
  188         val |= 1 << 6;          /* enable defer */
  189         val |= 1 << 5;          /* 43ms LED blink time */
  190         val |= 3 << 3;          /* 16:1 queue weight */
  191         val |= 1 << 2;          /* disable broadcast storm control */
  192         val |= 1 << 1;          /* enable power-on LED blinking */
  193         val |= 1 << 0;          /* reserved */
  194         MIIBUS_WRITEREG(sc->mii_dev, 0, 18, val);
  195 
  196         /* Port 0 Control Register 0 */
  197         val = 0;
  198         val |= 1 << 15;         /* reserved */
  199         val |= 1 << 11;         /* drop received packets with wrong VLAN tag */
  200         val |= 1 << 10;         /* disable 802.1p priority classification */
  201         val |= 1 << 9;          /* disable diffserv priority classification */
  202         val |= 1 << 6;          /* internal use */
  203         val |= 3 << 4;          /* internal use */
  204         val |= 1 << 3;          /* internal use */
  205         val |= 1 << 2;          /* internal use */
  206         val |= 1 << 0;          /* remove VLAN tags on output */
  207         MIIBUS_WRITEREG(sc->mii_dev, 0, 22, val);
  208 
  209         /* Port 1 Control Register 0 */
  210         val = 0;
  211         val |= 1 << 15;         /* reserved */
  212         val |= 1 << 11;         /* drop received packets with wrong VLAN tag */
  213         val |= 1 << 10;         /* disable 802.1p priority classification */
  214         val |= 1 << 9;          /* disable diffserv priority classification */
  215         val |= 1 << 6;          /* internal use */
  216         val |= 3 << 4;          /* internal use */
  217         val |= 1 << 3;          /* internal use */
  218         val |= 1 << 2;          /* internal use */
  219         val |= 1 << 0;          /* remove VLAN tags on output */
  220         MIIBUS_WRITEREG(sc->mii_dev, 1, 22, val);
  221 
  222         /* Port 2 Control Register 0 */
  223         val = 0;
  224         val |= 1 << 15;         /* reserved */
  225         val |= 1 << 11;         /* drop received packets with wrong VLAN tag */
  226         val |= 1 << 10;         /* disable 802.1p priority classification */
  227         val |= 1 << 9;          /* disable diffserv priority classification */
  228         val |= 1 << 6;          /* internal use */
  229         val |= 3 << 4;          /* internal use */
  230         val |= 1 << 3;          /* internal use */
  231         val |= 1 << 2;          /* internal use */
  232         val |= 1 << 0;          /* remove VLAN tags on output */
  233         MIIBUS_WRITEREG(sc->mii_dev, 2, 22, val);
  234 
  235         /* Port 3 Control Register 0 */
  236         val = 0;
  237         val |= 1 << 15;         /* reserved */
  238         val |= 1 << 11;         /* drop received packets with wrong VLAN tag */
  239         val |= 1 << 10;         /* disable 802.1p priority classification */
  240         val |= 1 << 9;          /* disable diffserv priority classification */
  241         val |= 1 << 6;          /* internal use */
  242         val |= 3 << 4;          /* internal use */
  243         val |= 1 << 3;          /* internal use */
  244         val |= 1 << 2;          /* internal use */
  245         val |= 1 << 0;          /* remove VLAN tags on output */
  246         MIIBUS_WRITEREG(sc->mii_dev, 3, 22, val);
  247 
  248         /* Port 4 (system port) Control Register 0 */
  249         val = 0;
  250         val |= 1 << 15;         /* reserved */
  251         val |= 0 << 11;         /* don't drop received packets with wrong VLAN tag */
  252         val |= 1 << 10;         /* disable 802.1p priority classification */
  253         val |= 1 << 9;          /* disable diffserv priority classification */
  254         val |= 1 << 6;          /* internal use */
  255         val |= 3 << 4;          /* internal use */
  256         val |= 1 << 3;          /* internal use */
  257         val |= 1 << 2;          /* internal use */
  258         val |= 2 << 0;          /* add VLAN tags for untagged packets on output */
  259         MIIBUS_WRITEREG(sc->mii_dev, 4, 22, val);
  260 
  261         /* Port 0 Control Register 1 and VLAN A */
  262         val = 0;
  263         val |= 0x0 << 12;       /* Port 0 VLAN Index */
  264         val |= 1 << 11;         /* internal use */
  265         val |= 1 << 10;         /* internal use */
  266         val |= 1 << 9;          /* internal use */
  267         val |= 1 << 7;          /* internal use */
  268         val |= 1 << 6;          /* internal use */
  269         val |= 0x11 << 0;       /* VLAN A membership */
  270         MIIBUS_WRITEREG(sc->mii_dev, 0, 24, val);
  271 
  272         /* Port 0 Control Register 2 and VLAN A */
  273         val = 0;
  274         val |= 1 << 15;         /* internal use */
  275         val |= 1 << 14;         /* internal use */
  276         val |= 1 << 13;         /* internal use */
  277         val |= 1 << 12;         /* internal use */
  278         val |= 0x100 << 0;      /* VLAN A ID */
  279         MIIBUS_WRITEREG(sc->mii_dev, 0, 25, val);
  280 
  281         /* Port 1 Control Register 1 and VLAN B */
  282         val = 0;
  283         val |= 0x1 << 12;       /* Port 1 VLAN Index */
  284         val |= 1 << 11;         /* internal use */
  285         val |= 1 << 10;         /* internal use */
  286         val |= 1 << 9;          /* internal use */
  287         val |= 1 << 7;          /* internal use */
  288         val |= 1 << 6;          /* internal use */
  289         val |= 0x12 << 0;       /* VLAN B membership */
  290         MIIBUS_WRITEREG(sc->mii_dev, 1, 24, val);
  291 
  292         /* Port 1 Control Register 2 and VLAN B */
  293         val = 0;
  294         val |= 1 << 15;         /* internal use */
  295         val |= 1 << 14;         /* internal use */
  296         val |= 1 << 13;         /* internal use */
  297         val |= 1 << 12;         /* internal use */
  298         val |= 0x101 << 0;      /* VLAN B ID */
  299         MIIBUS_WRITEREG(sc->mii_dev, 1, 25, val);
  300 
  301         /* Port 2 Control Register 1 and VLAN C */
  302         val = 0;
  303         val |= 0x2 << 12;       /* Port 2 VLAN Index */
  304         val |= 1 << 11;         /* internal use */
  305         val |= 1 << 10;         /* internal use */
  306         val |= 1 << 9;          /* internal use */
  307         val |= 1 << 7;          /* internal use */
  308         val |= 1 << 6;          /* internal use */
  309         val |= 0x14 << 0;       /* VLAN C membership */
  310         MIIBUS_WRITEREG(sc->mii_dev, 2, 24, val);
  311 
  312         /* Port 2 Control Register 2 and VLAN C */
  313         val = 0;
  314         val |= 1 << 15;         /* internal use */
  315         val |= 1 << 14;         /* internal use */
  316         val |= 1 << 13;         /* internal use */
  317         val |= 1 << 12;         /* internal use */
  318         val |= 0x102 << 0;      /* VLAN C ID */
  319         MIIBUS_WRITEREG(sc->mii_dev, 2, 25, val);
  320 
  321         /* Port 3 Control Register 1 and VLAN D */
  322         val = 0;
  323         val |= 0x3 << 12;       /* Port 3 VLAN Index */
  324         val |= 1 << 11;         /* internal use */
  325         val |= 1 << 10;         /* internal use */
  326         val |= 1 << 9;          /* internal use */
  327         val |= 1 << 7;          /* internal use */
  328         val |= 1 << 6;          /* internal use */
  329         val |= 0x18 << 0;       /* VLAN D membership */
  330         MIIBUS_WRITEREG(sc->mii_dev, 3, 24, val);
  331 
  332         /* Port 3 Control Register 2 and VLAN D */
  333         val = 0;
  334         val |= 1 << 15;         /* internal use */
  335         val |= 1 << 14;         /* internal use */
  336         val |= 1 << 13;         /* internal use */
  337         val |= 1 << 12;         /* internal use */
  338         val |= 0x103 << 0;      /* VLAN D ID */
  339         MIIBUS_WRITEREG(sc->mii_dev, 3, 25, val);
  340 
  341         /* Port 4 Control Register 1 and VLAN E */
  342         val = 0;
  343         val |= 0x0 << 12;       /* Port 4 VLAN Index */
  344         val |= 1 << 11;         /* internal use */
  345         val |= 1 << 10;         /* internal use */
  346         val |= 1 << 9;          /* internal use */
  347         val |= 1 << 7;          /* internal use */
  348         val |= 1 << 6;          /* internal use */
  349         val |= 0 << 0;          /* VLAN E membership */
  350         MIIBUS_WRITEREG(sc->mii_dev, 4, 24, val);
  351 
  352         /* Port 4 Control Register 2 and VLAN E */
  353         val = 0;
  354         val |= 1 << 15;         /* internal use */
  355         val |= 1 << 14;         /* internal use */
  356         val |= 1 << 13;         /* internal use */
  357         val |= 1 << 12;         /* internal use */
  358         val |= 0x104 << 0;      /* VLAN E ID */
  359         MIIBUS_WRITEREG(sc->mii_dev, 4, 25, val);
  360 #endif
  361 
  362 #ifdef RL_DEBUG
  363         rlswitch_phydump(dev);
  364 #endif
  365         MIIBUS_MEDIAINIT(sc->mii_dev);
  366         return (0);
  367 }
  368 
  369 static int
  370 rlswitch_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
  371 {
  372 
  373         switch (cmd) {
  374         case MII_POLLSTAT:
  375                 break;
  376 
  377         case MII_MEDIACHG:
  378                 break;
  379 
  380         case MII_TICK:
  381                 /*
  382                  * Is the interface even up?
  383                  */
  384                 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
  385                         return (0);
  386                 break;
  387         }
  388 
  389         /* Update the media status. */
  390         rlswitch_status(sc);
  391 
  392         /* Callback if something changed. */
  393         // mii_phy_update(sc, cmd);
  394         return (0);
  395 }
  396 
  397 static void
  398 rlswitch_status(struct mii_softc *phy)
  399 {
  400         struct mii_data *mii = phy->mii_pdata;
  401 
  402         mii->mii_media_status = IFM_AVALID;
  403         mii->mii_media_active = IFM_ETHER;
  404         mii->mii_media_status |= IFM_ACTIVE;
  405         mii->mii_media_active |= IFM_100_TX|IFM_FDX;
  406 }
  407 
  408 #ifdef RL_DEBUG
  409 static void
  410 rlswitch_phydump(device_t dev) {
  411         int phy, reg, val;
  412         struct mii_softc *sc;
  413 
  414         sc = device_get_softc(dev);
  415         device_printf(dev, "rlswitchphydump\n");
  416         for (phy = 0; phy <= 5; phy++) {
  417                 printf("PHY%i:", phy);
  418                 for (reg = 0; reg <= 31; reg++) {
  419                         val = MIIBUS_READREG(sc->mii_dev, phy, reg);
  420                         printf(" 0x%x", val);
  421                 }
  422                 printf("\n");
  423         }
  424 }
  425 #endif

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