FreeBSD/Linux Kernel Cross Reference
sys/dev/mii/smcphy.c
1 /*-
2 * Copyright (c) 2006 Benno Rice. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD: releng/8.4/sys/dev/mii/smcphy.c 230718 2012-01-29 01:35:14Z marius $");
27
28 /*
29 * Driver for the internal PHY on the SMSC LAN91C111.
30 */
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
35 #include <sys/socket.h>
36 #include <sys/errno.h>
37 #include <sys/module.h>
38 #include <sys/bus.h>
39 #include <sys/malloc.h>
40
41 #include <machine/bus.h>
42
43 #include <net/if.h>
44 #include <net/if_media.h>
45
46 #include <dev/mii/mii.h>
47 #include <dev/mii/miivar.h>
48 #include "miidevs.h"
49
50 #include "miibus_if.h"
51
52 static int smcphy_probe(device_t);
53 static int smcphy_attach(device_t);
54
55 static int smcphy_service(struct mii_softc *, struct mii_data *, int);
56 static void smcphy_reset(struct mii_softc *);
57 static void smcphy_auto(struct mii_softc *, int);
58
59 static device_method_t smcphy_methods[] = {
60 /* device interface */
61 DEVMETHOD(device_probe, smcphy_probe),
62 DEVMETHOD(device_attach, smcphy_attach),
63 DEVMETHOD(device_detach, mii_phy_detach),
64 DEVMETHOD(device_shutdown, bus_generic_shutdown),
65 DEVMETHOD_END
66 };
67
68 static devclass_t smcphy_devclass;
69
70 static driver_t smcphy_driver = {
71 "smcphy",
72 smcphy_methods,
73 sizeof(struct mii_softc)
74 };
75
76 DRIVER_MODULE(smcphy, miibus, smcphy_driver, smcphy_devclass, 0, 0);
77
78 static const struct mii_phydesc smcphys[] = {
79 MII_PHY_DESC(SMSC, LAN83C183),
80 MII_PHY_END
81 };
82
83 static int
84 smcphy_probe(device_t dev)
85 {
86
87 return (mii_phy_dev_probe(dev, smcphys, BUS_PROBE_DEFAULT));
88 }
89
90 static int
91 smcphy_attach(device_t dev)
92 {
93 struct mii_softc *sc;
94 struct mii_attach_args *ma;
95 struct mii_data *mii;
96
97 sc = device_get_softc(dev);
98 ma = device_get_ivars(dev);
99 sc->mii_dev = device_get_parent(dev);
100 mii = ma->mii_data;
101 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
102
103 sc->mii_flags = miibus_get_flags(dev);
104 sc->mii_inst = mii->mii_instance++;
105 sc->mii_phy = ma->mii_phyno;
106 sc->mii_service = smcphy_service;
107 sc->mii_pdata = mii;
108
109 sc->mii_flags |= MIIF_NOISOLATE | MIIF_NOLOOP | MIIF_NOMANPAUSE;
110
111 smcphy_reset(sc);
112
113 /* Mask interrupts, we poll instead. */
114 PHY_WRITE(sc, 0x1e, 0xffc0);
115
116 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
117 device_printf(dev, " ");
118 mii_phy_add_media(sc);
119 printf("\n");
120
121 MIIBUS_MEDIAINIT(sc->mii_dev);
122 mii_phy_setmedia(sc);
123
124 return (0);
125 }
126
127 static int
128 smcphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
129 {
130 struct ifmedia_entry *ife;
131 int reg;
132
133 ife = mii->mii_media.ifm_cur;
134
135 switch (cmd) {
136 case MII_POLLSTAT:
137 break;
138
139 case MII_MEDIACHG:
140 /*
141 * If the interface is not up, don't do anything.
142 */
143 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
144 break;
145
146 switch (IFM_SUBTYPE(ife->ifm_media)) {
147 case IFM_AUTO:
148 smcphy_auto(sc, ife->ifm_media);
149 break;
150
151 default:
152 mii_phy_setmedia(sc);
153 break;
154 }
155
156 break;
157
158 case MII_TICK:
159 if ((mii->mii_ifp->if_flags & IFF_UP) == 0) {
160 return (0);
161 }
162
163 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
164 break;
165 }
166
167 /* I have no idea why BMCR_ISO gets set. */
168 reg = PHY_READ(sc, MII_BMCR);
169 if (reg & BMCR_ISO) {
170 PHY_WRITE(sc, MII_BMCR, reg & ~BMCR_ISO);
171 }
172
173 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
174 if (reg & BMSR_LINK) {
175 sc->mii_ticks = 0;
176 break;
177 }
178
179 if (++sc->mii_ticks <= MII_ANEGTICKS) {
180 break;
181 }
182
183 sc->mii_ticks = 0;
184 smcphy_reset(sc);
185 smcphy_auto(sc, ife->ifm_media);
186 break;
187 }
188
189 /* Update the media status. */
190 ukphy_status(sc);
191
192 /* Callback if something changed. */
193 mii_phy_update(sc, cmd);
194 return (0);
195 }
196
197 static void
198 smcphy_reset(struct mii_softc *sc)
199 {
200 u_int bmcr;
201 int timeout;
202
203 PHY_WRITE(sc, MII_BMCR, BMCR_RESET);
204
205 for (timeout = 2; timeout > 0; timeout--) {
206 DELAY(50000);
207 bmcr = PHY_READ(sc, MII_BMCR);
208 if ((bmcr & BMCR_RESET) == 0)
209 break;
210 }
211
212 if (bmcr & BMCR_RESET)
213 device_printf(sc->mii_dev, "reset failed\n");
214
215 PHY_WRITE(sc, MII_BMCR, 0x3000);
216
217 /* Mask interrupts, we poll instead. */
218 PHY_WRITE(sc, 0x1e, 0xffc0);
219 }
220
221 static void
222 smcphy_auto(struct mii_softc *sc, int media)
223 {
224 uint16_t anar;
225
226 anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
227 if ((media & IFM_FLOW) != 0 || (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
228 anar |= ANAR_FC;
229 PHY_WRITE(sc, MII_ANAR, anar);
230 /* Apparently this helps. */
231 anar = PHY_READ(sc, MII_ANAR);
232 PHY_WRITE(sc, MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG);
233 }
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