ecc_e31200_reg.h

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    1 #ifndef _ECC_E31200_REG_H_
    2 #define _ECC_E31200_REG_H_
    3 
    4 #ifndef _SYS_BITOPS_H_
    5 #include <sys/bitops.h>
    6 #endif
    7 
    8 #define PCI_E31200_MCHBAR_LO            0x48
    9 #define PCI_E31200_MCHBAR_LO_EN         0x1
   10 #define PCI_E31200_MCHBAR_HI            0x4c
   11 
   12 #define PCI_E31200_ERRSTS               0xc8
   13 #define PCI_E31200_ERRSTS_DMERR         __BIT(1)
   14 #define PCI_E31200_ERRSTS_DSERR         __BIT(0)
   15 
   16 #define PCI_E31200_CAPID0_A             0xe4
   17 #define PCI_E31200_CAPID0_A_DMFC        __BITS(0, 2)    /* V1 */
   18 #define PCI_E31200_CAPID0_A_ECCDIS      __BIT(25)
   19 
   20 #define PCI_E31200_CAPID0_B             0xe8
   21 #define PCI_E31200_CAPID0_B_DMFC        __BITS(4, 6)    /* V2/V3 */
   22 
   23 #define PCI_E31200_CAPID0_DMFC_V1_ALL   0x0     /* V1 */
   24 #define PCI_E31200_CAPID0_DMFC_2933     0x0     /* V2/V3 */
   25 #define PCI_E31200_CAPID0_DMFC_2667     0x1     /* V2/V3 */
   26 #define PCI_E31200_CAPID0_DMFC_2400     0x2     /* V2/V3 */
   27 #define PCI_E31200_CAPID0_DMFC_2133     0x3     /* V2/V3 */
   28 #define PCI_E31200_CAPID0_DMFC_1867     0x4     /* V2/V3 */
   29 #define PCI_E31200_CAPID0_DMFC_1600     0x5     /* V2/V3 */
   30 #define PCI_E31200_CAPID0_DMFC_1333     0x6
   31 #define PCI_E31200_CAPID0_DMFC_1067     0x7
   32 
   33 #define PCI_E31200_MCHBAR_ADDRMASK      __BITS64(15, 38)
   34 
   35 #define MCH_E31200_SIZE                 (32 * 1024)
   36 
   37 #define MCH_E31200_ERRLOG0_C0           0x40c8
   38 #define MCH_E31200_ERRLOG1_C0           0x40cc
   39 
   40 #define MCH_E31200_ERRLOG0_C1           0x44c8
   41 #define MCH_E31200_ERRLOG1_C1           0x44cc
   42 
   43 #define MCH_E31200_ERRLOG0_CERRSTS      __BIT(0)
   44 #define MCH_E31200_ERRLOG0_MERRSTS      __BIT(1)
   45 #define MCH_E31200_ERRLOG0_ERRSYND      __BITS(16, 23)
   46 #define MCH_E31200_ERRLOG0_ERRCHUNK     __BITS(24, 26)
   47 #define MCH_E31200_ERRLOG0_ERRRANK      __BITS(27, 28)
   48 #define MCH_E31200_ERRLOG0_ERRBANK      __BITS(29, 31)
   49 
   50 #define MCH_E31200_ERRLOG1_ERRROW       __BITS(0, 15)
   51 #define MCH_E31200_ERRLOG1_ERRCOL       __BITS(16, 31)
   52 
   53 #define MCH_E31200_DIMM_CH0             0x5004
   54 #define MCH_E31200_DIMM_CH1             0x5008
   55 
   56 #define MCH_E31200_DIMM_SIZE_UNIT       256             /* MB */
   57 #define MCH_E31200_DIMM_A_SIZE          __BITS(0, 7)
   58 #define MCH_E31200_DIMM_B_SIZE          __BITS(8, 15)
   59 #define MCH_E31200_DIMM_A_DUAL_RANK     __BIT(17)
   60 #define MCH_E31200_DIMM_B_DUAL_RANK     __BIT(18)
   61 #define MCH_E31200_DIMM_A_X16           __BIT(19)
   62 #define MCH_E31200_DIMM_B_X16           __BIT(20)
   63 #define MCH_E31200_DIMM_RI              __BIT(21)       /* rank interleave */
   64 /* enchanced interleave */
   65 #define MCH_E31200_DIMM_ENHI            __BIT(22)
   66 #define MCH_E31200_DIMM_ECC             __BITS(24, 25)
   67 #define MCH_E31200_DIMM_ECC_NONE        0x0
   68 #define MCH_E31200_DIMM_ECC_IO          0x1
   69 #define MCH_E31200_DIMM_ECC_LOGIC       0x2
   70 #define MCH_E31200_DIMM_ECC_ALL         0x3
   71 /* high order rank interleave */
   72 #define MCH_E31200_DIMM_HORI            __BIT(26)       /* V3 */
   73 /* high order rank interleave address (addr bits [20,27]) */
   74 #define MCH_E31200_DIMM_HORIADDR        __BITS(27, 29)  /* V3 */
   75 
   76 #endif  /* !_ECC_E31200_REG_H_ */

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FreeBSD/Linux Kernel Cross Reference sys/dev/misc/ecc/ecc_e31200_reg.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/misc/ecc/ecc_e31200_reg.h