The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/misc/ecc/ecc_x3400.c

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    1 /*
    2  * Copyright (c) 2011 The DragonFly Project.  All rights reserved.
    3  *
    4  * This code is derived from software contributed to The DragonFly Project
    5  * by Sepherosa Ziehau <sepherosa@gmail.com>
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  *
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in
   15  *    the documentation and/or other materials provided with the
   16  *    distribution.
   17  * 3. Neither the name of The DragonFly Project nor the names of its
   18  *    contributors may be used to endorse or promote products derived
   19  *    from this software without specific, prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
   24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
   25  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
   26  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
   27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
   28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
   29  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   30  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
   31  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   32  * SUCH DAMAGE.
   33  */
   34 
   35 #include <sys/param.h>
   36 #include <sys/systm.h>
   37 #include <sys/bus.h>
   38 #include <sys/kernel.h>
   39 #include <sys/malloc.h>
   40 #include <sys/bitops.h>
   41 
   42 #include <bus/pci/pcivar.h>
   43 #include <bus/pci/pcireg.h>
   44 #include <bus/pci/pcibus.h>
   45 #include <bus/pci/pci_cfgreg.h>
   46 #include <bus/pci/pcib_private.h>
   47 
   48 #include <vm/pmap.h>
   49 
   50 #include "pcib_if.h"
   51 
   52 #include <dev/misc/ecc/ecc_x3400_reg.h>
   53 
   54 #define MC_READ_2(ofs) \
   55         pci_cfgregread(PCIBUS_X3400UC, PCISLOT_X3400UC_MC, \
   56             PCIFUNC_X3400UC_MC, (ofs), 2)
   57 #define MC_READ_4(ofs) \
   58         pci_cfgregread(PCIBUS_X3400UC, PCISLOT_X3400UC_MC, \
   59             PCIFUNC_X3400UC_MC, (ofs), 4)
   60 
   61 #define MCT2_READ_2(ofs) \
   62         pci_cfgregread(PCIBUS_X3400UC, PCISLOT_X3400UC_MCT2, \
   63             PCIFUNC_X3400UC_MCT2, (ofs), 2)
   64 #define MCT2_READ_4(ofs) \
   65         pci_cfgregread(PCIBUS_X3400UC, PCISLOT_X3400UC_MCT2, \
   66             PCIFUNC_X3400UC_MCT2, (ofs), 4)
   67 #define MCT2_WRITE_4(ofs, data) \
   68         pci_cfgregwrite(PCIBUS_X3400UC, PCISLOT_X3400UC_MCT2, \
   69             PCIFUNC_X3400UC_MCT2, (ofs), data, 4)
   70 
   71 struct ecc_x3400_memctrl {
   72         uint16_t        vid;
   73         uint16_t        did;
   74         const char      *desc;
   75 };
   76 
   77 struct ecc_x3400_softc {
   78         device_t        ecc_mydev;
   79         struct callout  ecc_callout;
   80         int             ecc_dimms;
   81 };
   82 
   83 #define ecc_printf(sc, fmt, arg...) \
   84         device_printf((sc)->ecc_mydev, fmt , ##arg)
   85 
   86 static int      ecc_x3400_probe(device_t);
   87 static int      ecc_x3400_attach(device_t);
   88 
   89 static void     ecc_x3400_status(struct ecc_x3400_softc *);
   90 static void     ecc_x3400_status_ch(struct ecc_x3400_softc *, int, int);
   91 static void     ecc_x3400_callout(void *);
   92 
   93 static const struct ecc_x3400_memctrl ecc_memctrls[] = {
   94         { 0x8086, 0xd130, "Intel X3400 memory controller" },
   95         { 0, 0, NULL } /* required last entry */
   96 };
   97 
   98 static device_method_t ecc_x3400_methods[] = {
   99         /* Device interface */
  100         DEVMETHOD(device_probe,         ecc_x3400_probe),
  101         DEVMETHOD(device_attach,        ecc_x3400_attach),
  102         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  103         DEVMETHOD(device_suspend,       bus_generic_suspend),
  104         DEVMETHOD(device_resume,        bus_generic_resume),
  105         DEVMETHOD_END
  106 };
  107 
  108 static driver_t ecc_x3400_driver = {
  109         "ecc",
  110         ecc_x3400_methods,
  111         sizeof(struct ecc_x3400_softc)
  112 };
  113 static devclass_t ecc_devclass;
  114 DRIVER_MODULE(ecc_x3400, hostb, ecc_x3400_driver, ecc_devclass, NULL, NULL);
  115 MODULE_DEPEND(ecc_x3400, pci, 1, 1, 1);
  116 
  117 static int
  118 ecc_x3400_probe(device_t dev)
  119 {
  120         const struct ecc_x3400_memctrl *mc;
  121         uint16_t vid, did;
  122 
  123         vid = pci_get_vendor(dev);
  124         did = pci_get_device(dev);
  125 
  126         for (mc = ecc_memctrls; mc->desc != NULL; ++mc) {
  127                 if (mc->vid == vid && mc->did == did) {
  128                         struct ecc_x3400_softc *sc = device_get_softc(dev);
  129 
  130                         if (MC_READ_2(PCIR_VENDOR) != PCI_X3400UC_MC_VID_ID ||
  131                             MC_READ_2(PCIR_DEVICE) != PCI_X3400UC_MC_DID_ID)
  132                                 return ENXIO;
  133                         if (MCT2_READ_2(PCIR_VENDOR) !=
  134                             PCI_X3400UC_MCT2_VID_ID ||
  135                             MCT2_READ_2(PCIR_DEVICE) !=
  136                             PCI_X3400UC_MCT2_DID_ID)
  137                                 return ENXIO;
  138 
  139                         device_set_desc(dev, mc->desc);
  140                         sc->ecc_mydev = dev;
  141                         return 0;
  142                 }
  143         }
  144         return ENXIO;
  145 }
  146 
  147 static int
  148 ecc_x3400_attach(device_t dev)
  149 {
  150         struct ecc_x3400_softc *sc = device_get_softc(dev);
  151         uint32_t val, dimms;
  152 
  153         val = MC_READ_4(PCI_X3400UC_MC_CTRL);
  154         if ((val & PCI_X3400UC_MC_CTRL_ECCEN) == 0) {
  155                 device_printf(dev, "ECC checking is not enabled\n");
  156                 return 0;
  157         }
  158 
  159         val = MC_READ_4(PCI_X3400UC_MC_STS);
  160         if ((val & PCI_X3400UC_MC_STS_ECCEN) == 0) {
  161                 device_printf(dev, "ECC is not enabled\n");
  162                 return 0;
  163         }
  164 
  165         val = MC_READ_4(PCI_X3400UC_MC_MAX_DOD);
  166         dimms = __SHIFTOUT(val, PCI_X3400UC_MC_MAX_DOD_DIMMS);
  167         sc->ecc_dimms = dimms + 1;
  168         device_printf(dev, "max dimms %d\n", sc->ecc_dimms);
  169 
  170         callout_init_mp(&sc->ecc_callout);
  171         callout_reset(&sc->ecc_callout, hz, ecc_x3400_callout, sc);
  172 
  173         return 0;
  174 }
  175 
  176 static void
  177 ecc_x3400_callout(void *xsc)
  178 {
  179         struct ecc_x3400_softc *sc = xsc;
  180 
  181         ecc_x3400_status(sc);
  182         callout_reset(&sc->ecc_callout, hz, ecc_x3400_callout, sc);
  183 }
  184 
  185 static void
  186 ecc_x3400_status(struct ecc_x3400_softc *sc)
  187 {
  188         ecc_x3400_status_ch(sc, PCI_X3400UC_MCT2_COR_ECC_CNT_0, 0);
  189         ecc_x3400_status_ch(sc, PCI_X3400UC_MCT2_COR_ECC_CNT_1, 1);
  190         ecc_x3400_status_ch(sc, PCI_X3400UC_MCT2_COR_ECC_CNT_2, 2);
  191         ecc_x3400_status_ch(sc, PCI_X3400UC_MCT2_COR_ECC_CNT_3, 3);
  192 }
  193 
  194 static void
  195 ecc_x3400_status_ch(struct ecc_x3400_softc *sc, int ofs, int idx)
  196 {
  197         uint32_t cor, err0, err1;
  198         const char *desc0 = NULL, *desc1 = NULL;
  199 
  200         cor = MCT2_READ_4(ofs);
  201         if (cor == 0)
  202                 return;
  203 
  204         if (sc->ecc_dimms > 2) {
  205                 switch (idx) {
  206                 case 0:
  207                         desc0 = "channel0, DIMM0";
  208                         desc1 = "channel0, DIMM1";
  209                         break;
  210 
  211                 case 1:
  212                         desc0 = "channel0, DIMM2";
  213                         break;
  214 
  215                 case 2:
  216                         desc0 = "channel1, DIMM0";
  217                         desc1 = "channel1, DIMM1";
  218                         break;
  219 
  220                 case 3:
  221                         desc0 = "channel1, DIMM2";
  222                         break;
  223 
  224                 default:
  225                         panic("unsupported index %d", idx);
  226                 }
  227         } else {
  228                 switch (idx) {
  229                 case 0:
  230                         desc0 = "channel0, DIMM0 RANK 0/1";
  231                         desc1 = "channel0, DIMM0 RANK 2/3";
  232                         break;
  233 
  234                 case 1:
  235                         desc0 = "channel0, DIMM1 RANK 0/1";
  236                         desc1 = "channel0, DIMM1 RANK 2/3";
  237                         break;
  238 
  239                 case 2:
  240                         desc0 = "channel1, DIMM0 RANK 0/1";
  241                         desc1 = "channel1, DIMM0 RANK 2/3";
  242                         break;
  243 
  244                 case 3:
  245                         desc0 = "channel1, DIMM1 RANK 0/1";
  246                         desc1 = "channel1, DIMM1 RANK 2/3";
  247                         break;
  248 
  249                 default:
  250                         panic("unsupported index %d", idx);
  251                 }
  252         }
  253 
  254         err0 = __SHIFTOUT(cor, PCI_X3400UC_MCT2_COR_DIMM0);
  255         if (cor & PCI_X3400UC_MCT2_COR_DIMM0_OV)
  256                 ecc_printf(sc, "%s has too many errors\n", desc0);
  257         else if (err0)
  258                 ecc_printf(sc, "%s has %d errors", desc0, err0);
  259 
  260         if (desc1 != NULL) {
  261                 err1 = __SHIFTOUT(cor, PCI_X3400UC_MCT2_COR_DIMM1);
  262                 if (cor & PCI_X3400UC_MCT2_COR_DIMM1_OV)
  263                         ecc_printf(sc, "%s has too many errors\n", desc1);
  264                 else if (err1)
  265                         ecc_printf(sc, "%s has %d errors\n", desc1, err1);
  266         }
  267 
  268         MCT2_WRITE_4(ofs, 0);
  269 }

Cache object: 443499fa8fe8da66826f208ae5b69d41


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