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sys/dev/mlx4/mlx4_core/mlx4_eq.c
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1 /* 2 * Copyright (c) 2005, 2006, 2007, 2008, 2014 Mellanox Technologies. All rights reserved. 3 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. 4 * 5 * This software is available to you under a choice of one of two 6 * licenses. You may choose to be licensed under the terms of the GNU 7 * General Public License (GPL) Version 2, available from the file 8 * COPYING in the main directory of this source tree, or the 9 * OpenIB.org BSD license below: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * - Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * - Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #include <linux/interrupt.h> 35 #include <linux/slab.h> 36 #include <linux/module.h> 37 #include <linux/mm.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/hardirq.h> 40 41 #include <dev/mlx4/cmd.h> 42 43 #include "mlx4.h" 44 #include "fw.h" 45 46 enum { 47 MLX4_IRQNAME_SIZE = 32 48 }; 49 50 enum { 51 MLX4_NUM_ASYNC_EQE = 0x100, 52 MLX4_NUM_SPARE_EQE = 0x80, 53 MLX4_EQ_ENTRY_SIZE = 0x20 54 }; 55 56 #define MLX4_EQ_STATUS_OK ( 0 << 28) 57 #define MLX4_EQ_STATUS_WRITE_FAIL (10 << 28) 58 #define MLX4_EQ_OWNER_SW ( 0 << 24) 59 #define MLX4_EQ_OWNER_HW ( 1 << 24) 60 #define MLX4_EQ_FLAG_EC ( 1 << 18) 61 #define MLX4_EQ_FLAG_OI ( 1 << 17) 62 #define MLX4_EQ_STATE_ARMED ( 9 << 8) 63 #define MLX4_EQ_STATE_FIRED (10 << 8) 64 #define MLX4_EQ_STATE_ALWAYS_ARMED (11 << 8) 65 66 #define MLX4_ASYNC_EVENT_MASK ((1ull << MLX4_EVENT_TYPE_PATH_MIG) | \ 67 (1ull << MLX4_EVENT_TYPE_COMM_EST) | \ 68 (1ull << MLX4_EVENT_TYPE_SQ_DRAINED) | \ 69 (1ull << MLX4_EVENT_TYPE_CQ_ERROR) | \ 70 (1ull << MLX4_EVENT_TYPE_WQ_CATAS_ERROR) | \ 71 (1ull << MLX4_EVENT_TYPE_EEC_CATAS_ERROR) | \ 72 (1ull << MLX4_EVENT_TYPE_PATH_MIG_FAILED) | \ 73 (1ull << MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 74 (1ull << MLX4_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 75 (1ull << MLX4_EVENT_TYPE_PORT_CHANGE) | \ 76 (1ull << MLX4_EVENT_TYPE_ECC_DETECT) | \ 77 (1ull << MLX4_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 78 (1ull << MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ 79 (1ull << MLX4_EVENT_TYPE_SRQ_LIMIT) | \ 80 (1ull << MLX4_EVENT_TYPE_CMD) | \ 81 (1ull << MLX4_EVENT_TYPE_OP_REQUIRED) | \ 82 (1ull << MLX4_EVENT_TYPE_COMM_CHANNEL) | \ 83 (1ull << MLX4_EVENT_TYPE_FLR_EVENT) | \ 84 (1ull << MLX4_EVENT_TYPE_FATAL_WARNING)) 85 86 static u64 get_async_ev_mask(struct mlx4_dev *dev) 87 { 88 u64 async_ev_mask = MLX4_ASYNC_EVENT_MASK; 89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) 90 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT); 91 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) 92 async_ev_mask |= (1ull << MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT); 93 94 return async_ev_mask; 95 } 96 97 static void eq_set_ci(struct mlx4_eq *eq, int req_not) 98 { 99 __raw_writel((__force u32) cpu_to_be32((eq->cons_index & 0xffffff) | 100 req_not << 31), 101 eq->doorbell); 102 /* We still want ordering, just not swabbing, so add a barrier */ 103 mb(); 104 } 105 106 static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor, 107 u8 eqe_size) 108 { 109 /* (entry & (eq->nent - 1)) gives us a cyclic array */ 110 unsigned long offset = (entry & (eq->nent - 1)) * eqe_size; 111 /* CX3 is capable of extending the EQE from 32 to 64 bytes with 112 * strides of 64B,128B and 256B. 113 * When 64B EQE is used, the first (in the lower addresses) 114 * 32 bytes in the 64 byte EQE are reserved and the next 32 bytes 115 * contain the legacy EQE information. 116 * In all other cases, the first 32B contains the legacy EQE info. 117 */ 118 return eq->page_list[offset / PAGE_SIZE].buf + (offset + (eqe_factor ? MLX4_EQ_ENTRY_SIZE : 0)) % PAGE_SIZE; 119 } 120 121 static struct mlx4_eqe *next_eqe_sw(struct mlx4_eq *eq, u8 eqe_factor, u8 size) 122 { 123 struct mlx4_eqe *eqe = get_eqe(eq, eq->cons_index, eqe_factor, size); 124 return !!(eqe->owner & 0x80) ^ !!(eq->cons_index & eq->nent) ? NULL : eqe; 125 } 126 127 static struct mlx4_eqe *next_slave_event_eqe(struct mlx4_slave_event_eq *slave_eq) 128 { 129 struct mlx4_eqe *eqe = 130 &slave_eq->event_eqe[slave_eq->cons & (SLAVE_EVENT_EQ_SIZE - 1)]; 131 return (!!(eqe->owner & 0x80) ^ 132 !!(slave_eq->cons & SLAVE_EVENT_EQ_SIZE)) ? 133 eqe : NULL; 134 } 135 136 void mlx4_gen_slave_eqe(struct work_struct *work) 137 { 138 struct mlx4_mfunc_master_ctx *master = 139 container_of(work, struct mlx4_mfunc_master_ctx, 140 slave_event_work); 141 struct mlx4_mfunc *mfunc = 142 container_of(master, struct mlx4_mfunc, master); 143 struct mlx4_priv *priv = container_of(mfunc, struct mlx4_priv, mfunc); 144 struct mlx4_dev *dev = &priv->dev; 145 struct mlx4_slave_event_eq *slave_eq = &mfunc->master.slave_eq; 146 struct mlx4_eqe *eqe; 147 u8 slave; 148 int i, phys_port, slave_port; 149 150 for (eqe = next_slave_event_eqe(slave_eq); eqe; 151 eqe = next_slave_event_eqe(slave_eq)) { 152 slave = eqe->slave_id; 153 154 if (eqe->type == MLX4_EVENT_TYPE_PORT_CHANGE && 155 eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN && 156 mlx4_is_bonded(dev)) { 157 struct mlx4_port_cap port_cap; 158 159 if (!mlx4_QUERY_PORT(dev, 1, &port_cap) && port_cap.link_state) 160 goto consume; 161 162 if (!mlx4_QUERY_PORT(dev, 2, &port_cap) && port_cap.link_state) 163 goto consume; 164 } 165 /* All active slaves need to receive the event */ 166 if (slave == ALL_SLAVES) { 167 for (i = 0; i <= dev->persist->num_vfs; i++) { 168 phys_port = 0; 169 if (eqe->type == MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT && 170 eqe->subtype == MLX4_DEV_PMC_SUBTYPE_PORT_INFO) { 171 phys_port = eqe->event.port_mgmt_change.port; 172 slave_port = mlx4_phys_to_slave_port(dev, i, phys_port); 173 if (slave_port < 0) /* VF doesn't have this port */ 174 continue; 175 eqe->event.port_mgmt_change.port = slave_port; 176 } 177 if (mlx4_GEN_EQE(dev, i, eqe)) 178 mlx4_warn(dev, "Failed to generate event for slave %d\n", 179 i); 180 if (phys_port) 181 eqe->event.port_mgmt_change.port = phys_port; 182 } 183 } else { 184 if (mlx4_GEN_EQE(dev, slave, eqe)) 185 mlx4_warn(dev, "Failed to generate event for slave %d\n", 186 slave); 187 } 188 consume: 189 ++slave_eq->cons; 190 } 191 } 192 193 194 static void slave_event(struct mlx4_dev *dev, u8 slave, struct mlx4_eqe *eqe) 195 { 196 struct mlx4_priv *priv = mlx4_priv(dev); 197 struct mlx4_slave_event_eq *slave_eq = &priv->mfunc.master.slave_eq; 198 struct mlx4_eqe *s_eqe; 199 unsigned long flags; 200 201 spin_lock_irqsave(&slave_eq->event_lock, flags); 202 s_eqe = &slave_eq->event_eqe[slave_eq->prod & (SLAVE_EVENT_EQ_SIZE - 1)]; 203 if ((!!(s_eqe->owner & 0x80)) ^ 204 (!!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE))) { 205 mlx4_warn(dev, "Master failed to generate an EQE for slave: %d. No free EQE on slave events queue\n", 206 slave); 207 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 208 return; 209 } 210 211 memcpy(s_eqe, eqe, sizeof(struct mlx4_eqe) - 1); 212 s_eqe->slave_id = slave; 213 /* ensure all information is written before setting the ownersip bit */ 214 wmb(); 215 s_eqe->owner = !!(slave_eq->prod & SLAVE_EVENT_EQ_SIZE) ? 0x0 : 0x80; 216 ++slave_eq->prod; 217 218 queue_work(priv->mfunc.master.comm_wq, 219 &priv->mfunc.master.slave_event_work); 220 spin_unlock_irqrestore(&slave_eq->event_lock, flags); 221 } 222 223 static void mlx4_slave_event(struct mlx4_dev *dev, int slave, 224 struct mlx4_eqe *eqe) 225 { 226 struct mlx4_priv *priv = mlx4_priv(dev); 227 228 if (slave < 0 || slave > dev->persist->num_vfs || 229 slave == dev->caps.function || 230 !priv->mfunc.master.slave_state[slave].active) 231 return; 232 233 slave_event(dev, slave, eqe); 234 } 235 236 static void mlx4_set_eq_affinity_hint(struct mlx4_priv *priv, int vec) 237 { 238 int hint_err; 239 struct mlx4_dev *dev = &priv->dev; 240 struct mlx4_eq *eq = &priv->eq_table.eq[vec]; 241 242 hint_err = bind_irq_to_cpu(eq->irq, eq->affinity_cpu_id); 243 244 if (hint_err) 245 mlx4_warn(dev, "bind_irq_to_cpu failed, err %d\n", hint_err); 246 } 247 248 int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port) 249 { 250 struct mlx4_eqe eqe; 251 252 struct mlx4_priv *priv = mlx4_priv(dev); 253 struct mlx4_slave_state *s_slave = &priv->mfunc.master.slave_state[slave]; 254 255 if (!s_slave->active) 256 return 0; 257 258 memset(&eqe, 0, sizeof eqe); 259 260 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 261 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE; 262 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port); 263 264 return mlx4_GEN_EQE(dev, slave, &eqe); 265 } 266 EXPORT_SYMBOL(mlx4_gen_pkey_eqe); 267 268 int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port) 269 { 270 struct mlx4_eqe eqe; 271 272 /*don't send if we don't have the that slave */ 273 if (dev->persist->num_vfs < slave) 274 return 0; 275 memset(&eqe, 0, sizeof eqe); 276 277 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 278 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_GUID_INFO; 279 eqe.event.port_mgmt_change.port = mlx4_phys_to_slave_port(dev, slave, port); 280 281 return mlx4_GEN_EQE(dev, slave, &eqe); 282 } 283 EXPORT_SYMBOL(mlx4_gen_guid_change_eqe); 284 285 int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, 286 u8 port_subtype_change) 287 { 288 struct mlx4_eqe eqe; 289 u8 slave_port = mlx4_phys_to_slave_port(dev, slave, port); 290 291 /*don't send if we don't have the that slave */ 292 if (dev->persist->num_vfs < slave) 293 return 0; 294 memset(&eqe, 0, sizeof eqe); 295 296 eqe.type = MLX4_EVENT_TYPE_PORT_CHANGE; 297 eqe.subtype = port_subtype_change; 298 eqe.event.port_change.port = cpu_to_be32(slave_port << 28); 299 300 mlx4_dbg(dev, "%s: sending: %d to slave: %d on port: %d\n", __func__, 301 port_subtype_change, slave, port); 302 return mlx4_GEN_EQE(dev, slave, &eqe); 303 } 304 EXPORT_SYMBOL(mlx4_gen_port_state_change_eqe); 305 306 enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port) 307 { 308 struct mlx4_priv *priv = mlx4_priv(dev); 309 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 310 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 311 312 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 313 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 314 pr_err("%s: Error: asking for slave:%d, port:%d\n", 315 __func__, slave, port); 316 return SLAVE_PORT_DOWN; 317 } 318 return s_state[slave].port_state[port]; 319 } 320 EXPORT_SYMBOL(mlx4_get_slave_port_state); 321 322 static int mlx4_set_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, 323 enum slave_port_state state) 324 { 325 struct mlx4_priv *priv = mlx4_priv(dev); 326 struct mlx4_slave_state *s_state = priv->mfunc.master.slave_state; 327 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 328 329 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 330 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 331 pr_err("%s: Error: asking for slave:%d, port:%d\n", 332 __func__, slave, port); 333 return -1; 334 } 335 s_state[slave].port_state[port] = state; 336 337 return 0; 338 } 339 340 static void set_all_slave_state(struct mlx4_dev *dev, u8 port, int event) 341 { 342 int i; 343 enum slave_port_gen_event gen_event; 344 struct mlx4_slaves_pport slaves_pport = mlx4_phys_to_slaves_pport(dev, 345 port); 346 347 for (i = 0; i < dev->persist->num_vfs + 1; i++) 348 if (test_bit(i, slaves_pport.slaves)) 349 set_and_calc_slave_port_state(dev, i, port, 350 event, &gen_event); 351 } 352 /************************************************************************** 353 The function get as input the new event to that port, 354 and according to the prev state change the slave's port state. 355 The events are: 356 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 357 MLX4_PORT_STATE_DEV_EVENT_PORT_UP 358 MLX4_PORT_STATE_IB_EVENT_GID_VALID 359 MLX4_PORT_STATE_IB_EVENT_GID_INVALID 360 ***************************************************************************/ 361 int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, 362 u8 port, int event, 363 enum slave_port_gen_event *gen_event) 364 { 365 struct mlx4_priv *priv = mlx4_priv(dev); 366 struct mlx4_slave_state *ctx = NULL; 367 unsigned long flags; 368 int ret = -1; 369 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave); 370 enum slave_port_state cur_state = 371 mlx4_get_slave_port_state(dev, slave, port); 372 373 *gen_event = SLAVE_PORT_GEN_EVENT_NONE; 374 375 if (slave >= dev->num_slaves || port > dev->caps.num_ports || 376 port <= 0 || !test_bit(port - 1, actv_ports.ports)) { 377 pr_err("%s: Error: asking for slave:%d, port:%d\n", 378 __func__, slave, port); 379 return ret; 380 } 381 382 ctx = &priv->mfunc.master.slave_state[slave]; 383 spin_lock_irqsave(&ctx->lock, flags); 384 385 switch (cur_state) { 386 case SLAVE_PORT_DOWN: 387 if (MLX4_PORT_STATE_DEV_EVENT_PORT_UP == event) 388 mlx4_set_slave_port_state(dev, slave, port, 389 SLAVE_PENDING_UP); 390 break; 391 case SLAVE_PENDING_UP: 392 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) 393 mlx4_set_slave_port_state(dev, slave, port, 394 SLAVE_PORT_DOWN); 395 else if (MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID == event) { 396 mlx4_set_slave_port_state(dev, slave, port, 397 SLAVE_PORT_UP); 398 *gen_event = SLAVE_PORT_GEN_EVENT_UP; 399 } 400 break; 401 case SLAVE_PORT_UP: 402 if (MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN == event) { 403 mlx4_set_slave_port_state(dev, slave, port, 404 SLAVE_PORT_DOWN); 405 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 406 } else if (MLX4_PORT_STATE_IB_EVENT_GID_INVALID == 407 event) { 408 mlx4_set_slave_port_state(dev, slave, port, 409 SLAVE_PENDING_UP); 410 *gen_event = SLAVE_PORT_GEN_EVENT_DOWN; 411 } 412 break; 413 default: 414 pr_err("%s: BUG!!! UNKNOWN state: slave:%d, port:%d\n", 415 __func__, slave, port); 416 goto out; 417 } 418 ret = mlx4_get_slave_port_state(dev, slave, port); 419 420 out: 421 spin_unlock_irqrestore(&ctx->lock, flags); 422 return ret; 423 } 424 425 EXPORT_SYMBOL(set_and_calc_slave_port_state); 426 427 int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr) 428 { 429 struct mlx4_eqe eqe; 430 431 memset(&eqe, 0, sizeof eqe); 432 433 eqe.type = MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT; 434 eqe.subtype = MLX4_DEV_PMC_SUBTYPE_PORT_INFO; 435 eqe.event.port_mgmt_change.port = port; 436 eqe.event.port_mgmt_change.params.port_info.changed_attr = 437 cpu_to_be32((u32) attr); 438 439 slave_event(dev, ALL_SLAVES, &eqe); 440 return 0; 441 } 442 EXPORT_SYMBOL(mlx4_gen_slaves_port_mgt_ev); 443 444 void mlx4_master_handle_slave_flr(struct work_struct *work) 445 { 446 struct mlx4_mfunc_master_ctx *master = 447 container_of(work, struct mlx4_mfunc_master_ctx, 448 slave_flr_event_work); 449 struct mlx4_mfunc *mfunc = 450 container_of(master, struct mlx4_mfunc, master); 451 struct mlx4_priv *priv = 452 container_of(mfunc, struct mlx4_priv, mfunc); 453 struct mlx4_dev *dev = &priv->dev; 454 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state; 455 int i; 456 int err; 457 unsigned long flags; 458 459 mlx4_dbg(dev, "mlx4_handle_slave_flr\n"); 460 461 for (i = 0 ; i < dev->num_slaves; i++) { 462 463 if (MLX4_COMM_CMD_FLR == slave_state[i].last_cmd) { 464 mlx4_dbg(dev, "mlx4_handle_slave_flr: clean slave: %d\n", 465 i); 466 /* In case of 'Reset flow' FLR can be generated for 467 * a slave before mlx4_load_one is done. 468 * make sure interface is up before trying to delete 469 * slave resources which weren't allocated yet. 470 */ 471 if (dev->persist->interface_state & 472 MLX4_INTERFACE_STATE_UP) 473 mlx4_delete_all_resources_for_slave(dev, i); 474 /*return the slave to running mode*/ 475 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 476 slave_state[i].last_cmd = MLX4_COMM_CMD_RESET; 477 slave_state[i].is_slave_going_down = 0; 478 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 479 /*notify the FW:*/ 480 err = mlx4_cmd(dev, 0, i, 0, MLX4_CMD_INFORM_FLR_DONE, 481 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 482 if (err) 483 mlx4_warn(dev, "Failed to notify FW on FLR done (slave:%d)\n", 484 i); 485 } 486 } 487 } 488 489 static int mlx4_eq_int(struct mlx4_dev *dev, struct mlx4_eq *eq) 490 { 491 struct mlx4_priv *priv = mlx4_priv(dev); 492 struct mlx4_eqe *eqe; 493 int cqn = -1; 494 int eqes_found = 0; 495 int set_ci = 0; 496 int port; 497 int slave = 0; 498 int ret; 499 u32 flr_slave; 500 u8 update_slave_state; 501 int i; 502 enum slave_port_gen_event gen_event; 503 unsigned long flags; 504 int eqe_size = dev->caps.eqe_size; 505 506 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) { 507 /* 508 * Make sure we read EQ entry contents after we've 509 * checked the ownership bit. 510 */ 511 rmb(); 512 513 switch (eqe->type) { 514 case MLX4_EVENT_TYPE_COMP: 515 cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff; 516 mlx4_cq_completion(dev, cqn); 517 break; 518 519 case MLX4_EVENT_TYPE_PATH_MIG: 520 case MLX4_EVENT_TYPE_COMM_EST: 521 case MLX4_EVENT_TYPE_SQ_DRAINED: 522 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE: 523 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR: 524 case MLX4_EVENT_TYPE_PATH_MIG_FAILED: 525 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 526 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR: 527 mlx4_dbg(dev, "event %d arrived\n", eqe->type); 528 if (mlx4_is_master(dev)) { 529 /* forward only to slave owning the QP */ 530 ret = mlx4_get_slave_from_resource_id(dev, 531 RES_QP, 532 be32_to_cpu(eqe->event.qp.qpn) 533 & 0xffffff, &slave); 534 if (ret && ret != -ENOENT) { 535 mlx4_dbg(dev, "QP event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 536 eqe->type, eqe->subtype, 537 eq->eqn, eq->cons_index, ret); 538 break; 539 } 540 541 if (!ret && slave != dev->caps.function) { 542 mlx4_slave_event(dev, slave, eqe); 543 break; 544 } 545 546 } 547 mlx4_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 548 0xffffff, eqe->type); 549 break; 550 551 case MLX4_EVENT_TYPE_SRQ_LIMIT: 552 mlx4_dbg(dev, "%s: MLX4_EVENT_TYPE_SRQ_LIMIT\n", 553 __func__); 554 case MLX4_EVENT_TYPE_SRQ_CATAS_ERROR: 555 if (mlx4_is_master(dev)) { 556 /* forward only to slave owning the SRQ */ 557 ret = mlx4_get_slave_from_resource_id(dev, 558 RES_SRQ, 559 be32_to_cpu(eqe->event.srq.srqn) 560 & 0xffffff, 561 &slave); 562 if (ret && ret != -ENOENT) { 563 mlx4_warn(dev, "SRQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 564 eqe->type, eqe->subtype, 565 eq->eqn, eq->cons_index, ret); 566 break; 567 } 568 mlx4_warn(dev, "%s: slave:%d, srq_no:0x%x, event: %02x(%02x)\n", 569 __func__, slave, 570 be32_to_cpu(eqe->event.srq.srqn), 571 eqe->type, eqe->subtype); 572 573 if (!ret && slave != dev->caps.function) { 574 mlx4_warn(dev, "%s: sending event %02x(%02x) to slave:%d\n", 575 __func__, eqe->type, 576 eqe->subtype, slave); 577 mlx4_slave_event(dev, slave, eqe); 578 break; 579 } 580 } 581 mlx4_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 582 0xffffff, eqe->type); 583 break; 584 585 case MLX4_EVENT_TYPE_CMD: 586 mlx4_cmd_event(dev, 587 be16_to_cpu(eqe->event.cmd.token), 588 eqe->event.cmd.status, 589 be64_to_cpu(eqe->event.cmd.out_param)); 590 break; 591 592 case MLX4_EVENT_TYPE_PORT_CHANGE: { 593 struct mlx4_slaves_pport slaves_port; 594 port = be32_to_cpu(eqe->event.port_change.port) >> 28; 595 slaves_port = mlx4_phys_to_slaves_pport(dev, port); 596 if (eqe->subtype == MLX4_PORT_CHANGE_SUBTYPE_DOWN) { 597 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_DOWN, 598 port); 599 mlx4_priv(dev)->sense.do_sense_port[port] = 1; 600 if (!mlx4_is_master(dev)) 601 break; 602 for (i = 0; i < dev->persist->num_vfs + 1; 603 i++) { 604 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port); 605 606 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev)) 607 continue; 608 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { 609 if (i == mlx4_master_func_num(dev)) 610 continue; 611 mlx4_dbg(dev, "%s: Sending MLX4_PORT_CHANGE_SUBTYPE_DOWN to slave: %d, port:%d\n", 612 __func__, i, port); 613 if (0 /*IFLA_VF_LINK_STATE_AUTO == s_info->link_state*/) { 614 eqe->event.port_change.port = 615 cpu_to_be32( 616 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 617 | (reported_port << 28)); 618 mlx4_slave_event(dev, i, eqe); 619 } 620 } else { /* IB port */ 621 set_and_calc_slave_port_state(dev, i, port, 622 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, 623 &gen_event); 624 /*we can be in pending state, then do not send port_down event*/ 625 if (SLAVE_PORT_GEN_EVENT_DOWN == gen_event) { 626 if (i == mlx4_master_func_num(dev)) 627 continue; 628 eqe->event.port_change.port = 629 cpu_to_be32( 630 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 631 | (mlx4_phys_to_slave_port(dev, i, port) << 28)); 632 mlx4_slave_event(dev, i, eqe); 633 } 634 } 635 } 636 } else { 637 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_UP, port); 638 639 mlx4_priv(dev)->sense.do_sense_port[port] = 0; 640 641 if (!mlx4_is_master(dev)) 642 break; 643 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) 644 for (i = 0; 645 i < dev->persist->num_vfs + 1; 646 i++) { 647 int reported_port = mlx4_is_bonded(dev) ? 1 : mlx4_phys_to_slave_port(dev, i, port); 648 649 if (!test_bit(i, slaves_port.slaves) && !mlx4_is_bonded(dev)) 650 continue; 651 if (i == mlx4_master_func_num(dev)) 652 continue; 653 if (0 /*IFLA_VF_LINK_STATE_AUTO == s_info->link_state*/) { 654 eqe->event.port_change.port = 655 cpu_to_be32( 656 (be32_to_cpu(eqe->event.port_change.port) & 0xFFFFFFF) 657 | (reported_port << 28)); 658 mlx4_slave_event(dev, i, eqe); 659 } 660 } 661 else /* IB port */ 662 /* port-up event will be sent to a slave when the 663 * slave's alias-guid is set. This is done in alias_GUID.c 664 */ 665 set_all_slave_state(dev, port, MLX4_DEV_EVENT_PORT_UP); 666 } 667 break; 668 } 669 670 case MLX4_EVENT_TYPE_CQ_ERROR: 671 mlx4_warn(dev, "CQ %s on CQN %06x\n", 672 eqe->event.cq_err.syndrome == 1 ? 673 "overrun" : "access violation", 674 be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff); 675 if (mlx4_is_master(dev)) { 676 ret = mlx4_get_slave_from_resource_id(dev, 677 RES_CQ, 678 be32_to_cpu(eqe->event.cq_err.cqn) 679 & 0xffffff, &slave); 680 if (ret && ret != -ENOENT) { 681 mlx4_dbg(dev, "CQ event %02x(%02x) on EQ %d at index %u: could not get slave id (%d)\n", 682 eqe->type, eqe->subtype, 683 eq->eqn, eq->cons_index, ret); 684 break; 685 } 686 687 if (!ret && slave != dev->caps.function) { 688 mlx4_slave_event(dev, slave, eqe); 689 break; 690 } 691 } 692 mlx4_cq_event(dev, 693 be32_to_cpu(eqe->event.cq_err.cqn) 694 & 0xffffff, 695 eqe->type); 696 break; 697 698 case MLX4_EVENT_TYPE_EQ_OVERFLOW: 699 mlx4_warn(dev, "EQ overrun on EQN %d\n", eq->eqn); 700 break; 701 702 case MLX4_EVENT_TYPE_OP_REQUIRED: 703 atomic_inc(&priv->opreq_count); 704 /* FW commands can't be executed from interrupt context 705 * working in deferred task 706 */ 707 queue_work(mlx4_wq, &priv->opreq_task); 708 break; 709 710 case MLX4_EVENT_TYPE_COMM_CHANNEL: 711 if (!mlx4_is_master(dev)) { 712 mlx4_warn(dev, "Received comm channel event for non master device\n"); 713 break; 714 } 715 memcpy(&priv->mfunc.master.comm_arm_bit_vector, 716 eqe->event.comm_channel_arm.bit_vec, 717 sizeof eqe->event.comm_channel_arm.bit_vec); 718 queue_work(priv->mfunc.master.comm_wq, 719 &priv->mfunc.master.comm_work); 720 break; 721 722 case MLX4_EVENT_TYPE_FLR_EVENT: 723 flr_slave = be32_to_cpu(eqe->event.flr_event.slave_id); 724 if (!mlx4_is_master(dev)) { 725 mlx4_warn(dev, "Non-master function received FLR event\n"); 726 break; 727 } 728 729 mlx4_dbg(dev, "FLR event for slave: %d\n", flr_slave); 730 731 if (flr_slave >= dev->num_slaves) { 732 mlx4_warn(dev, 733 "Got FLR for unknown function: %d\n", 734 flr_slave); 735 update_slave_state = 0; 736 } else 737 update_slave_state = 1; 738 739 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags); 740 if (update_slave_state) { 741 priv->mfunc.master.slave_state[flr_slave].active = false; 742 priv->mfunc.master.slave_state[flr_slave].last_cmd = MLX4_COMM_CMD_FLR; 743 priv->mfunc.master.slave_state[flr_slave].is_slave_going_down = 1; 744 } 745 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags); 746 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, 747 flr_slave); 748 queue_work(priv->mfunc.master.comm_wq, 749 &priv->mfunc.master.slave_flr_event_work); 750 break; 751 752 case MLX4_EVENT_TYPE_FATAL_WARNING: 753 if (eqe->subtype == MLX4_FATAL_WARNING_SUBTYPE_WARMING) { 754 if (mlx4_is_master(dev)) 755 for (i = 0; i < dev->num_slaves; i++) { 756 mlx4_dbg(dev, "%s: Sending MLX4_FATAL_WARNING_SUBTYPE_WARMING to slave: %d\n", 757 __func__, i); 758 if (i == dev->caps.function) 759 continue; 760 mlx4_slave_event(dev, i, eqe); 761 } 762 mlx4_err(dev, "Temperature Threshold was reached! Threshold: %d celsius degrees; Current Temperature: %d\n", 763 be16_to_cpu(eqe->event.warming.warning_threshold), 764 be16_to_cpu(eqe->event.warming.current_temperature)); 765 } else 766 mlx4_warn(dev, "Unhandled event FATAL WARNING (%02x), subtype %02x on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 767 eqe->type, eqe->subtype, eq->eqn, 768 eq->cons_index, eqe->owner, eq->nent, 769 eqe->slave_id, 770 !!(eqe->owner & 0x80) ^ 771 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 772 773 break; 774 775 case MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT: 776 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_PORT_MGMT_CHANGE, 777 (unsigned long) eqe); 778 break; 779 780 case MLX4_EVENT_TYPE_RECOVERABLE_ERROR_EVENT: 781 switch (eqe->subtype) { 782 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_BAD_CABLE: 783 mlx4_warn(dev, "Bad cable detected on port %u\n", 784 eqe->event.bad_cable.port); 785 break; 786 case MLX4_RECOVERABLE_ERROR_EVENT_SUBTYPE_UNSUPPORTED_CABLE: 787 mlx4_warn(dev, "Unsupported cable detected\n"); 788 break; 789 default: 790 mlx4_dbg(dev, 791 "Unhandled recoverable error event detected: %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, ownership=%s\n", 792 eqe->type, eqe->subtype, eq->eqn, 793 eq->cons_index, eqe->owner, eq->nent, 794 !!(eqe->owner & 0x80) ^ 795 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 796 break; 797 } 798 break; 799 800 case MLX4_EVENT_TYPE_EEC_CATAS_ERROR: 801 case MLX4_EVENT_TYPE_ECC_DETECT: 802 default: 803 mlx4_warn(dev, "Unhandled event %02x(%02x) on EQ %d at index %u. owner=%x, nent=0x%x, slave=%x, ownership=%s\n", 804 eqe->type, eqe->subtype, eq->eqn, 805 eq->cons_index, eqe->owner, eq->nent, 806 eqe->slave_id, 807 !!(eqe->owner & 0x80) ^ 808 !!(eq->cons_index & eq->nent) ? "HW" : "SW"); 809 break; 810 } 811 812 ++eq->cons_index; 813 eqes_found = 1; 814 ++set_ci; 815 816 /* 817 * The HCA will think the queue has overflowed if we 818 * don't tell it we've been processing events. We 819 * create our EQs with MLX4_NUM_SPARE_EQE extra 820 * entries, so we must update our consumer index at 821 * least that often. 822 */ 823 if (unlikely(set_ci >= MLX4_NUM_SPARE_EQE)) { 824 eq_set_ci(eq, 0); 825 set_ci = 0; 826 } 827 } 828 829 eq_set_ci(eq, 1); 830 831 return eqes_found; 832 } 833 834 static irqreturn_t mlx4_interrupt(int irq, void *dev_ptr) 835 { 836 struct mlx4_dev *dev = dev_ptr; 837 struct mlx4_priv *priv = mlx4_priv(dev); 838 int work = 0; 839 int i; 840 841 writel(priv->eq_table.clr_mask, priv->eq_table.clr_int); 842 843 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 844 work |= mlx4_eq_int(dev, &priv->eq_table.eq[i]); 845 846 return IRQ_RETVAL(work); 847 } 848 849 static irqreturn_t mlx4_msi_x_interrupt(int irq, void *eq_ptr) 850 { 851 struct mlx4_eq *eq = eq_ptr; 852 struct mlx4_dev *dev = eq->dev; 853 854 mlx4_eq_int(dev, eq); 855 856 /* MSI-X vectors always belong to us */ 857 return IRQ_HANDLED; 858 } 859 860 int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, 861 struct mlx4_vhcr *vhcr, 862 struct mlx4_cmd_mailbox *inbox, 863 struct mlx4_cmd_mailbox *outbox, 864 struct mlx4_cmd_info *cmd) 865 { 866 struct mlx4_priv *priv = mlx4_priv(dev); 867 struct mlx4_slave_event_eq_info *event_eq = 868 priv->mfunc.master.slave_state[slave].event_eq; 869 u32 in_modifier = vhcr->in_modifier; 870 u32 eqn = in_modifier & 0x3FF; 871 u64 in_param = vhcr->in_param; 872 int err = 0; 873 int i; 874 875 if (slave == dev->caps.function) 876 err = mlx4_cmd(dev, in_param, (in_modifier & 0x80000000) | eqn, 877 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 878 MLX4_CMD_NATIVE); 879 if (!err) 880 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) 881 if (in_param & (1LL << i)) 882 event_eq[i].eqn = in_modifier >> 31 ? -1 : eqn; 883 884 return err; 885 } 886 887 static int mlx4_MAP_EQ(struct mlx4_dev *dev, u64 event_mask, int unmap, 888 int eq_num) 889 { 890 return mlx4_cmd(dev, event_mask, (unmap << 31) | eq_num, 891 0, MLX4_CMD_MAP_EQ, MLX4_CMD_TIME_CLASS_B, 892 MLX4_CMD_WRAPPED); 893 } 894 895 static int mlx4_SW2HW_EQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, 896 int eq_num) 897 { 898 return mlx4_cmd(dev, mailbox->dma, eq_num, 0, 899 MLX4_CMD_SW2HW_EQ, MLX4_CMD_TIME_CLASS_A, 900 MLX4_CMD_WRAPPED); 901 } 902 903 static int mlx4_HW2SW_EQ(struct mlx4_dev *dev, int eq_num) 904 { 905 return mlx4_cmd(dev, 0, eq_num, 1, MLX4_CMD_HW2SW_EQ, 906 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); 907 } 908 909 static int mlx4_num_eq_uar(struct mlx4_dev *dev) 910 { 911 /* 912 * Each UAR holds 4 EQ doorbells. To figure out how many UARs 913 * we need to map, take the difference of highest index and 914 * the lowest index we'll use and add 1. 915 */ 916 return (dev->caps.num_comp_vectors + 1 + dev->caps.reserved_eqs) / 4 - 917 dev->caps.reserved_eqs / 4 + 1; 918 } 919 920 static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq) 921 { 922 struct mlx4_priv *priv = mlx4_priv(dev); 923 int index; 924 925 index = eq->eqn / 4 - dev->caps.reserved_eqs / 4; 926 927 if (!priv->eq_table.uar_map[index]) { 928 priv->eq_table.uar_map[index] = 929 ioremap(pci_resource_start(dev->persist->pdev, 2) + 930 ((eq->eqn / 4) << (dev->uar_page_shift)), 931 (1 << (dev->uar_page_shift))); 932 if (!priv->eq_table.uar_map[index]) { 933 mlx4_err(dev, "Couldn't map EQ doorbell for EQN 0x%06x\n", 934 eq->eqn); 935 return NULL; 936 } 937 } 938 939 return priv->eq_table.uar_map[index] + 0x800 + 8 * (eq->eqn % 4); 940 } 941 942 static void mlx4_unmap_uar(struct mlx4_dev *dev) 943 { 944 struct mlx4_priv *priv = mlx4_priv(dev); 945 int i; 946 947 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 948 if (priv->eq_table.uar_map[i]) { 949 iounmap(priv->eq_table.uar_map[i]); 950 priv->eq_table.uar_map[i] = NULL; 951 } 952 } 953 954 static int mlx4_create_eq(struct mlx4_dev *dev, int nent, 955 u8 intr, struct mlx4_eq *eq) 956 { 957 struct mlx4_priv *priv = mlx4_priv(dev); 958 struct mlx4_cmd_mailbox *mailbox; 959 struct mlx4_eq_context *eq_context; 960 int npages; 961 u64 *dma_list = NULL; 962 dma_addr_t t; 963 u64 mtt_addr; 964 int err = -ENOMEM; 965 int i; 966 967 eq->dev = dev; 968 eq->nent = roundup_pow_of_two(max(nent, 2)); 969 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with 970 * strides of 64B,128B and 256B. 971 */ 972 npages = PAGE_ALIGN(eq->nent * dev->caps.eqe_size) / PAGE_SIZE; 973 974 eq->page_list = kmalloc(npages * sizeof *eq->page_list, 975 GFP_KERNEL); 976 if (!eq->page_list) 977 goto err_out; 978 979 for (i = 0; i < npages; ++i) 980 eq->page_list[i].buf = NULL; 981 982 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL); 983 if (!dma_list) 984 goto err_out_free; 985 986 mailbox = mlx4_alloc_cmd_mailbox(dev); 987 if (IS_ERR(mailbox)) 988 goto err_out_free; 989 eq_context = mailbox->buf; 990 991 for (i = 0; i < npages; ++i) { 992 eq->page_list[i].buf = dma_alloc_coherent(&dev->persist-> 993 pdev->dev, 994 PAGE_SIZE, &t, 995 GFP_KERNEL); 996 if (!eq->page_list[i].buf) 997 goto err_out_free_pages; 998 999 dma_list[i] = t; 1000 eq->page_list[i].map = t; 1001 1002 memset(eq->page_list[i].buf, 0, PAGE_SIZE); 1003 } 1004 1005 eq->eqn = mlx4_bitmap_alloc(&priv->eq_table.bitmap); 1006 if (eq->eqn == -1) 1007 goto err_out_free_pages; 1008 1009 eq->doorbell = mlx4_get_eq_uar(dev, eq); 1010 if (!eq->doorbell) { 1011 err = -ENOMEM; 1012 goto err_out_free_eq; 1013 } 1014 1015 err = mlx4_mtt_init(dev, npages, PAGE_SHIFT, &eq->mtt); 1016 if (err) 1017 goto err_out_free_eq; 1018 1019 err = mlx4_write_mtt(dev, &eq->mtt, 0, npages, dma_list); 1020 if (err) 1021 goto err_out_free_mtt; 1022 1023 eq_context->flags = cpu_to_be32(MLX4_EQ_STATUS_OK | 1024 MLX4_EQ_STATE_ARMED); 1025 eq_context->log_eq_size = ilog2(eq->nent); 1026 eq_context->intr = intr; 1027 eq_context->log_page_size = PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT; 1028 1029 mtt_addr = mlx4_mtt_addr(dev, &eq->mtt); 1030 eq_context->mtt_base_addr_h = mtt_addr >> 32; 1031 eq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff); 1032 1033 err = mlx4_SW2HW_EQ(dev, mailbox, eq->eqn); 1034 if (err) { 1035 mlx4_warn(dev, "SW2HW_EQ failed (%d)\n", err); 1036 goto err_out_free_mtt; 1037 } 1038 1039 kfree(dma_list); 1040 mlx4_free_cmd_mailbox(dev, mailbox); 1041 1042 eq->cons_index = 0; 1043 1044 return err; 1045 1046 err_out_free_mtt: 1047 mlx4_mtt_cleanup(dev, &eq->mtt); 1048 1049 err_out_free_eq: 1050 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1051 1052 err_out_free_pages: 1053 for (i = 0; i < npages; ++i) 1054 if (eq->page_list[i].buf) 1055 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, 1056 eq->page_list[i].buf, 1057 eq->page_list[i].map); 1058 1059 mlx4_free_cmd_mailbox(dev, mailbox); 1060 1061 err_out_free: 1062 kfree(eq->page_list); 1063 kfree(dma_list); 1064 1065 err_out: 1066 return err; 1067 } 1068 1069 static void mlx4_free_eq(struct mlx4_dev *dev, 1070 struct mlx4_eq *eq) 1071 { 1072 struct mlx4_priv *priv = mlx4_priv(dev); 1073 int err; 1074 int i; 1075 /* CX3 is capable of extending the CQE/EQE from 32 to 64 bytes, with 1076 * strides of 64B,128B and 256B 1077 */ 1078 int npages = PAGE_ALIGN(dev->caps.eqe_size * eq->nent) / PAGE_SIZE; 1079 1080 err = mlx4_HW2SW_EQ(dev, eq->eqn); 1081 if (err) 1082 mlx4_warn(dev, "HW2SW_EQ failed (%d)\n", err); 1083 1084 synchronize_irq(eq->irq); 1085 1086 mlx4_mtt_cleanup(dev, &eq->mtt); 1087 for (i = 0; i < npages; ++i) 1088 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE, 1089 eq->page_list[i].buf, 1090 eq->page_list[i].map); 1091 1092 kfree(eq->page_list); 1093 mlx4_bitmap_free(&priv->eq_table.bitmap, eq->eqn, MLX4_USE_RR); 1094 } 1095 1096 static void mlx4_free_irqs(struct mlx4_dev *dev) 1097 { 1098 struct mlx4_eq_table *eq_table = &mlx4_priv(dev)->eq_table; 1099 int i; 1100 1101 if (eq_table->have_irq) 1102 free_irq(dev->persist->pdev->irq, dev); 1103 1104 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1105 if (eq_table->eq[i].have_irq) { 1106 eq_table->eq[i].affinity_cpu_id = NOCPU; 1107 free_irq(eq_table->eq[i].irq, eq_table->eq + i); 1108 eq_table->eq[i].have_irq = 0; 1109 } 1110 1111 kfree(eq_table->irq_names); 1112 } 1113 1114 static int mlx4_map_clr_int(struct mlx4_dev *dev) 1115 { 1116 struct mlx4_priv *priv = mlx4_priv(dev); 1117 1118 priv->clr_base = ioremap(pci_resource_start(dev->persist->pdev, 1119 priv->fw.clr_int_bar) + 1120 priv->fw.clr_int_base, MLX4_CLR_INT_SIZE); 1121 if (!priv->clr_base) { 1122 mlx4_err(dev, "Couldn't map interrupt clear register, aborting\n"); 1123 return -ENOMEM; 1124 } 1125 1126 return 0; 1127 } 1128 1129 static void mlx4_unmap_clr_int(struct mlx4_dev *dev) 1130 { 1131 struct mlx4_priv *priv = mlx4_priv(dev); 1132 1133 iounmap(priv->clr_base); 1134 } 1135 1136 int mlx4_alloc_eq_table(struct mlx4_dev *dev) 1137 { 1138 struct mlx4_priv *priv = mlx4_priv(dev); 1139 1140 priv->eq_table.eq = kcalloc(dev->caps.num_eqs - dev->caps.reserved_eqs, 1141 sizeof *priv->eq_table.eq, GFP_KERNEL); 1142 if (!priv->eq_table.eq) 1143 return -ENOMEM; 1144 1145 return 0; 1146 } 1147 1148 void mlx4_free_eq_table(struct mlx4_dev *dev) 1149 { 1150 kfree(mlx4_priv(dev)->eq_table.eq); 1151 } 1152 1153 int mlx4_init_eq_table(struct mlx4_dev *dev) 1154 { 1155 struct mlx4_priv *priv = mlx4_priv(dev); 1156 int err; 1157 int i; 1158 1159 priv->eq_table.uar_map = kcalloc(mlx4_num_eq_uar(dev), 1160 sizeof *priv->eq_table.uar_map, 1161 GFP_KERNEL); 1162 if (!priv->eq_table.uar_map) { 1163 err = -ENOMEM; 1164 goto err_out_free; 1165 } 1166 1167 err = mlx4_bitmap_init(&priv->eq_table.bitmap, 1168 roundup_pow_of_two(dev->caps.num_eqs), 1169 dev->caps.num_eqs - 1, 1170 dev->caps.reserved_eqs, 1171 roundup_pow_of_two(dev->caps.num_eqs) - 1172 dev->caps.num_eqs); 1173 if (err) 1174 goto err_out_free; 1175 1176 for (i = 0; i < mlx4_num_eq_uar(dev); ++i) 1177 priv->eq_table.uar_map[i] = NULL; 1178 1179 if (!mlx4_is_slave(dev)) { 1180 err = mlx4_map_clr_int(dev); 1181 if (err) 1182 goto err_out_bitmap; 1183 1184 priv->eq_table.clr_mask = 1185 swab32(1 << (priv->eq_table.inta_pin & 31)); 1186 priv->eq_table.clr_int = priv->clr_base + 1187 (priv->eq_table.inta_pin < 32 ? 4 : 0); 1188 } 1189 1190 priv->eq_table.irq_names = 1191 kmalloc(MLX4_IRQNAME_SIZE * (dev->caps.num_comp_vectors + 1), 1192 GFP_KERNEL); 1193 if (!priv->eq_table.irq_names) { 1194 err = -ENOMEM; 1195 goto err_out_clr_int; 1196 } 1197 1198 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) { 1199 if (i == MLX4_EQ_ASYNC) { 1200 err = mlx4_create_eq(dev, 1201 MLX4_NUM_ASYNC_EQE + MLX4_NUM_SPARE_EQE, 1202 0, &priv->eq_table.eq[MLX4_EQ_ASYNC]); 1203 } else { 1204 struct mlx4_eq *eq = &priv->eq_table.eq[i]; 1205 #ifdef CONFIG_RFS_ACCEL 1206 int port = find_first_bit(eq->actv_ports.ports, 1207 dev->caps.num_ports) + 1; 1208 1209 if (port <= dev->caps.num_ports) { 1210 struct mlx4_port_info *info = 1211 &mlx4_priv(dev)->port[port]; 1212 1213 if (!info->rmap) { 1214 info->rmap = alloc_irq_cpu_rmap( 1215 mlx4_get_eqs_per_port(dev, port)); 1216 if (!info->rmap) { 1217 mlx4_warn(dev, "Failed to allocate cpu rmap\n"); 1218 err = -ENOMEM; 1219 goto err_out_unmap; 1220 } 1221 } 1222 1223 err = irq_cpu_rmap_add( 1224 info->rmap, eq->irq); 1225 if (err) 1226 mlx4_warn(dev, "Failed adding irq rmap\n"); 1227 } 1228 #endif 1229 err = mlx4_create_eq(dev, dev->quotas.cq + 1230 MLX4_NUM_SPARE_EQE, 1231 (dev->flags & MLX4_FLAG_MSI_X) ? 1232 i + 1 - !!(i > MLX4_EQ_ASYNC) : 0, 1233 eq); 1234 } 1235 if (err) 1236 goto err_out_unmap; 1237 } 1238 1239 if (dev->flags & MLX4_FLAG_MSI_X) { 1240 const char *eq_name; 1241 1242 snprintf(priv->eq_table.irq_names + 1243 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE, 1244 MLX4_IRQNAME_SIZE, 1245 "mlx4-async@pci:%s", 1246 pci_name(dev->persist->pdev)); 1247 eq_name = priv->eq_table.irq_names + 1248 MLX4_EQ_ASYNC * MLX4_IRQNAME_SIZE; 1249 1250 err = request_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq, 1251 mlx4_msi_x_interrupt, 0, eq_name, 1252 priv->eq_table.eq + MLX4_EQ_ASYNC); 1253 if (err) 1254 goto err_out_unmap; 1255 1256 priv->eq_table.eq[MLX4_EQ_ASYNC].have_irq = 1; 1257 } else { 1258 snprintf(priv->eq_table.irq_names, 1259 MLX4_IRQNAME_SIZE, 1260 DRV_NAME "@pci:%s", 1261 pci_name(dev->persist->pdev)); 1262 err = request_irq(dev->persist->pdev->irq, mlx4_interrupt, 1263 IRQF_SHARED, priv->eq_table.irq_names, dev); 1264 if (err) 1265 goto err_out_unmap; 1266 1267 priv->eq_table.have_irq = 1; 1268 } 1269 1270 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1271 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); 1272 if (err) 1273 mlx4_warn(dev, "MAP_EQ for async EQ %d failed (%d)\n", 1274 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn, err); 1275 1276 /* arm ASYNC eq */ 1277 eq_set_ci(&priv->eq_table.eq[MLX4_EQ_ASYNC], 1); 1278 1279 return 0; 1280 1281 err_out_unmap: 1282 while (i > 0) 1283 mlx4_free_eq(dev, &priv->eq_table.eq[--i]); 1284 #ifdef CONFIG_RFS_ACCEL 1285 for (i = 1; i <= dev->caps.num_ports; i++) { 1286 if (mlx4_priv(dev)->port[i].rmap) { 1287 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap); 1288 mlx4_priv(dev)->port[i].rmap = NULL; 1289 } 1290 } 1291 #endif 1292 mlx4_free_irqs(dev); 1293 1294 err_out_clr_int: 1295 if (!mlx4_is_slave(dev)) 1296 mlx4_unmap_clr_int(dev); 1297 1298 err_out_bitmap: 1299 mlx4_unmap_uar(dev); 1300 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1301 1302 err_out_free: 1303 kfree(priv->eq_table.uar_map); 1304 1305 return err; 1306 } 1307 1308 void mlx4_cleanup_eq_table(struct mlx4_dev *dev) 1309 { 1310 struct mlx4_priv *priv = mlx4_priv(dev); 1311 int i; 1312 1313 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 1, 1314 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); 1315 1316 #ifdef CONFIG_RFS_ACCEL 1317 for (i = 1; i <= dev->caps.num_ports; i++) { 1318 if (mlx4_priv(dev)->port[i].rmap) { 1319 free_irq_cpu_rmap(mlx4_priv(dev)->port[i].rmap); 1320 mlx4_priv(dev)->port[i].rmap = NULL; 1321 } 1322 } 1323 #endif 1324 mlx4_free_irqs(dev); 1325 1326 for (i = 0; i < dev->caps.num_comp_vectors + 1; ++i) 1327 mlx4_free_eq(dev, &priv->eq_table.eq[i]); 1328 1329 if (!mlx4_is_slave(dev)) 1330 mlx4_unmap_clr_int(dev); 1331 1332 mlx4_unmap_uar(dev); 1333 mlx4_bitmap_cleanup(&priv->eq_table.bitmap); 1334 1335 kfree(priv->eq_table.uar_map); 1336 } 1337 1338 /* A test that verifies that we can accept interrupts 1339 * on the vector allocated for asynchronous events 1340 */ 1341 int mlx4_test_async(struct mlx4_dev *dev) 1342 { 1343 return mlx4_NOP(dev); 1344 } 1345 EXPORT_SYMBOL(mlx4_test_async); 1346 1347 /* A test that verifies that we can accept interrupts 1348 * on the given irq vector of the tested port. 1349 * Interrupts are checked using the NOP command. 1350 */ 1351 int mlx4_test_interrupt(struct mlx4_dev *dev, int vector) 1352 { 1353 struct mlx4_priv *priv = mlx4_priv(dev); 1354 int err; 1355 1356 /* Temporary use polling for command completions */ 1357 mlx4_cmd_use_polling(dev); 1358 1359 /* Map the new eq to handle all asynchronous events */ 1360 err = mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1361 priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn); 1362 if (err) { 1363 mlx4_warn(dev, "Failed mapping eq for interrupt test\n"); 1364 goto out; 1365 } 1366 1367 /* Go back to using events */ 1368 mlx4_cmd_use_events(dev); 1369 err = mlx4_NOP(dev); 1370 1371 /* Return to default */ 1372 mlx4_cmd_use_polling(dev); 1373 out: 1374 mlx4_MAP_EQ(dev, get_async_ev_mask(dev), 0, 1375 priv->eq_table.eq[MLX4_EQ_ASYNC].eqn); 1376 mlx4_cmd_use_events(dev); 1377 1378 return err; 1379 } 1380 EXPORT_SYMBOL(mlx4_test_interrupt); 1381 1382 bool mlx4_is_eq_vector_valid(struct mlx4_dev *dev, u8 port, int vector) 1383 { 1384 struct mlx4_priv *priv = mlx4_priv(dev); 1385 1386 vector = MLX4_CQ_TO_EQ_VECTOR(vector); 1387 if (vector < 0 || (vector >= dev->caps.num_comp_vectors + 1) || 1388 (vector == MLX4_EQ_ASYNC)) 1389 return false; 1390 1391 return test_bit(port - 1, priv->eq_table.eq[vector].actv_ports.ports); 1392 } 1393 EXPORT_SYMBOL(mlx4_is_eq_vector_valid); 1394 1395 u32 mlx4_get_eqs_per_port(struct mlx4_dev *dev, u8 port) 1396 { 1397 struct mlx4_priv *priv = mlx4_priv(dev); 1398 unsigned int i; 1399 unsigned int sum = 0; 1400 1401 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) 1402 sum += !!test_bit(port - 1, 1403 priv->eq_table.eq[i].actv_ports.ports); 1404 1405 return sum; 1406 } 1407 EXPORT_SYMBOL(mlx4_get_eqs_per_port); 1408 1409 int mlx4_is_eq_shared(struct mlx4_dev *dev, int vector) 1410 { 1411 struct mlx4_priv *priv = mlx4_priv(dev); 1412 1413 vector = MLX4_CQ_TO_EQ_VECTOR(vector); 1414 if (vector <= 0 || (vector >= dev->caps.num_comp_vectors + 1)) 1415 return -EINVAL; 1416 1417 return !!(bitmap_weight(priv->eq_table.eq[vector].actv_ports.ports, 1418 dev->caps.num_ports) > 1); 1419 } 1420 EXPORT_SYMBOL(mlx4_is_eq_shared); 1421 1422 int mlx4_assign_eq(struct mlx4_dev *dev, u8 port, int *vector) 1423 { 1424 struct mlx4_priv *priv = mlx4_priv(dev); 1425 int err = 0, i = 0; 1426 u32 min_ref_count_val = (u32)-1; 1427 int requested_vector = MLX4_CQ_TO_EQ_VECTOR(*vector); 1428 int *prequested_vector = NULL; 1429 1430 1431 mutex_lock(&priv->msix_ctl.pool_lock); 1432 if (requested_vector < (dev->caps.num_comp_vectors + 1) && 1433 (requested_vector >= 0) && 1434 (requested_vector != MLX4_EQ_ASYNC)) { 1435 if (test_bit(port - 1, 1436 priv->eq_table.eq[requested_vector].actv_ports.ports)) { 1437 prequested_vector = &requested_vector; 1438 } else { 1439 struct mlx4_eq *eq; 1440 1441 for (i = 1; i < port; 1442 requested_vector += mlx4_get_eqs_per_port(dev, i++)) 1443 ; 1444 1445 eq = &priv->eq_table.eq[requested_vector]; 1446 if (requested_vector < dev->caps.num_comp_vectors + 1 && 1447 test_bit(port - 1, eq->actv_ports.ports)) { 1448 prequested_vector = &requested_vector; 1449 } 1450 } 1451 } 1452 1453 if (!prequested_vector) { 1454 requested_vector = -1; 1455 for (i = 0; min_ref_count_val && i < dev->caps.num_comp_vectors + 1; 1456 i++) { 1457 struct mlx4_eq *eq = &priv->eq_table.eq[i]; 1458 1459 if (min_ref_count_val > eq->ref_count && 1460 test_bit(port - 1, eq->actv_ports.ports)) { 1461 min_ref_count_val = eq->ref_count; 1462 requested_vector = i; 1463 } 1464 } 1465 1466 if (requested_vector < 0) { 1467 err = -ENOSPC; 1468 goto err_unlock; 1469 } 1470 1471 prequested_vector = &requested_vector; 1472 } 1473 1474 if (!test_bit(*prequested_vector, priv->msix_ctl.pool_bm) && 1475 dev->flags & MLX4_FLAG_MSI_X) { 1476 set_bit(*prequested_vector, priv->msix_ctl.pool_bm); 1477 snprintf(priv->eq_table.irq_names + 1478 *prequested_vector * MLX4_IRQNAME_SIZE, 1479 MLX4_IRQNAME_SIZE, "mlx4-%d@%s", 1480 *prequested_vector, dev_name(&dev->persist->pdev->dev)); 1481 1482 err = request_irq(priv->eq_table.eq[*prequested_vector].irq, 1483 mlx4_msi_x_interrupt, 0, 1484 &priv->eq_table.irq_names[*prequested_vector << 5], 1485 priv->eq_table.eq + *prequested_vector); 1486 1487 if (err) { 1488 clear_bit(*prequested_vector, priv->msix_ctl.pool_bm); 1489 *prequested_vector = -1; 1490 } else { 1491 mlx4_set_eq_affinity_hint(priv, *prequested_vector); 1492 eq_set_ci(&priv->eq_table.eq[*prequested_vector], 1); 1493 priv->eq_table.eq[*prequested_vector].have_irq = 1; 1494 } 1495 } 1496 1497 if (!err && *prequested_vector >= 0) 1498 priv->eq_table.eq[*prequested_vector].ref_count++; 1499 1500 err_unlock: 1501 mutex_unlock(&priv->msix_ctl.pool_lock); 1502 1503 if (!err && *prequested_vector >= 0) 1504 *vector = MLX4_EQ_TO_CQ_VECTOR(*prequested_vector); 1505 else 1506 *vector = 0; 1507 1508 return err; 1509 } 1510 EXPORT_SYMBOL(mlx4_assign_eq); 1511 1512 int mlx4_eq_get_irq(struct mlx4_dev *dev, int cq_vec) 1513 { 1514 struct mlx4_priv *priv = mlx4_priv(dev); 1515 1516 return priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq_vec)].irq; 1517 } 1518 EXPORT_SYMBOL(mlx4_eq_get_irq); 1519 1520 void mlx4_release_eq(struct mlx4_dev *dev, int vec) 1521 { 1522 struct mlx4_priv *priv = mlx4_priv(dev); 1523 int eq_vec = MLX4_CQ_TO_EQ_VECTOR(vec); 1524 1525 mutex_lock(&priv->msix_ctl.pool_lock); 1526 priv->eq_table.eq[eq_vec].ref_count--; 1527 1528 /* once we allocated EQ, we don't release it because it might be binded 1529 * to cpu_rmap. 1530 */ 1531 mutex_unlock(&priv->msix_ctl.pool_lock); 1532 } 1533 EXPORT_SYMBOL(mlx4_release_eq); 1534 1535 void 1536 mlx4_disable_interrupts(struct mlx4_dev *dev) 1537 { 1538 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 1539 int i; 1540 1541 if (dev->flags & MLX4_FLAG_MSI_X) { 1542 for (i = 0; i < (dev->caps.num_comp_vectors + 1); ++i) 1543 disable_irq(priv->eq_table.eq[i].irq); 1544 } else { 1545 disable_irq(dev->persist->pdev->irq); 1546 } 1547 } 1548 EXPORT_SYMBOL(mlx4_disable_interrupts); 1549 1550 void 1551 mlx4_poll_interrupts(struct mlx4_dev *dev) 1552 { 1553 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); 1554 int i; 1555 1556 if (dev->flags & MLX4_FLAG_MSI_X) { 1557 for (i = 0; i < (dev->caps.num_comp_vectors + 1); ++i) { 1558 mlx4_msi_x_interrupt(priv->eq_table.eq[i].irq, 1559 priv->eq_table.eq + i); 1560 } 1561 } else { 1562 mlx4_interrupt(dev->persist->pdev->irq, dev); 1563 } 1564 } 1565 EXPORT_SYMBOL(mlx4_poll_interrupts);
Cache object: 94c4ddf3e5b41dc65678bf335ffd6361
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