Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mlx4/mlx4_core/mlx4_profile.c
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1 /* 2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. 3 * Copyright (c) 2005, 2014 Mellanox Technologies. All rights reserved. 4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #include <linux/slab.h> 36 37 #include "mlx4.h" 38 #include "fw.h" 39 40 enum { 41 MLX4_RES_QP, 42 MLX4_RES_RDMARC, 43 MLX4_RES_ALTC, 44 MLX4_RES_AUXC, 45 MLX4_RES_SRQ, 46 MLX4_RES_CQ, 47 MLX4_RES_EQ, 48 MLX4_RES_DMPT, 49 MLX4_RES_CMPT, 50 MLX4_RES_MTT, 51 MLX4_RES_MCG, 52 MLX4_RES_NUM 53 }; 54 55 static const char *res_name[] = { 56 [MLX4_RES_QP] = "QP", 57 [MLX4_RES_RDMARC] = "RDMARC", 58 [MLX4_RES_ALTC] = "ALTC", 59 [MLX4_RES_AUXC] = "AUXC", 60 [MLX4_RES_SRQ] = "SRQ", 61 [MLX4_RES_CQ] = "CQ", 62 [MLX4_RES_EQ] = "EQ", 63 [MLX4_RES_DMPT] = "DMPT", 64 [MLX4_RES_CMPT] = "CMPT", 65 [MLX4_RES_MTT] = "MTT", 66 [MLX4_RES_MCG] = "MCG", 67 }; 68 69 u64 mlx4_make_profile(struct mlx4_dev *dev, 70 struct mlx4_profile *request, 71 struct mlx4_dev_cap *dev_cap, 72 struct mlx4_init_hca_param *init_hca) 73 { 74 struct mlx4_priv *priv = mlx4_priv(dev); 75 struct mlx4_resource { 76 u64 size; 77 u64 start; 78 int type; 79 u32 num; 80 int log_num; 81 }; 82 83 u64 total_size = 0; 84 struct mlx4_resource *profile; 85 int i, j; 86 87 profile = kcalloc(MLX4_RES_NUM, sizeof(*profile), GFP_KERNEL); 88 if (!profile) 89 return -ENOMEM; 90 91 profile[MLX4_RES_QP].size = dev_cap->qpc_entry_sz; 92 profile[MLX4_RES_RDMARC].size = dev_cap->rdmarc_entry_sz; 93 profile[MLX4_RES_ALTC].size = dev_cap->altc_entry_sz; 94 profile[MLX4_RES_AUXC].size = dev_cap->aux_entry_sz; 95 profile[MLX4_RES_SRQ].size = dev_cap->srq_entry_sz; 96 profile[MLX4_RES_CQ].size = dev_cap->cqc_entry_sz; 97 profile[MLX4_RES_EQ].size = dev_cap->eqc_entry_sz; 98 profile[MLX4_RES_DMPT].size = dev_cap->dmpt_entry_sz; 99 profile[MLX4_RES_CMPT].size = dev_cap->cmpt_entry_sz; 100 profile[MLX4_RES_MTT].size = dev_cap->mtt_entry_sz; 101 profile[MLX4_RES_MCG].size = mlx4_get_mgm_entry_size(dev); 102 103 profile[MLX4_RES_QP].num = request->num_qp; 104 profile[MLX4_RES_RDMARC].num = request->num_qp * request->rdmarc_per_qp; 105 profile[MLX4_RES_ALTC].num = request->num_qp; 106 profile[MLX4_RES_AUXC].num = request->num_qp; 107 profile[MLX4_RES_SRQ].num = request->num_srq; 108 profile[MLX4_RES_CQ].num = request->num_cq; 109 profile[MLX4_RES_EQ].num = mlx4_is_mfunc(dev) ? dev->phys_caps.num_phys_eqs : 110 min_t(unsigned, dev_cap->max_eqs, MAX_MSIX); 111 profile[MLX4_RES_DMPT].num = request->num_mpt; 112 profile[MLX4_RES_CMPT].num = MLX4_NUM_CMPTS; 113 profile[MLX4_RES_MTT].num = request->num_mtt * (1 << log_mtts_per_seg); 114 profile[MLX4_RES_MCG].num = request->num_mcg; 115 116 for (i = 0; i < MLX4_RES_NUM; ++i) { 117 profile[i].type = i; 118 profile[i].num = roundup_pow_of_two(profile[i].num); 119 profile[i].log_num = ilog2(profile[i].num); 120 profile[i].size *= profile[i].num; 121 profile[i].size = max(profile[i].size, (u64) PAGE_SIZE); 122 } 123 124 /* 125 * Sort the resources in decreasing order of size. Since they 126 * all have sizes that are powers of 2, we'll be able to keep 127 * resources aligned to their size and pack them without gaps 128 * using the sorted order. 129 */ 130 for (i = MLX4_RES_NUM; i > 0; --i) 131 for (j = 1; j < i; ++j) { 132 if (profile[j].size > profile[j - 1].size) 133 swap(profile[j], profile[j - 1]); 134 } 135 136 for (i = 0; i < MLX4_RES_NUM; ++i) { 137 if (profile[i].size) { 138 profile[i].start = total_size; 139 total_size += profile[i].size; 140 } 141 142 if (total_size > dev_cap->max_icm_sz) { 143 mlx4_err(dev, "Profile requires 0x%llx bytes; won't fit in 0x%llx bytes of context memory\n", 144 (unsigned long long) total_size, 145 (unsigned long long) dev_cap->max_icm_sz); 146 kfree(profile); 147 return -ENOMEM; 148 } 149 150 if (profile[i].size) 151 mlx4_dbg(dev, " profile[%2d] (%6s): 2^%02d entries @ 0x%10llx, size 0x%10llx\n", 152 i, res_name[profile[i].type], 153 profile[i].log_num, 154 (unsigned long long) profile[i].start, 155 (unsigned long long) profile[i].size); 156 } 157 158 mlx4_dbg(dev, "HCA context memory: reserving %d KB\n", 159 (int) (total_size >> 10)); 160 161 for (i = 0; i < MLX4_RES_NUM; ++i) { 162 switch (profile[i].type) { 163 case MLX4_RES_QP: 164 dev->caps.num_qps = profile[i].num; 165 init_hca->qpc_base = profile[i].start; 166 init_hca->log_num_qps = profile[i].log_num; 167 break; 168 case MLX4_RES_RDMARC: 169 for (priv->qp_table.rdmarc_shift = 0; 170 request->num_qp << priv->qp_table.rdmarc_shift < profile[i].num; 171 ++priv->qp_table.rdmarc_shift) 172 ; /* nothing */ 173 dev->caps.max_qp_dest_rdma = 1 << priv->qp_table.rdmarc_shift; 174 priv->qp_table.rdmarc_base = (u32) profile[i].start; 175 init_hca->rdmarc_base = profile[i].start; 176 init_hca->log_rd_per_qp = priv->qp_table.rdmarc_shift; 177 break; 178 case MLX4_RES_ALTC: 179 init_hca->altc_base = profile[i].start; 180 break; 181 case MLX4_RES_AUXC: 182 init_hca->auxc_base = profile[i].start; 183 break; 184 case MLX4_RES_SRQ: 185 dev->caps.num_srqs = profile[i].num; 186 init_hca->srqc_base = profile[i].start; 187 init_hca->log_num_srqs = profile[i].log_num; 188 break; 189 case MLX4_RES_CQ: 190 dev->caps.num_cqs = profile[i].num; 191 init_hca->cqc_base = profile[i].start; 192 init_hca->log_num_cqs = profile[i].log_num; 193 break; 194 case MLX4_RES_EQ: 195 if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) { 196 init_hca->log_num_eqs = 0x1f; 197 init_hca->eqc_base = profile[i].start; 198 init_hca->num_sys_eqs = dev_cap->num_sys_eqs; 199 } else { 200 dev->caps.num_eqs = roundup_pow_of_two( 201 min_t(unsigned, 202 dev_cap->max_eqs, 203 MAX_MSIX)); 204 init_hca->eqc_base = profile[i].start; 205 init_hca->log_num_eqs = ilog2(dev->caps.num_eqs); 206 } 207 break; 208 case MLX4_RES_DMPT: 209 dev->caps.num_mpts = profile[i].num; 210 priv->mr_table.mpt_base = profile[i].start; 211 init_hca->dmpt_base = profile[i].start; 212 init_hca->log_mpt_sz = profile[i].log_num; 213 break; 214 case MLX4_RES_CMPT: 215 init_hca->cmpt_base = profile[i].start; 216 break; 217 case MLX4_RES_MTT: 218 dev->caps.num_mtts = profile[i].num; 219 priv->mr_table.mtt_base = profile[i].start; 220 init_hca->mtt_base = profile[i].start; 221 break; 222 case MLX4_RES_MCG: 223 init_hca->mc_base = profile[i].start; 224 init_hca->log_mc_entry_sz = 225 ilog2(mlx4_get_mgm_entry_size(dev)); 226 init_hca->log_mc_table_sz = profile[i].log_num; 227 if (dev->caps.steering_mode == 228 MLX4_STEERING_MODE_DEVICE_MANAGED) { 229 dev->caps.num_mgms = profile[i].num; 230 } else { 231 init_hca->log_mc_hash_sz = 232 profile[i].log_num - 1; 233 dev->caps.num_mgms = profile[i].num >> 1; 234 dev->caps.num_amgms = profile[i].num >> 1; 235 } 236 break; 237 default: 238 break; 239 } 240 } 241 242 /* 243 * PDs don't take any HCA memory, but we assign them as part 244 * of the HCA profile anyway. 245 */ 246 dev->caps.num_pds = MLX4_NUM_PDS; 247 248 kfree(profile); 249 return total_size; 250 }
Cache object: 8f722e91e994aff6578f89decbb5e2ce
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