The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mlx4/qp.h

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    1 /*
    2  * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
    3  *
    4  * This software is available to you under a choice of one of two
    5  * licenses.  You may choose to be licensed under the terms of the GNU
    6  * General Public License (GPL) Version 2, available from the file
    7  * COPYING in the main directory of this source tree, or the
    8  * OpenIB.org BSD license below:
    9  *
   10  *     Redistribution and use in source and binary forms, with or
   11  *     without modification, are permitted provided that the following
   12  *     conditions are met:
   13  *
   14  *      - Redistributions of source code must retain the above
   15  *        copyright notice, this list of conditions and the following
   16  *        disclaimer.
   17  *
   18  *      - Redistributions in binary form must reproduce the above
   19  *        copyright notice, this list of conditions and the following
   20  *        disclaimer in the documentation and/or other materials
   21  *        provided with the distribution.
   22  *
   23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
   24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
   25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
   26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
   27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
   28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
   29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
   30  * SOFTWARE.
   31  */
   32 
   33 #ifndef MLX4_QP_H
   34 #define MLX4_QP_H
   35 
   36 #include <linux/types.h>
   37 
   38 #include <dev/mlx4/device.h>
   39 
   40 #define MLX4_INVALID_LKEY       0x100
   41 #define DS_SIZE_ALIGNMENT       16
   42 
   43 #define SET_BYTE_COUNT(byte_count) cpu_to_be32(byte_count)
   44 #define SET_LSO_MSS(mss_hdr_size) cpu_to_be32(mss_hdr_size)
   45 #define DS_BYTE_COUNT_MASK      cpu_to_be32(0x7fffffff)
   46 
   47 enum mlx4_qp_optpar {
   48         MLX4_QP_OPTPAR_ALT_ADDR_PATH            = 1 << 0,
   49         MLX4_QP_OPTPAR_RRE                      = 1 << 1,
   50         MLX4_QP_OPTPAR_RAE                      = 1 << 2,
   51         MLX4_QP_OPTPAR_RWE                      = 1 << 3,
   52         MLX4_QP_OPTPAR_PKEY_INDEX               = 1 << 4,
   53         MLX4_QP_OPTPAR_Q_KEY                    = 1 << 5,
   54         MLX4_QP_OPTPAR_RNR_TIMEOUT              = 1 << 6,
   55         MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH        = 1 << 7,
   56         MLX4_QP_OPTPAR_SRA_MAX                  = 1 << 8,
   57         MLX4_QP_OPTPAR_RRA_MAX                  = 1 << 9,
   58         MLX4_QP_OPTPAR_PM_STATE                 = 1 << 10,
   59         MLX4_QP_OPTPAR_RETRY_COUNT              = 1 << 12,
   60         MLX4_QP_OPTPAR_RNR_RETRY                = 1 << 13,
   61         MLX4_QP_OPTPAR_ACK_TIMEOUT              = 1 << 14,
   62         MLX4_QP_OPTPAR_SCHED_QUEUE              = 1 << 16,
   63         MLX4_QP_OPTPAR_COUNTER_INDEX            = 1 << 20,
   64         MLX4_QP_OPTPAR_VLAN_STRIPPING           = 1 << 21,
   65 };
   66 
   67 enum mlx4_qp_state {
   68         MLX4_QP_STATE_RST                       = 0,
   69         MLX4_QP_STATE_INIT                      = 1,
   70         MLX4_QP_STATE_RTR                       = 2,
   71         MLX4_QP_STATE_RTS                       = 3,
   72         MLX4_QP_STATE_SQER                      = 4,
   73         MLX4_QP_STATE_SQD                       = 5,
   74         MLX4_QP_STATE_ERR                       = 6,
   75         MLX4_QP_STATE_SQ_DRAINING               = 7,
   76         MLX4_QP_NUM_STATE
   77 };
   78 
   79 enum {
   80         MLX4_QP_ST_RC                           = 0x0,
   81         MLX4_QP_ST_UC                           = 0x1,
   82         MLX4_QP_ST_RD                           = 0x2,
   83         MLX4_QP_ST_UD                           = 0x3,
   84         MLX4_QP_ST_XRC                          = 0x6,
   85         MLX4_QP_ST_MLX                          = 0x7
   86 };
   87 
   88 enum {
   89         MLX4_QP_PM_MIGRATED                     = 0x3,
   90         MLX4_QP_PM_ARMED                        = 0x0,
   91         MLX4_QP_PM_REARM                        = 0x1
   92 };
   93 
   94 enum {
   95         /* params1 */
   96         MLX4_QP_BIT_SRE                         = 1 << 15,
   97         MLX4_QP_BIT_SWE                         = 1 << 14,
   98         MLX4_QP_BIT_SAE                         = 1 << 13,
   99         /* params2 */
  100         MLX4_QP_BIT_RRE                         = 1 << 15,
  101         MLX4_QP_BIT_RWE                         = 1 << 14,
  102         MLX4_QP_BIT_RAE                         = 1 << 13,
  103         MLX4_QP_BIT_FPP                         = 1 <<  3,
  104         MLX4_QP_BIT_RIC                         = 1 <<  4,
  105 };
  106 
  107 enum {
  108         MLX4_RSS_HASH_XOR                       = 0,
  109         MLX4_RSS_HASH_TOP                       = 1,
  110 
  111         MLX4_RSS_UDP_IPV6                       = 1 << 0,
  112         MLX4_RSS_UDP_IPV4                       = 1 << 1,
  113         MLX4_RSS_TCP_IPV6                       = 1 << 2,
  114         MLX4_RSS_IPV6                           = 1 << 3,
  115         MLX4_RSS_TCP_IPV4                       = 1 << 4,
  116         MLX4_RSS_IPV4                           = 1 << 5,
  117 
  118         MLX4_RSS_BY_OUTER_HEADERS               = 0 << 6,
  119         MLX4_RSS_BY_INNER_HEADERS               = 2 << 6,
  120         MLX4_RSS_BY_INNER_HEADERS_IPONLY        = 3 << 6,
  121 
  122         /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
  123         MLX4_RSS_OFFSET_IN_QPC_PRI_PATH         = 0x24,
  124         /* offset of being RSS indirection QP within mlx4_qp_context.flags */
  125         MLX4_RSS_QPC_FLAG_OFFSET                = 13,
  126 };
  127 
  128 #define MLX4_EN_RSS_KEY_SIZE 40
  129 
  130 struct mlx4_rss_context {
  131         __be32                  base_qpn;
  132         __be32                  default_qpn;
  133         u16                     reserved;
  134         u8                      hash_fn;
  135         u8                      flags;
  136         __be32                  rss_key[MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)];
  137         __be32                  base_qpn_udp;
  138 };
  139 
  140 struct mlx4_qp_path {
  141         u8                      fl;
  142         union {
  143                 u8                      vlan_control;
  144                 u8                      control;
  145         };
  146         u8                      disable_pkey_check;
  147         u8                      pkey_index;
  148         u8                      counter_index;
  149         u8                      grh_mylmc;
  150         __be16                  rlid;
  151         u8                      ackto;
  152         u8                      mgid_index;
  153         u8                      static_rate;
  154         u8                      hop_limit;
  155         __be32                  tclass_flowlabel;
  156         u8                      rgid[16];
  157         u8                      sched_queue;
  158         u8                      vlan_index;
  159         u8                      feup;
  160         u8                      fvl_rx;
  161         u8                      reserved4[2];
  162         u8                      dmac[ETH_ALEN];
  163 };
  164 
  165 enum { /* fl */
  166         MLX4_FL_CV      = 1 << 6,
  167         MLX4_FL_SV      = 1 << 5,
  168         MLX4_FL_ETH_HIDE_CQE_VLAN       = 1 << 2,
  169         MLX4_FL_ETH_SRC_CHECK_MC_LB     = 1 << 1,
  170         MLX4_FL_ETH_SRC_CHECK_UC_LB     = 1 << 0,
  171 };
  172 
  173 enum { /* control */
  174         MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER      = 1 << 7,
  175 };
  176 
  177 enum { /* vlan_control */
  178         MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED      = 1 << 6,
  179         MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */
  180         MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED    = 1 << 4,
  181         MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED      = 1 << 2,
  182         MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
  183         MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED    = 1 << 0
  184 };
  185 
  186 enum { /* feup */
  187         MLX4_FEUP_FORCE_ETH_UP          = 1 << 6, /* force Eth UP */
  188         MLX4_FSM_FORCE_ETH_SRC_MAC      = 1 << 5, /* force Source MAC */
  189         MLX4_FVL_FORCE_ETH_VLAN         = 1 << 3  /* force Eth vlan */
  190 };
  191 
  192 enum { /* fvl_rx */
  193         MLX4_FVL_RX_FORCE_ETH_VLAN      = 1 << 0 /* enforce Eth rx vlan */
  194 };
  195 
  196 struct mlx4_qp_context {
  197         __be32                  flags;
  198         __be32                  pd;
  199         u8                      mtu_msgmax;
  200         u8                      rq_size_stride;
  201         u8                      sq_size_stride;
  202         u8                      rlkey_roce_mode;
  203         __be32                  usr_page;
  204         __be32                  local_qpn;
  205         __be32                  remote_qpn;
  206         struct                  mlx4_qp_path pri_path;
  207         struct                  mlx4_qp_path alt_path;
  208         __be32                  params1;
  209         u32                     reserved1;
  210         __be32                  next_send_psn;
  211         __be32                  cqn_send;
  212         __be16                  roce_entropy;
  213         __be16                  reserved2[3];
  214         __be32                  last_acked_psn;
  215         __be32                  ssn;
  216         __be32                  params2;
  217         __be32                  rnr_nextrecvpsn;
  218         __be32                  xrcd;
  219         __be32                  cqn_recv;
  220         __be64                  db_rec_addr;
  221         __be32                  qkey;
  222         __be32                  srqn;
  223         __be32                  msn;
  224         __be16                  rq_wqe_counter;
  225         __be16                  sq_wqe_counter;
  226         u32                     reserved3;
  227         __be16                  rate_limit_params;
  228         u8                      reserved4;
  229         u8                      qos_vport;
  230         __be32                  param3;
  231         __be32                  nummmcpeers_basemkey;
  232         u8                      log_page_size;
  233         u8                      reserved5[2];
  234         u8                      mtt_base_addr_h;
  235         __be32                  mtt_base_addr_l;
  236         u32                     reserved6[10];
  237 };
  238 
  239 struct mlx4_update_qp_context {
  240         __be64                  qp_mask;
  241         __be64                  primary_addr_path_mask;
  242         __be64                  secondary_addr_path_mask;
  243         u64                     reserved1;
  244         struct mlx4_qp_context  qp_context;
  245         u64                     reserved2[58];
  246 };
  247 
  248 enum {
  249         MLX4_UPD_QP_MASK_PM_STATE       = 32,
  250         MLX4_UPD_QP_MASK_VSD            = 33,
  251         MLX4_UPD_QP_MASK_QOS_VPP        = 34,
  252         MLX4_UPD_QP_MASK_RATE_LIMIT     = 35,
  253 };
  254 
  255 enum {
  256         MLX4_UPD_QP_PATH_MASK_PKEY_INDEX                = 0 + 32,
  257         MLX4_UPD_QP_PATH_MASK_FSM                       = 1 + 32,
  258         MLX4_UPD_QP_PATH_MASK_MAC_INDEX                 = 2 + 32,
  259         MLX4_UPD_QP_PATH_MASK_FVL                       = 3 + 32,
  260         MLX4_UPD_QP_PATH_MASK_CV                        = 4 + 32,
  261         MLX4_UPD_QP_PATH_MASK_VLAN_INDEX                = 5 + 32,
  262         MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN         = 6 + 32,
  263         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED     = 7 + 32,
  264         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P           = 8 + 32,
  265         MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED       = 9 + 32,
  266         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED     = 10 + 32,
  267         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P           = 11 + 32,
  268         MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED       = 12 + 32,
  269         MLX4_UPD_QP_PATH_MASK_FEUP                      = 13 + 32,
  270         MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE               = 14 + 32,
  271         MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX          = 15 + 32,
  272         MLX4_UPD_QP_PATH_MASK_FVL_RX                    = 16 + 32,
  273         MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB       = 18 + 32,
  274         MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB       = 19 + 32,
  275         MLX4_UPD_QP_PATH_MASK_SV                        = 22 + 32,
  276 };
  277 
  278 enum { /* param3 */
  279         MLX4_STRIP_VLAN = 1 << 30
  280 };
  281 
  282 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
  283 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
  284 
  285 enum {
  286         MLX4_WQE_CTRL_OWN               = 1 << 31,
  287         MLX4_WQE_CTRL_NEC               = 1 << 29,
  288         MLX4_WQE_CTRL_RR                = 1 << 6,
  289         MLX4_WQE_CTRL_IIP               = 1 << 28,
  290         MLX4_WQE_CTRL_ILP               = 1 << 27,
  291         MLX4_WQE_CTRL_FENCE             = 1 << 6,
  292         MLX4_WQE_CTRL_CQ_UPDATE         = 3 << 2,
  293         MLX4_WQE_CTRL_SOLICITED         = 1 << 1,
  294         MLX4_WQE_CTRL_IP_CSUM           = 1 << 4,
  295         MLX4_WQE_CTRL_TCP_UDP_CSUM      = 1 << 5,
  296         MLX4_WQE_CTRL_INS_CVLAN         = 1 << 6,
  297         MLX4_WQE_CTRL_INS_SVLAN         = 1 << 7,
  298         MLX4_WQE_CTRL_STRONG_ORDER      = 1 << 7,
  299         MLX4_WQE_CTRL_FORCE_LOOPBACK    = 1 << 0,
  300 };
  301 
  302 struct mlx4_wqe_ctrl_seg {
  303         __be32                  owner_opcode;
  304         union {
  305                 struct {
  306                         __be16                  vlan_tag;
  307                         u8                      ins_vlan;
  308                         u8                      fence_size;
  309                 };
  310                 __be32                  bf_qpn;
  311         };
  312         /*
  313          * High 24 bits are SRC remote buffer; low 8 bits are flags:
  314          * [7]   SO (strong ordering)
  315          * [5]   TCP/UDP checksum
  316          * [4]   IP checksum
  317          * [3:2] C (generate completion queue entry)
  318          * [1]   SE (solicited event)
  319          * [0]   FL (force loopback)
  320          */
  321         union {
  322                 __be32                  srcrb_flags;
  323                 __be16                  srcrb_flags16[2];
  324         };
  325         /*
  326          * imm is immediate data for send/RDMA write w/ immediate;
  327          * also invalidation key for send with invalidate; input
  328          * modifier for WQEs on CCQs.
  329          */
  330         __be32                  imm;
  331 };
  332 
  333 enum {
  334         MLX4_WQE_MLX_VL15       = 1 << 17,
  335         MLX4_WQE_MLX_SLR        = 1 << 16
  336 };
  337 
  338 struct mlx4_wqe_mlx_seg {
  339         u8                      owner;
  340         u8                      reserved1[2];
  341         u8                      opcode;
  342         __be16                  sched_prio;
  343         u8                      reserved2;
  344         u8                      size;
  345         /*
  346          * [17]    VL15
  347          * [16]    SLR
  348          * [15:12] static rate
  349          * [11:8]  SL
  350          * [4]     ICRC
  351          * [3:2]   C
  352          * [0]     FL (force loopback)
  353          */
  354         __be32                  flags;
  355         __be16                  rlid;
  356         u16                     reserved3;
  357 };
  358 
  359 struct mlx4_wqe_datagram_seg {
  360         __be32                  av[8];
  361         __be32                  dqpn;
  362         __be32                  qkey;
  363         __be16                  vlan;
  364         u8                      mac[ETH_ALEN];
  365 };
  366 
  367 struct mlx4_wqe_lso_seg {
  368         __be32                  mss_hdr_size;
  369         __be32                  header[0];
  370 };
  371 
  372 enum mlx4_wqe_bind_seg_flags2 {
  373         MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
  374         MLX4_WQE_BIND_TYPE_2     = (1 << 31),
  375 };
  376 
  377 struct mlx4_wqe_bind_seg {
  378         __be32                  flags1;
  379         __be32                  flags2;
  380         __be32                  new_rkey;
  381         __be32                  lkey;
  382         __be64                  addr;
  383         __be64                  length;
  384 };
  385 
  386 enum {
  387         MLX4_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
  388         MLX4_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
  389         MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  = 1 << 29,
  390         MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
  391         MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC       = 1 << 31
  392 };
  393 
  394 struct mlx4_wqe_fmr_seg {
  395         __be32                  flags;
  396         __be32                  mem_key;
  397         __be64                  buf_list;
  398         __be64                  start_addr;
  399         __be64                  reg_len;
  400         __be32                  offset;
  401         __be32                  page_size;
  402         u32                     reserved[2];
  403 };
  404 
  405 struct mlx4_wqe_fmr_ext_seg {
  406         u8                      flags;
  407         u8                      reserved;
  408         __be16                  app_mask;
  409         __be16                  wire_app_tag;
  410         __be16                  mem_app_tag;
  411         __be32                  wire_ref_tag_base;
  412         __be32                  mem_ref_tag_base;
  413 };
  414 
  415 struct mlx4_wqe_local_inval_seg {
  416         u64                     reserved1;
  417         __be32                  mem_key;
  418         u32                     reserved2;
  419         u64                     reserved3[2];
  420 };
  421 
  422 struct mlx4_wqe_raddr_seg {
  423         __be64                  raddr;
  424         __be32                  rkey;
  425         u32                     reserved;
  426 };
  427 
  428 struct mlx4_wqe_atomic_seg {
  429         __be64                  swap_add;
  430         __be64                  compare;
  431 };
  432 
  433 struct mlx4_wqe_masked_atomic_seg {
  434         __be64                  swap_add;
  435         __be64                  compare;
  436         __be64                  swap_add_mask;
  437         __be64                  compare_mask;
  438 };
  439 
  440 struct mlx4_wqe_data_seg {
  441         __be32                  byte_count;
  442         __be32                  lkey;
  443         __be64                  addr;
  444 };
  445 
  446 enum {
  447         MLX4_INLINE_ALIGN       = 64,
  448         MLX4_INLINE_SEG         = 1 << 31,
  449 };
  450 
  451 struct mlx4_wqe_inline_seg {
  452         __be32                  byte_count;
  453 };
  454 
  455 enum mlx4_update_qp_attr {
  456         MLX4_UPDATE_QP_SMAC             = 1 << 0,
  457         MLX4_UPDATE_QP_VSD              = 1 << 1,
  458         MLX4_UPDATE_QP_RATE_LIMIT       = 1 << 2,
  459         MLX4_UPDATE_QP_QOS_VPORT        = 1 << 3,
  460         MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB      = 1 << 4,
  461         MLX4_UPDATE_QP_SUPPORTED_ATTRS  = (1 << 5) - 1
  462 };
  463 
  464 enum mlx4_update_qp_params_flags {
  465         MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB     = 1 << 0,
  466         MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE          = 1 << 1,
  467 };
  468 
  469 struct mlx4_update_qp_params {
  470         u8      smac_index;
  471         u8      qos_vport;
  472         u32     flags;
  473         u16     rate_unit;
  474         u16     rate_val;
  475 };
  476 
  477 int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
  478                    enum mlx4_update_qp_attr attr,
  479                    struct mlx4_update_qp_params *params);
  480 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
  481                    enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
  482                    struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
  483                    int sqd_event, struct mlx4_qp *qp);
  484 
  485 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
  486                   struct mlx4_qp_context *context);
  487 
  488 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
  489                      struct mlx4_qp_context *context,
  490                      struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
  491 
  492 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
  493 {
  494         return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
  495 }
  496 
  497 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
  498 
  499 static inline u16 folded_qp(u32 q)
  500 {
  501         u16 res;
  502 
  503         res = ((q & 0xff) ^ ((q & 0xff0000) >> 16)) | (q & 0xff00);
  504         return res;
  505 }
  506 
  507 u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn);
  508 
  509 #endif /* MLX4_QP_H */

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