The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mlx5/diagnostics.h

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    1 /*-
    2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
   14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23  * SUCH DAMAGE.
   24  *
   25  * $FreeBSD$
   26  */
   27 
   28 #ifndef MLX5_CORE_DIAGNOSTICS_H
   29 #define MLX5_CORE_DIAGNOSTICS_H
   30 
   31 #define MLX5_CORE_DIAGNOSTICS_NUM(n, s, t) n
   32 #define MLX5_CORE_DIAGNOSTICS_STRUCT(n, s, t) s,
   33 #define MLX5_CORE_DIAGNOSTICS_ENTRY(n, s, t) { #s, (t) },
   34 
   35 static MALLOC_DEFINE(M_MLX5_EEPROM, "MLX5EEPROM", "MLX5 EEPROM information");
   36 
   37 struct mlx5_core_diagnostics_entry {
   38         const char *desc;
   39         u16     counter_id;
   40 };
   41 
   42 #define MLX5_CORE_PCI_DIAGNOSTICS(m) \
   43 m(+1, pxd_ready_bp, 0x0401) \
   44 m(+1, pci_write_bp, 0x0402) \
   45 m(+1, pci_read_bp, 0x0403) \
   46 m(+1, pci_read_stuck_no_completion_buffer, 0x0404) \
   47 m(+1, max_pci_bw, 0x0405) \
   48 m(+1, used_pci_bw, 0x0406) \
   49 m(+1, rx_pci_errors, 0) \
   50 m(+1, tx_pci_errors, 0) \
   51 m(+1, tx_pci_correctable_errors, 0) \
   52 m(+1, tx_pci_non_fatal_errors, 0) \
   53 m(+1, tx_pci_fatal_errors, 0)
   54 
   55 #define MLX5_CORE_PCI_DIAGNOSTICS_NUM \
   56         (0 MLX5_CORE_PCI_DIAGNOSTICS(MLX5_CORE_DIAGNOSTICS_NUM))
   57 
   58 union mlx5_core_pci_diagnostics {
   59         u64     array[MLX5_CORE_PCI_DIAGNOSTICS_NUM];
   60         struct {
   61                 u64     MLX5_CORE_PCI_DIAGNOSTICS(
   62                         MLX5_CORE_DIAGNOSTICS_STRUCT) dummy[0];
   63         }       counter;
   64 };
   65 
   66 extern const struct mlx5_core_diagnostics_entry
   67         mlx5_core_pci_diagnostics_table[MLX5_CORE_PCI_DIAGNOSTICS_NUM];
   68 
   69 #define MLX5_CORE_GENERAL_DIAGNOSTICS(m) \
   70 m(+1, l0_mtt_miss, 0x0801) \
   71 m(+1, l0_mtt_hit, 0x0802) \
   72 m(+1, l1_mtt_miss, 0x0803) \
   73 m(+1, l1_mtt_hit, 0x0804) \
   74 m(+1, l0_mpt_miss, 0x0805) \
   75 m(+1, l0_mpt_hit, 0x0806) \
   76 m(+1, l1_mpt_miss, 0x0807) \
   77 m(+1, l1_mpt_hit, 0x0808) \
   78 m(+1, rxb_no_slow_path_credits, 0x0c01) \
   79 m(+1, rxb_no_fast_path_credits, 0x0c02) \
   80 m(+1, rxb_rxt_no_slow_path_cred_perf_count, 0x0c03) \
   81 m(+1, rxb_rxt_no_fast_path_cred_perf_count, 0x0c04) \
   82 m(+1, rxt_ctrl_perf_slice_load_slow, 0x1001) \
   83 m(+1, rxt_ctrl_perf_slice_load_fast, 0x1002) \
   84 m(+1, rxt_steering_perf_count_steering0_rse_work_rate, 0x1003) \
   85 m(+1, rxt_steering_perf_count_steering1_rse_work_rate, 0x1004) \
   86 m(+1, perf_count_tpt_credit, 0x1401) \
   87 m(+1, perf_wb_miss, 0x1402) \
   88 m(+1, perf_wb_hit, 0x1403) \
   89 m(+1, rxw_perf_rx_l1_slow_miss_ldb, 0x1404) \
   90 m(+1, rxw_perf_rx_l1_slow_hit_ldb, 0x1405) \
   91 m(+1, rxw_perf_rx_l1_fast_miss_ldb, 0x1406) \
   92 m(+1, rxw_perf_rx_l1_fast_hit_ldb, 0x1407) \
   93 m(+1, rxw_perf_l2_cache_read_miss_ldb, 0x1408) \
   94 m(+1, rxw_perf_l2_cache_read_hit_ldb, 0x1409) \
   95 m(+1, rxw_perf_rx_l1_slow_miss_reqsl, 0x140a) \
   96 m(+1, rxw_perf_rx_l1_slow_hit_reqsl, 0x140b) \
   97 m(+1, rxw_perf_rx_l1_fast_miss_reqsl, 0x140c) \
   98 m(+1, rxw_perf_rx_l1_fast_hit_reqsl, 0x140d) \
   99 m(+1, rxw_perf_l2_cache_read_miss_reqsl, 0x140e) \
  100 m(+1, rxw_perf_l2_cache_read_hit_reqsl, 0x140f) \
  101 m(+1, rxs_no_pxt_credits, 0x1801) \
  102 m(+1, rxc_eq_all_slices_busy, 0x1c01) \
  103 m(+1, rxc_cq_all_slices_busy, 0x1c02) \
  104 m(+1, rxc_msix_all_slices_busy, 0x1c03) \
  105 m(+1, sxw_qp_done_due_to_vl_limited, 0x2001) \
  106 m(+1, sxw_qp_done_due_to_desched, 0x2002) \
  107 m(+1, sxw_qp_done_due_to_work_done, 0x2003) \
  108 m(+1, sxw_qp_done_due_to_limited, 0x2004) \
  109 m(+1, sxw_qp_done_due_to_e2e_credits, 0x2005) \
  110 m(+1, sxw_packet_send_sxw2sxp_go_vld, 0x2006) \
  111 m(+1, sxw_perf_count_steering_hit, 0x2007) \
  112 m(+1, sxw_perf_count_steering_miss, 0x2008) \
  113 m(+1, sxw_perf_count_steering_rse_0, 0x2009) \
  114 m(+1, sxd_no_sched_credits, 0x2401) \
  115 m(+1, sxd_no_slow_path_sched_credits, 0x2402) \
  116 m(+1, tpt_indirect_mem_key, 0x2801)
  117 
  118 #define MLX5_CORE_GENERAL_DIAGNOSTICS_NUM \
  119         (0 MLX5_CORE_GENERAL_DIAGNOSTICS(MLX5_CORE_DIAGNOSTICS_NUM))
  120 
  121 union mlx5_core_general_diagnostics {
  122         u64     array[MLX5_CORE_GENERAL_DIAGNOSTICS_NUM];
  123         struct {
  124                 u64     MLX5_CORE_GENERAL_DIAGNOSTICS(
  125                         MLX5_CORE_DIAGNOSTICS_STRUCT) dummy[0];
  126         }       counter;
  127 };
  128 
  129 extern const struct mlx5_core_diagnostics_entry
  130         mlx5_core_general_diagnostics_table[MLX5_CORE_GENERAL_DIAGNOSTICS_NUM];
  131 
  132 struct mlx5_eeprom {
  133         int     lock_bit;
  134         int     i2c_addr;
  135         int     page_num;
  136         int     device_addr;
  137         int     module_num;
  138         int     len;
  139         int     type;
  140         int     page_valid;
  141         u32     *data;
  142 };
  143 
  144 /* function prototypes */
  145 int mlx5_core_set_diagnostics_full(struct mlx5_core_dev *mdev,
  146                                    u8 enable_pci, u8 enable_general);
  147 int mlx5_core_get_diagnostics_full(struct mlx5_core_dev *mdev,
  148                                    union mlx5_core_pci_diagnostics *ppci,
  149                                    union mlx5_core_general_diagnostics *pgen);
  150 int mlx5_core_supports_diagnostics(struct mlx5_core_dev *mdev, u16 counter_id);
  151 int mlx5_read_eeprom(struct mlx5_core_dev *dev, struct mlx5_eeprom *eeprom);
  152 int mlx5_get_eeprom_info(struct mlx5_core_dev *dev, struct mlx5_eeprom *eeprom);
  153 int mlx5_get_eeprom(struct mlx5_core_dev *dev, struct mlx5_eeprom *ee);
  154 
  155 #endif                                  /* MLX5_CORE_DIAGNOSTICS_H */

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