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sys/dev/mlx5/driver.h
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1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #ifndef MLX5_DRIVER_H 29 #define MLX5_DRIVER_H 30 31 #include "opt_ratelimit.h" 32 33 #include <linux/kernel.h> 34 #include <linux/completion.h> 35 #include <linux/pci.h> 36 #include <linux/cache.h> 37 #include <linux/rbtree.h> 38 #include <linux/if_ether.h> 39 #include <linux/semaphore.h> 40 #include <linux/slab.h> 41 #include <linux/vmalloc.h> 42 #include <linux/radix-tree.h> 43 #include <linux/idr.h> 44 #include <linux/wait.h> 45 46 #include <dev/mlx5/device.h> 47 #include <dev/mlx5/doorbell.h> 48 #include <dev/mlx5/srq.h> 49 50 #define MLX5_QCOUNTER_SETS_NETDEV 64 51 #define MLX5_MAX_NUMBER_OF_VFS 128 52 53 #define MLX5_INVALID_QUEUE_HANDLE 0xffffffff 54 55 enum { 56 MLX5_BOARD_ID_LEN = 64, 57 MLX5_MAX_NAME_LEN = 16, 58 }; 59 60 enum { 61 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, 62 }; 63 64 enum { 65 CMD_OWNER_SW = 0x0, 66 CMD_OWNER_HW = 0x1, 67 CMD_STATUS_SUCCESS = 0, 68 }; 69 70 enum mlx5_sqp_t { 71 MLX5_SQP_SMI = 0, 72 MLX5_SQP_GSI = 1, 73 MLX5_SQP_IEEE_1588 = 2, 74 MLX5_SQP_SNIFFER = 3, 75 MLX5_SQP_SYNC_UMR = 4, 76 }; 77 78 enum { 79 MLX5_MAX_PORTS = 2, 80 }; 81 82 enum { 83 MLX5_EQ_VEC_PAGES = 0, 84 MLX5_EQ_VEC_CMD = 1, 85 MLX5_EQ_VEC_ASYNC = 2, 86 MLX5_EQ_VEC_COMP_BASE, 87 }; 88 89 enum { 90 MLX5_ATOMIC_MODE_OFF = 16, 91 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF, 92 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF, 93 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF, 94 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF, 95 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF, 96 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF, 97 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF, 98 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF, 99 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF, 100 }; 101 102 enum { 103 MLX5_ATOMIC_MODE_DCT_OFF = 20, 104 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF, 105 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF, 106 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF, 107 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF, 108 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF, 109 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF, 110 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF, 111 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF, 112 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF, 113 }; 114 115 enum { 116 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, 117 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, 118 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2, 119 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3, 120 }; 121 122 enum { 123 MLX5_REG_QPTS = 0x4002, 124 MLX5_REG_QETCR = 0x4005, 125 MLX5_REG_QPDP = 0x4007, 126 MLX5_REG_QTCT = 0x400A, 127 MLX5_REG_QPDPM = 0x4013, 128 MLX5_REG_QHLL = 0x4016, 129 MLX5_REG_QCAM = 0x4019, 130 MLX5_REG_DCBX_PARAM = 0x4020, 131 MLX5_REG_DCBX_APP = 0x4021, 132 MLX5_REG_FPGA_CAP = 0x4022, 133 MLX5_REG_FPGA_CTRL = 0x4023, 134 MLX5_REG_FPGA_ACCESS_REG = 0x4024, 135 MLX5_REG_FPGA_SHELL_CNTR = 0x4025, 136 MLX5_REG_PCAP = 0x5001, 137 MLX5_REG_PMLP = 0x5002, 138 MLX5_REG_PMTU = 0x5003, 139 MLX5_REG_PTYS = 0x5004, 140 MLX5_REG_PAOS = 0x5006, 141 MLX5_REG_PFCC = 0x5007, 142 MLX5_REG_PPCNT = 0x5008, 143 MLX5_REG_PUDE = 0x5009, 144 MLX5_REG_PPTB = 0x500B, 145 MLX5_REG_PBMC = 0x500C, 146 MLX5_REG_PELC = 0x500E, 147 MLX5_REG_PVLC = 0x500F, 148 MLX5_REG_PMPE = 0x5010, 149 MLX5_REG_PMAOS = 0x5012, 150 MLX5_REG_PPLM = 0x5023, 151 MLX5_REG_PDDR = 0x5031, 152 MLX5_REG_PBSR = 0x5038, 153 MLX5_REG_PCAM = 0x507f, 154 MLX5_REG_NODE_DESC = 0x6001, 155 MLX5_REG_HOST_ENDIANNESS = 0x7004, 156 MLX5_REG_MTMP = 0x900a, 157 MLX5_REG_MCIA = 0x9014, 158 MLX5_REG_MFRL = 0x9028, 159 MLX5_REG_MPCNT = 0x9051, 160 MLX5_REG_MCQI = 0x9061, 161 MLX5_REG_MCC = 0x9062, 162 MLX5_REG_MCDA = 0x9063, 163 MLX5_REG_MCAM = 0x907f, 164 }; 165 166 enum dbg_rsc_type { 167 MLX5_DBG_RSC_QP, 168 MLX5_DBG_RSC_EQ, 169 MLX5_DBG_RSC_CQ, 170 }; 171 172 enum { 173 MLX5_INTERFACE_PROTOCOL_IB = 0, 174 MLX5_INTERFACE_PROTOCOL_ETH = 1, 175 MLX5_INTERFACE_NUMBER = 2, 176 }; 177 178 struct mlx5_field_desc { 179 struct dentry *dent; 180 int i; 181 }; 182 183 struct mlx5_rsc_debug { 184 struct mlx5_core_dev *dev; 185 void *object; 186 enum dbg_rsc_type type; 187 struct dentry *root; 188 struct mlx5_field_desc fields[0]; 189 }; 190 191 enum mlx5_dev_event { 192 MLX5_DEV_EVENT_SYS_ERROR, 193 MLX5_DEV_EVENT_PORT_UP, 194 MLX5_DEV_EVENT_PORT_DOWN, 195 MLX5_DEV_EVENT_PORT_INITIALIZED, 196 MLX5_DEV_EVENT_LID_CHANGE, 197 MLX5_DEV_EVENT_PKEY_CHANGE, 198 MLX5_DEV_EVENT_GUID_CHANGE, 199 MLX5_DEV_EVENT_CLIENT_REREG, 200 MLX5_DEV_EVENT_VPORT_CHANGE, 201 MLX5_DEV_EVENT_ERROR_STATE_DCBX, 202 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE, 203 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE, 204 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE, 205 }; 206 207 enum mlx5_port_status { 208 MLX5_PORT_UP = 1 << 0, 209 MLX5_PORT_DOWN = 1 << 1, 210 }; 211 212 enum { 213 MLX5_VSC_SPACE_SUPPORTED = 0x1, 214 MLX5_VSC_SPACE_OFFSET = 0x4, 215 MLX5_VSC_COUNTER_OFFSET = 0x8, 216 MLX5_VSC_SEMA_OFFSET = 0xC, 217 MLX5_VSC_ADDR_OFFSET = 0x10, 218 MLX5_VSC_DATA_OFFSET = 0x14, 219 MLX5_VSC_MAX_RETRIES = 0x1000, 220 }; 221 222 #define MLX5_PROT_MASK(link_mode) (1 << link_mode) 223 224 struct mlx5_cmd_first { 225 __be32 data[4]; 226 }; 227 228 struct cache_ent; 229 struct mlx5_fw_page { 230 union { 231 struct rb_node rb_node; 232 struct list_head list; 233 }; 234 struct mlx5_cmd_first first; 235 struct mlx5_core_dev *dev; 236 bus_dmamap_t dma_map; 237 bus_addr_t dma_addr; 238 void *virt_addr; 239 struct cache_ent *cache; 240 u32 numpages; 241 u16 load_done; 242 #define MLX5_LOAD_ST_NONE 0 243 #define MLX5_LOAD_ST_SUCCESS 1 244 #define MLX5_LOAD_ST_FAILURE 2 245 u16 func_id; 246 }; 247 #define mlx5_cmd_msg mlx5_fw_page 248 249 struct mlx5_cmd_debug { 250 struct dentry *dbg_root; 251 struct dentry *dbg_in; 252 struct dentry *dbg_out; 253 struct dentry *dbg_outlen; 254 struct dentry *dbg_status; 255 struct dentry *dbg_run; 256 void *in_msg; 257 void *out_msg; 258 u8 status; 259 u16 inlen; 260 u16 outlen; 261 }; 262 263 struct cache_ent { 264 /* protect block chain allocations 265 */ 266 spinlock_t lock; 267 struct list_head head; 268 }; 269 270 struct cmd_msg_cache { 271 struct cache_ent large; 272 struct cache_ent med; 273 274 }; 275 276 struct mlx5_traffic_counter { 277 u64 packets; 278 u64 octets; 279 }; 280 281 enum mlx5_cmd_mode { 282 MLX5_CMD_MODE_POLLING, 283 MLX5_CMD_MODE_EVENTS 284 }; 285 286 struct mlx5_cmd_stats { 287 u64 sum; 288 u64 n; 289 struct dentry *root; 290 struct dentry *avg; 291 struct dentry *count; 292 /* protect command average calculations */ 293 spinlock_t lock; 294 }; 295 296 struct mlx5_cmd { 297 struct mlx5_fw_page *cmd_page; 298 bus_dma_tag_t dma_tag; 299 struct sx dma_sx; 300 struct mtx dma_mtx; 301 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx) 302 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx) 303 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx) 304 struct cv dma_cv; 305 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv) 306 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx) 307 void *cmd_buf; 308 dma_addr_t dma; 309 u16 cmdif_rev; 310 u8 log_sz; 311 u8 log_stride; 312 int max_reg_cmds; 313 int events; 314 u32 __iomem *vector; 315 316 /* protect command queue allocations 317 */ 318 spinlock_t alloc_lock; 319 320 /* protect token allocations 321 */ 322 spinlock_t token_lock; 323 u8 token; 324 unsigned long bitmask; 325 struct semaphore sem; 326 struct semaphore pages_sem; 327 enum mlx5_cmd_mode mode; 328 struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS]; 329 volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS]; 330 struct mlx5_cmd_debug dbg; 331 struct cmd_msg_cache cache; 332 int checksum_disabled; 333 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; 334 }; 335 336 struct mlx5_port_caps { 337 int gid_table_len; 338 int pkey_table_len; 339 u8 ext_port_cap; 340 }; 341 342 struct mlx5_buf { 343 bus_dma_tag_t dma_tag; 344 bus_dmamap_t dma_map; 345 struct mlx5_core_dev *dev; 346 struct { 347 void *buf; 348 } direct; 349 u64 *page_list; 350 int npages; 351 int size; 352 u8 page_shift; 353 u8 load_done; 354 }; 355 356 struct mlx5_frag_buf { 357 struct mlx5_buf_list *frags; 358 int npages; 359 int size; 360 u8 page_shift; 361 }; 362 363 struct mlx5_eq { 364 struct mlx5_core_dev *dev; 365 __be32 __iomem *doorbell; 366 u32 cons_index; 367 struct mlx5_buf buf; 368 int size; 369 u8 irqn; 370 u8 eqn; 371 int nent; 372 u64 mask; 373 struct list_head list; 374 int index; 375 struct mlx5_rsc_debug *dbg; 376 }; 377 378 struct mlx5_core_psv { 379 u32 psv_idx; 380 struct psv_layout { 381 u32 pd; 382 u16 syndrome; 383 u16 reserved; 384 u16 bg; 385 u16 app_tag; 386 u32 ref_tag; 387 } psv; 388 }; 389 390 struct mlx5_core_sig_ctx { 391 struct mlx5_core_psv psv_memory; 392 struct mlx5_core_psv psv_wire; 393 struct ib_sig_err err_item; 394 bool sig_status_checked; 395 bool sig_err_exists; 396 u32 sigerr_count; 397 }; 398 399 enum { 400 MLX5_MKEY_MR = 1, 401 MLX5_MKEY_MW, 402 MLX5_MKEY_INDIRECT_DEVX, 403 }; 404 405 struct mlx5_core_mkey { 406 u64 iova; 407 u64 size; 408 u32 key; 409 u32 pd; 410 u32 type; 411 }; 412 413 enum mlx5_res_type { 414 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, 415 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, 416 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, 417 MLX5_RES_SRQ = 3, 418 MLX5_RES_XSRQ = 4, 419 MLX5_RES_XRQ = 5, 420 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, 421 }; 422 423 struct mlx5_core_rsc_common { 424 enum mlx5_res_type res; 425 atomic_t refcount; 426 struct completion free; 427 }; 428 429 struct mlx5_uars_page { 430 void __iomem *map; 431 bool wc; 432 u32 index; 433 struct list_head list; 434 unsigned int bfregs; 435 unsigned long *reg_bitmap; /* for non fast path bf regs */ 436 unsigned long *fp_bitmap; 437 unsigned int reg_avail; 438 unsigned int fp_avail; 439 struct kref ref_count; 440 struct mlx5_core_dev *mdev; 441 }; 442 443 struct mlx5_bfreg_head { 444 /* protect blue flame registers allocations */ 445 struct mutex lock; 446 struct list_head list; 447 }; 448 449 struct mlx5_bfreg_data { 450 struct mlx5_bfreg_head reg_head; 451 struct mlx5_bfreg_head wc_head; 452 }; 453 454 struct mlx5_sq_bfreg { 455 void __iomem *map; 456 struct mlx5_uars_page *up; 457 bool wc; 458 u32 index; 459 unsigned int offset; 460 }; 461 462 struct mlx5_core_srq { 463 struct mlx5_core_rsc_common common; /* must be first */ 464 u32 srqn; 465 int max; 466 size_t max_gs; 467 size_t max_avail_gather; 468 int wqe_shift; 469 void (*event)(struct mlx5_core_srq *, int); 470 atomic_t refcount; 471 struct completion free; 472 }; 473 474 struct mlx5_ib_dev; 475 struct mlx5_eq_table { 476 void __iomem *update_ci; 477 void __iomem *update_arm_ci; 478 struct list_head comp_eqs_list; 479 struct mlx5_eq pages_eq; 480 struct mlx5_eq async_eq; 481 struct mlx5_eq cmd_eq; 482 int num_comp_vectors; 483 spinlock_t lock; /* protect EQs list */ 484 struct mlx5_ib_dev *dev; /* for devx event notifier */ 485 bool (*cb)(struct mlx5_core_dev *mdev, 486 uint8_t event_type, void *data); 487 }; 488 489 struct mlx5_core_health { 490 struct mlx5_health_buffer __iomem *health; 491 __be32 __iomem *health_counter; 492 struct timer_list timer; 493 u32 prev; 494 int miss_counter; 495 u32 fatal_error; 496 struct workqueue_struct *wq_watchdog; 497 struct work_struct work_watchdog; 498 /* wq spinlock to synchronize draining */ 499 spinlock_t wq_lock; 500 struct workqueue_struct *wq; 501 unsigned long flags; 502 struct work_struct work; 503 struct delayed_work recover_work; 504 unsigned int last_reset_req; 505 struct work_struct work_cmd_completion; 506 struct workqueue_struct *wq_cmd; 507 }; 508 509 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024 510 511 struct mlx5_cq_linear_array_entry { 512 struct mlx5_core_cq * volatile cq; 513 }; 514 515 struct mlx5_cq_table { 516 /* protect radix tree 517 */ 518 spinlock_t writerlock; 519 atomic_t writercount; 520 struct radix_tree_root tree; 521 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE]; 522 }; 523 524 struct mlx5_qp_table { 525 /* protect radix tree 526 */ 527 spinlock_t lock; 528 struct radix_tree_root tree; 529 }; 530 531 struct mlx5_srq_table { 532 /* protect radix tree 533 */ 534 spinlock_t lock; 535 struct radix_tree_root tree; 536 }; 537 538 struct mlx5_mr_table { 539 /* protect radix tree 540 */ 541 spinlock_t lock; 542 struct radix_tree_root tree; 543 }; 544 545 #ifdef RATELIMIT 546 struct mlx5_rl_entry { 547 u32 rate; 548 u16 burst; 549 u16 index; 550 u32 qos_handle; /* schedule queue handle */ 551 u32 refcount; 552 }; 553 554 struct mlx5_rl_table { 555 struct mutex rl_lock; 556 u16 max_size; 557 u32 max_rate; 558 u32 min_rate; 559 struct mlx5_rl_entry *rl_entry; 560 }; 561 #endif 562 563 struct mlx5_pme_stats { 564 u64 status_counters[MLX5_MODULE_STATUS_NUM]; 565 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM]; 566 }; 567 568 struct mlx5_priv { 569 char name[MLX5_MAX_NAME_LEN]; 570 struct mlx5_eq_table eq_table; 571 struct msix_entry *msix_arr; 572 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); 573 int disable_irqs; 574 575 /* pages stuff */ 576 struct workqueue_struct *pg_wq; 577 struct rb_root page_root; 578 s64 fw_pages; 579 atomic_t reg_pages; 580 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS]; 581 struct mlx5_core_health health; 582 583 struct mlx5_srq_table srq_table; 584 585 /* start: qp staff */ 586 struct mlx5_qp_table qp_table; 587 struct dentry *qp_debugfs; 588 struct dentry *eq_debugfs; 589 struct dentry *cq_debugfs; 590 struct dentry *cmdif_debugfs; 591 /* end: qp staff */ 592 593 /* start: cq staff */ 594 struct mlx5_cq_table cq_table; 595 /* end: cq staff */ 596 597 /* start: mr staff */ 598 struct mlx5_mr_table mr_table; 599 /* end: mr staff */ 600 601 /* start: alloc staff */ 602 int numa_node; 603 604 struct mutex pgdir_mutex; 605 struct list_head pgdir_list; 606 /* end: alloc staff */ 607 struct dentry *dbg_root; 608 609 /* protect mkey key part */ 610 spinlock_t mkey_lock; 611 u8 mkey_key; 612 613 struct list_head dev_list; 614 struct list_head ctx_list; 615 spinlock_t ctx_lock; 616 unsigned long pci_dev_data; 617 #ifdef RATELIMIT 618 struct mlx5_rl_table rl_table; 619 #endif 620 struct mlx5_pme_stats pme_stats; 621 622 struct mlx5_eswitch *eswitch; 623 624 struct mlx5_bfreg_data bfregs; 625 struct mlx5_uars_page *uar; 626 }; 627 628 enum mlx5_device_state { 629 MLX5_DEVICE_STATE_UP, 630 MLX5_DEVICE_STATE_INTERNAL_ERROR, 631 }; 632 633 enum mlx5_interface_state { 634 MLX5_INTERFACE_STATE_UP = 0x1, 635 MLX5_INTERFACE_STATE_TEARDOWN = 0x2, 636 }; 637 638 enum mlx5_pci_status { 639 MLX5_PCI_STATUS_DISABLED, 640 MLX5_PCI_STATUS_ENABLED, 641 }; 642 643 #define MLX5_MAX_RESERVED_GIDS 8 644 645 struct mlx5_rsvd_gids { 646 unsigned int start; 647 unsigned int count; 648 struct ida ida; 649 }; 650 651 struct mlx5_special_contexts { 652 int resd_lkey; 653 }; 654 655 struct mlx5_flow_root_namespace; 656 struct mlx5_core_dev { 657 struct pci_dev *pdev; 658 /* sync pci state */ 659 struct mutex pci_status_mutex; 660 enum mlx5_pci_status pci_status; 661 char board_id[MLX5_BOARD_ID_LEN]; 662 struct mlx5_cmd cmd; 663 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 664 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 665 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; 666 struct { 667 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; 668 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; 669 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; 670 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; 671 } caps; 672 phys_addr_t iseg_base; 673 struct mlx5_init_seg __iomem *iseg; 674 enum mlx5_device_state state; 675 /* sync interface state */ 676 struct mutex intf_state_mutex; 677 unsigned long intf_state; 678 void (*event) (struct mlx5_core_dev *dev, 679 enum mlx5_dev_event event, 680 unsigned long param); 681 struct mlx5_priv priv; 682 struct mlx5_profile *profile; 683 atomic_t num_qps; 684 u32 vsc_addr; 685 u32 issi; 686 struct mlx5_special_contexts special_contexts; 687 unsigned int module_status[MLX5_MAX_PORTS]; 688 struct mlx5_flow_root_namespace *root_ns; 689 struct mlx5_flow_root_namespace *fdb_root_ns; 690 struct mlx5_flow_root_namespace *esw_egress_root_ns; 691 struct mlx5_flow_root_namespace *esw_ingress_root_ns; 692 struct mlx5_flow_root_namespace *sniffer_rx_root_ns; 693 struct mlx5_flow_root_namespace *sniffer_tx_root_ns; 694 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER]; 695 struct mlx5_crspace_regmap *dump_rege; 696 uint32_t *dump_data; 697 unsigned dump_size; 698 bool dump_valid; 699 bool dump_copyout; 700 struct mtx dump_lock; 701 702 struct sysctl_ctx_list sysctl_ctx; 703 int msix_eqvec; 704 int pwr_status; 705 int pwr_value; 706 707 struct { 708 struct mlx5_rsvd_gids reserved_gids; 709 atomic_t roce_en; 710 } roce; 711 712 struct { 713 spinlock_t spinlock; 714 #define MLX5_MPFS_TABLE_MAX 32 715 long bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)]; 716 } mpfs; 717 #ifdef CONFIG_MLX5_FPGA 718 struct mlx5_fpga_device *fpga; 719 #endif 720 }; 721 722 enum { 723 MLX5_WOL_DISABLE = 0, 724 MLX5_WOL_SECURED_MAGIC = 1 << 1, 725 MLX5_WOL_MAGIC = 1 << 2, 726 MLX5_WOL_ARP = 1 << 3, 727 MLX5_WOL_BROADCAST = 1 << 4, 728 MLX5_WOL_MULTICAST = 1 << 5, 729 MLX5_WOL_UNICAST = 1 << 6, 730 MLX5_WOL_PHY_ACTIVITY = 1 << 7, 731 }; 732 733 struct mlx5_db { 734 __be32 *db; 735 union { 736 struct mlx5_db_pgdir *pgdir; 737 struct mlx5_ib_user_db_page *user_page; 738 } u; 739 dma_addr_t dma; 740 int index; 741 }; 742 743 struct mlx5_net_counters { 744 u64 packets; 745 u64 octets; 746 }; 747 748 struct mlx5_ptys_reg { 749 u8 an_dis_admin; 750 u8 an_dis_ap; 751 u8 local_port; 752 u8 proto_mask; 753 u32 eth_proto_cap; 754 u16 ib_link_width_cap; 755 u16 ib_proto_cap; 756 u32 eth_proto_admin; 757 u16 ib_link_width_admin; 758 u16 ib_proto_admin; 759 u32 eth_proto_oper; 760 u16 ib_link_width_oper; 761 u16 ib_proto_oper; 762 u32 eth_proto_lp_advertise; 763 }; 764 765 struct mlx5_pvlc_reg { 766 u8 local_port; 767 u8 vl_hw_cap; 768 u8 vl_admin; 769 u8 vl_operational; 770 }; 771 772 struct mlx5_pmtu_reg { 773 u8 local_port; 774 u16 max_mtu; 775 u16 admin_mtu; 776 u16 oper_mtu; 777 }; 778 779 struct mlx5_vport_counters { 780 struct mlx5_net_counters received_errors; 781 struct mlx5_net_counters transmit_errors; 782 struct mlx5_net_counters received_ib_unicast; 783 struct mlx5_net_counters transmitted_ib_unicast; 784 struct mlx5_net_counters received_ib_multicast; 785 struct mlx5_net_counters transmitted_ib_multicast; 786 struct mlx5_net_counters received_eth_broadcast; 787 struct mlx5_net_counters transmitted_eth_broadcast; 788 struct mlx5_net_counters received_eth_unicast; 789 struct mlx5_net_counters transmitted_eth_unicast; 790 struct mlx5_net_counters received_eth_multicast; 791 struct mlx5_net_counters transmitted_eth_multicast; 792 }; 793 794 enum { 795 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES, 796 }; 797 798 struct mlx5_core_dct { 799 struct mlx5_core_rsc_common common; /* must be first */ 800 void (*event)(struct mlx5_core_dct *, int); 801 int dctn; 802 struct completion drained; 803 struct mlx5_rsc_debug *dbg; 804 int pid; 805 u16 uid; 806 }; 807 808 enum { 809 MLX5_COMP_EQ_SIZE = 1024, 810 }; 811 812 enum { 813 MLX5_PTYS_IB = 1 << 0, 814 MLX5_PTYS_EN = 1 << 2, 815 }; 816 817 struct mlx5_db_pgdir { 818 struct list_head list; 819 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); 820 struct mlx5_fw_page *fw_page; 821 __be32 *db_page; 822 dma_addr_t db_dma; 823 }; 824 825 typedef void (*mlx5_cmd_cbk_t)(int status, void *context); 826 827 struct mlx5_cmd_work_ent { 828 struct mlx5_cmd_msg *in; 829 struct mlx5_cmd_msg *out; 830 int uin_size; 831 void *uout; 832 int uout_size; 833 mlx5_cmd_cbk_t callback; 834 struct delayed_work cb_timeout_work; 835 void *context; 836 int idx; 837 struct completion done; 838 struct mlx5_cmd *cmd; 839 struct work_struct work; 840 struct mlx5_cmd_layout *lay; 841 int ret; 842 int page_queue; 843 u8 status; 844 u8 token; 845 u64 ts1; 846 u64 ts2; 847 u16 op; 848 u8 busy; 849 bool polling; 850 }; 851 852 struct mlx5_pas { 853 u64 pa; 854 u8 log_sz; 855 }; 856 857 enum port_state_policy { 858 MLX5_POLICY_DOWN = 0, 859 MLX5_POLICY_UP = 1, 860 MLX5_POLICY_FOLLOW = 2, 861 MLX5_POLICY_INVALID = 0xffffffff 862 }; 863 864 static inline void * 865 mlx5_buf_offset(struct mlx5_buf *buf, int offset) 866 { 867 return ((char *)buf->direct.buf + offset); 868 } 869 870 871 extern struct workqueue_struct *mlx5_core_wq; 872 873 #define STRUCT_FIELD(header, field) \ 874 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ 875 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field 876 877 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) 878 { 879 return pci_get_drvdata(pdev); 880 } 881 882 extern struct dentry *mlx5_debugfs_root; 883 884 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) 885 { 886 return ioread32be(&dev->iseg->fw_rev) & 0xffff; 887 } 888 889 static inline u16 fw_rev_min(struct mlx5_core_dev *dev) 890 { 891 return ioread32be(&dev->iseg->fw_rev) >> 16; 892 } 893 894 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) 895 { 896 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; 897 } 898 899 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev) 900 { 901 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 902 } 903 904 static inline int mlx5_get_gid_table_len(u16 param) 905 { 906 if (param > 4) { 907 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n"); 908 return 0; 909 } 910 911 return 8 * (1 << param); 912 } 913 914 static inline void *mlx5_vzalloc(unsigned long size) 915 { 916 void *rtn; 917 918 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); 919 return rtn; 920 } 921 922 static inline void *mlx5_vmalloc(unsigned long size) 923 { 924 void *rtn; 925 926 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN); 927 if (!rtn) 928 rtn = vmalloc(size); 929 return rtn; 930 } 931 932 static inline u32 mlx5_base_mkey(const u32 key) 933 { 934 return key & 0xffffff00u; 935 } 936 937 int mlx5_cmd_init(struct mlx5_core_dev *dev); 938 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 939 void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 940 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 941 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); 942 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); 943 944 struct mlx5_async_ctx { 945 struct mlx5_core_dev *dev; 946 atomic_t num_inflight; 947 struct wait_queue_head wait; 948 }; 949 950 struct mlx5_async_work; 951 952 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); 953 954 struct mlx5_async_work { 955 struct mlx5_async_ctx *ctx; 956 mlx5_async_cbk_t user_callback; 957 }; 958 959 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 960 struct mlx5_async_ctx *ctx); 961 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); 962 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 963 void *out, int out_size, mlx5_async_cbk_t callback, 964 struct mlx5_async_work *work); 965 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 966 int out_size); 967 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 968 void *out, int out_size); 969 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 970 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 971 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, 972 bool map_wc, bool fast_path); 973 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); 974 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); 975 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); 976 void mlx5_health_cleanup(struct mlx5_core_dev *dev); 977 int mlx5_health_init(struct mlx5_core_dev *dev); 978 void mlx5_start_health_poll(struct mlx5_core_dev *dev); 979 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); 980 void mlx5_drain_health_wq(struct mlx5_core_dev *dev); 981 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev); 982 void mlx5_trigger_health_work(struct mlx5_core_dev *dev); 983 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev); 984 985 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, 986 struct mlx5_buf *buf); 987 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); 988 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 989 struct mlx5_srq_attr *in); 990 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); 991 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 992 struct mlx5_srq_attr *out); 993 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 994 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, 995 u16 lwm, int is_srq); 996 void mlx5_init_mr_table(struct mlx5_core_dev *dev); 997 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); 998 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, 999 struct mlx5_core_mkey *mkey, 1000 struct mlx5_async_ctx *async_ctx, u32 *in, 1001 int inlen, u32 *out, int outlen, 1002 mlx5_async_cbk_t callback, 1003 struct mlx5_async_work *context); 1004 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 1005 struct mlx5_core_mkey *mr, 1006 u32 *in, int inlen); 1007 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey); 1008 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 1009 u32 *out, int outlen); 1010 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mr, 1011 u32 *mkey); 1012 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn, u16 uid); 1013 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn, u16 uid); 1014 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, 1015 u16 opmod, u8 port); 1016 void mlx5_fwp_flush(struct mlx5_fw_page *fwp); 1017 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp); 1018 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num); 1019 void mlx5_fwp_free(struct mlx5_fw_page *fwp); 1020 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset); 1021 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset); 1022 void mlx5_pagealloc_init(struct mlx5_core_dev *dev); 1023 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 1024 int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 1025 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 1026 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 1027 s32 npages); 1028 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 1029 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); 1030 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev); 1031 void mlx5_register_debugfs(void); 1032 void mlx5_unregister_debugfs(void); 1033 int mlx5_eq_init(struct mlx5_core_dev *dev); 1034 void mlx5_eq_cleanup(struct mlx5_core_dev *dev); 1035 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); 1036 void mlx5_cq_completion(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); 1037 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); 1038 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); 1039 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); 1040 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode); 1041 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); 1042 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 1043 int nent, u64 mask); 1044 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1045 int mlx5_start_eqs(struct mlx5_core_dev *dev); 1046 int mlx5_stop_eqs(struct mlx5_core_dev *dev); 1047 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); 1048 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1049 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); 1050 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable, 1051 u64 addr); 1052 1053 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); 1054 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); 1055 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, 1056 int size_in, void *data_out, int size_out, 1057 u16 reg_num, int arg, int write); 1058 1059 void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 1060 1061 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1062 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 1063 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 1064 u32 *out, int outlen); 1065 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 1066 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 1067 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 1068 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); 1069 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); 1070 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); 1071 1072 static inline struct domainset * 1073 mlx5_dev_domainset(struct mlx5_core_dev *mdev) 1074 { 1075 return (linux_get_vm_domain_set(mdev->priv.numa_node)); 1076 } 1077 1078 const char *mlx5_command_str(int command); 1079 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); 1080 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); 1081 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, 1082 int npsvs, u32 *sig_index); 1083 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); 1084 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); 1085 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev); 1086 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode); 1087 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout); 1088 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout); 1089 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode); 1090 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev, 1091 struct mlx5_pvlc_reg *pvlc, int write); 1092 int mlx5_core_access_ptys(struct mlx5_core_dev *dev, 1093 struct mlx5_ptys_reg *ptys, int write); 1094 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev, 1095 struct mlx5_pmtu_reg *pmtu, int write); 1096 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port); 1097 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port); 1098 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1099 int priority, int *is_enable); 1100 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol, 1101 int priority, int enable); 1102 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol, 1103 void *out, int out_size); 1104 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev, 1105 void *in, int in_size); 1106 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear, 1107 void *out, int out_size); 1108 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in, 1109 int in_size); 1110 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev, 1111 u8 num_of_samples, u16 sample_index, 1112 void *out, int out_size); 1113 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev); 1114 int mlx5_vsc_lock(struct mlx5_core_dev *mdev); 1115 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev); 1116 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space); 1117 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected); 1118 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data); 1119 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data); 1120 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1121 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr); 1122 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev, 1123 u16 *p_power, u8 *p_status); 1124 1125 static inline u32 mlx5_mkey_to_idx(u32 mkey) 1126 { 1127 return mkey >> 8; 1128 } 1129 1130 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) 1131 { 1132 return mkey_idx << 8; 1133 } 1134 1135 static inline u8 mlx5_mkey_variant(u32 mkey) 1136 { 1137 return mkey & 0xff; 1138 } 1139 1140 enum { 1141 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, 1142 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, 1143 }; 1144 1145 enum { 1146 MAX_MR_CACHE_ENTRIES = 15, 1147 }; 1148 1149 struct mlx5_interface { 1150 void * (*add)(struct mlx5_core_dev *dev); 1151 void (*remove)(struct mlx5_core_dev *dev, void *context); 1152 void (*event)(struct mlx5_core_dev *dev, void *context, 1153 enum mlx5_dev_event event, unsigned long param); 1154 void * (*get_dev)(void *context); 1155 int protocol; 1156 struct list_head list; 1157 }; 1158 1159 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); 1160 int mlx5_register_interface(struct mlx5_interface *intf); 1161 void mlx5_unregister_interface(struct mlx5_interface *intf); 1162 1163 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); 1164 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, 1165 u8 roce_version, u8 roce_l3_type, const u8 *gid, 1166 const u8 *mac, bool vlan, u16 vlan_id); 1167 1168 struct mlx5_profile { 1169 u64 mask; 1170 u8 log_max_qp; 1171 struct { 1172 int size; 1173 int limit; 1174 } mr_cache[MAX_MR_CACHE_ENTRIES]; 1175 }; 1176 1177 enum { 1178 MLX5_PCI_DEV_IS_VF = 1 << 0, 1179 }; 1180 1181 enum { 1182 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, 1183 }; 1184 1185 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) 1186 { 1187 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); 1188 } 1189 #ifdef RATELIMIT 1190 int mlx5_init_rl_table(struct mlx5_core_dev *dev); 1191 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); 1192 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index); 1193 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst); 1194 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst); 1195 int mlx5e_query_rate_limit_cmd(struct mlx5_core_dev *dev, u16 index, u32 *scq_handle); 1196 1197 static inline u32 mlx5_rl_get_scq_handle(struct mlx5_core_dev *dev, uint16_t index) 1198 { 1199 KASSERT(index > 0, 1200 ("invalid rate index for sq remap, failed retrieving SCQ handle")); 1201 1202 return (dev->priv.rl_table.rl_entry[index - 1].qos_handle); 1203 } 1204 1205 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) 1206 { 1207 return !!(dev->priv.rl_table.max_size); 1208 } 1209 #endif 1210 1211 void mlx5_disable_interrupts(struct mlx5_core_dev *); 1212 void mlx5_poll_interrupts(struct mlx5_core_dev *); 1213 1214 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev) 1215 { 1216 return !MLX5_CAP_ROCE(dev, qp_ts_format) ? 1217 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING : 1218 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT; 1219 } 1220 1221 static inline int mlx5_get_rq_default_ts(struct mlx5_core_dev *dev) 1222 { 1223 return !MLX5_CAP_GEN(dev, rq_ts_format) ? 1224 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING : 1225 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT; 1226 } 1227 1228 static inline int mlx5_get_sq_default_ts(struct mlx5_core_dev *dev) 1229 { 1230 return !MLX5_CAP_GEN(dev, sq_ts_format) ? 1231 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING : 1232 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT; 1233 } 1234 1235 #endif /* MLX5_DRIVER_H */
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