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sys/dev/mlx5/mlx5_core/mlx5_cmd.c
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1 /*- 2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28 #include "opt_rss.h" 29 #include "opt_ratelimit.h" 30 31 #include <linux/module.h> 32 #include <linux/errno.h> 33 #include <linux/pci.h> 34 #include <linux/dma-mapping.h> 35 #include <linux/slab.h> 36 #include <linux/delay.h> 37 #include <linux/random.h> 38 #include <linux/io-mapping.h> 39 #include <linux/hardirq.h> 40 #include <linux/ktime.h> 41 #include <dev/mlx5/driver.h> 42 #include <dev/mlx5/cmd.h> 43 #include <dev/mlx5/mlx5_core/mlx5_core.h> 44 45 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size); 46 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev, 47 struct mlx5_cmd_msg *msg); 48 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg); 49 50 enum { 51 CMD_IF_REV = 5, 52 }; 53 54 enum { 55 NUM_LONG_LISTS = 2, 56 NUM_MED_LISTS = 64, 57 LONG_LIST_SIZE = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 + 58 MLX5_CMD_DATA_BLOCK_SIZE, 59 MED_LIST_SIZE = 16 + MLX5_CMD_DATA_BLOCK_SIZE, 60 }; 61 62 enum { 63 MLX5_CMD_DELIVERY_STAT_OK = 0x0, 64 MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR = 0x1, 65 MLX5_CMD_DELIVERY_STAT_TOK_ERR = 0x2, 66 MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR = 0x3, 67 MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR = 0x4, 68 MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR = 0x5, 69 MLX5_CMD_DELIVERY_STAT_FW_ERR = 0x6, 70 MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR = 0x7, 71 MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR = 0x8, 72 MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR = 0x9, 73 MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR = 0x10, 74 }; 75 76 struct mlx5_ifc_mbox_out_bits { 77 u8 status[0x8]; 78 u8 reserved_at_8[0x18]; 79 80 u8 syndrome[0x20]; 81 82 u8 reserved_at_40[0x40]; 83 }; 84 85 struct mlx5_ifc_mbox_in_bits { 86 u8 opcode[0x10]; 87 u8 reserved_at_10[0x10]; 88 89 u8 reserved_at_20[0x10]; 90 u8 op_mod[0x10]; 91 92 u8 reserved_at_40[0x40]; 93 }; 94 95 96 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd, 97 struct mlx5_cmd_msg *in, 98 int uin_size, 99 struct mlx5_cmd_msg *out, 100 void *uout, int uout_size, 101 mlx5_cmd_cbk_t cbk, 102 void *context, int page_queue) 103 { 104 gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL; 105 struct mlx5_cmd_work_ent *ent; 106 107 ent = kzalloc(sizeof(*ent), alloc_flags); 108 if (!ent) 109 return ERR_PTR(-ENOMEM); 110 111 ent->in = in; 112 ent->uin_size = uin_size; 113 ent->out = out; 114 ent->uout = uout; 115 ent->uout_size = uout_size; 116 ent->callback = cbk; 117 ent->context = context; 118 ent->cmd = cmd; 119 ent->page_queue = page_queue; 120 121 return ent; 122 } 123 124 static u8 alloc_token(struct mlx5_cmd *cmd) 125 { 126 u8 token; 127 128 spin_lock(&cmd->token_lock); 129 cmd->token++; 130 if (cmd->token == 0) 131 cmd->token++; 132 token = cmd->token; 133 spin_unlock(&cmd->token_lock); 134 135 return token; 136 } 137 138 static int alloc_ent(struct mlx5_cmd_work_ent *ent) 139 { 140 unsigned long flags; 141 struct mlx5_cmd *cmd = ent->cmd; 142 struct mlx5_core_dev *dev = 143 container_of(cmd, struct mlx5_core_dev, cmd); 144 int ret = cmd->max_reg_cmds; 145 146 spin_lock_irqsave(&cmd->alloc_lock, flags); 147 if (!ent->page_queue) { 148 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds); 149 if (ret >= cmd->max_reg_cmds) 150 ret = -1; 151 } 152 153 if (dev->state != MLX5_DEVICE_STATE_UP) 154 ret = -1; 155 156 if (ret != -1) { 157 ent->busy = 1; 158 ent->idx = ret; 159 clear_bit(ent->idx, &cmd->bitmask); 160 cmd->ent_mode[ent->idx] = 161 ent->polling ? MLX5_CMD_MODE_POLLING : MLX5_CMD_MODE_EVENTS; 162 cmd->ent_arr[ent->idx] = ent; 163 } 164 spin_unlock_irqrestore(&cmd->alloc_lock, flags); 165 166 return ret; 167 } 168 169 static void free_ent(struct mlx5_cmd *cmd, int idx) 170 { 171 unsigned long flags; 172 173 spin_lock_irqsave(&cmd->alloc_lock, flags); 174 cmd->ent_arr[idx] = NULL; /* safety clear */ 175 cmd->ent_mode[idx] = MLX5_CMD_MODE_POLLING; /* reset mode */ 176 set_bit(idx, &cmd->bitmask); 177 spin_unlock_irqrestore(&cmd->alloc_lock, flags); 178 } 179 180 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx) 181 { 182 return cmd->cmd_buf + (idx << cmd->log_stride); 183 } 184 185 static u8 xor8_buf(void *buf, int len) 186 { 187 u8 *ptr = buf; 188 u8 sum = 0; 189 int i; 190 191 for (i = 0; i < len; i++) 192 sum ^= ptr[i]; 193 194 return sum; 195 } 196 197 static int verify_block_sig(struct mlx5_cmd_prot_block *block) 198 { 199 if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff) 200 return -EINVAL; 201 202 if (xor8_buf(block, sizeof(*block)) != 0xff) 203 return -EINVAL; 204 205 return 0; 206 } 207 208 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token, 209 int csum) 210 { 211 block->token = token; 212 if (csum) { 213 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) - 214 sizeof(block->data) - 2); 215 block->sig = ~xor8_buf(block, sizeof(*block) - 1); 216 } 217 } 218 219 static void 220 calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum) 221 { 222 size_t i; 223 224 for (i = 0; i != (msg->numpages * MLX5_NUM_CMDS_IN_ADAPTER_PAGE); i++) { 225 struct mlx5_cmd_prot_block *block; 226 227 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 228 229 /* compute signature */ 230 calc_block_sig(block, token, csum); 231 232 /* check for last block */ 233 if (block->next == 0) 234 break; 235 } 236 237 /* make sure data gets written to RAM */ 238 mlx5_fwp_flush(msg); 239 } 240 241 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum) 242 { 243 ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay)); 244 calc_chain_sig(ent->in, ent->token, csum); 245 calc_chain_sig(ent->out, ent->token, csum); 246 } 247 248 static void poll_timeout(struct mlx5_cmd_work_ent *ent) 249 { 250 struct mlx5_core_dev *dev = container_of(ent->cmd, 251 struct mlx5_core_dev, cmd); 252 int poll_end = jiffies + 253 msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000); 254 u8 own; 255 256 do { 257 own = ent->lay->status_own; 258 if (!(own & CMD_OWNER_HW) || 259 dev->state != MLX5_DEVICE_STATE_UP) { 260 ent->ret = 0; 261 return; 262 } 263 usleep_range(5000, 10000); 264 } while (time_before(jiffies, poll_end)); 265 266 ent->ret = -ETIMEDOUT; 267 } 268 269 static void free_cmd(struct mlx5_cmd_work_ent *ent) 270 { 271 cancel_delayed_work_sync(&ent->cb_timeout_work); 272 kfree(ent); 273 } 274 275 static int 276 verify_signature(struct mlx5_cmd_work_ent *ent) 277 { 278 struct mlx5_cmd_msg *msg = ent->out; 279 size_t i; 280 int err; 281 u8 sig; 282 283 sig = xor8_buf(ent->lay, sizeof(*ent->lay)); 284 if (sig != 0xff) 285 return -EINVAL; 286 287 for (i = 0; i != (msg->numpages * MLX5_NUM_CMDS_IN_ADAPTER_PAGE); i++) { 288 struct mlx5_cmd_prot_block *block; 289 290 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 291 292 /* compute signature */ 293 err = verify_block_sig(block); 294 if (err != 0) 295 return (err); 296 297 /* check for last block */ 298 if (block->next == 0) 299 break; 300 } 301 return (0); 302 } 303 304 static void dump_buf(void *buf, int size, int data_only, int offset) 305 { 306 __be32 *p = buf; 307 int i; 308 309 for (i = 0; i < size; i += 16) { 310 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]), 311 be32_to_cpu(p[1]), be32_to_cpu(p[2]), 312 be32_to_cpu(p[3])); 313 p += 4; 314 offset += 16; 315 } 316 if (!data_only) 317 pr_debug("\n"); 318 } 319 320 enum { 321 MLX5_DRIVER_STATUS_ABORTED = 0xfe, 322 MLX5_DRIVER_SYND = 0xbadd00de, 323 }; 324 325 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op, 326 u32 *synd, u8 *status) 327 { 328 *synd = 0; 329 *status = 0; 330 331 switch (op) { 332 case MLX5_CMD_OP_TEARDOWN_HCA: 333 case MLX5_CMD_OP_DISABLE_HCA: 334 case MLX5_CMD_OP_MANAGE_PAGES: 335 case MLX5_CMD_OP_DESTROY_MKEY: 336 case MLX5_CMD_OP_DESTROY_EQ: 337 case MLX5_CMD_OP_DESTROY_CQ: 338 case MLX5_CMD_OP_DESTROY_QP: 339 case MLX5_CMD_OP_DESTROY_PSV: 340 case MLX5_CMD_OP_DESTROY_SRQ: 341 case MLX5_CMD_OP_DESTROY_XRC_SRQ: 342 case MLX5_CMD_OP_DESTROY_DCT: 343 case MLX5_CMD_OP_DEALLOC_Q_COUNTER: 344 case MLX5_CMD_OP_DEALLOC_PD: 345 case MLX5_CMD_OP_DEALLOC_UAR: 346 case MLX5_CMD_OP_DETACH_FROM_MCG: 347 case MLX5_CMD_OP_DEALLOC_XRCD: 348 case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN: 349 case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT: 350 case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY: 351 case MLX5_CMD_OP_DESTROY_TIR: 352 case MLX5_CMD_OP_DESTROY_SQ: 353 case MLX5_CMD_OP_DESTROY_RQ: 354 case MLX5_CMD_OP_DESTROY_RMP: 355 case MLX5_CMD_OP_DESTROY_TIS: 356 case MLX5_CMD_OP_DESTROY_RQT: 357 case MLX5_CMD_OP_DESTROY_FLOW_TABLE: 358 case MLX5_CMD_OP_DESTROY_FLOW_GROUP: 359 case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY: 360 case MLX5_CMD_OP_2ERR_QP: 361 case MLX5_CMD_OP_2RST_QP: 362 case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT: 363 case MLX5_CMD_OP_MODIFY_FLOW_TABLE: 364 case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY: 365 case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT: 366 case MLX5_CMD_OP_DESTROY_GENERAL_OBJ: 367 return MLX5_CMD_STAT_OK; 368 369 case MLX5_CMD_OP_QUERY_HCA_CAP: 370 case MLX5_CMD_OP_QUERY_ADAPTER: 371 case MLX5_CMD_OP_INIT_HCA: 372 case MLX5_CMD_OP_ENABLE_HCA: 373 case MLX5_CMD_OP_QUERY_PAGES: 374 case MLX5_CMD_OP_SET_HCA_CAP: 375 case MLX5_CMD_OP_QUERY_ISSI: 376 case MLX5_CMD_OP_SET_ISSI: 377 case MLX5_CMD_OP_CREATE_MKEY: 378 case MLX5_CMD_OP_QUERY_MKEY: 379 case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS: 380 case MLX5_CMD_OP_PAGE_FAULT_RESUME: 381 case MLX5_CMD_OP_CREATE_EQ: 382 case MLX5_CMD_OP_QUERY_EQ: 383 case MLX5_CMD_OP_GEN_EQE: 384 case MLX5_CMD_OP_CREATE_CQ: 385 case MLX5_CMD_OP_QUERY_CQ: 386 case MLX5_CMD_OP_MODIFY_CQ: 387 case MLX5_CMD_OP_CREATE_QP: 388 case MLX5_CMD_OP_RST2INIT_QP: 389 case MLX5_CMD_OP_INIT2RTR_QP: 390 case MLX5_CMD_OP_RTR2RTS_QP: 391 case MLX5_CMD_OP_RTS2RTS_QP: 392 case MLX5_CMD_OP_SQERR2RTS_QP: 393 case MLX5_CMD_OP_QUERY_QP: 394 case MLX5_CMD_OP_SQD_RTS_QP: 395 case MLX5_CMD_OP_INIT2INIT_QP: 396 case MLX5_CMD_OP_CREATE_PSV: 397 case MLX5_CMD_OP_CREATE_SRQ: 398 case MLX5_CMD_OP_QUERY_SRQ: 399 case MLX5_CMD_OP_ARM_RQ: 400 case MLX5_CMD_OP_CREATE_XRC_SRQ: 401 case MLX5_CMD_OP_QUERY_XRC_SRQ: 402 case MLX5_CMD_OP_ARM_XRC_SRQ: 403 case MLX5_CMD_OP_CREATE_DCT: 404 case MLX5_CMD_OP_DRAIN_DCT: 405 case MLX5_CMD_OP_QUERY_DCT: 406 case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION: 407 case MLX5_CMD_OP_QUERY_VPORT_STATE: 408 case MLX5_CMD_OP_MODIFY_VPORT_STATE: 409 case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT: 410 case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT: 411 case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT: 412 case MLX5_CMD_OP_QUERY_ROCE_ADDRESS: 413 case MLX5_CMD_OP_SET_ROCE_ADDRESS: 414 case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT: 415 case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT: 416 case MLX5_CMD_OP_QUERY_HCA_VPORT_GID: 417 case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY: 418 case MLX5_CMD_OP_QUERY_VNIC_ENV: 419 case MLX5_CMD_OP_QUERY_VPORT_COUNTER: 420 case MLX5_CMD_OP_ALLOC_Q_COUNTER: 421 case MLX5_CMD_OP_QUERY_Q_COUNTER: 422 case MLX5_CMD_OP_ALLOC_PD: 423 case MLX5_CMD_OP_ALLOC_UAR: 424 case MLX5_CMD_OP_CONFIG_INT_MODERATION: 425 case MLX5_CMD_OP_ACCESS_REG: 426 case MLX5_CMD_OP_ATTACH_TO_MCG: 427 case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG: 428 case MLX5_CMD_OP_MAD_IFC: 429 case MLX5_CMD_OP_QUERY_MAD_DEMUX: 430 case MLX5_CMD_OP_SET_MAD_DEMUX: 431 case MLX5_CMD_OP_NOP: 432 case MLX5_CMD_OP_ALLOC_XRCD: 433 case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN: 434 case MLX5_CMD_OP_QUERY_CONG_STATUS: 435 case MLX5_CMD_OP_MODIFY_CONG_STATUS: 436 case MLX5_CMD_OP_QUERY_CONG_PARAMS: 437 case MLX5_CMD_OP_MODIFY_CONG_PARAMS: 438 case MLX5_CMD_OP_QUERY_CONG_STATISTICS: 439 case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT: 440 case MLX5_CMD_OP_SET_L2_TABLE_ENTRY: 441 case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY: 442 case MLX5_CMD_OP_CREATE_TIR: 443 case MLX5_CMD_OP_MODIFY_TIR: 444 case MLX5_CMD_OP_QUERY_TIR: 445 case MLX5_CMD_OP_CREATE_SQ: 446 case MLX5_CMD_OP_MODIFY_SQ: 447 case MLX5_CMD_OP_QUERY_SQ: 448 case MLX5_CMD_OP_CREATE_RQ: 449 case MLX5_CMD_OP_MODIFY_RQ: 450 case MLX5_CMD_OP_QUERY_RQ: 451 case MLX5_CMD_OP_CREATE_RMP: 452 case MLX5_CMD_OP_MODIFY_RMP: 453 case MLX5_CMD_OP_QUERY_RMP: 454 case MLX5_CMD_OP_CREATE_TIS: 455 case MLX5_CMD_OP_MODIFY_TIS: 456 case MLX5_CMD_OP_QUERY_TIS: 457 case MLX5_CMD_OP_CREATE_RQT: 458 case MLX5_CMD_OP_MODIFY_RQT: 459 case MLX5_CMD_OP_QUERY_RQT: 460 case MLX5_CMD_OP_CREATE_FLOW_TABLE: 461 case MLX5_CMD_OP_QUERY_FLOW_TABLE: 462 case MLX5_CMD_OP_CREATE_FLOW_GROUP: 463 case MLX5_CMD_OP_QUERY_FLOW_GROUP: 464 case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY: 465 case MLX5_CMD_OP_CREATE_GENERAL_OBJ: 466 case MLX5_CMD_OP_MODIFY_GENERAL_OBJ: 467 case MLX5_CMD_OP_QUERY_GENERAL_OBJ: 468 *status = MLX5_DRIVER_STATUS_ABORTED; 469 *synd = MLX5_DRIVER_SYND; 470 return -EIO; 471 default: 472 mlx5_core_err(dev, "Unknown FW command (%d)\n", op); 473 return -EINVAL; 474 } 475 } 476 477 const char *mlx5_command_str(int command) 478 { 479 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd 480 481 switch (command) { 482 MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP); 483 MLX5_COMMAND_STR_CASE(SET_HCA_CAP); 484 MLX5_COMMAND_STR_CASE(QUERY_ADAPTER); 485 MLX5_COMMAND_STR_CASE(INIT_HCA); 486 MLX5_COMMAND_STR_CASE(TEARDOWN_HCA); 487 MLX5_COMMAND_STR_CASE(ENABLE_HCA); 488 MLX5_COMMAND_STR_CASE(DISABLE_HCA); 489 MLX5_COMMAND_STR_CASE(QUERY_PAGES); 490 MLX5_COMMAND_STR_CASE(MANAGE_PAGES); 491 MLX5_COMMAND_STR_CASE(QUERY_ISSI); 492 MLX5_COMMAND_STR_CASE(SET_ISSI); 493 MLX5_COMMAND_STR_CASE(CREATE_MKEY); 494 MLX5_COMMAND_STR_CASE(QUERY_MKEY); 495 MLX5_COMMAND_STR_CASE(DESTROY_MKEY); 496 MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS); 497 MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME); 498 MLX5_COMMAND_STR_CASE(CREATE_EQ); 499 MLX5_COMMAND_STR_CASE(DESTROY_EQ); 500 MLX5_COMMAND_STR_CASE(QUERY_EQ); 501 MLX5_COMMAND_STR_CASE(GEN_EQE); 502 MLX5_COMMAND_STR_CASE(CREATE_CQ); 503 MLX5_COMMAND_STR_CASE(DESTROY_CQ); 504 MLX5_COMMAND_STR_CASE(QUERY_CQ); 505 MLX5_COMMAND_STR_CASE(MODIFY_CQ); 506 MLX5_COMMAND_STR_CASE(CREATE_QP); 507 MLX5_COMMAND_STR_CASE(DESTROY_QP); 508 MLX5_COMMAND_STR_CASE(RST2INIT_QP); 509 MLX5_COMMAND_STR_CASE(INIT2RTR_QP); 510 MLX5_COMMAND_STR_CASE(RTR2RTS_QP); 511 MLX5_COMMAND_STR_CASE(RTS2RTS_QP); 512 MLX5_COMMAND_STR_CASE(SQERR2RTS_QP); 513 MLX5_COMMAND_STR_CASE(2ERR_QP); 514 MLX5_COMMAND_STR_CASE(2RST_QP); 515 MLX5_COMMAND_STR_CASE(QUERY_QP); 516 MLX5_COMMAND_STR_CASE(SQD_RTS_QP); 517 MLX5_COMMAND_STR_CASE(MAD_IFC); 518 MLX5_COMMAND_STR_CASE(INIT2INIT_QP); 519 MLX5_COMMAND_STR_CASE(CREATE_PSV); 520 MLX5_COMMAND_STR_CASE(DESTROY_PSV); 521 MLX5_COMMAND_STR_CASE(CREATE_SRQ); 522 MLX5_COMMAND_STR_CASE(DESTROY_SRQ); 523 MLX5_COMMAND_STR_CASE(QUERY_SRQ); 524 MLX5_COMMAND_STR_CASE(ARM_RQ); 525 MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ); 526 MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ); 527 MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ); 528 MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ); 529 MLX5_COMMAND_STR_CASE(CREATE_DCT); 530 MLX5_COMMAND_STR_CASE(SET_DC_CNAK_TRACE); 531 MLX5_COMMAND_STR_CASE(DESTROY_DCT); 532 MLX5_COMMAND_STR_CASE(DRAIN_DCT); 533 MLX5_COMMAND_STR_CASE(QUERY_DCT); 534 MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION); 535 MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE); 536 MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE); 537 MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT); 538 MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT); 539 MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT); 540 MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT); 541 MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS); 542 MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS); 543 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT); 544 MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT); 545 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID); 546 MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY); 547 MLX5_COMMAND_STR_CASE(QUERY_VNIC_ENV); 548 MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER); 549 MLX5_COMMAND_STR_CASE(SET_WOL_ROL); 550 MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL); 551 MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER); 552 MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER); 553 MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER); 554 MLX5_COMMAND_STR_CASE(ALLOC_PD); 555 MLX5_COMMAND_STR_CASE(DEALLOC_PD); 556 MLX5_COMMAND_STR_CASE(ALLOC_UAR); 557 MLX5_COMMAND_STR_CASE(DEALLOC_UAR); 558 MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION); 559 MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG); 560 MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG); 561 MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG); 562 MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX); 563 MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX); 564 MLX5_COMMAND_STR_CASE(NOP); 565 MLX5_COMMAND_STR_CASE(ALLOC_XRCD); 566 MLX5_COMMAND_STR_CASE(DEALLOC_XRCD); 567 MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN); 568 MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN); 569 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS); 570 MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS); 571 MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS); 572 MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS); 573 MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS); 574 MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT); 575 MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT); 576 MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY); 577 MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY); 578 MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY); 579 MLX5_COMMAND_STR_CASE(CREATE_RMP); 580 MLX5_COMMAND_STR_CASE(MODIFY_RMP); 581 MLX5_COMMAND_STR_CASE(DESTROY_RMP); 582 MLX5_COMMAND_STR_CASE(QUERY_RMP); 583 MLX5_COMMAND_STR_CASE(CREATE_RQT); 584 MLX5_COMMAND_STR_CASE(MODIFY_RQT); 585 MLX5_COMMAND_STR_CASE(DESTROY_RQT); 586 MLX5_COMMAND_STR_CASE(QUERY_RQT); 587 MLX5_COMMAND_STR_CASE(ACCESS_REG); 588 MLX5_COMMAND_STR_CASE(CREATE_SQ); 589 MLX5_COMMAND_STR_CASE(MODIFY_SQ); 590 MLX5_COMMAND_STR_CASE(DESTROY_SQ); 591 MLX5_COMMAND_STR_CASE(QUERY_SQ); 592 MLX5_COMMAND_STR_CASE(CREATE_RQ); 593 MLX5_COMMAND_STR_CASE(MODIFY_RQ); 594 MLX5_COMMAND_STR_CASE(DESTROY_RQ); 595 MLX5_COMMAND_STR_CASE(QUERY_RQ); 596 MLX5_COMMAND_STR_CASE(CREATE_TIR); 597 MLX5_COMMAND_STR_CASE(MODIFY_TIR); 598 MLX5_COMMAND_STR_CASE(DESTROY_TIR); 599 MLX5_COMMAND_STR_CASE(QUERY_TIR); 600 MLX5_COMMAND_STR_CASE(CREATE_TIS); 601 MLX5_COMMAND_STR_CASE(MODIFY_TIS); 602 MLX5_COMMAND_STR_CASE(DESTROY_TIS); 603 MLX5_COMMAND_STR_CASE(QUERY_TIS); 604 MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE); 605 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE); 606 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE); 607 MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP); 608 MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP); 609 MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP); 610 MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY); 611 MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY); 612 MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY); 613 MLX5_COMMAND_STR_CASE(SET_DIAGNOSTICS); 614 MLX5_COMMAND_STR_CASE(QUERY_DIAGNOSTICS); 615 MLX5_COMMAND_STR_CASE(CREATE_GENERAL_OBJ); 616 MLX5_COMMAND_STR_CASE(MODIFY_GENERAL_OBJ); 617 MLX5_COMMAND_STR_CASE(QUERY_GENERAL_OBJ); 618 MLX5_COMMAND_STR_CASE(DESTROY_GENERAL_OBJ); 619 default: return "unknown command opcode"; 620 } 621 } 622 623 static const char *cmd_status_str(u8 status) 624 { 625 switch (status) { 626 case MLX5_CMD_STAT_OK: 627 return "OK"; 628 case MLX5_CMD_STAT_INT_ERR: 629 return "internal error"; 630 case MLX5_CMD_STAT_BAD_OP_ERR: 631 return "bad operation"; 632 case MLX5_CMD_STAT_BAD_PARAM_ERR: 633 return "bad parameter"; 634 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: 635 return "bad system state"; 636 case MLX5_CMD_STAT_BAD_RES_ERR: 637 return "bad resource"; 638 case MLX5_CMD_STAT_RES_BUSY: 639 return "resource busy"; 640 case MLX5_CMD_STAT_LIM_ERR: 641 return "limits exceeded"; 642 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: 643 return "bad resource state"; 644 case MLX5_CMD_STAT_IX_ERR: 645 return "bad index"; 646 case MLX5_CMD_STAT_NO_RES_ERR: 647 return "no resources"; 648 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: 649 return "bad input length"; 650 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: 651 return "bad output length"; 652 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: 653 return "bad QP state"; 654 case MLX5_CMD_STAT_BAD_PKT_ERR: 655 return "bad packet (discarded)"; 656 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: 657 return "bad size too many outstanding CQEs"; 658 default: 659 return "unknown status"; 660 } 661 } 662 663 static int cmd_status_to_err_helper(u8 status) 664 { 665 switch (status) { 666 case MLX5_CMD_STAT_OK: return 0; 667 case MLX5_CMD_STAT_INT_ERR: return -EIO; 668 case MLX5_CMD_STAT_BAD_OP_ERR: return -EINVAL; 669 case MLX5_CMD_STAT_BAD_PARAM_ERR: return -EINVAL; 670 case MLX5_CMD_STAT_BAD_SYS_STATE_ERR: return -EIO; 671 case MLX5_CMD_STAT_BAD_RES_ERR: return -EINVAL; 672 case MLX5_CMD_STAT_RES_BUSY: return -EBUSY; 673 case MLX5_CMD_STAT_LIM_ERR: return -ENOMEM; 674 case MLX5_CMD_STAT_BAD_RES_STATE_ERR: return -EINVAL; 675 case MLX5_CMD_STAT_IX_ERR: return -EINVAL; 676 case MLX5_CMD_STAT_NO_RES_ERR: return -EAGAIN; 677 case MLX5_CMD_STAT_BAD_INP_LEN_ERR: return -EIO; 678 case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR: return -EIO; 679 case MLX5_CMD_STAT_BAD_QP_STATE_ERR: return -EINVAL; 680 case MLX5_CMD_STAT_BAD_PKT_ERR: return -EINVAL; 681 case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR: return -EINVAL; 682 default: return -EIO; 683 } 684 } 685 686 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome) 687 { 688 *status = MLX5_GET(mbox_out, out, status); 689 *syndrome = MLX5_GET(mbox_out, out, syndrome); 690 } 691 692 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out) 693 { 694 u32 syndrome; 695 u8 status; 696 u16 opcode; 697 u16 op_mod; 698 699 mlx5_cmd_mbox_status(out, &status, &syndrome); 700 if (!status) 701 return 0; 702 703 opcode = MLX5_GET(mbox_in, in, opcode); 704 op_mod = MLX5_GET(mbox_in, in, op_mod); 705 706 mlx5_core_err(dev, 707 "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n", 708 mlx5_command_str(opcode), 709 opcode, op_mod, 710 cmd_status_str(status), 711 status, 712 syndrome); 713 714 return cmd_status_to_err_helper(status); 715 } 716 717 static void dump_command(struct mlx5_core_dev *dev, 718 struct mlx5_cmd_work_ent *ent, int input) 719 { 720 struct mlx5_cmd_msg *msg = input ? ent->in : ent->out; 721 u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode); 722 size_t i; 723 int data_only; 724 int offset = 0; 725 int msg_len = input ? ent->uin_size : ent->uout_size; 726 int dump_len; 727 728 data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA)); 729 730 if (data_only) 731 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA, 732 "dump command data %s(0x%x) %s\n", 733 mlx5_command_str(op), op, 734 input ? "INPUT" : "OUTPUT"); 735 else 736 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n", 737 mlx5_command_str(op), op, 738 input ? "INPUT" : "OUTPUT"); 739 740 if (data_only) { 741 if (input) { 742 dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset); 743 offset += sizeof(ent->lay->in); 744 } else { 745 dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset); 746 offset += sizeof(ent->lay->out); 747 } 748 } else { 749 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset); 750 offset += sizeof(*ent->lay); 751 } 752 753 for (i = 0; i != (msg->numpages * MLX5_NUM_CMDS_IN_ADAPTER_PAGE); i++) { 754 struct mlx5_cmd_prot_block *block; 755 756 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 757 758 if (data_only) { 759 if (offset >= msg_len) 760 break; 761 dump_len = min_t(int, 762 MLX5_CMD_DATA_BLOCK_SIZE, msg_len - offset); 763 764 dump_buf(block->data, dump_len, 1, offset); 765 offset += MLX5_CMD_DATA_BLOCK_SIZE; 766 } else { 767 mlx5_core_dbg(dev, "command block:\n"); 768 dump_buf(block, sizeof(*block), 0, offset); 769 offset += sizeof(*block); 770 } 771 772 /* check for last block */ 773 if (block->next == 0) 774 break; 775 } 776 777 if (data_only) 778 pr_debug("\n"); 779 } 780 781 static u16 msg_to_opcode(struct mlx5_cmd_msg *in) 782 { 783 return MLX5_GET(mbox_in, in->first.data, opcode); 784 } 785 786 static void cb_timeout_handler(struct work_struct *work) 787 { 788 struct delayed_work *dwork = container_of(work, struct delayed_work, 789 work); 790 struct mlx5_cmd_work_ent *ent = container_of(dwork, 791 struct mlx5_cmd_work_ent, 792 cb_timeout_work); 793 struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev, 794 cmd); 795 796 ent->ret = -ETIMEDOUT; 797 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n", 798 mlx5_command_str(msg_to_opcode(ent->in)), 799 msg_to_opcode(ent->in)); 800 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, MLX5_CMD_MODE_EVENTS); 801 } 802 803 static void complete_command(struct mlx5_cmd_work_ent *ent) 804 { 805 struct mlx5_cmd *cmd = ent->cmd; 806 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, 807 cmd); 808 mlx5_cmd_cbk_t callback; 809 void *context; 810 811 s64 ds; 812 struct mlx5_cmd_stats *stats; 813 unsigned long flags; 814 int err; 815 struct semaphore *sem; 816 817 if (ent->page_queue) 818 sem = &cmd->pages_sem; 819 else 820 sem = &cmd->sem; 821 822 if (dev->state != MLX5_DEVICE_STATE_UP) { 823 u8 status = 0; 824 u32 drv_synd; 825 826 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status); 827 MLX5_SET(mbox_out, ent->out, status, status); 828 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd); 829 } 830 831 if (ent->callback) { 832 ds = ent->ts2 - ent->ts1; 833 if (ent->op < ARRAY_SIZE(cmd->stats)) { 834 stats = &cmd->stats[ent->op]; 835 spin_lock_irqsave(&stats->lock, flags); 836 stats->sum += ds; 837 ++stats->n; 838 spin_unlock_irqrestore(&stats->lock, flags); 839 } 840 841 callback = ent->callback; 842 context = ent->context; 843 err = ent->ret; 844 if (!err) { 845 err = mlx5_copy_from_msg(ent->uout, 846 ent->out, 847 ent->uout_size); 848 err = err ? err : mlx5_cmd_check(dev, 849 ent->in->first.data, 850 ent->uout); 851 } 852 853 mlx5_free_cmd_msg(dev, ent->out); 854 free_msg(dev, ent->in); 855 856 err = err ? err : ent->status; 857 free_cmd(ent); 858 callback(err, context); 859 } else { 860 complete(&ent->done); 861 } 862 up(sem); 863 } 864 865 static void cmd_work_handler(struct work_struct *work) 866 { 867 struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work); 868 struct mlx5_cmd *cmd = ent->cmd; 869 struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd); 870 unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC); 871 struct mlx5_cmd_layout *lay; 872 struct semaphore *sem; 873 bool poll_cmd = ent->polling; 874 875 sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem; 876 down(sem); 877 878 if (alloc_ent(ent) < 0) { 879 complete_command(ent); 880 return; 881 } 882 883 ent->token = alloc_token(cmd); 884 lay = get_inst(cmd, ent->idx); 885 ent->lay = lay; 886 memset(lay, 0, sizeof(*lay)); 887 memcpy(lay->in, ent->in->first.data, sizeof(lay->in)); 888 ent->op = be32_to_cpu(lay->in[0]) >> 16; 889 if (ent->in->numpages != 0) 890 lay->in_ptr = cpu_to_be64(mlx5_fwp_get_dma(ent->in, 0)); 891 if (ent->out->numpages != 0) 892 lay->out_ptr = cpu_to_be64(mlx5_fwp_get_dma(ent->out, 0)); 893 lay->inlen = cpu_to_be32(ent->uin_size); 894 lay->outlen = cpu_to_be32(ent->uout_size); 895 lay->type = MLX5_PCI_CMD_XPORT; 896 lay->token = ent->token; 897 lay->status_own = CMD_OWNER_HW; 898 set_signature(ent, !cmd->checksum_disabled); 899 dump_command(dev, ent, 1); 900 ent->ts1 = ktime_get_ns(); 901 ent->busy = 0; 902 if (ent->callback) 903 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout); 904 905 /* ring doorbell after the descriptor is valid */ 906 mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx); 907 /* make sure data is written to RAM */ 908 mlx5_fwp_flush(cmd->cmd_page); 909 iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell); 910 mmiowb(); 911 912 /* if not in polling don't use ent after this point */ 913 if (poll_cmd) { 914 poll_timeout(ent); 915 /* make sure we read the descriptor after ownership is SW */ 916 mlx5_cmd_comp_handler(dev, 1U << ent->idx, MLX5_CMD_MODE_POLLING); 917 } 918 } 919 920 static const char *deliv_status_to_str(u8 status) 921 { 922 switch (status) { 923 case MLX5_CMD_DELIVERY_STAT_OK: 924 return "no errors"; 925 case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR: 926 return "signature error"; 927 case MLX5_CMD_DELIVERY_STAT_TOK_ERR: 928 return "token error"; 929 case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR: 930 return "bad block number"; 931 case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR: 932 return "output pointer not aligned to block size"; 933 case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR: 934 return "input pointer not aligned to block size"; 935 case MLX5_CMD_DELIVERY_STAT_FW_ERR: 936 return "firmware internal error"; 937 case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR: 938 return "command input length error"; 939 case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR: 940 return "command output length error"; 941 case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR: 942 return "reserved fields not cleared"; 943 case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR: 944 return "bad command descriptor type"; 945 default: 946 return "unknown status code"; 947 } 948 } 949 950 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent) 951 { 952 int timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC); 953 int err; 954 955 if (ent->polling) { 956 wait_for_completion(&ent->done); 957 } else if (!wait_for_completion_timeout(&ent->done, timeout)) { 958 ent->ret = -ETIMEDOUT; 959 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, MLX5_CMD_MODE_EVENTS); 960 } 961 962 err = ent->ret; 963 964 if (err == -ETIMEDOUT) { 965 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n", 966 mlx5_command_str(msg_to_opcode(ent->in)), 967 msg_to_opcode(ent->in)); 968 } 969 mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n", 970 err, deliv_status_to_str(ent->status), ent->status); 971 972 return err; 973 } 974 975 /* Notes: 976 * 1. Callback functions may not sleep 977 * 2. page queue commands do not support asynchrous completion 978 */ 979 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in, 980 int uin_size, 981 struct mlx5_cmd_msg *out, void *uout, int uout_size, 982 mlx5_cmd_cbk_t callback, 983 void *context, int page_queue, u8 *status, 984 bool force_polling) 985 { 986 struct mlx5_cmd *cmd = &dev->cmd; 987 struct mlx5_cmd_work_ent *ent; 988 struct mlx5_cmd_stats *stats; 989 int err = 0; 990 s64 ds; 991 u16 op; 992 993 if (callback && page_queue) 994 return -EINVAL; 995 996 ent = alloc_cmd(cmd, in, uin_size, out, uout, uout_size, callback, 997 context, page_queue); 998 if (IS_ERR(ent)) 999 return PTR_ERR(ent); 1000 1001 ent->polling = force_polling || (cmd->mode == MLX5_CMD_MODE_POLLING); 1002 1003 if (!callback) 1004 init_completion(&ent->done); 1005 1006 INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler); 1007 INIT_WORK(&ent->work, cmd_work_handler); 1008 if (page_queue) { 1009 cmd_work_handler(&ent->work); 1010 } else if (!queue_work(dev->priv.health.wq_cmd, &ent->work)) { 1011 mlx5_core_warn(dev, "failed to queue work\n"); 1012 err = -ENOMEM; 1013 goto out_free; 1014 } 1015 1016 if (callback) 1017 goto out; 1018 1019 err = wait_func(dev, ent); 1020 if (err == -ETIMEDOUT) 1021 goto out; 1022 1023 ds = ent->ts2 - ent->ts1; 1024 op = MLX5_GET(mbox_in, in->first.data, opcode); 1025 if (op < ARRAY_SIZE(cmd->stats)) { 1026 stats = &cmd->stats[op]; 1027 spin_lock_irq(&stats->lock); 1028 stats->sum += ds; 1029 ++stats->n; 1030 spin_unlock_irq(&stats->lock); 1031 } 1032 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME, 1033 "fw exec time for %s is %lld nsec\n", 1034 mlx5_command_str(op), (long long)ds); 1035 *status = ent->status; 1036 free_cmd(ent); 1037 1038 return err; 1039 1040 out_free: 1041 free_cmd(ent); 1042 out: 1043 return err; 1044 } 1045 1046 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, size_t size) 1047 { 1048 size_t delta; 1049 size_t i; 1050 1051 if (to == NULL || from == NULL) 1052 return (-ENOMEM); 1053 1054 delta = min_t(size_t, size, sizeof(to->first.data)); 1055 memcpy(to->first.data, from, delta); 1056 from = (char *)from + delta; 1057 size -= delta; 1058 1059 for (i = 0; size != 0; i++) { 1060 struct mlx5_cmd_prot_block *block; 1061 1062 block = mlx5_fwp_get_virt(to, i * MLX5_CMD_MBOX_SIZE); 1063 1064 delta = min_t(size_t, size, MLX5_CMD_DATA_BLOCK_SIZE); 1065 memcpy(block->data, from, delta); 1066 from = (char *)from + delta; 1067 size -= delta; 1068 } 1069 return (0); 1070 } 1071 1072 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size) 1073 { 1074 size_t delta; 1075 size_t i; 1076 1077 if (to == NULL || from == NULL) 1078 return (-ENOMEM); 1079 1080 delta = min_t(size_t, size, sizeof(from->first.data)); 1081 memcpy(to, from->first.data, delta); 1082 to = (char *)to + delta; 1083 size -= delta; 1084 1085 for (i = 0; size != 0; i++) { 1086 struct mlx5_cmd_prot_block *block; 1087 1088 block = mlx5_fwp_get_virt(from, i * MLX5_CMD_MBOX_SIZE); 1089 1090 delta = min_t(size_t, size, MLX5_CMD_DATA_BLOCK_SIZE); 1091 memcpy(to, block->data, delta); 1092 to = (char *)to + delta; 1093 size -= delta; 1094 } 1095 return (0); 1096 } 1097 1098 static struct mlx5_cmd_msg * 1099 mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev, gfp_t flags, size_t size) 1100 { 1101 struct mlx5_cmd_msg *msg; 1102 size_t blen; 1103 size_t n; 1104 size_t i; 1105 1106 blen = size - min_t(size_t, sizeof(msg->first.data), size); 1107 n = howmany(blen, MLX5_CMD_DATA_BLOCK_SIZE); 1108 1109 msg = mlx5_fwp_alloc(dev, flags, howmany(n, MLX5_NUM_CMDS_IN_ADAPTER_PAGE)); 1110 if (msg == NULL) 1111 return (ERR_PTR(-ENOMEM)); 1112 1113 for (i = 0; i != n; i++) { 1114 struct mlx5_cmd_prot_block *block; 1115 1116 block = mlx5_fwp_get_virt(msg, i * MLX5_CMD_MBOX_SIZE); 1117 1118 memset(block, 0, MLX5_CMD_MBOX_SIZE); 1119 1120 if (i != (n - 1)) { 1121 u64 dma = mlx5_fwp_get_dma(msg, (i + 1) * MLX5_CMD_MBOX_SIZE); 1122 block->next = cpu_to_be64(dma); 1123 } 1124 block->block_num = cpu_to_be32(i); 1125 } 1126 1127 /* make sure initial data is written to RAM */ 1128 mlx5_fwp_flush(msg); 1129 1130 return (msg); 1131 } 1132 1133 static void 1134 mlx5_free_cmd_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg) 1135 { 1136 1137 mlx5_fwp_free(msg); 1138 } 1139 1140 static void clean_debug_files(struct mlx5_core_dev *dev) 1141 { 1142 } 1143 1144 1145 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode) 1146 { 1147 struct mlx5_cmd *cmd = &dev->cmd; 1148 int i; 1149 1150 if (cmd->mode == mode) 1151 return; 1152 1153 for (i = 0; i < cmd->max_reg_cmds; i++) 1154 down(&cmd->sem); 1155 1156 down(&cmd->pages_sem); 1157 cmd->mode = mode; 1158 1159 up(&cmd->pages_sem); 1160 for (i = 0; i < cmd->max_reg_cmds; i++) 1161 up(&cmd->sem); 1162 } 1163 1164 void mlx5_cmd_use_events(struct mlx5_core_dev *dev) 1165 { 1166 mlx5_cmd_change_mod(dev, MLX5_CMD_MODE_EVENTS); 1167 } 1168 1169 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev) 1170 { 1171 mlx5_cmd_change_mod(dev, MLX5_CMD_MODE_POLLING); 1172 } 1173 1174 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg) 1175 { 1176 unsigned long flags; 1177 1178 if (msg->cache) { 1179 spin_lock_irqsave(&msg->cache->lock, flags); 1180 list_add_tail(&msg->list, &msg->cache->head); 1181 spin_unlock_irqrestore(&msg->cache->lock, flags); 1182 } else { 1183 mlx5_free_cmd_msg(dev, msg); 1184 } 1185 } 1186 1187 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector_flags, 1188 enum mlx5_cmd_mode cmd_mode) 1189 { 1190 struct mlx5_cmd *cmd = &dev->cmd; 1191 struct mlx5_cmd_work_ent *ent; 1192 bool triggered = (vector_flags & MLX5_TRIGGERED_CMD_COMP) ? 1 : 0; 1193 u32 vector = vector_flags; /* discard flags in the upper dword */ 1194 int i; 1195 1196 /* make sure data gets read from RAM */ 1197 mlx5_fwp_invalidate(cmd->cmd_page); 1198 1199 while (vector != 0) { 1200 i = ffs(vector) - 1; 1201 vector &= ~(1U << i); 1202 /* check command mode */ 1203 if (cmd->ent_mode[i] != cmd_mode) 1204 continue; 1205 ent = cmd->ent_arr[i]; 1206 /* check if command was already handled */ 1207 if (ent == NULL) 1208 continue; 1209 if (ent->callback) 1210 cancel_delayed_work(&ent->cb_timeout_work); 1211 ent->ts2 = ktime_get_ns(); 1212 memcpy(ent->out->first.data, ent->lay->out, 1213 sizeof(ent->lay->out)); 1214 /* make sure data gets read from RAM */ 1215 mlx5_fwp_invalidate(ent->out); 1216 dump_command(dev, ent, 0); 1217 if (!ent->ret) { 1218 if (!cmd->checksum_disabled) 1219 ent->ret = verify_signature(ent); 1220 else 1221 ent->ret = 0; 1222 1223 if (triggered) 1224 ent->status = MLX5_DRIVER_STATUS_ABORTED; 1225 else 1226 ent->status = ent->lay->status_own >> 1; 1227 1228 mlx5_core_dbg(dev, 1229 "FW command ret 0x%x, status %s(0x%x)\n", 1230 ent->ret, 1231 deliv_status_to_str(ent->status), 1232 ent->status); 1233 } 1234 free_ent(cmd, ent->idx); 1235 complete_command(ent); 1236 } 1237 } 1238 EXPORT_SYMBOL(mlx5_cmd_comp_handler); 1239 1240 static int status_to_err(u8 status) 1241 { 1242 return status ? -EIO : 0; /* TBD more meaningful codes */ 1243 } 1244 1245 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size, 1246 gfp_t gfp) 1247 { 1248 struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM); 1249 struct mlx5_cmd *cmd = &dev->cmd; 1250 struct cache_ent *ent = NULL; 1251 1252 if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE) 1253 ent = &cmd->cache.large; 1254 else if (in_size > 16 && in_size <= MED_LIST_SIZE) 1255 ent = &cmd->cache.med; 1256 1257 if (ent) { 1258 spin_lock_irq(&ent->lock); 1259 if (!list_empty(&ent->head)) { 1260 msg = list_entry(ent->head.next, struct mlx5_cmd_msg, 1261 list); 1262 list_del(&msg->list); 1263 } 1264 spin_unlock_irq(&ent->lock); 1265 } 1266 1267 if (IS_ERR(msg)) 1268 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size); 1269 1270 return msg; 1271 } 1272 1273 static int is_manage_pages(void *in) 1274 { 1275 return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES; 1276 } 1277 1278 static int cmd_exec_helper(struct mlx5_core_dev *dev, 1279 void *in, int in_size, 1280 void *out, int out_size, 1281 mlx5_cmd_cbk_t callback, void *context, 1282 bool force_polling) 1283 { 1284 struct mlx5_cmd_msg *inb; 1285 struct mlx5_cmd_msg *outb; 1286 int pages_queue; 1287 const gfp_t gfp = GFP_KERNEL; 1288 int err; 1289 u8 status = 0; 1290 u32 drv_synd; 1291 1292 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) { 1293 u16 opcode = MLX5_GET(mbox_in, in, opcode); 1294 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status); 1295 MLX5_SET(mbox_out, out, status, status); 1296 MLX5_SET(mbox_out, out, syndrome, drv_synd); 1297 return err; 1298 } 1299 1300 pages_queue = is_manage_pages(in); 1301 1302 inb = alloc_msg(dev, in_size, gfp); 1303 if (IS_ERR(inb)) { 1304 err = PTR_ERR(inb); 1305 return err; 1306 } 1307 1308 err = mlx5_copy_to_msg(inb, in, in_size); 1309 if (err) { 1310 mlx5_core_warn(dev, "err %d\n", err); 1311 goto out_in; 1312 } 1313 1314 outb = mlx5_alloc_cmd_msg(dev, gfp, out_size); 1315 if (IS_ERR(outb)) { 1316 err = PTR_ERR(outb); 1317 goto out_in; 1318 } 1319 1320 err = mlx5_cmd_invoke(dev, inb, in_size, outb, out, out_size, callback, 1321 context, pages_queue, &status, force_polling); 1322 if (err) { 1323 if (err == -ETIMEDOUT) 1324 return err; 1325 goto out_out; 1326 } 1327 1328 mlx5_core_dbg(dev, "err %d, status %d\n", err, status); 1329 if (status) { 1330 err = status_to_err(status); 1331 goto out_out; 1332 } 1333 1334 if (callback) 1335 return err; 1336 1337 err = mlx5_copy_from_msg(out, outb, out_size); 1338 1339 out_out: 1340 mlx5_free_cmd_msg(dev, outb); 1341 1342 out_in: 1343 free_msg(dev, inb); 1344 return err; 1345 } 1346 1347 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 1348 int out_size) 1349 { 1350 int err; 1351 1352 err = cmd_exec_helper(dev, in, in_size, out, out_size, NULL, NULL, false); 1353 return err ? : mlx5_cmd_check(dev, in, out); 1354 } 1355 EXPORT_SYMBOL(mlx5_cmd_exec); 1356 1357 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, 1358 struct mlx5_async_ctx *ctx) 1359 { 1360 ctx->dev = dev; 1361 /* Starts at 1 to avoid doing wake_up if we are not cleaning up */ 1362 atomic_set(&ctx->num_inflight, 1); 1363 init_waitqueue_head(&ctx->wait); 1364 } 1365 EXPORT_SYMBOL(mlx5_cmd_init_async_ctx); 1366 1367 /** 1368 * mlx5_cmd_cleanup_async_ctx - Clean up an async_ctx 1369 * @ctx: The ctx to clean 1370 * 1371 * Upon return all callbacks given to mlx5_cmd_exec_cb() have been called. The 1372 * caller must ensure that mlx5_cmd_exec_cb() is not called during or after 1373 * the call mlx5_cleanup_async_ctx(). 1374 */ 1375 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx) 1376 { 1377 atomic_dec(&ctx->num_inflight); 1378 wait_event(ctx->wait, atomic_read(&ctx->num_inflight) == 0); 1379 } 1380 EXPORT_SYMBOL(mlx5_cmd_cleanup_async_ctx); 1381 1382 static void mlx5_cmd_exec_cb_handler(int status, void *_work) 1383 { 1384 struct mlx5_async_work *work = _work; 1385 struct mlx5_async_ctx *ctx = work->ctx; 1386 1387 work->user_callback(status, work); 1388 if (atomic_dec_and_test(&ctx->num_inflight)) 1389 wake_up(&ctx->wait); 1390 } 1391 1392 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, 1393 void *out, int out_size, mlx5_async_cbk_t callback, 1394 struct mlx5_async_work *work) 1395 { 1396 int ret; 1397 1398 work->ctx = ctx; 1399 work->user_callback = callback; 1400 if (WARN_ON(!atomic_inc_not_zero(&ctx->num_inflight))) 1401 return -EIO; 1402 ret = cmd_exec_helper(ctx->dev, in, in_size, out, out_size, 1403 mlx5_cmd_exec_cb_handler, work, false); 1404 if (ret && atomic_dec_and_test(&ctx->num_inflight)) 1405 wake_up(&ctx->wait); 1406 1407 return ret; 1408 } 1409 EXPORT_SYMBOL(mlx5_cmd_exec_cb); 1410 1411 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, 1412 void *out, int out_size) 1413 { 1414 int err; 1415 1416 err = cmd_exec_helper(dev, in, in_size, out, out_size, NULL, NULL, true); 1417 return err ? : mlx5_cmd_check(dev, in, out); 1418 } 1419 EXPORT_SYMBOL(mlx5_cmd_exec_polling); 1420 1421 static void destroy_msg_cache(struct mlx5_core_dev *dev) 1422 { 1423 struct mlx5_cmd *cmd = &dev->cmd; 1424 struct mlx5_cmd_msg *msg; 1425 struct mlx5_cmd_msg *n; 1426 1427 list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) { 1428 list_del(&msg->list); 1429 mlx5_free_cmd_msg(dev, msg); 1430 } 1431 1432 list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) { 1433 list_del(&msg->list); 1434 mlx5_free_cmd_msg(dev, msg); 1435 } 1436 } 1437 1438 static int create_msg_cache(struct mlx5_core_dev *dev) 1439 { 1440 struct mlx5_cmd *cmd = &dev->cmd; 1441 struct mlx5_cmd_msg *msg; 1442 int err; 1443 int i; 1444 1445 spin_lock_init(&cmd->cache.large.lock); 1446 INIT_LIST_HEAD(&cmd->cache.large.head); 1447 spin_lock_init(&cmd->cache.med.lock); 1448 INIT_LIST_HEAD(&cmd->cache.med.head); 1449 1450 for (i = 0; i < NUM_LONG_LISTS; i++) { 1451 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE); 1452 if (IS_ERR(msg)) { 1453 err = PTR_ERR(msg); 1454 goto ex_err; 1455 } 1456 msg->cache = &cmd->cache.large; 1457 list_add_tail(&msg->list, &cmd->cache.large.head); 1458 } 1459 1460 for (i = 0; i < NUM_MED_LISTS; i++) { 1461 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE); 1462 if (IS_ERR(msg)) { 1463 err = PTR_ERR(msg); 1464 goto ex_err; 1465 } 1466 msg->cache = &cmd->cache.med; 1467 list_add_tail(&msg->list, &cmd->cache.med.head); 1468 } 1469 1470 return 0; 1471 1472 ex_err: 1473 destroy_msg_cache(dev); 1474 return err; 1475 } 1476 1477 static int 1478 alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd) 1479 { 1480 int err; 1481 1482 sx_init(&cmd->dma_sx, "MLX5-DMA-SX"); 1483 mtx_init(&cmd->dma_mtx, "MLX5-DMA-MTX", NULL, MTX_DEF); 1484 cv_init(&cmd->dma_cv, "MLX5-DMA-CV"); 1485 1486 /* 1487 * Create global DMA descriptor tag for allocating 1488 * 4K firmware pages: 1489 */ 1490 err = -bus_dma_tag_create( 1491 bus_get_dma_tag(dev->pdev->dev.bsddev), 1492 MLX5_ADAPTER_PAGE_SIZE, /* alignment */ 1493 0, /* no boundary */ 1494 BUS_SPACE_MAXADDR, /* lowaddr */ 1495 BUS_SPACE_MAXADDR, /* highaddr */ 1496 NULL, NULL, /* filter, filterarg */ 1497 MLX5_ADAPTER_PAGE_SIZE, /* maxsize */ 1498 1, /* nsegments */ 1499 MLX5_ADAPTER_PAGE_SIZE, /* maxsegsize */ 1500 0, /* flags */ 1501 NULL, NULL, /* lockfunc, lockfuncarg */ 1502 &cmd->dma_tag); 1503 if (err != 0) 1504 goto failure_destroy_sx; 1505 1506 cmd->cmd_page = mlx5_fwp_alloc(dev, GFP_KERNEL, 1); 1507 if (cmd->cmd_page == NULL) { 1508 err = -ENOMEM; 1509 goto failure_alloc_page; 1510 } 1511 cmd->dma = mlx5_fwp_get_dma(cmd->cmd_page, 0); 1512 cmd->cmd_buf = mlx5_fwp_get_virt(cmd->cmd_page, 0); 1513 return (0); 1514 1515 failure_alloc_page: 1516 bus_dma_tag_destroy(cmd->dma_tag); 1517 1518 failure_destroy_sx: 1519 cv_destroy(&cmd->dma_cv); 1520 mtx_destroy(&cmd->dma_mtx); 1521 sx_destroy(&cmd->dma_sx); 1522 return (err); 1523 } 1524 1525 static void 1526 free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd) 1527 { 1528 1529 mlx5_fwp_free(cmd->cmd_page); 1530 bus_dma_tag_destroy(cmd->dma_tag); 1531 cv_destroy(&cmd->dma_cv); 1532 mtx_destroy(&cmd->dma_mtx); 1533 sx_destroy(&cmd->dma_sx); 1534 } 1535 1536 int mlx5_cmd_init(struct mlx5_core_dev *dev) 1537 { 1538 struct mlx5_cmd *cmd = &dev->cmd; 1539 u32 cmd_h, cmd_l; 1540 u16 cmd_if_rev; 1541 int err; 1542 int i; 1543 1544 memset(cmd, 0, sizeof(*cmd)); 1545 cmd_if_rev = cmdif_rev_get(dev); 1546 if (cmd_if_rev != CMD_IF_REV) { 1547 mlx5_core_err(dev, 1548 "Driver cmdif rev(%d) differs from firmware's(%d)\n", 1549 CMD_IF_REV, cmd_if_rev); 1550 return -EINVAL; 1551 } 1552 1553 err = alloc_cmd_page(dev, cmd); 1554 if (err) 1555 goto err_free_pool; 1556 1557 cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff; 1558 cmd->log_sz = cmd_l >> 4 & 0xf; 1559 cmd->log_stride = cmd_l & 0xf; 1560 if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) { 1561 mlx5_core_err(dev, 1562 "firmware reports too many outstanding commands %d\n", 1563 1 << cmd->log_sz); 1564 err = -EINVAL; 1565 goto err_free_page; 1566 } 1567 1568 if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) { 1569 mlx5_core_err(dev, 1570 "command queue size overflow\n"); 1571 err = -EINVAL; 1572 goto err_free_page; 1573 } 1574 1575 cmd->checksum_disabled = 1; 1576 cmd->max_reg_cmds = (1 << cmd->log_sz) - 1; 1577 cmd->bitmask = (1 << cmd->max_reg_cmds) - 1; 1578 1579 cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; 1580 if (cmd->cmdif_rev > CMD_IF_REV) { 1581 mlx5_core_err(dev, 1582 "driver does not support command interface version. driver %d, firmware %d\n", 1583 CMD_IF_REV, cmd->cmdif_rev); 1584 err = -ENOTSUPP; 1585 goto err_free_page; 1586 } 1587 1588 spin_lock_init(&cmd->alloc_lock); 1589 spin_lock_init(&cmd->token_lock); 1590 for (i = 0; i < ARRAY_SIZE(cmd->stats); i++) 1591 spin_lock_init(&cmd->stats[i].lock); 1592 1593 sema_init(&cmd->sem, cmd->max_reg_cmds); 1594 sema_init(&cmd->pages_sem, 1); 1595 1596 cmd_h = (u32)((u64)(cmd->dma) >> 32); 1597 cmd_l = (u32)(cmd->dma); 1598 if (cmd_l & 0xfff) { 1599 mlx5_core_err(dev, "invalid command queue address\n"); 1600 err = -ENOMEM; 1601 goto err_free_page; 1602 } 1603 1604 iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h); 1605 iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz); 1606 1607 /* Make sure firmware sees the complete address before we proceed */ 1608 wmb(); 1609 1610 mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma)); 1611 1612 cmd->mode = MLX5_CMD_MODE_POLLING; 1613 1614 err = create_msg_cache(dev); 1615 if (err) { 1616 mlx5_core_err(dev, "failed to create command cache\n"); 1617 goto err_free_page; 1618 } 1619 return 0; 1620 1621 err_free_page: 1622 free_cmd_page(dev, cmd); 1623 1624 err_free_pool: 1625 return err; 1626 } 1627 EXPORT_SYMBOL(mlx5_cmd_init); 1628 1629 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev) 1630 { 1631 struct mlx5_cmd *cmd = &dev->cmd; 1632 1633 clean_debug_files(dev); 1634 flush_workqueue(dev->priv.health.wq_cmd); 1635 destroy_msg_cache(dev); 1636 free_cmd_page(dev, cmd); 1637 } 1638 EXPORT_SYMBOL(mlx5_cmd_cleanup); 1639 1640 int mlx5_cmd_query_cong_counter(struct mlx5_core_dev *dev, 1641 bool reset, void *out, int out_size) 1642 { 1643 u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)] = { }; 1644 1645 MLX5_SET(query_cong_statistics_in, in, opcode, 1646 MLX5_CMD_OP_QUERY_CONG_STATISTICS); 1647 MLX5_SET(query_cong_statistics_in, in, clear, reset); 1648 return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size); 1649 } 1650 EXPORT_SYMBOL(mlx5_cmd_query_cong_counter); 1651 1652 int mlx5_cmd_query_cong_params(struct mlx5_core_dev *dev, int cong_point, 1653 void *out, int out_size) 1654 { 1655 u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = { }; 1656 1657 MLX5_SET(query_cong_params_in, in, opcode, 1658 MLX5_CMD_OP_QUERY_CONG_PARAMS); 1659 MLX5_SET(query_cong_params_in, in, cong_protocol, cong_point); 1660 1661 return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size); 1662 } 1663 EXPORT_SYMBOL(mlx5_cmd_query_cong_params); 1664 1665 int mlx5_cmd_modify_cong_params(struct mlx5_core_dev *dev, 1666 void *in, int in_size) 1667 { 1668 u32 out[MLX5_ST_SZ_DW(modify_cong_params_out)] = { }; 1669 1670 return mlx5_cmd_exec(dev, in, in_size, out, sizeof(out)); 1671 } 1672 EXPORT_SYMBOL(mlx5_cmd_modify_cong_params); 1673 1674 int mlx5_cmd_query_cong_status(struct mlx5_core_dev *dev, int cong_point, 1675 int prio, void *out, int out_size) 1676 { 1677 u32 in[MLX5_ST_SZ_DW(query_cong_status_in)] = { }; 1678 1679 MLX5_SET(query_cong_status_in, in, opcode, 1680 MLX5_CMD_OP_QUERY_CONG_STATUS); 1681 MLX5_SET(query_cong_status_in, in, priority, prio); 1682 MLX5_SET(query_cong_status_in, in, cong_protocol, cong_point); 1683 1684 return mlx5_cmd_exec(dev, in, sizeof(in), out, out_size); 1685 } 1686 EXPORT_SYMBOL(mlx5_cmd_query_cong_status); 1687 1688 int mlx5_cmd_modify_cong_status(struct mlx5_core_dev *dev, 1689 void *in, int in_size) 1690 { 1691 u32 out[MLX5_ST_SZ_DW(modify_cong_status_out)] = { }; 1692 1693 return mlx5_cmd_exec(dev, in, in_size, out, sizeof(out)); 1694 } 1695 EXPORT_SYMBOL(mlx5_cmd_modify_cong_status);
Cache object: 3241ebfba19bd5cc5ce51f73d718a446
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