FreeBSD/Linux Kernel Cross Reference
sys/dev/mlx5/qp.h
1 /*-
2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28 #ifndef MLX5_QP_H
29 #define MLX5_QP_H
30
31 #include <dev/mlx5/driver.h>
32
33 #define MLX5_INVALID_LKEY 0x100
34 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
35 #define MLX5_DIF_SIZE 8
36 #define MLX5_STRIDE_BLOCK_OP 0x400
37 #define MLX5_CPY_GRD_MASK 0xc0
38 #define MLX5_CPY_APP_MASK 0x30
39 #define MLX5_CPY_REF_MASK 0x0f
40 #define MLX5_BSF_INC_REFTAG (1 << 6)
41 #define MLX5_BSF_INL_VALID (1 << 15)
42 #define MLX5_BSF_REFRESH_DIF (1 << 14)
43 #define MLX5_BSF_REPEAT_BLOCK (1 << 7)
44 #define MLX5_BSF_APPTAG_ESCAPE 0x1
45 #define MLX5_BSF_APPREF_ESCAPE 0x2
46 #define MLX5_WQE_DS_UNITS 16
47
48 enum mlx5_qp_optpar {
49 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
50 MLX5_QP_OPTPAR_RRE = 1 << 1,
51 MLX5_QP_OPTPAR_RAE = 1 << 2,
52 MLX5_QP_OPTPAR_RWE = 1 << 3,
53 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
54 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
55 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
56 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
57 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
58 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
59 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
60 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
61 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
62 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
63 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
64 MLX5_QP_OPTPAR_SRQN = 1 << 18,
65 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
66 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
67 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
68 };
69
70 enum mlx5_qp_state {
71 MLX5_QP_STATE_RST = 0,
72 MLX5_QP_STATE_INIT = 1,
73 MLX5_QP_STATE_RTR = 2,
74 MLX5_QP_STATE_RTS = 3,
75 MLX5_QP_STATE_SQER = 4,
76 MLX5_QP_STATE_SQD = 5,
77 MLX5_QP_STATE_ERR = 6,
78 MLX5_QP_STATE_SQ_DRAINING = 7,
79 MLX5_QP_STATE_SUSPENDED = 9,
80 MLX5_QP_NUM_STATE,
81 MLX5_QP_STATE,
82 MLX5_QP_STATE_BAD,
83 };
84
85 enum {
86 MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
87 MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
88 MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
89 MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
90 };
91
92 enum {
93 MLX5_QP_ST_RC = 0x0,
94 MLX5_QP_ST_UC = 0x1,
95 MLX5_QP_ST_UD = 0x2,
96 MLX5_QP_ST_XRC = 0x3,
97 MLX5_QP_ST_MLX = 0x4,
98 MLX5_QP_ST_DCI = 0x5,
99 MLX5_QP_ST_DCT = 0x6,
100 MLX5_QP_ST_QP0 = 0x7,
101 MLX5_QP_ST_QP1 = 0x8,
102 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
103 MLX5_QP_ST_RAW_IPV6 = 0xa,
104 MLX5_QP_ST_SNIFFER = 0xb,
105 MLX5_QP_ST_SYNC_UMR = 0xe,
106 MLX5_QP_ST_PTP_1588 = 0xd,
107 MLX5_QP_ST_REG_UMR = 0xc,
108 MLX5_QP_ST_SW_CNAK = 0x10,
109 MLX5_QP_ST_MAX
110 };
111
112 enum {
113 MLX5_NON_ZERO_RQ = 0x0,
114 MLX5_SRQ_RQ = 0x1,
115 MLX5_CRQ_RQ = 0x2,
116 MLX5_ZERO_LEN_RQ = 0x3
117 };
118
119 enum {
120 /* params1 */
121 MLX5_QP_BIT_SRE = 1 << 15,
122 MLX5_QP_BIT_SWE = 1 << 14,
123 MLX5_QP_BIT_SAE = 1 << 13,
124 /* params2 */
125 MLX5_QP_BIT_RRE = 1 << 15,
126 MLX5_QP_BIT_RWE = 1 << 14,
127 MLX5_QP_BIT_RAE = 1 << 13,
128 MLX5_QP_BIT_RIC = 1 << 4,
129 MLX5_QP_BIT_COLL_SYNC_RQ = 1 << 2,
130 MLX5_QP_BIT_COLL_SYNC_SQ = 1 << 1,
131 MLX5_QP_BIT_COLL_MASTER = 1 << 0
132 };
133
134 enum {
135 MLX5_DCT_BIT_RRE = 1 << 19,
136 MLX5_DCT_BIT_RWE = 1 << 18,
137 MLX5_DCT_BIT_RAE = 1 << 17,
138 };
139
140 enum {
141 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
142 MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
143 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
144 };
145
146 #define MLX5_SEND_WQE_DS 16
147 #define MLX5_SEND_WQE_BB 64
148 #define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
149
150 enum {
151 MLX5_SEND_WQE_MAX_WQEBBS = 16,
152 };
153
154 enum {
155 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
156 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
157 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
158 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
159 MLX5_WQE_FMR_PERM_ATOMIC = 1U << 31
160 };
161
162 enum {
163 MLX5_FENCE_MODE_NONE = 0 << 5,
164 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
165 MLX5_FENCE_MODE_FENCE = 2 << 5,
166 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
167 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
168 };
169
170 enum {
171 MLX5_RCV_DBR = 0,
172 MLX5_SND_DBR = 1,
173 };
174
175 enum {
176 MLX5_FLAGS_INLINE = 1<<7,
177 MLX5_FLAGS_CHECK_FREE = 1<<5,
178 };
179
180 struct mlx5_wqe_fmr_seg {
181 __be32 flags;
182 __be32 mem_key;
183 __be64 buf_list;
184 __be64 start_addr;
185 __be64 reg_len;
186 __be32 offset;
187 __be32 page_size;
188 u32 reserved[2];
189 };
190
191 struct mlx5_wqe_ctrl_seg {
192 __be32 opmod_idx_opcode;
193 __be32 qpn_ds;
194 u8 signature;
195 u8 rsvd[2];
196 u8 fm_ce_se;
197 __be32 imm;
198 };
199
200 #define MLX5_WQE_CTRL_DS_MASK 0x3f
201
202 enum {
203 MLX5_MLX_FLAG_MASK_VL15 = 0x40,
204 MLX5_MLX_FLAG_MASK_SLR = 0x20,
205 MLX5_MLX_FLAG_MASK_ICRC = 0x8,
206 MLX5_MLX_FLAG_MASK_FL = 4
207 };
208
209 struct mlx5_mlx_seg {
210 __be32 rsvd0;
211 u8 flags;
212 u8 stat_rate_sl;
213 u8 rsvd1[8];
214 __be16 dlid;
215 };
216
217 enum {
218 MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
219 MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
220 MLX5_ETH_WQE_L3_CSUM = 1 << 6,
221 MLX5_ETH_WQE_L4_CSUM = 1 << 7,
222 };
223
224 enum {
225 MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 0,
226 MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 1,
227 MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 4,
228 MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 5,
229 };
230
231 struct mlx5_wqe_eth_seg {
232 u8 swp_outer_l4_offset;
233 u8 swp_outer_l3_offset;
234 u8 swp_inner_l4_offset;
235 u8 swp_inner_l3_offset;
236 u8 cs_flags;
237 u8 swp_flags;
238 __be16 mss;
239 __be32 rsvd2;
240 union {
241 struct {
242 __be16 inline_hdr_sz;
243 u8 inline_hdr_start[2];
244 };
245 struct {
246 __be16 vlan_cmd;
247 __be16 vlan_hdr;
248 };
249 };
250 };
251
252 struct mlx5_wqe_xrc_seg {
253 __be32 xrc_srqn;
254 u8 rsvd[12];
255 };
256
257 struct mlx5_wqe_masked_atomic_seg {
258 __be64 swap_add;
259 __be64 compare;
260 __be64 swap_add_mask;
261 __be64 compare_mask;
262 };
263
264 struct mlx5_av {
265 union {
266 struct {
267 __be32 qkey;
268 __be32 reserved;
269 } qkey;
270 __be64 dc_key;
271 } key;
272 __be32 dqp_dct;
273 u8 stat_rate_sl;
274 u8 fl_mlid;
275 union {
276 __be16 rlid;
277 __be16 udp_sport;
278 };
279 u8 reserved0[4];
280 u8 rmac[6];
281 u8 tclass;
282 u8 hop_limit;
283 __be32 grh_gid_fl;
284 u8 rgid[16];
285 };
286
287 struct mlx5_wqe_datagram_seg {
288 struct mlx5_av av;
289 };
290
291 struct mlx5_wqe_raddr_seg {
292 __be64 raddr;
293 __be32 rkey;
294 u32 reserved;
295 };
296
297 struct mlx5_wqe_atomic_seg {
298 __be64 swap_add;
299 __be64 compare;
300 };
301
302 struct mlx5_wqe_data_seg {
303 __be32 byte_count;
304 __be32 lkey;
305 __be64 addr;
306 };
307
308 struct mlx5_wqe_umr_ctrl_seg {
309 u8 flags;
310 u8 rsvd0[3];
311 __be16 klm_octowords;
312 __be16 bsf_octowords;
313 __be64 mkey_mask;
314 u8 rsvd1[32];
315 };
316
317 struct mlx5_seg_set_psv {
318 __be32 psv_num;
319 __be16 syndrome;
320 __be16 status;
321 __be32 transient_sig;
322 __be32 ref_tag;
323 };
324
325 struct mlx5_wqe_qos_remap_seg {
326 u8 rsvd0[4];
327 u8 rsvd1[4];
328 __be32 qos_handle;
329 __be32 queue_handle;
330 };
331
332 struct mlx5_seg_get_psv {
333 u8 rsvd[19];
334 u8 num_psv;
335 __be32 l_key;
336 __be64 va;
337 __be32 psv_index[4];
338 };
339
340 struct mlx5_seg_check_psv {
341 u8 rsvd0[2];
342 __be16 err_coalescing_op;
343 u8 rsvd1[2];
344 __be16 xport_err_op;
345 u8 rsvd2[2];
346 __be16 xport_err_mask;
347 u8 rsvd3[7];
348 u8 num_psv;
349 __be32 l_key;
350 __be64 va;
351 __be32 psv_index[4];
352 };
353
354 struct mlx5_rwqe_sig {
355 u8 rsvd0[4];
356 u8 signature;
357 u8 rsvd1[11];
358 };
359
360 struct mlx5_wqe_signature_seg {
361 u8 rsvd0[4];
362 u8 signature;
363 u8 rsvd1[11];
364 };
365
366 struct mlx5_wqe_inline_seg {
367 __be32 byte_count;
368 };
369
370 enum mlx5_sig_type {
371 MLX5_DIF_CRC = 0x1,
372 MLX5_DIF_IPCS = 0x2,
373 };
374
375 struct mlx5_bsf_inl {
376 __be16 vld_refresh;
377 __be16 dif_apptag;
378 __be32 dif_reftag;
379 u8 sig_type;
380 u8 rp_inv_seed;
381 u8 rsvd[3];
382 u8 dif_inc_ref_guard_check;
383 __be16 dif_app_bitmask_check;
384 };
385
386 struct mlx5_bsf {
387 struct mlx5_bsf_basic {
388 u8 bsf_size_sbs;
389 u8 check_byte_mask;
390 union {
391 u8 copy_byte_mask;
392 u8 bs_selector;
393 u8 rsvd_wflags;
394 } wire;
395 union {
396 u8 bs_selector;
397 u8 rsvd_mflags;
398 } mem;
399 __be32 raw_data_size;
400 __be32 w_bfs_psv;
401 __be32 m_bfs_psv;
402 } basic;
403 struct mlx5_bsf_ext {
404 __be32 t_init_gen_pro_size;
405 __be32 rsvd_epi_size;
406 __be32 w_tfs_psv;
407 __be32 m_tfs_psv;
408 } ext;
409 struct mlx5_bsf_inl w_inl;
410 struct mlx5_bsf_inl m_inl;
411 };
412
413 struct mlx5_klm {
414 __be32 bcount;
415 __be32 key;
416 __be64 va;
417 };
418
419 struct mlx5_stride_block_entry {
420 __be16 stride;
421 __be16 bcount;
422 __be32 key;
423 __be64 va;
424 };
425
426 struct mlx5_stride_block_ctrl_seg {
427 __be32 bcount_per_cycle;
428 __be32 op;
429 __be32 repeat_count;
430 u16 rsvd;
431 __be16 num_entries;
432 };
433
434 enum mlx5_pagefault_flags {
435 MLX5_PFAULT_REQUESTOR = 1 << 0,
436 MLX5_PFAULT_WRITE = 1 << 1,
437 MLX5_PFAULT_RDMA = 1 << 2,
438 };
439
440 /* Contains the details of a pagefault. */
441 struct mlx5_pagefault {
442 u32 bytes_committed;
443 u8 event_subtype;
444 enum mlx5_pagefault_flags flags;
445 union {
446 /* Initiator or send message responder pagefault details. */
447 struct {
448 /* Received packet size, only valid for responders. */
449 u32 packet_size;
450 /*
451 * WQE index. Refers to either the send queue or
452 * receive queue, according to event_subtype.
453 */
454 u16 wqe_index;
455 } wqe;
456 /* RDMA responder pagefault details */
457 struct {
458 u32 r_key;
459 /*
460 * Received packet size, minimal size page fault
461 * resolution required for forward progress.
462 */
463 u32 packet_size;
464 u32 rdma_op_len;
465 u64 rdma_va;
466 } rdma;
467 };
468 };
469
470 struct mlx5_core_qp {
471 struct mlx5_core_rsc_common common; /* must be first */
472 void (*event) (struct mlx5_core_qp *, int);
473 int qpn;
474 struct mlx5_rsc_debug *dbg;
475 int pid;
476 u16 uid;
477 };
478
479 struct mlx5_qp_path {
480 u8 fl_free_ar;
481 u8 rsvd3;
482 __be16 pkey_index;
483 u8 rsvd0;
484 u8 grh_mlid;
485 __be16 rlid;
486 u8 ackto_lt;
487 u8 mgid_index;
488 u8 static_rate;
489 u8 hop_limit;
490 __be32 tclass_flowlabel;
491 union {
492 u8 rgid[16];
493 u8 rip[16];
494 };
495 u8 f_dscp_ecn_prio;
496 u8 ecn_dscp;
497 __be16 udp_sport;
498 u8 dci_cfi_prio_sl;
499 u8 port;
500 u8 rmac[6];
501 };
502
503 struct mlx5_qp_context {
504 __be32 flags;
505 __be32 flags_pd;
506 u8 mtu_msgmax;
507 u8 rq_size_stride;
508 __be16 sq_crq_size;
509 __be32 qp_counter_set_usr_page;
510 __be32 wire_qpn;
511 __be32 log_pg_sz_remote_qpn;
512 struct mlx5_qp_path pri_path;
513 struct mlx5_qp_path alt_path;
514 __be32 params1;
515 u8 reserved2[4];
516 __be32 next_send_psn;
517 __be32 cqn_send;
518 __be32 deth_sqpn;
519 u8 reserved3[4];
520 __be32 last_acked_psn;
521 __be32 ssn;
522 __be32 params2;
523 __be32 rnr_nextrecvpsn;
524 __be32 xrcd;
525 __be32 cqn_recv;
526 __be64 db_rec_addr;
527 __be32 qkey;
528 __be32 rq_type_srqn;
529 __be32 rmsn;
530 __be16 hw_sq_wqe_counter;
531 __be16 sw_sq_wqe_counter;
532 __be16 hw_rcyclic_byte_counter;
533 __be16 hw_rq_counter;
534 __be16 sw_rcyclic_byte_counter;
535 __be16 sw_rq_counter;
536 u8 rsvd0[5];
537 u8 cgs;
538 u8 cs_req;
539 u8 cs_res;
540 __be64 dc_access_key;
541 u8 rsvd1[24];
542 };
543
544 struct mlx5_dct_context {
545 u8 state;
546 u8 rsvd0[7];
547 __be32 cqn;
548 __be32 flags;
549 u8 rsvd1;
550 u8 cs_res;
551 u8 min_rnr;
552 u8 rsvd2;
553 __be32 srqn;
554 __be32 pdn;
555 __be32 tclass_flow_label;
556 __be64 access_key;
557 u8 mtu;
558 u8 port;
559 __be16 pkey_index;
560 u8 rsvd4;
561 u8 mgid_index;
562 u8 rsvd5;
563 u8 hop_limit;
564 __be32 access_violations;
565 u8 rsvd[12];
566 };
567
568 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
569 {
570 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
571 }
572
573 static inline struct mlx5_core_mkey *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
574 {
575 return radix_tree_lookup(&dev->priv.mr_table.tree, key);
576 }
577
578 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
579 struct mlx5_core_qp *qp,
580 u32 *in,
581 int inlen);
582 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 opcode,
583 u32 opt_param_mask, void *qpc,
584 struct mlx5_core_qp *qp);
585 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
586 struct mlx5_core_qp *qp);
587 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
588 u32 *out, int outlen);
589 int mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct,
590 u32 *out, int outlen);
591 int mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct);
592
593 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
594 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
595 int mlx5_core_create_dct(struct mlx5_core_dev *dev,
596 struct mlx5_core_dct *dct,
597 u32 *in, int inlen,
598 u32 *out, int outlen);
599 int mlx5_core_destroy_dct(struct mlx5_core_dev *dev,
600 struct mlx5_core_dct *dct);
601 int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
602 struct mlx5_core_qp *rq);
603 void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev,
604 struct mlx5_core_qp *rq);
605 int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
606 struct mlx5_core_qp *sq);
607 void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev,
608 struct mlx5_core_qp *sq);
609 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
610 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
611 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
612 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
613
614 static inline const char *mlx5_qp_type_str(int type)
615 {
616 switch (type) {
617 case MLX5_QP_ST_RC: return "RC";
618 case MLX5_QP_ST_UC: return "C";
619 case MLX5_QP_ST_UD: return "UD";
620 case MLX5_QP_ST_XRC: return "XRC";
621 case MLX5_QP_ST_MLX: return "MLX";
622 case MLX5_QP_ST_DCI: return "DCI";
623 case MLX5_QP_ST_QP0: return "QP0";
624 case MLX5_QP_ST_QP1: return "QP1";
625 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
626 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
627 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
628 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
629 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
630 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
631 case MLX5_QP_ST_SW_CNAK: return "DC_CNAK";
632 default: return "Invalid transport type";
633 }
634 }
635
636 static inline const char *mlx5_qp_state_str(int state)
637 {
638 switch (state) {
639 case MLX5_QP_STATE_RST:
640 return "RST";
641 case MLX5_QP_STATE_INIT:
642 return "INIT";
643 case MLX5_QP_STATE_RTR:
644 return "RTR";
645 case MLX5_QP_STATE_RTS:
646 return "RTS";
647 case MLX5_QP_STATE_SQER:
648 return "SQER";
649 case MLX5_QP_STATE_SQD:
650 return "SQD";
651 case MLX5_QP_STATE_ERR:
652 return "ERR";
653 case MLX5_QP_STATE_SQ_DRAINING:
654 return "SQ_DRAINING";
655 case MLX5_QP_STATE_SUSPENDED:
656 return "SUSPENDED";
657 default: return "Invalid QP state";
658 }
659 }
660
661 #endif /* MLX5_QP_H */
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