FreeBSD/Linux Kernel Cross Reference
sys/dev/mmc/mmcreg.h
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
5 * Copyright (c) 2017 Marius Strobl <marius@FreeBSD.org>
6 * Copyright (c) 2015-2016 Ilya Bakulin <kibab@FreeBSD.org>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Portions of this software may have been developed with reference to
29 * the SD Simplified Specification. The following disclaimer may apply:
30 *
31 * The following conditions apply to the release of the simplified
32 * specification ("Simplified Specification") by the SD Card Association and
33 * the SD Group. The Simplified Specification is a subset of the complete SD
34 * Specification which is owned by the SD Card Association and the SD
35 * Group. This Simplified Specification is provided on a non-confidential
36 * basis subject to the disclaimers below. Any implementation of the
37 * Simplified Specification may require a license from the SD Card
38 * Association, SD Group, SD-3C LLC or other third parties.
39 *
40 * Disclaimers:
41 *
42 * The information contained in the Simplified Specification is presented only
43 * as a standard specification for SD Cards and SD Host/Ancillary products and
44 * is provided "AS-IS" without any representations or warranties of any
45 * kind. No responsibility is assumed by the SD Group, SD-3C LLC or the SD
46 * Card Association for any damages, any infringements of patents or other
47 * right of the SD Group, SD-3C LLC, the SD Card Association or any third
48 * parties, which may result from its use. No license is granted by
49 * implication, estoppel or otherwise under any patent or other rights of the
50 * SD Group, SD-3C LLC, the SD Card Association or any third party. Nothing
51 * herein shall be construed as an obligation by the SD Group, the SD-3C LLC
52 * or the SD Card Association to disclose or distribute any technical
53 * information, know-how or other confidential information to any third party.
54 *
55 * $FreeBSD$
56 */
57
58 #ifndef DEV_MMC_MMCREG_H
59 #define DEV_MMC_MMCREG_H
60
61 /*
62 * This file contains the register definitions for the mmc and sd buses.
63 * They are taken from publicly available sources.
64 */
65
66 struct mmc_data;
67 struct mmc_request;
68
69 struct mmc_command {
70 uint32_t opcode;
71 uint32_t arg;
72 uint32_t resp[4];
73 uint32_t flags; /* Expected responses */
74 #define MMC_RSP_PRESENT (1ul << 0) /* Response */
75 #define MMC_RSP_136 (1ul << 1) /* 136 bit response */
76 #define MMC_RSP_CRC (1ul << 2) /* Expect valid crc */
77 #define MMC_RSP_BUSY (1ul << 3) /* Card may send busy */
78 #define MMC_RSP_OPCODE (1ul << 4) /* Response include opcode */
79 #define MMC_RSP_MASK 0x1ful
80 #define MMC_CMD_AC (0ul << 5) /* Addressed Command, no data */
81 #define MMC_CMD_ADTC (1ul << 5) /* Addressed Data transfer cmd */
82 #define MMC_CMD_BC (2ul << 5) /* Broadcast command, no response */
83 #define MMC_CMD_BCR (3ul << 5) /* Broadcast command with response */
84 #define MMC_CMD_MASK (3ul << 5)
85
86 /* Possible response types defined in the standard: */
87 #define MMC_RSP_NONE (0)
88 #define MMC_RSP_R1 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
89 #define MMC_RSP_R1B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
90 #define MMC_RSP_R2 (MMC_RSP_PRESENT | MMC_RSP_136 | MMC_RSP_CRC)
91 #define MMC_RSP_R3 (MMC_RSP_PRESENT)
92 #define MMC_RSP_R4 (MMC_RSP_PRESENT)
93 #define MMC_RSP_R5 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
94 #define MMC_RSP_R5B (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE | MMC_RSP_BUSY)
95 #define MMC_RSP_R6 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
96 #define MMC_RSP_R7 (MMC_RSP_PRESENT | MMC_RSP_CRC | MMC_RSP_OPCODE)
97 #define MMC_RSP(x) ((x) & MMC_RSP_MASK)
98 uint32_t retries;
99 uint32_t error;
100 #define MMC_ERR_NONE 0
101 #define MMC_ERR_TIMEOUT 1
102 #define MMC_ERR_BADCRC 2
103 #define MMC_ERR_FIFO 3
104 #define MMC_ERR_FAILED 4
105 #define MMC_ERR_INVALID 5
106 #define MMC_ERR_NO_MEMORY 6
107 #define MMC_ERR_MAX 6
108 struct mmc_data *data; /* Data segment with cmd */
109 struct mmc_request *mrq; /* backpointer to request */
110 };
111
112 /*
113 * R1 responses
114 *
115 * Types (per SD 2.0 standard)
116 * e : error bit
117 * s : status bit
118 * r : detected and set for the actual command response
119 * x : Detected and set during command execution. The host can get
120 * the status by issuing a command with R1 response.
121 *
122 * Clear Condition (per SD 2.0 standard)
123 * a : according to the card current state.
124 * b : always related to the previous command. reception of a valid
125 * command will clear it (with a delay of one command).
126 * c : clear by read
127 */
128 #define R1_OUT_OF_RANGE (1u << 31) /* erx, c */
129 #define R1_ADDRESS_ERROR (1u << 30) /* erx, c */
130 #define R1_BLOCK_LEN_ERROR (1u << 29) /* erx, c */
131 #define R1_ERASE_SEQ_ERROR (1u << 28) /* er, c */
132 #define R1_ERASE_PARAM (1u << 27) /* erx, c */
133 #define R1_WP_VIOLATION (1u << 26) /* erx, c */
134 #define R1_CARD_IS_LOCKED (1u << 25) /* sx, a */
135 #define R1_LOCK_UNLOCK_FAILED (1u << 24) /* erx, c */
136 #define R1_COM_CRC_ERROR (1u << 23) /* er, b */
137 #define R1_ILLEGAL_COMMAND (1u << 22) /* er, b */
138 #define R1_CARD_ECC_FAILED (1u << 21) /* erx, c */
139 #define R1_CC_ERROR (1u << 20) /* erx, c */
140 #define R1_ERROR (1u << 19) /* erx, c */
141 #define R1_CSD_OVERWRITE (1u << 16) /* erx, c */
142 #define R1_WP_ERASE_SKIP (1u << 15) /* erx, c */
143 #define R1_CARD_ECC_DISABLED (1u << 14) /* sx, a */
144 #define R1_ERASE_RESET (1u << 13) /* sr, c */
145 #define R1_CURRENT_STATE_MASK (0xfu << 9) /* sx, b */
146 #define R1_READY_FOR_DATA (1u << 8) /* sx, a */
147 #define R1_SWITCH_ERROR (1u << 7) /* sx, c */
148 #define R1_APP_CMD (1u << 5) /* sr, c */
149 #define R1_AKE_SEQ_ERROR (1u << 3) /* er, c */
150 #define R1_STATUS(x) ((x) & 0xFFFFE000)
151 #define R1_CURRENT_STATE(x) (((x) & R1_CURRENT_STATE_MASK) >> 9)
152 #define R1_STATE_IDLE 0
153 #define R1_STATE_READY 1
154 #define R1_STATE_IDENT 2
155 #define R1_STATE_STBY 3
156 #define R1_STATE_TRAN 4
157 #define R1_STATE_DATA 5
158 #define R1_STATE_RCV 6
159 #define R1_STATE_PRG 7
160 #define R1_STATE_DIS 8
161
162 /* R4 responses (SDIO) */
163 #define R4_IO_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x3)
164 #define R4_IO_MEM_PRESENT (0x1 << 27)
165 #define R4_IO_OCR_MASK 0x00fffff0
166
167 /*
168 * R5 responses
169 *
170 * Types (per SD 2.0 standard)
171 * e : error bit
172 * s : status bit
173 * r : detected and set for the actual command response
174 * x : Detected and set during command execution. The host can get
175 * the status by issuing a command with R1 response.
176 *
177 * Clear Condition (per SD 2.0 standard)
178 * a : according to the card current state.
179 * b : always related to the previous command. reception of a valid
180 * command will clear it (with a delay of one command).
181 * c : clear by read
182 */
183 #define R5_COM_CRC_ERROR (1u << 15) /* er, b */
184 #define R5_ILLEGAL_COMMAND (1u << 14) /* er, b */
185 #define R5_IO_CURRENT_STATE_MASK (3u << 12) /* s, b */
186 #define R5_IO_CURRENT_STATE(x) (((x) & R5_IO_CURRENT_STATE_MASK) >> 12)
187 #define R5_ERROR (1u << 11) /* erx, c */
188 #define R5_FUNCTION_NUMBER (1u << 9) /* er, c */
189 #define R5_OUT_OF_RANGE (1u << 8) /* er, c */
190
191 struct mmc_data {
192 size_t len; /* size of the data */
193 size_t xfer_len;
194 void *data; /* data buffer */
195 uint32_t flags;
196 #define MMC_DATA_WRITE (1UL << 0)
197 #define MMC_DATA_READ (1UL << 1)
198 #define MMC_DATA_STREAM (1UL << 2)
199 #define MMC_DATA_MULTI (1UL << 3)
200 struct mmc_request *mrq;
201 };
202
203 struct mmc_request {
204 struct mmc_command *cmd;
205 struct mmc_command *stop;
206 void (*done)(struct mmc_request *); /* Completion function */
207 void *done_data; /* requestor set data */
208 uint32_t flags;
209 #define MMC_REQ_DONE 1
210 #define MMC_TUNE_DONE 2
211 };
212
213 /* Command definitions */
214
215 /* Class 0 and 1: Basic commands & read stream commands */
216 #define MMC_GO_IDLE_STATE 0
217 #define MMC_SEND_OP_COND 1
218 #define MMC_ALL_SEND_CID 2
219 #define MMC_SET_RELATIVE_ADDR 3
220 #define SD_SEND_RELATIVE_ADDR 3
221 #define MMC_SET_DSR 4
222 #define MMC_SLEEP_AWAKE 5
223 #define IO_SEND_OP_COND 5
224 #define MMC_SWITCH_FUNC 6
225 #define MMC_SWITCH_FUNC_CMDS 0
226 #define MMC_SWITCH_FUNC_SET 1
227 #define MMC_SWITCH_FUNC_CLR 2
228 #define MMC_SWITCH_FUNC_WR 3
229 #define MMC_SELECT_CARD 7
230 #define MMC_DESELECT_CARD 7
231 #define MMC_SEND_EXT_CSD 8
232 #define SD_SEND_IF_COND 8
233 #define MMC_SEND_CSD 9
234 #define MMC_SEND_CID 10
235 #define MMC_READ_DAT_UNTIL_STOP 11
236 #define MMC_STOP_TRANSMISSION 12
237 #define MMC_SEND_STATUS 13
238 #define MMC_BUSTEST_R 14
239 #define MMC_GO_INACTIVE_STATE 15
240 #define MMC_BUSTEST_W 19
241
242 /* Class 2: Block oriented read commands */
243 #define MMC_SET_BLOCKLEN 16
244 #define MMC_READ_SINGLE_BLOCK 17
245 #define MMC_READ_MULTIPLE_BLOCK 18
246 #define MMC_SEND_TUNING_BLOCK 19
247 #define MMC_SEND_TUNING_BLOCK_HS200 21
248
249 /* Class 3: Stream write commands */
250 #define MMC_WRITE_DAT_UNTIL_STOP 20
251 /* reserved: 22 */
252
253 /* Class 4: Block oriented write commands */
254 #define MMC_SET_BLOCK_COUNT 23
255 #define MMC_WRITE_BLOCK 24
256 #define MMC_WRITE_MULTIPLE_BLOCK 25
257 #define MMC_PROGARM_CID 26
258 #define MMC_PROGRAM_CSD 27
259
260 /* Class 6: Block oriented write protection commands */
261 #define MMC_SET_WRITE_PROT 28
262 #define MMC_CLR_WRITE_PROT 29
263 #define MMC_SEND_WRITE_PROT 30
264 /* reserved: 31 */
265
266 /* Class 5: Erase commands */
267 #define SD_ERASE_WR_BLK_START 32
268 #define SD_ERASE_WR_BLK_END 33
269 /* 34 -- reserved old command */
270 #define MMC_ERASE_GROUP_START 35
271 #define MMC_ERASE_GROUP_END 36
272 /* 37 -- reserved old command */
273 #define MMC_ERASE 38
274 #define MMC_ERASE_ERASE 0x00000000
275 #define MMC_ERASE_TRIM 0x00000001
276 #define MMC_ERASE_FULE 0x00000002
277 #define MMC_ERASE_DISCARD 0x00000003
278 #define MMC_ERASE_SECURE_ERASE 0x80000000
279 #define MMC_ERASE_SECURE_TRIM1 0x80000001
280 #define MMC_ERASE_SECURE_TRIM2 0x80008000
281
282 /* Class 9: I/O mode commands */
283 #define MMC_FAST_IO 39
284 #define MMC_GO_IRQ_STATE 40
285 /* reserved: 41 */
286
287 /* Class 7: Lock card */
288 #define MMC_LOCK_UNLOCK 42
289 /* reserved: 43 */
290 /* reserved: 44 */
291 /* reserved: 45 */
292 /* reserved: 46 */
293 /* reserved: 47 */
294 /* reserved: 48 */
295 /* reserved: 49 */
296 /* reserved: 50 */
297 /* reserved: 51 */
298 /* reserved: 54 */
299
300 /* Class 8: Application specific commands */
301 #define MMC_APP_CMD 55
302 #define MMC_GEN_CMD 56
303 /* reserved: 57 */
304 /* reserved: 58 */
305 /* reserved: 59 */
306 /* reserved for mfg: 60 */
307 /* reserved for mfg: 61 */
308 /* reserved for mfg: 62 */
309 /* reserved for mfg: 63 */
310
311 /* Class 9: I/O cards (sd) */
312 #define SD_IO_RW_DIRECT 52
313 /* CMD52 arguments */
314 #define SD_ARG_CMD52_READ (0 << 31)
315 #define SD_ARG_CMD52_WRITE (1 << 31)
316 #define SD_ARG_CMD52_FUNC_SHIFT 28
317 #define SD_ARG_CMD52_FUNC_MASK 0x7
318 #define SD_ARG_CMD52_EXCHANGE (1 << 27)
319 #define SD_ARG_CMD52_REG_SHIFT 9
320 #define SD_ARG_CMD52_REG_MASK 0x1ffff
321 #define SD_ARG_CMD52_DATA_SHIFT 0
322 #define SD_ARG_CMD52_DATA_MASK 0xff
323 #define SD_R5_DATA(resp) ((resp)[0] & 0xff)
324
325 #define SD_IO_RW_EXTENDED 53
326 /* CMD53 arguments */
327 #define SD_ARG_CMD53_READ (0 << 31)
328 #define SD_ARG_CMD53_WRITE (1 << 31)
329 #define SD_ARG_CMD53_FUNC_SHIFT 28
330 #define SD_ARG_CMD53_FUNC_MASK 0x7
331 #define SD_ARG_CMD53_BLOCK_MODE (1 << 27)
332 #define SD_ARG_CMD53_INCREMENT (1 << 26)
333 #define SD_ARG_CMD53_REG_SHIFT 9
334 #define SD_ARG_CMD53_REG_MASK 0x1ffff
335 #define SD_ARG_CMD53_LENGTH_SHIFT 0
336 #define SD_ARG_CMD53_LENGTH_MASK 0x1ff
337 #define SD_ARG_CMD53_LENGTH_MAX 64 /* XXX should be 511? */
338
339 /* Class 10: Switch function commands */
340 #define SD_SWITCH_FUNC 6
341 /* reserved: 34 */
342 /* reserved: 35 */
343 /* reserved: 36 */
344 /* reserved: 37 */
345 /* reserved: 50 */
346 /* reserved: 57 */
347
348 /* Application specific commands for SD */
349 #define ACMD_SET_BUS_WIDTH 6
350 #define ACMD_SD_STATUS 13
351 #define ACMD_SEND_NUM_WR_BLOCKS 22
352 #define ACMD_SET_WR_BLK_ERASE_COUNT 23
353 #define ACMD_SD_SEND_OP_COND 41
354 #define ACMD_SET_CLR_CARD_DETECT 42
355 #define ACMD_SEND_SCR 51
356
357 /*
358 * EXT_CSD fields
359 */
360 #define EXT_CSD_FLUSH_CACHE 32 /* W/E */
361 #define EXT_CSD_CACHE_CTRL 33 /* R/W/E */
362 #define EXT_CSD_EXT_PART_ATTR 52 /* R/W, 2 bytes */
363 #define EXT_CSD_ENH_START_ADDR 136 /* R/W, 4 bytes */
364 #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W, 3 bytes */
365 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W, 12 bytes */
366 #define EXT_CSD_PART_SET 155 /* R/W */
367 #define EXT_CSD_PART_ATTR 156 /* R/W */
368 #define EXT_CSD_PART_SUPPORT 160 /* RO */
369 #define EXT_CSD_RPMB_MULT 168 /* RO */
370 #define EXT_CSD_BOOT_WP_STATUS 174 /* RO */
371 #define EXT_CSD_ERASE_GRP_DEF 175 /* R/W */
372 #define EXT_CSD_PART_CONFIG 179 /* R/W */
373 #define EXT_CSD_BUS_WIDTH 183 /* R/W */
374 #define EXT_CSD_STROBE_SUPPORT 184 /* RO */
375 #define EXT_CSD_HS_TIMING 185 /* R/W */
376 #define EXT_CSD_POWER_CLASS 187 /* R/W */
377 #define EXT_CSD_CARD_TYPE 196 /* RO */
378 #define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
379 #define EXT_CSD_REV 192 /* RO */
380 #define EXT_CSD_PART_SWITCH_TO 199 /* RO */
381 #define EXT_CSD_PWR_CL_52_195 200 /* RO */
382 #define EXT_CSD_PWR_CL_26_195 201 /* RO */
383 #define EXT_CSD_PWR_CL_52_360 202 /* RO */
384 #define EXT_CSD_PWR_CL_26_360 203 /* RO */
385 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
386 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
387 #define EXT_CSD_ERASE_TO_MULT 223 /* RO */
388 #define EXT_CSD_ERASE_GRP_SIZE 224 /* RO */
389 #define EXT_CSD_BOOT_SIZE_MULT 226 /* RO */
390 #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
391 #define EXT_CSD_PWR_CL_200_195 236 /* RO */
392 #define EXT_CSD_PWR_CL_200_360 237 /* RO */
393 #define EXT_CSD_PWR_CL_52_195_DDR 238 /* RO */
394 #define EXT_CSD_PWR_CL_52_360_DDR 239 /* RO */
395 #define EXT_CSD_CACHE_FLUSH_POLICY 249 /* RO */
396 #define EXT_CSD_GEN_CMD6_TIME 248 /* RO */
397 #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */
398 #define EXT_CSD_PWR_CL_200_360_DDR 253 /* RO */
399
400 /*
401 * EXT_CSD field definitions
402 */
403 #define EXT_CSD_FLUSH_CACHE_FLUSH 0x01
404 #define EXT_CSD_FLUSH_CACHE_BARRIER 0x02
405
406 #define EXT_CSD_CACHE_CTRL_CACHE_EN 0x01
407
408 #define EXT_CSD_EXT_PART_ATTR_DEFAULT 0x0
409 #define EXT_CSD_EXT_PART_ATTR_SYSTEMCODE 0x1
410 #define EXT_CSD_EXT_PART_ATTR_NPERSISTENT 0x2
411
412 #define EXT_CSD_PART_SET_COMPLETED 0x01
413
414 #define EXT_CSD_PART_ATTR_ENH_USR 0x01
415 #define EXT_CSD_PART_ATTR_ENH_GP0 0x02
416 #define EXT_CSD_PART_ATTR_ENH_GP1 0x04
417 #define EXT_CSD_PART_ATTR_ENH_GP2 0x08
418 #define EXT_CSD_PART_ATTR_ENH_GP3 0x10
419 #define EXT_CSD_PART_ATTR_ENH_MASK 0x1f
420
421 #define EXT_CSD_PART_SUPPORT_EN 0x01
422 #define EXT_CSD_PART_SUPPORT_ENH_ATTR_EN 0x02
423 #define EXT_CSD_PART_SUPPORT_EXT_ATTR_EN 0x04
424
425 #define EXT_CSD_BOOT_WP_STATUS_BOOT0_PWR 0x01
426 #define EXT_CSD_BOOT_WP_STATUS_BOOT0_PERM 0x02
427 #define EXT_CSD_BOOT_WP_STATUS_BOOT0_MASK 0x03
428 #define EXT_CSD_BOOT_WP_STATUS_BOOT1_PWR 0x04
429 #define EXT_CSD_BOOT_WP_STATUS_BOOT1_PERM 0x08
430 #define EXT_CSD_BOOT_WP_STATUS_BOOT1_MASK 0x0c
431
432 #define EXT_CSD_ERASE_GRP_DEF_EN 0x01
433
434 #define EXT_CSD_PART_CONFIG_ACC_DEFAULT 0x00
435 #define EXT_CSD_PART_CONFIG_ACC_BOOT0 0x01
436 #define EXT_CSD_PART_CONFIG_ACC_BOOT1 0x02
437 #define EXT_CSD_PART_CONFIG_ACC_RPMB 0x03
438 #define EXT_CSD_PART_CONFIG_ACC_GP0 0x04
439 #define EXT_CSD_PART_CONFIG_ACC_GP1 0x05
440 #define EXT_CSD_PART_CONFIG_ACC_GP2 0x06
441 #define EXT_CSD_PART_CONFIG_ACC_GP3 0x07
442 #define EXT_CSD_PART_CONFIG_ACC_MASK 0x07
443 #define EXT_CSD_PART_CONFIG_BOOT0 0x08
444 #define EXT_CSD_PART_CONFIG_BOOT1 0x10
445 #define EXT_CSD_PART_CONFIG_BOOT_USR 0x38
446 #define EXT_CSD_PART_CONFIG_BOOT_MASK 0x38
447 #define EXT_CSD_PART_CONFIG_BOOT_ACK 0x40
448
449 #define EXT_CSD_CMD_SET_NORMAL 1
450 #define EXT_CSD_CMD_SET_SECURE 2
451 #define EXT_CSD_CMD_SET_CPSECURE 4
452
453 #define EXT_CSD_HS_TIMING_BC 0
454 #define EXT_CSD_HS_TIMING_HS 1
455 #define EXT_CSD_HS_TIMING_HS200 2
456 #define EXT_CSD_HS_TIMING_HS400 3
457 #define EXT_CSD_HS_TIMING_DRV_STR_SHIFT 4
458
459 #define EXT_CSD_POWER_CLASS_8BIT_MASK 0xf0
460 #define EXT_CSD_POWER_CLASS_8BIT_SHIFT 4
461 #define EXT_CSD_POWER_CLASS_4BIT_MASK 0x0f
462 #define EXT_CSD_POWER_CLASS_4BIT_SHIFT 0
463
464 #define EXT_CSD_CARD_TYPE_HS_26 0x0001
465 #define EXT_CSD_CARD_TYPE_HS_52 0x0002
466 #define EXT_CSD_CARD_TYPE_DDR_52_1_8V 0x0004
467 #define EXT_CSD_CARD_TYPE_DDR_52_1_2V 0x0008
468 #define EXT_CSD_CARD_TYPE_HS200_1_8V 0x0010
469 #define EXT_CSD_CARD_TYPE_HS200_1_2V 0x0020
470 #define EXT_CSD_CARD_TYPE_HS400_1_8V 0x0040
471 #define EXT_CSD_CARD_TYPE_HS400_1_2V 0x0080
472
473 #define EXT_CSD_BUS_WIDTH_1 0
474 #define EXT_CSD_BUS_WIDTH_4 1
475 #define EXT_CSD_BUS_WIDTH_8 2
476 #define EXT_CSD_BUS_WIDTH_4_DDR 5
477 #define EXT_CSD_BUS_WIDTH_8_DDR 6
478 #define EXT_CSD_BUS_WIDTH_ES 0x80
479
480 #define EXT_CSD_STROBE_SUPPORT_EN 0x01
481
482 #define EXT_CSD_SEC_FEATURE_SUPPORT_ER_EN 0x01
483 #define EXT_CSD_SEC_FEATURE_SUPPORT_BD_BLK_EN 0x04
484 #define EXT_CSD_SEC_FEATURE_SUPPORT_GB_CL_EN 0x10
485 #define EXT_CSD_SEC_FEATURE_SUPPORT_SANITIZE 0x40
486
487 #define EXT_CSD_CACHE_FLUSH_POLICY_FIFO 0x01
488
489 /*
490 * Vendor specific EXT_CSD fields
491 */
492 /* SanDisk iNAND */
493 #define EXT_CSD_INAND_CMD38 113
494 #define EXT_CSD_INAND_CMD38_ERASE 0x00
495 #define EXT_CSD_INAND_CMD38_TRIM 0x01
496 #define EXT_CSD_INAND_CMD38_SECURE_ERASE 0x80
497 #define EXT_CSD_INAND_CMD38_SECURE_TRIM1 0x81
498 #define EXT_CSD_INAND_CMD38_SECURE_TRIM2 0x82
499
500 #define MMC_TYPE_HS_26_MAX 26000000
501 #define MMC_TYPE_HS_52_MAX 52000000
502 #define MMC_TYPE_DDR52_MAX 52000000
503 #define MMC_TYPE_HS200_HS400ES_MAX 200000000
504
505 /*
506 * SD bus widths
507 */
508 #define SD_BUS_WIDTH_1 0
509 #define SD_BUS_WIDTH_4 2
510
511 /*
512 * SD Switch
513 */
514 #define SD_SWITCH_MODE_CHECK 0
515 #define SD_SWITCH_MODE_SET 1
516 #define SD_SWITCH_GROUP1 0
517 #define SD_SWITCH_NORMAL_MODE 0
518 #define SD_SWITCH_HS_MODE 1
519 #define SD_SWITCH_SDR50_MODE 2
520 #define SD_SWITCH_SDR104_MODE 3
521 #define SD_SWITCH_DDR50 4
522 #define SD_SWITCH_NOCHANGE 0xF
523
524 #define SD_CLR_CARD_DETECT 0
525 #define SD_SET_CARD_DETECT 1
526
527 #define SD_HS_MAX 50000000
528 #define SD_DDR50_MAX 50000000
529 #define SD_SDR12_MAX 25000000
530 #define SD_SDR25_MAX 50000000
531 #define SD_SDR50_MAX 100000000
532 #define SD_SDR104_MAX 208000000
533
534 /* Specifications require 400 kHz max. during ID phase. */
535 #define SD_MMC_CARD_ID_FREQUENCY 400000
536
537 /*
538 * SDIO Direct & Extended I/O
539 */
540 #define SD_IO_RW_WR (1u << 31)
541 #define SD_IO_RW_FUNC(x) (((x) & 0x7) << 28)
542 #define SD_IO_RW_RAW (1u << 27)
543 #define SD_IO_RW_INCR (1u << 26)
544 #define SD_IO_RW_ADR(x) (((x) & 0x1FFFF) << 9)
545 #define SD_IO_RW_DAT(x) (((x) & 0xFF) << 0)
546 #define SD_IO_RW_LEN(x) (((x) & 0xFF) << 0)
547
548 #define SD_IOE_RW_LEN(x) (((x) & 0x1FF) << 0)
549 #define SD_IOE_RW_BLK (1u << 27)
550
551 /* Card Common Control Registers (CCCR) */
552 #define SD_IO_CCCR_START 0x00000
553 #define SD_IO_CCCR_SIZE 0x100
554 #define SD_IO_CCCR_FN_ENABLE 0x02
555 #define SD_IO_CCCR_FN_READY 0x03
556 #define SD_IO_CCCR_INT_ENABLE 0x04
557 #define SD_IO_CCCR_INT_PENDING 0x05
558 #define SD_IO_CCCR_CTL 0x06
559 #define CCCR_CTL_RES (1 << 3)
560 #define SD_IO_CCCR_BUS_WIDTH 0x07
561 #define CCCR_BUS_WIDTH_4 (1 << 1)
562 #define CCCR_BUS_WIDTH_1 (1 << 0)
563 #define SD_IO_CCCR_CARDCAP 0x08
564 #define SD_IO_CCCR_CISPTR 0x09 /* XXX 9-10, 10-11, or 9-12 */
565
566 /* Function Basic Registers (FBR) */
567 #define SD_IO_FBR_START 0x00100
568 #define SD_IO_FBR_SIZE 0x00700
569
570 /* Card Information Structure (CIS) */
571 #define SD_IO_CIS_START 0x01000
572 #define SD_IO_CIS_SIZE 0x17000
573
574 /* CIS tuple codes (based on PC Card 16) */
575 #define SD_IO_CISTPL_VERS_1 0x15
576 #define SD_IO_CISTPL_MANFID 0x20
577 #define SD_IO_CISTPL_FUNCID 0x21
578 #define SD_IO_CISTPL_FUNCE 0x22
579 #define SD_IO_CISTPL_END 0xff
580
581 /* CISTPL_FUNCID codes */
582 /* OpenBSD incorrectly defines 0x0c as FUNCTION_WLAN */
583 /* #define SDMMC_FUNCTION_WLAN 0x0c */
584
585 /* OCR bits */
586
587 /*
588 * in SD 2.0 spec, bits 8-14 are now marked reserved
589 * Low voltage in SD2.0 spec is bit 7, TBD voltage
590 * Low voltage in MC 3.31 spec is bit 7, 1.65-1.95V
591 * Specs prior to MMC 3.31 defined bits 0-7 as voltages down to 1.5V.
592 * 3.31 redefined them to be reserved and also said that cards had to
593 * support the 2.7-3.6V and fixed the OCR to be 0xfff8000 for high voltage
594 * cards. MMC 4.0 says that a dual voltage card responds with 0xfff8080.
595 * Looks like the fine-grained control of the voltage tolerance ranges
596 * was abandoned.
597 *
598 * The MMC_OCR_CCS appears to be valid for only SD cards.
599 */
600 #define MMC_OCR_VOLTAGE 0x3fffffffU /* Vdd Voltage mask */
601 #define MMC_OCR_LOW_VOLTAGE (1u << 7) /* Low Voltage Range -- tbd */
602 #define MMC_OCR_MIN_VOLTAGE_SHIFT 7
603 #define MMC_OCR_200_210 (1U << 8) /* Vdd voltage 2.00 ~ 2.10 */
604 #define MMC_OCR_210_220 (1U << 9) /* Vdd voltage 2.10 ~ 2.20 */
605 #define MMC_OCR_220_230 (1U << 10) /* Vdd voltage 2.20 ~ 2.30 */
606 #define MMC_OCR_230_240 (1U << 11) /* Vdd voltage 2.30 ~ 2.40 */
607 #define MMC_OCR_240_250 (1U << 12) /* Vdd voltage 2.40 ~ 2.50 */
608 #define MMC_OCR_250_260 (1U << 13) /* Vdd voltage 2.50 ~ 2.60 */
609 #define MMC_OCR_260_270 (1U << 14) /* Vdd voltage 2.60 ~ 2.70 */
610 #define MMC_OCR_270_280 (1U << 15) /* Vdd voltage 2.70 ~ 2.80 */
611 #define MMC_OCR_280_290 (1U << 16) /* Vdd voltage 2.80 ~ 2.90 */
612 #define MMC_OCR_290_300 (1U << 17) /* Vdd voltage 2.90 ~ 3.00 */
613 #define MMC_OCR_300_310 (1U << 18) /* Vdd voltage 3.00 ~ 3.10 */
614 #define MMC_OCR_310_320 (1U << 19) /* Vdd voltage 3.10 ~ 3.20 */
615 #define MMC_OCR_320_330 (1U << 20) /* Vdd voltage 3.20 ~ 3.30 */
616 #define MMC_OCR_330_340 (1U << 21) /* Vdd voltage 3.30 ~ 3.40 */
617 #define MMC_OCR_340_350 (1U << 22) /* Vdd voltage 3.40 ~ 3.50 */
618 #define MMC_OCR_350_360 (1U << 23) /* Vdd voltage 3.50 ~ 3.60 */
619 #define MMC_OCR_MAX_VOLTAGE_SHIFT 23
620 #define MMC_OCR_S18R (1U << 24) /* Switching to 1.8 V requested (SD) */
621 #define MMC_OCR_S18A MMC_OCR_S18R /* Switching to 1.8 V accepted (SD) */
622 #define MMC_OCR_XPC (1U << 28) /* SDXC Power Control */
623 #define MMC_OCR_ACCESS_MODE_BYTE (0U << 29) /* Access Mode Byte (MMC) */
624 #define MMC_OCR_ACCESS_MODE_SECT (1U << 29) /* Access Mode Sector (MMC) */
625 #define MMC_OCR_ACCESS_MODE_MASK (3U << 29)
626 #define MMC_OCR_CCS (1u << 30) /* Card Capacity status (SD vs SDHC) */
627 #define MMC_OCR_CARD_BUSY (1U << 31) /* Card Power up status */
628
629 /* CSD -- decoded structure */
630 struct mmc_cid {
631 uint32_t mid;
632 char pnm[8];
633 uint32_t psn;
634 uint16_t oid;
635 uint16_t mdt_year;
636 uint8_t mdt_month;
637 uint8_t prv;
638 uint8_t fwrev;
639 };
640
641 struct mmc_csd {
642 uint8_t csd_structure;
643 uint8_t spec_vers;
644 uint16_t ccc;
645 uint16_t tacc;
646 uint32_t nsac;
647 uint32_t r2w_factor;
648 uint32_t tran_speed;
649 uint32_t read_bl_len;
650 uint32_t write_bl_len;
651 uint32_t vdd_r_curr_min;
652 uint32_t vdd_r_curr_max;
653 uint32_t vdd_w_curr_min;
654 uint32_t vdd_w_curr_max;
655 uint32_t wp_grp_size;
656 uint32_t erase_sector;
657 uint64_t capacity;
658 unsigned int read_bl_partial:1,
659 read_blk_misalign:1,
660 write_bl_partial:1,
661 write_blk_misalign:1,
662 dsr_imp:1,
663 erase_blk_en:1,
664 wp_grp_enable:1;
665 };
666
667 struct mmc_scr {
668 unsigned char sda_vsn;
669 unsigned char bus_widths;
670 #define SD_SCR_BUS_WIDTH_1 (1 << 0)
671 #define SD_SCR_BUS_WIDTH_4 (1 << 2)
672 };
673
674 struct mmc_sd_status {
675 uint8_t bus_width;
676 uint8_t secured_mode;
677 uint16_t card_type;
678 uint16_t prot_area;
679 uint8_t speed_class;
680 uint8_t perf_move;
681 uint8_t au_size;
682 uint16_t erase_size;
683 uint8_t erase_timeout;
684 uint8_t erase_offset;
685 };
686
687 struct mmc_quirk {
688 uint32_t mid;
689 #define MMC_QUIRK_MID_ANY ((uint32_t)-1)
690 uint16_t oid;
691 #define MMC_QUIRK_OID_ANY ((uint16_t)-1)
692 const char *pnm;
693 uint32_t quirks;
694 #define MMC_QUIRK_INAND_CMD38 0x0001
695 #define MMC_QUIRK_BROKEN_TRIM 0x0002
696 };
697
698 #define MMC_QUIRKS_FMT "\020" "\001INAND_CMD38" "\002BROKEN_TRIM"
699
700 /*
701 * Various MMC/SD constants
702 */
703 #define MMC_BOOT_RPMB_BLOCK_SIZE (128 * 1024)
704
705 #define MMC_EXTCSD_SIZE 512
706
707 #define MMC_PART_GP_MAX 4
708 #define MMC_PART_MAX 8
709
710 #define MMC_TUNING_MAX 64 /* Maximum tuning iterations */
711 #define MMC_TUNING_LEN 64 /* Size of tuning data */
712 #define MMC_TUNING_LEN_HS200 128 /* Size of tuning data in HS200 mode */
713
714 /*
715 * Older versions of the MMC standard had a variable sector size. However,
716 * I've been able to find no old MMC or SD cards that have a non 512
717 * byte sector size anywhere, so we assume that such cards are very rare
718 * and only note their existence in passing here...
719 */
720 #define MMC_SECTOR_SIZE 512
721
722 #endif /* DEV_MMCREG_H */
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