The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/dev/mpr/mpi/mpi2_cnfg.h

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    1 /*-
    2  * Copyright (c) 2012-2015 LSI Corp.
    3  * Copyright (c) 2013-2016 Avago Technologies
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. Neither the name of the author nor the names of any co-contributors
   15  *    may be used to endorse or promote products derived from this software
   16  *    without specific prior written permission.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
   31  *
   32  * $FreeBSD$
   33  */
   34 
   35 /*
   36  *  Copyright (c) 2000-2015 LSI Corporation.
   37  *  Copyright (c) 2013-2016 Avago Technologies
   38  *  All rights reserved.
   39  *
   40  *
   41  *           Name:  mpi2_cnfg.h
   42  *          Title:  MPI Configuration messages and pages
   43  *  Creation Date:  November 10, 2006
   44  *
   45  *    mpi2_cnfg.h Version:  02.00.40
   46  *
   47  *  NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
   48  *        prefix are for use only on MPI v2.5 products, and must not be used
   49  *        with MPI v2.0 products. Unless otherwise noted, names beginning with
   50  *        MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
   51  *
   52  *  Version History
   53  *  ---------------
   54  *
   55  *  Date      Version   Description
   56  *  --------  --------  ------------------------------------------------------
   57  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
   58  *  06-04-07  02.00.01  Added defines for SAS IO Unit Page 2 PhyFlags.
   59  *                      Added Manufacturing Page 11.
   60  *                      Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
   61  *                      define.
   62  *  06-26-07  02.00.02  Adding generic structure for product-specific
   63  *                      Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
   64  *                      Rework of BIOS Page 2 configuration page.
   65  *                      Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
   66  *                      forms.
   67  *                      Added configuration pages IOC Page 8 and Driver
   68  *                      Persistent Mapping Page 0.
   69  *  08-31-07  02.00.03  Modified configuration pages dealing with Integrated
   70  *                      RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
   71  *                      RAID Physical Disk Pages 0 and 1, RAID Configuration
   72  *                      Page 0).
   73  *                      Added new value for AccessStatus field of SAS Device
   74  *                      Page 0 (_SATA_NEEDS_INITIALIZATION).
   75  *  10-31-07  02.00.04  Added missing SEPDevHandle field to
   76  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
   77  *  12-18-07  02.00.05  Modified IO Unit Page 0 to use 32-bit version fields for
   78  *                      NVDATA.
   79  *                      Modified IOC Page 7 to use masks and added field for
   80  *                      SASBroadcastPrimitiveMasks.
   81  *                      Added MPI2_CONFIG_PAGE_BIOS_4.
   82  *                      Added MPI2_CONFIG_PAGE_LOG_0.
   83  *  02-29-08  02.00.06  Modified various names to make them 32-character unique.
   84  *                      Added SAS Device IDs.
   85  *                      Updated Integrated RAID configuration pages including
   86  *                      Manufacturing Page 4, IOC Page 6, and RAID Configuration
   87  *                      Page 0.
   88  *  05-21-08  02.00.07  Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
   89  *                      Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
   90  *                      Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
   91  *                      Added missing MaxNumRoutedSasAddresses field to
   92  *                      MPI2_CONFIG_PAGE_EXPANDER_0.
   93  *                      Added SAS Port Page 0.
   94  *                      Modified structure layout for
   95  *                      MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
   96  *  06-27-08  02.00.08  Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
   97  *                      MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
   98  *  10-02-08  02.00.09  Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
   99  *                      to 0x000000FF.
  100  *                      Added two new values for the Physical Disk Coercion Size
  101  *                      bits in the Flags field of Manufacturing Page 4.
  102  *                      Added product-specific Manufacturing pages 16 to 31.
  103  *                      Modified Flags bits for controlling write cache on SATA
  104  *                      drives in IO Unit Page 1.
  105  *                      Added new bit to AdditionalControlFlags of SAS IO Unit
  106  *                      Page 1 to control Invalid Topology Correction.
  107  *                      Added additional defines for RAID Volume Page 0
  108  *                      VolumeStatusFlags field.
  109  *                      Modified meaning of RAID Volume Page 0 VolumeSettings
  110  *                      define for auto-configure of hot-swap drives.
  111  *                      Added SupportedPhysDisks field to RAID Volume Page 1 and
  112  *                      added related defines.
  113  *                      Added PhysDiskAttributes field (and related defines) to
  114  *                      RAID Physical Disk Page 0.
  115  *                      Added MPI2_SAS_PHYINFO_PHY_VACANT define.
  116  *                      Added three new DiscoveryStatus bits for SAS IO Unit
  117  *                      Page 0 and SAS Expander Page 0.
  118  *                      Removed multiplexing information from SAS IO Unit pages.
  119  *                      Added BootDeviceWaitTime field to SAS IO Unit Page 4.
  120  *                      Removed Zone Address Resolved bit from PhyInfo and from
  121  *                      Expander Page 0 Flags field.
  122  *                      Added two new AccessStatus values to SAS Device Page 0
  123  *                      for indicating routing problems. Added 3 reserved words
  124  *                      to this page.
  125  *  01-19-09  02.00.10  Fixed defines for GPIOVal field of IO Unit Page 3.
  126  *                      Inserted missing reserved field into structure for IOC
  127  *                      Page 6.
  128  *                      Added more pending task bits to RAID Volume Page 0
  129  *                      VolumeStatusFlags defines.
  130  *                      Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
  131  *                      Added a new DiscoveryStatus bit for SAS IO Unit Page 0
  132  *                      and SAS Expander Page 0 to flag a downstream initiator
  133  *                      when in simplified routing mode.
  134  *                      Removed SATA Init Failure defines for DiscoveryStatus
  135  *                      fields of SAS IO Unit Page 0 and SAS Expander Page 0.
  136  *                      Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
  137  *                      Added PortGroups, DmaGroup, and ControlGroup fields to
  138  *                      SAS Device Page 0.
  139  *  05-06-09  02.00.11  Added structures and defines for IO Unit Page 5 and IO
  140  *                      Unit Page 6.
  141  *                      Added expander reduced functionality data to SAS
  142  *                      Expander Page 0.
  143  *                      Added SAS PHY Page 2 and SAS PHY Page 3.
  144  *  07-30-09  02.00.12  Added IO Unit Page 7.
  145  *                      Added new device ids.
  146  *                      Added SAS IO Unit Page 5.
  147  *                      Added partial and slumber power management capable flags
  148  *                      to SAS Device Page 0 Flags field.
  149  *                      Added PhyInfo defines for power condition.
  150  *                      Added Ethernet configuration pages.
  151  *  10-28-09  02.00.13  Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
  152  *                      Added SAS PHY Page 4 structure and defines.
  153  *  02-10-10  02.00.14  Modified the comments for the configuration page
  154  *                      structures that contain an array of data. The host
  155  *                      should use the "count" field in the page data (e.g. the
  156  *                      NumPhys field) to determine the number of valid elements
  157  *                      in the array.
  158  *                      Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
  159  *                      Added PowerManagementCapabilities to IO Unit Page 7.
  160  *                      Added PortWidthModGroup field to
  161  *                      MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
  162  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
  163  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
  164  *                      Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
  165  *  05-12-10  02.00.15  Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
  166  *                      define.
  167  *                      Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
  168  *                      Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
  169  *  08-11-10  02.00.16  Removed IO Unit Page 1 device path (multi-pathing)
  170  *                      defines.
  171  *  11-10-10  02.00.17  Added ReceptacleID field (replacing Reserved1) to
  172  *                      MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
  173  *                      the Pinout field.
  174  *                      Added BoardTemperature and BoardTemperatureUnits fields
  175  *                      to MPI2_CONFIG_PAGE_IO_UNIT_7.
  176  *                      Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
  177  *                      and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
  178  *  02-23-11  02.00.18  Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
  179  *                      Added IO Unit Page 8, IO Unit Page 9,
  180  *                      and IO Unit Page 10.
  181  *                      Added SASNotifyPrimitiveMasks field to
  182  *                      MPI2_CONFIG_PAGE_IOC_7.
  183  *  03-09-11  02.00.19  Fixed IO Unit Page 10 (to match the spec).
  184  *  05-25-11  02.00.20  Cleaned up a few comments.
  185  *  08-24-11  02.00.21  Marked the IO Unit Page 7 PowerManagementCapabilities
  186  *                      for PCIe link as obsolete.
  187  *                      Added SpinupFlags field containing a Disable Spin-up bit
  188  *                      to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
  189  *                      Unit Page 4.
  190  *  11-18-11  02.00.22  Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
  191  *                      Added UEFIVersion field to BIOS Page 1 and defined new
  192  *                      BiosOptions bits.
  193  *                      Incorporating additions for MPI v2.5.
  194  *  11-27-12  02.00.23  Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
  195  *                      Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
  196  *  12-20-12  02.00.24  Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as
  197  *                      obsolete for MPI v2.5 and later.
  198  *                      Added some defines for 12G SAS speeds.
  199  *  04-09-13  02.00.25  Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK.
  200  *                      Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to
  201  *                      match the specification.
  202  *  08-19-13  02.00.26  Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for
  203  *                      future use.
  204  *  12-05-13  02.00.27  Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for
  205  *                      MPI2_CONFIG_PAGE_MAN_7.
  206  *                      Added EnclosureLevel and ConnectorName fields to
  207  *                      MPI2_CONFIG_PAGE_SAS_DEV_0.
  208  *                      Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for
  209  *                      MPI2_CONFIG_PAGE_SAS_DEV_0.
  210  *                      Added EnclosureLevel field to
  211  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
  212  *                      Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for
  213  *                      MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
  214  *  01-08-14  02.00.28  Added more defines for the BiosOptions field of
  215  *                      MPI2_CONFIG_PAGE_BIOS_1.
  216  *  06-13-14  02.00.29  Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and
  217  *                      more defines for the BiosOptions field.
  218  *  11-18-14  02.00.30  Updated copyright information.
  219  *                      Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG.
  220  *                      Added AdapterOrderAux fields to BIOS Page 3.
  221  *  03-16-15  02.00.31  Updated for MPI v2.6.
  222  *                      Added BoardPowerRequirement, PCISlotPowerAllocation, and
  223  *                      Flags field to IO Unit Page 7.
  224  *                      Added IO Unit Page 11.
  225  *                      Added new SAS Phy Event codes
  226  *                      Added PCIe configuration pages.
  227  *  03-19-15  02.00.32  Fixed PCIe Link Config page structure names to be
  228  *                      unique in first 32 characters.
  229  *  05-25-15  02.00.33  Added more defines for the BiosOptions field of
  230  *                      MPI2_CONFIG_PAGE_BIOS_1.
  231  *  08-25-15  02.00.34  Added PCIe Device Page 2 SGL format capability.
  232  *  12-18-15  02.00.35  Added SATADeviceWaitTime to SAS IO Unit Page 4.
  233  *  01-21-16  02.00.36  Added/modified MPI2_MFGPAGE_DEVID_SAS defines.
  234  *                      Added Link field to PCIe Link Pages
  235  *                      Added EnclosureLevel and ConnectorName to PCIe
  236  *                      Device Page 0.
  237  *                      Added define for PCIE IoUnit page 1 max rate shift.
  238  *                      Added comment for reserved ExtPageTypes.
  239  *                      Added SAS 4 22.5 gbs speed support.
  240  *                      Added PCIe 4 16.0 GT/sec speec support.
  241  *                      Removed AHCI support.
  242  *                      Removed SOP support.
  243  *                      Added NegotiatedLinkRate and NegotiatedPortWidth to
  244  *                      PCIe device page 0.
  245  *  04-10-16  02.00.37  Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines
  246  *  07-01-16  02.00.38  Added Manufacturing page 7 Connector types.
  247  *                      Changed declaration of ConnectorName in PCIe DevicePage0
  248  *                      to match SAS DevicePage 0.
  249  *                      Added SATADeviceWaitTime to IO Unit Page 11.
  250  *                      Added MPI26_MFGPAGE_DEVID_SAS4008
  251  *                      Added x16 PCIe width to IO Unit Page 7
  252  *                      Added LINKFLAGS to control SRIS in PCIe IO Unit page 1
  253  *                      phy data.
  254  *                      Added InitStatus to PCIe IO Unit Page 1 header.
  255  *  09-01-16  02.00.39  Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines.
  256  *                      Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and
  257  *                      MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats.
  258  *  02-02-17  02.00.40  Added MPI2_MANPAGE7_SLOT_UNKNOWN.
  259  *                      Added ChassisSlot field to SAS Enclosure Page 0.
  260  *                      Added ChassisSlot Valid bit (bit 5) to the Flags field
  261  *                      in SAS Enclosure Page 0.
  262  *  --------------------------------------------------------------------------
  263  */
  264 
  265 #ifndef MPI2_CNFG_H
  266 #define MPI2_CNFG_H
  267 
  268 /*****************************************************************************
  269 *   Configuration Page Header and defines
  270 *****************************************************************************/
  271 
  272 /* Config Page Header */
  273 typedef struct _MPI2_CONFIG_PAGE_HEADER
  274 {
  275     U8                 PageVersion;                /* 0x00 */
  276     U8                 PageLength;                 /* 0x01 */
  277     U8                 PageNumber;                 /* 0x02 */
  278     U8                 PageType;                   /* 0x03 */
  279 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
  280   Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
  281 
  282 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
  283 {
  284    MPI2_CONFIG_PAGE_HEADER  Struct;
  285    U8                       Bytes[4];
  286    U16                      Word16[2];
  287    U32                      Word32;
  288 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
  289   Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
  290 
  291 /* Extended Config Page Header */
  292 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
  293 {
  294     U8                  PageVersion;                /* 0x00 */
  295     U8                  Reserved1;                  /* 0x01 */
  296     U8                  PageNumber;                 /* 0x02 */
  297     U8                  PageType;                   /* 0x03 */
  298     U16                 ExtPageLength;              /* 0x04 */
  299     U8                  ExtPageType;                /* 0x06 */
  300     U8                  Reserved2;                  /* 0x07 */
  301 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
  302   MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
  303   Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
  304 
  305 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
  306 {
  307    MPI2_CONFIG_PAGE_HEADER          Struct;
  308    MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
  309    U8                               Bytes[8];
  310    U16                              Word16[4];
  311    U32                              Word32[2];
  312 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
  313   Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
  314 
  315 
  316 /* PageType field values */
  317 #define MPI2_CONFIG_PAGEATTR_READ_ONLY              (0x00)
  318 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE             (0x10)
  319 #define MPI2_CONFIG_PAGEATTR_PERSISTENT             (0x20)
  320 #define MPI2_CONFIG_PAGEATTR_MASK                   (0xF0)
  321 
  322 #define MPI2_CONFIG_PAGETYPE_IO_UNIT                (0x00)
  323 #define MPI2_CONFIG_PAGETYPE_IOC                    (0x01)
  324 #define MPI2_CONFIG_PAGETYPE_BIOS                   (0x02)
  325 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME            (0x08)
  326 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING          (0x09)
  327 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK          (0x0A)
  328 #define MPI2_CONFIG_PAGETYPE_EXTENDED               (0x0F)
  329 #define MPI2_CONFIG_PAGETYPE_MASK                   (0x0F)
  330 
  331 #define MPI2_CONFIG_TYPENUM_MASK                    (0x0FFF)
  332 
  333 
  334 /* ExtPageType field values */
  335 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT         (0x10)
  336 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER        (0x11)
  337 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE          (0x12)
  338 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY             (0x13)
  339 #define MPI2_CONFIG_EXTPAGETYPE_LOG                 (0x14)
  340 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE           (0x15)
  341 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG         (0x16)
  342 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING      (0x17)
  343 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT            (0x18)
  344 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET            (0x19)
  345 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING   (0x1A)
  346 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT        (0x1B) /* MPI v2.6 and later */
  347 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH         (0x1C) /* MPI v2.6 and later */
  348 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE         (0x1D) /* MPI v2.6 and later */
  349 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK           (0x1E) /* MPI v2.6 and later */
  350 /*  Product specific reserved values  0xE0 - 0xEF */
  351 /*  Vendor specific reserved values   0xF0 - 0xFF */
  352 
  353 
  354 /*****************************************************************************
  355 *   PageAddress defines
  356 *****************************************************************************/
  357 
  358 /* RAID Volume PageAddress format */
  359 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK             (0xF0000000)
  360 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE  (0x00000000)
  361 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE           (0x10000000)
  362 
  363 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK           (0x0000FFFF)
  364 
  365 
  366 /* RAID Physical Disk PageAddress format */
  367 #define MPI2_PHYSDISK_PGAD_FORM_MASK                    (0xF0000000)
  368 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM    (0x00000000)
  369 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM             (0x10000000)
  370 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE               (0x20000000)
  371 
  372 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK             (0x000000FF)
  373 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK               (0x0000FFFF)
  374 
  375 
  376 /* SAS Expander PageAddress format */
  377 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK              (0xF0000000)
  378 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL     (0x00000000)
  379 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM      (0x10000000)
  380 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL              (0x20000000)
  381 
  382 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK            (0x0000FFFF)
  383 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK            (0x00FF0000)
  384 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT           (16)
  385 
  386 
  387 /* SAS Device PageAddress format */
  388 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK              (0xF0000000)
  389 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
  390 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE            (0x20000000)
  391 
  392 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK            (0x0000FFFF)
  393 
  394 
  395 /* SAS PHY PageAddress format */
  396 #define MPI2_SAS_PHY_PGAD_FORM_MASK                 (0xF0000000)
  397 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER           (0x00000000)
  398 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX        (0x10000000)
  399 
  400 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK           (0x000000FF)
  401 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK        (0x0000FFFF)
  402 
  403 
  404 /* SAS Port PageAddress format */
  405 #define MPI2_SASPORT_PGAD_FORM_MASK                 (0xF0000000)
  406 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT        (0x00000000)
  407 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM             (0x10000000)
  408 
  409 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK           (0x00000FFF)
  410 
  411 
  412 /* SAS Enclosure PageAddress format */
  413 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK              (0xF0000000)
  414 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE   (0x00000000)
  415 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE            (0x10000000)
  416 
  417 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK            (0x0000FFFF)
  418 
  419 /* Enclosure PageAddress format */
  420 #define MPI26_ENCLOS_PGAD_FORM_MASK                 (0xF0000000)
  421 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE      (0x00000000)
  422 #define MPI26_ENCLOS_PGAD_FORM_HANDLE               (0x10000000)
  423 
  424 #define MPI26_ENCLOS_PGAD_HANDLE_MASK               (0x0000FFFF)
  425 
  426 /* RAID Configuration PageAddress format */
  427 #define MPI2_RAID_PGAD_FORM_MASK                    (0xF0000000)
  428 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM      (0x00000000)
  429 #define MPI2_RAID_PGAD_FORM_CONFIGNUM               (0x10000000)
  430 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG           (0x20000000)
  431 
  432 #define MPI2_RAID_PGAD_CONFIGNUM_MASK               (0x000000FF)
  433 
  434 
  435 /* Driver Persistent Mapping PageAddress format */
  436 #define MPI2_DPM_PGAD_FORM_MASK                     (0xF0000000)
  437 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE              (0x00000000)
  438 
  439 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK              (0x0FFF0000)
  440 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT             (16)
  441 #define MPI2_DPM_PGAD_START_ENTRY_MASK              (0x0000FFFF)
  442 
  443 
  444 /* Ethernet PageAddress format */
  445 #define MPI2_ETHERNET_PGAD_FORM_MASK                (0xF0000000)
  446 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM              (0x00000000)
  447 
  448 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK           (0x000000FF)
  449 
  450 
  451 /* PCIe Switch PageAddress format */
  452 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK            (0xF0000000)
  453 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL   (0x00000000)
  454 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM    (0x10000000)
  455 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL     (0x20000000)
  456 
  457 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK          (0x0000FFFF)
  458 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK         (0x00FF0000)
  459 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT        (16)
  460 
  461 
  462 /* PCIe Device PageAddress format */
  463 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK            (0xF0000000)
  464 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
  465 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE          (0x20000000)
  466 
  467 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK          (0x0000FFFF)
  468 
  469 /* PCIe Link PageAddress format */
  470 #define MPI26_PCIE_LINK_PGAD_FORM_MASK            (0xF0000000)
  471 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK   (0x00000000)
  472 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM        (0x10000000)
  473 
  474 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK       (0x000000FF)
  475 
  476 
  477 
  478 /****************************************************************************
  479 *   Configuration messages
  480 ****************************************************************************/
  481 
  482 /* Configuration Request Message */
  483 typedef struct _MPI2_CONFIG_REQUEST
  484 {
  485     U8                      Action;                     /* 0x00 */
  486     U8                      SGLFlags;                   /* 0x01 */
  487     U8                      ChainOffset;                /* 0x02 */
  488     U8                      Function;                   /* 0x03 */
  489     U16                     ExtPageLength;              /* 0x04 */
  490     U8                      ExtPageType;                /* 0x06 */
  491     U8                      MsgFlags;                   /* 0x07 */
  492     U8                      VP_ID;                      /* 0x08 */
  493     U8                      VF_ID;                      /* 0x09 */
  494     U16                     Reserved1;                  /* 0x0A */
  495     U8                      Reserved2;                  /* 0x0C */
  496     U8                      ProxyVF_ID;                 /* 0x0D */
  497     U16                     Reserved4;                  /* 0x0E */
  498     U32                     Reserved3;                  /* 0x10 */
  499     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
  500     U32                     PageAddress;                /* 0x18 */
  501     MPI2_SGE_IO_UNION       PageBufferSGE;              /* 0x1C */
  502 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
  503   Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
  504 
  505 /* values for the Action field */
  506 #define MPI2_CONFIG_ACTION_PAGE_HEADER              (0x00)
  507 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT        (0x01)
  508 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT       (0x02)
  509 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT             (0x03)
  510 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM         (0x04)
  511 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT        (0x05)
  512 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM          (0x06)
  513 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE      (0x07)
  514 
  515 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
  516 
  517 
  518 /* Config Reply Message */
  519 typedef struct _MPI2_CONFIG_REPLY
  520 {
  521     U8                      Action;                     /* 0x00 */
  522     U8                      SGLFlags;                   /* 0x01 */
  523     U8                      MsgLength;                  /* 0x02 */
  524     U8                      Function;                   /* 0x03 */
  525     U16                     ExtPageLength;              /* 0x04 */
  526     U8                      ExtPageType;                /* 0x06 */
  527     U8                      MsgFlags;                   /* 0x07 */
  528     U8                      VP_ID;                      /* 0x08 */
  529     U8                      VF_ID;                      /* 0x09 */
  530     U16                     Reserved1;                  /* 0x0A */
  531     U16                     Reserved2;                  /* 0x0C */
  532     U16                     IOCStatus;                  /* 0x0E */
  533     U32                     IOCLogInfo;                 /* 0x10 */
  534     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x14 */
  535 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
  536   Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
  537 
  538 
  539 
  540 /*****************************************************************************
  541 *
  542 *               C o n f i g u r a t i o n    P a g e s
  543 *
  544 *****************************************************************************/
  545 
  546 /****************************************************************************
  547 *   Manufacturing Config pages
  548 ****************************************************************************/
  549 
  550 #define MPI2_MFGPAGE_VENDORID_LSI                   (0x1000)
  551 
  552 /* MPI v2.0 SAS products */
  553 #define MPI2_MFGPAGE_DEVID_SAS2004                  (0x0070)
  554 #define MPI2_MFGPAGE_DEVID_SAS2008                  (0x0072)
  555 #define MPI2_MFGPAGE_DEVID_SAS2108_1                (0x0074)
  556 #define MPI2_MFGPAGE_DEVID_SAS2108_2                (0x0076)
  557 #define MPI2_MFGPAGE_DEVID_SAS2108_3                (0x0077)
  558 #define MPI2_MFGPAGE_DEVID_SAS2116_1                (0x0064)
  559 #define MPI2_MFGPAGE_DEVID_SAS2116_2                (0x0065)
  560 
  561 #define MPI2_MFGPAGE_DEVID_SSS6200                  (0x007E)
  562 
  563 #define MPI2_MFGPAGE_DEVID_SAS2208_1                (0x0080)
  564 #define MPI2_MFGPAGE_DEVID_SAS2208_2                (0x0081)
  565 #define MPI2_MFGPAGE_DEVID_SAS2208_3                (0x0082)
  566 #define MPI2_MFGPAGE_DEVID_SAS2208_4                (0x0083)
  567 #define MPI2_MFGPAGE_DEVID_SAS2208_5                (0x0084)
  568 #define MPI2_MFGPAGE_DEVID_SAS2208_6                (0x0085)
  569 #define MPI2_MFGPAGE_DEVID_SAS2308_1                (0x0086)
  570 #define MPI2_MFGPAGE_DEVID_SAS2308_2                (0x0087)
  571 #define MPI2_MFGPAGE_DEVID_SAS2308_3                (0x006E)
  572 
  573 /* MPI v2.5 SAS products */
  574 #define MPI25_MFGPAGE_DEVID_SAS3004                 (0x0096)
  575 #define MPI25_MFGPAGE_DEVID_SAS3008                 (0x0097)
  576 #define MPI25_MFGPAGE_DEVID_SAS3108_1               (0x0090)
  577 #define MPI25_MFGPAGE_DEVID_SAS3108_2               (0x0091)
  578 #define MPI25_MFGPAGE_DEVID_SAS3108_5               (0x0094)
  579 #define MPI25_MFGPAGE_DEVID_SAS3108_6               (0x0095)
  580 
  581 /* MPI v2.6 SAS Products */
  582 #define MPI26_MFGPAGE_DEVID_SAS3216                 (0x00C9)
  583 #define MPI26_MFGPAGE_DEVID_SAS3224                 (0x00C4)
  584 #define MPI26_MFGPAGE_DEVID_SAS3316_1               (0x00C5)
  585 #define MPI26_MFGPAGE_DEVID_SAS3316_2               (0x00C6)
  586 #define MPI26_MFGPAGE_DEVID_SAS3316_3               (0x00C7)
  587 #define MPI26_MFGPAGE_DEVID_SAS3316_4               (0x00C8)
  588 #define MPI26_MFGPAGE_DEVID_SAS3324_1               (0x00C0)
  589 #define MPI26_MFGPAGE_DEVID_SAS3324_2               (0x00C1)
  590 #define MPI26_MFGPAGE_DEVID_SAS3324_3               (0x00C2)
  591 #define MPI26_MFGPAGE_DEVID_SAS3324_4               (0x00C3)
  592 
  593 #define MPI26_MFGPAGE_DEVID_SAS3516                 (0x00AA)
  594 #define MPI26_MFGPAGE_DEVID_SAS3516_1               (0x00AB)
  595 #define MPI26_MFGPAGE_DEVID_SAS3416                 (0x00AC)
  596 #define MPI26_MFGPAGE_DEVID_SAS3508                 (0x00AD)
  597 #define MPI26_MFGPAGE_DEVID_SAS3508_1               (0x00AE)
  598 #define MPI26_MFGPAGE_DEVID_SAS3408                 (0x00AF)
  599 
  600 #define MPI26_MFGPAGE_DEVID_SAS3716                 (0x00D0)
  601 #define MPI26_MFGPAGE_DEVID_SAS3616                 (0x00D1)
  602 #define MPI26_MFGPAGE_DEVID_SAS3708                 (0x00D2)
  603 
  604 #define MPI26_MFGPAGE_DEVID_SAS4008                 (0x00A1)
  605 
  606 
  607 /* Manufacturing Page 0 */
  608 
  609 typedef struct _MPI2_CONFIG_PAGE_MAN_0
  610 {
  611     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
  612     U8                      ChipName[16];               /* 0x04 */
  613     U8                      ChipRevision[8];            /* 0x14 */
  614     U8                      BoardName[16];              /* 0x1C */
  615     U8                      BoardAssembly[16];          /* 0x2C */
  616     U8                      BoardTracerNumber[16];      /* 0x3C */
  617 } MPI2_CONFIG_PAGE_MAN_0,
  618   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
  619   Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
  620 
  621 #define MPI2_MANUFACTURING0_PAGEVERSION                (0x00)
  622 
  623 
  624 /* Manufacturing Page 1 */
  625 
  626 typedef struct _MPI2_CONFIG_PAGE_MAN_1
  627 {
  628     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
  629     U8                      VPD[256];                   /* 0x04 */
  630 } MPI2_CONFIG_PAGE_MAN_1,
  631   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
  632   Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
  633 
  634 #define MPI2_MANUFACTURING1_PAGEVERSION                (0x00)
  635 
  636 
  637 typedef struct _MPI2_CHIP_REVISION_ID
  638 {
  639     U16 DeviceID;                                       /* 0x00 */
  640     U8  PCIRevisionID;                                  /* 0x02 */
  641     U8  Reserved;                                       /* 0x03 */
  642 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
  643   Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
  644 
  645 
  646 /* Manufacturing Page 2 */
  647 
  648 /*
  649  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  650  * one and check Header.PageLength at runtime.
  651  */
  652 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
  653 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS   (1)
  654 #endif
  655 
  656 typedef struct _MPI2_CONFIG_PAGE_MAN_2
  657 {
  658     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
  659     MPI2_CHIP_REVISION_ID   ChipId;                     /* 0x04 */
  660     U32                     HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
  661 } MPI2_CONFIG_PAGE_MAN_2,
  662   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
  663   Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
  664 
  665 #define MPI2_MANUFACTURING2_PAGEVERSION                 (0x00)
  666 
  667 
  668 /* Manufacturing Page 3 */
  669 
  670 /*
  671  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  672  * one and check Header.PageLength at runtime.
  673  */
  674 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
  675 #define MPI2_MAN_PAGE_3_INFO_WORDS          (1)
  676 #endif
  677 
  678 typedef struct _MPI2_CONFIG_PAGE_MAN_3
  679 {
  680     MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
  681     MPI2_CHIP_REVISION_ID               ChipId;         /* 0x04 */
  682     U32                                 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
  683 } MPI2_CONFIG_PAGE_MAN_3,
  684   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
  685   Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
  686 
  687 #define MPI2_MANUFACTURING3_PAGEVERSION                 (0x00)
  688 
  689 
  690 /* Manufacturing Page 4 */
  691 
  692 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
  693 {
  694     U8                          PowerSaveFlags;                 /* 0x00 */
  695     U8                          InternalOperationsSleepTime;    /* 0x01 */
  696     U8                          InternalOperationsRunTime;      /* 0x02 */
  697     U8                          HostIdleTime;                   /* 0x03 */
  698 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
  699   MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
  700   Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
  701 
  702 /* defines for the PowerSaveFlags field */
  703 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE               (0x03)
  704 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED           (0x00)
  705 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE             (0x01)
  706 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE               (0x02)
  707 
  708 typedef struct _MPI2_CONFIG_PAGE_MAN_4
  709 {
  710     MPI2_CONFIG_PAGE_HEADER             Header;                 /* 0x00 */
  711     U32                                 Reserved1;              /* 0x04 */
  712     U32                                 Flags;                  /* 0x08 */
  713     U8                                  InquirySize;            /* 0x0C */
  714     U8                                  Reserved2;              /* 0x0D */
  715     U16                                 Reserved3;              /* 0x0E */
  716     U8                                  InquiryData[56];        /* 0x10 */
  717     U32                                 RAID0VolumeSettings;    /* 0x48 */
  718     U32                                 RAID1EVolumeSettings;   /* 0x4C */
  719     U32                                 RAID1VolumeSettings;    /* 0x50 */
  720     U32                                 RAID10VolumeSettings;   /* 0x54 */
  721     U32                                 Reserved4;              /* 0x58 */
  722     U32                                 Reserved5;              /* 0x5C */
  723     MPI2_MANPAGE4_PWR_SAVE_SETTINGS     PowerSaveSettings;      /* 0x60 */
  724     U8                                  MaxOCEDisks;            /* 0x64 */
  725     U8                                  ResyncRate;             /* 0x65 */
  726     U16                                 DataScrubDuration;      /* 0x66 */
  727     U8                                  MaxHotSpares;           /* 0x68 */
  728     U8                                  MaxPhysDisksPerVol;     /* 0x69 */
  729     U8                                  MaxPhysDisks;           /* 0x6A */
  730     U8                                  MaxVolumes;             /* 0x6B */
  731 } MPI2_CONFIG_PAGE_MAN_4,
  732   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
  733   Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
  734 
  735 #define MPI2_MANUFACTURING4_PAGEVERSION                 (0x0A)
  736 
  737 /* Manufacturing Page 4 Flags field */
  738 #define MPI2_MANPAGE4_METADATA_SIZE_MASK                (0x00030000)
  739 #define MPI2_MANPAGE4_METADATA_512MB                    (0x00000000)
  740 
  741 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA                  (0x00008000)
  742 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD               (0x00004000)
  743 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR              (0x00002000)
  744 
  745 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION            (0x00001C00)
  746 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB             (0x00000000)
  747 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION           (0x00000400)
  748 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION        (0x00000800)
  749 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION            (0x00000C00)
  750 
  751 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING            (0x00000300)
  752 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING         (0x00000000)
  753 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING           (0x00000100)
  754 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING      (0x00000200)
  755 
  756 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER            (0x00000080)
  757 #define MPI2_MANPAGE4_RAID10_DISABLE                    (0x00000040)
  758 #define MPI2_MANPAGE4_RAID1E_DISABLE                    (0x00000020)
  759 #define MPI2_MANPAGE4_RAID1_DISABLE                     (0x00000010)
  760 #define MPI2_MANPAGE4_RAID0_DISABLE                     (0x00000008)
  761 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE              (0x00000004)
  762 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE            (0x00000002)
  763 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA                (0x00000001)
  764 
  765 
  766 /* Manufacturing Page 5 */
  767 
  768 /*
  769  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  770  * one and check the value returned for NumPhys at runtime.
  771  */
  772 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
  773 #define MPI2_MAN_PAGE_5_PHY_ENTRIES         (1)
  774 #endif
  775 
  776 typedef struct _MPI2_MANUFACTURING5_ENTRY
  777 {
  778     U64                                 WWID;           /* 0x00 */
  779     U64                                 DeviceName;     /* 0x08 */
  780 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
  781   Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
  782 
  783 typedef struct _MPI2_CONFIG_PAGE_MAN_5
  784 {
  785     MPI2_CONFIG_PAGE_HEADER             Header;         /* 0x00 */
  786     U8                                  NumPhys;        /* 0x04 */
  787     U8                                  Reserved1;      /* 0x05 */
  788     U16                                 Reserved2;      /* 0x06 */
  789     U32                                 Reserved3;      /* 0x08 */
  790     U32                                 Reserved4;      /* 0x0C */
  791     MPI2_MANUFACTURING5_ENTRY           Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
  792 } MPI2_CONFIG_PAGE_MAN_5,
  793   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
  794   Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
  795 
  796 #define MPI2_MANUFACTURING5_PAGEVERSION                 (0x03)
  797 
  798 
  799 /* Manufacturing Page 6 */
  800 
  801 typedef struct _MPI2_CONFIG_PAGE_MAN_6
  802 {
  803     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
  804     U32                             ProductSpecificInfo;/* 0x04 */
  805 } MPI2_CONFIG_PAGE_MAN_6,
  806   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
  807   Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
  808 
  809 #define MPI2_MANUFACTURING6_PAGEVERSION                 (0x00)
  810 
  811 
  812 /* Manufacturing Page 7 */
  813 
  814 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
  815 {
  816     U32                         Pinout;                 /* 0x00 */
  817     U8                          Connector[16];          /* 0x04 */
  818     U8                          Location;               /* 0x14 */
  819     U8                          ReceptacleID;           /* 0x15 */
  820     U16                         Slot;                   /* 0x16 */
  821     U32                         Reserved2;              /* 0x18 */
  822 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
  823   Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
  824 
  825 /* defines for the Pinout field */
  826 #define MPI2_MANPAGE7_PINOUT_LANE_MASK                  (0x0000FF00)
  827 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT                 (8)
  828 
  829 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK                  (0x000000FF)
  830 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN               (0x00)
  831 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE                (0x01)
  832 #define MPI2_MANPAGE7_PINOUT_SFF_8482                   (0x02)
  833 #define MPI2_MANPAGE7_PINOUT_SFF_8486                   (0x03)
  834 #define MPI2_MANPAGE7_PINOUT_SFF_8484                   (0x04)
  835 #define MPI2_MANPAGE7_PINOUT_SFF_8087                   (0x05)
  836 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I                (0x06)
  837 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I                (0x07)
  838 #define MPI2_MANPAGE7_PINOUT_SFF_8470                   (0x08)
  839 #define MPI2_MANPAGE7_PINOUT_SFF_8088                   (0x09)
  840 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X                (0x0A)
  841 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X                (0x0B)
  842 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X               (0x0C)
  843 #define MPI2_MANPAGE7_PINOUT_SFF_8436                   (0x0D)
  844 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A                 (0x0E)
  845 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i               (0x0F)
  846 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i                (0x10)
  847 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i                (0x11)
  848 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i                (0x12)
  849 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i                (0x13)
  850 
  851 /* defines for the Location field */
  852 #define MPI2_MANPAGE7_LOCATION_UNKNOWN                  (0x01)
  853 #define MPI2_MANPAGE7_LOCATION_INTERNAL                 (0x02)
  854 #define MPI2_MANPAGE7_LOCATION_EXTERNAL                 (0x04)
  855 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE               (0x08)
  856 #define MPI2_MANPAGE7_LOCATION_AUTO                     (0x10)
  857 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT              (0x20)
  858 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED            (0x80)
  859 
  860 /* defines for the Slot field */
  861 #define MPI2_MANPAGE7_SLOT_UNKNOWN                      (0xFFFF)
  862 
  863 /*
  864  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  865  * one and check the value returned for NumPhys at runtime.
  866  */
  867 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
  868 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX  (1)
  869 #endif
  870 
  871 typedef struct _MPI2_CONFIG_PAGE_MAN_7
  872 {
  873     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
  874     U32                             Reserved1;          /* 0x04 */
  875     U32                             Reserved2;          /* 0x08 */
  876     U32                             Flags;              /* 0x0C */
  877     U8                              EnclosureName[16];  /* 0x10 */
  878     U8                              NumPhys;            /* 0x20 */
  879     U8                              Reserved3;          /* 0x21 */
  880     U16                             Reserved4;          /* 0x22 */
  881     MPI2_MANPAGE7_CONNECTOR_INFO    ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
  882 } MPI2_CONFIG_PAGE_MAN_7,
  883   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
  884   Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
  885 
  886 #define MPI2_MANUFACTURING7_PAGEVERSION                 (0x01)
  887 
  888 /* defines for the Flags field */
  889 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL         (0x00000008)
  890 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER       (0x00000002)
  891 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO                (0x00000001)
  892 
  893 
  894 /*
  895  * Generic structure to use for product-specific manufacturing pages
  896  * (currently Manufacturing Page 8 through Manufacturing Page 31).
  897  */
  898 
  899 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
  900 {
  901     MPI2_CONFIG_PAGE_HEADER         Header;             /* 0x00 */
  902     U32                             ProductSpecificInfo;/* 0x04 */
  903 } MPI2_CONFIG_PAGE_MAN_PS,
  904   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
  905   Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
  906 
  907 #define MPI2_MANUFACTURING8_PAGEVERSION                 (0x00)
  908 #define MPI2_MANUFACTURING9_PAGEVERSION                 (0x00)
  909 #define MPI2_MANUFACTURING10_PAGEVERSION                (0x00)
  910 #define MPI2_MANUFACTURING11_PAGEVERSION                (0x00)
  911 #define MPI2_MANUFACTURING12_PAGEVERSION                (0x00)
  912 #define MPI2_MANUFACTURING13_PAGEVERSION                (0x00)
  913 #define MPI2_MANUFACTURING14_PAGEVERSION                (0x00)
  914 #define MPI2_MANUFACTURING15_PAGEVERSION                (0x00)
  915 #define MPI2_MANUFACTURING16_PAGEVERSION                (0x00)
  916 #define MPI2_MANUFACTURING17_PAGEVERSION                (0x00)
  917 #define MPI2_MANUFACTURING18_PAGEVERSION                (0x00)
  918 #define MPI2_MANUFACTURING19_PAGEVERSION                (0x00)
  919 #define MPI2_MANUFACTURING20_PAGEVERSION                (0x00)
  920 #define MPI2_MANUFACTURING21_PAGEVERSION                (0x00)
  921 #define MPI2_MANUFACTURING22_PAGEVERSION                (0x00)
  922 #define MPI2_MANUFACTURING23_PAGEVERSION                (0x00)
  923 #define MPI2_MANUFACTURING24_PAGEVERSION                (0x00)
  924 #define MPI2_MANUFACTURING25_PAGEVERSION                (0x00)
  925 #define MPI2_MANUFACTURING26_PAGEVERSION                (0x00)
  926 #define MPI2_MANUFACTURING27_PAGEVERSION                (0x00)
  927 #define MPI2_MANUFACTURING28_PAGEVERSION                (0x00)
  928 #define MPI2_MANUFACTURING29_PAGEVERSION                (0x00)
  929 #define MPI2_MANUFACTURING30_PAGEVERSION                (0x00)
  930 #define MPI2_MANUFACTURING31_PAGEVERSION                (0x00)
  931 
  932 
  933 /****************************************************************************
  934 *   IO Unit Config Pages
  935 ****************************************************************************/
  936 
  937 /* IO Unit Page 0 */
  938 
  939 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
  940 {
  941     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
  942     U64                     UniqueValue;                /* 0x04 */
  943     MPI2_VERSION_UNION      NvdataVersionDefault;       /* 0x08 */
  944     MPI2_VERSION_UNION      NvdataVersionPersistent;    /* 0x0A */
  945 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
  946   Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
  947 
  948 #define MPI2_IOUNITPAGE0_PAGEVERSION                    (0x02)
  949 
  950 
  951 /* IO Unit Page 1 */
  952 
  953 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
  954 {
  955     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
  956     U32                     Flags;                      /* 0x04 */
  957 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
  958   Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
  959 
  960 #define MPI2_IOUNITPAGE1_PAGEVERSION                    (0x04)
  961 
  962 /* IO Unit Page 1 Flags defines */
  963 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK       (0x00004000)
  964 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE  (0x00002000)
  965 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH             (0x00001000)
  966 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY    (0x00000800)
  967 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE          (0x00000600)
  968 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT         (9)
  969 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE        (0x00000000)
  970 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE       (0x00000200)
  971 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE     (0x00000400)
  972 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE       (0x00000100)
  973 #define MPI2_IOUNITPAGE1_DISABLE_IR                     (0x00000040)
  974 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
  975 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID        (0x00000004)
  976 
  977 
  978 /* IO Unit Page 3 */
  979 
  980 /*
  981  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  982  * one and check the value returned for GPIOCount at runtime.
  983  */
  984 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
  985 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX    (1)
  986 #endif
  987 
  988 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
  989 {
  990     MPI2_CONFIG_PAGE_HEADER Header;                                   /* 0x00 */
  991     U8                      GPIOCount;                                /* 0x04 */
  992     U8                      Reserved1;                                /* 0x05 */
  993     U16                     Reserved2;                                /* 0x06 */
  994     U16                     GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
  995 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
  996   Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
  997 
  998 #define MPI2_IOUNITPAGE3_PAGEVERSION                    (0x01)
  999 
 1000 /* defines for IO Unit Page 3 GPIOVal field */
 1001 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK             (0xFFFC)
 1002 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT            (2)
 1003 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF               (0x0000)
 1004 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON                (0x0001)
 1005 
 1006 
 1007 /* IO Unit Page 5 */
 1008 
 1009 /*
 1010  * Upper layer code (drivers, utilities, etc.) should leave this define set to
 1011  * one and check the value returned for NumDmaEngines at runtime.
 1012  */
 1013 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
 1014 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES      (1)
 1015 #endif
 1016 
 1017 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5
 1018 {
 1019     MPI2_CONFIG_PAGE_HEADER Header;                                     /* 0x00 */
 1020     U64                     RaidAcceleratorBufferBaseAddress;           /* 0x04 */
 1021     U64                     RaidAcceleratorBufferSize;                  /* 0x0C */
 1022     U64                     RaidAcceleratorControlBaseAddress;          /* 0x14 */
 1023     U8                      RAControlSize;                              /* 0x1C */
 1024     U8                      NumDmaEngines;                              /* 0x1D */
 1025     U8                      RAMinControlSize;                           /* 0x1E */
 1026     U8                      RAMaxControlSize;                           /* 0x1F */
 1027     U32                     Reserved1;                                  /* 0x20 */
 1028     U32                     Reserved2;                                  /* 0x24 */
 1029     U32                     Reserved3;                                  /* 0x28 */
 1030     U32                     DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
 1031 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
 1032   Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
 1033 
 1034 #define MPI2_IOUNITPAGE5_PAGEVERSION                    (0x00)
 1035 
 1036 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
 1037 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS      (0xFFFF0000)
 1038 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS     (16)
 1039 
 1040 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP                   (0x0008)
 1041 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION      (0x0004)
 1042 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING                (0x0002)
 1043 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION             (0x0001)
 1044 
 1045 
 1046 /* IO Unit Page 6 */
 1047 
 1048 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6
 1049 {
 1050     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
 1051     U16                     Flags;                                  /* 0x04 */
 1052     U8                      RAHostControlSize;                      /* 0x06 */
 1053     U8                      Reserved0;                              /* 0x07 */
 1054     U64                     RaidAcceleratorHostControlBaseAddress;  /* 0x08 */
 1055     U32                     Reserved1;                              /* 0x10 */
 1056     U32                     Reserved2;                              /* 0x14 */
 1057     U32                     Reserved3;                              /* 0x18 */
 1058 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
 1059   Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
 1060 
 1061 #define MPI2_IOUNITPAGE6_PAGEVERSION                    (0x00)
 1062 
 1063 /* defines for IO Unit Page 6 Flags field */
 1064 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR  (0x0001)
 1065 
 1066 
 1067 /* IO Unit Page 7 */
 1068 
 1069 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7
 1070 {
 1071     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
 1072     U8                      CurrentPowerMode;                       /* 0x04 */ /* reserved in MPI 2.0 */
 1073     U8                      PreviousPowerMode;                      /* 0x05 */ /* reserved in MPI 2.0 */
 1074     U8                      PCIeWidth;                              /* 0x06 */
 1075     U8                      PCIeSpeed;                              /* 0x07 */
 1076     U32                     ProcessorState;                         /* 0x08 */
 1077     U32                     PowerManagementCapabilities;            /* 0x0C */
 1078     U16                     IOCTemperature;                         /* 0x10 */
 1079     U8                      IOCTemperatureUnits;                    /* 0x12 */
 1080     U8                      IOCSpeed;                               /* 0x13 */
 1081     U16                     BoardTemperature;                       /* 0x14 */
 1082     U8                      BoardTemperatureUnits;                  /* 0x16 */
 1083     U8                      Reserved3;                              /* 0x17 */
 1084     U32                     BoardPowerRequirement;                              /* 0x18 */ /* reserved prior to MPI v2.6 */
 1085     U32                     PCISlotPowerAllocation;                              /* 0x1C */ /* reserved prior to MPI v2.6 */
 1086     U8                      Flags;                              /* 0x20 */ /* reserved prior to MPI v2.6 */
 1087     U8                      Reserved6;                              /* 0x21 */
 1088     U16                     Reserved7;                              /* 0x22 */
 1089     U32                     Reserved8;                              /* 0x24 */
 1090 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
 1091   Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
 1092 
 1093 #define MPI2_IOUNITPAGE7_PAGEVERSION                    (0x05)
 1094 
 1095 /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
 1096 #define MPI25_IOUNITPAGE7_PM_INIT_MASK              (0xC0)
 1097 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE       (0x00)
 1098 #define MPI25_IOUNITPAGE7_PM_INIT_HOST              (0x40)
 1099 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT           (0x80)
 1100 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA          (0xC0)
 1101 
 1102 #define MPI25_IOUNITPAGE7_PM_MODE_MASK              (0x07)
 1103 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE       (0x00)
 1104 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN           (0x01)
 1105 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER        (0x04)
 1106 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER     (0x05)
 1107 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY           (0x06)
 1108 
 1109 
 1110 /* defines for IO Unit Page 7 PCIeWidth field */
 1111 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1              (0x01)
 1112 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2              (0x02)
 1113 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4              (0x04)
 1114 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8              (0x08)
 1115 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16             (0x10)
 1116 
 1117 /* defines for IO Unit Page 7 PCIeSpeed field */
 1118 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS        (0x00)
 1119 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS        (0x01)
 1120 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS        (0x02)
 1121 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS       (0x03)
 1122 
 1123 /* defines for IO Unit Page 7 ProcessorState field */
 1124 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND         (0x0000000F)
 1125 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND        (0)
 1126 
 1127 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT         (0x00)
 1128 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED            (0x01)
 1129 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED             (0x02)
 1130 
 1131 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
 1132 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE       (0x00400000)
 1133 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE    (0x00200000)
 1134 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE        (0x00100000)
 1135 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE      (0x00040000)
 1136 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE   (0x00020000)
 1137 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE       (0x00010000)
 1138 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE        (0x00004000)
 1139 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE     (0x00002000)
 1140 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE         (0x00001000)
 1141 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED   (0x00000400)
 1142 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED   (0x00000200)
 1143 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED   (0x00000100)
 1144 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED    (0x00000040)
 1145 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED    (0x00000020)
 1146 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED    (0x00000010)
 1147 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE   (0x00000008) /* obsolete */
 1148 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE   (0x00000004) /* obsolete */
 1149 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE    (0x00000002) /* obsolete */
 1150 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE    (0x00000001) /* obsolete */
 1151 
 1152 /* obsolete names for the PowerManagementCapabilities bits (above) */
 1153 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED    (0x00000400)
 1154 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED    (0x00000200)
 1155 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED    (0x00000100)
 1156 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE    (0x00000008) /* obsolete */
 1157 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE    (0x00000004) /* obsolete */
 1158 
 1159 
 1160 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
 1161 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT       (0x00)
 1162 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT        (0x01)
 1163 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS           (0x02)
 1164 
 1165 /* defines for IO Unit Page 7 IOCSpeed field */
 1166 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL             (0x01)
 1167 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF             (0x02)
 1168 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER          (0x04)
 1169 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH           (0x08)
 1170 
 1171 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
 1172 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT     (0x00)
 1173 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT      (0x01)
 1174 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS         (0x02)
 1175 
 1176 /* defines for IO Unit Page 7 Flags field */
 1177 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC       (0x01)
 1178 
 1179 
 1180 /* IO Unit Page 8 */
 1181 
 1182 #define MPI2_IOUNIT8_NUM_THRESHOLDS     (4)
 1183 
 1184 typedef struct _MPI2_IOUNIT8_SENSOR
 1185 {
 1186     U16                     Flags;                                  /* 0x00 */
 1187     U16                     Reserved1;                              /* 0x02 */
 1188     U16                     Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
 1189     U32                     Reserved2;                              /* 0x0C */
 1190     U32                     Reserved3;                              /* 0x10 */
 1191     U32                     Reserved4;                              /* 0x14 */
 1192 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
 1193   Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
 1194 
 1195 /* defines for IO Unit Page 8 Sensor Flags field */
 1196 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE         (0x0008)
 1197 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE         (0x0004)
 1198 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE         (0x0002)
 1199 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE         (0x0001)
 1200 
 1201 /*
 1202  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 1203  * one and check the value returned for NumSensors at runtime.
 1204  */
 1205 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
 1206 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES     (1)
 1207 #endif
 1208 
 1209 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8
 1210 {
 1211     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
 1212     U32                     Reserved1;                              /* 0x04 */
 1213     U32                     Reserved2;                              /* 0x08 */
 1214     U8                      NumSensors;                             /* 0x0C */
 1215     U8                      PollingInterval;                        /* 0x0D */
 1216     U16                     Reserved3;                              /* 0x0E */
 1217     MPI2_IOUNIT8_SENSOR     Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
 1218 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
 1219   Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
 1220 
 1221 #define MPI2_IOUNITPAGE8_PAGEVERSION                    (0x00)
 1222 
 1223 
 1224 /* IO Unit Page 9 */
 1225 
 1226 typedef struct _MPI2_IOUNIT9_SENSOR
 1227 {
 1228     U16                     CurrentTemperature;                     /* 0x00 */
 1229     U16                     Reserved1;                              /* 0x02 */
 1230     U8                      Flags;                                  /* 0x04 */
 1231     U8                      Reserved2;                              /* 0x05 */
 1232     U16                     Reserved3;                              /* 0x06 */
 1233     U32                     Reserved4;                              /* 0x08 */
 1234     U32                     Reserved5;                              /* 0x0C */
 1235 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
 1236   Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
 1237 
 1238 /* defines for IO Unit Page 9 Sensor Flags field */
 1239 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID        (0x01)
 1240 
 1241 /*
 1242  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 1243  * one and check the value returned for NumSensors at runtime.
 1244  */
 1245 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
 1246 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES     (1)
 1247 #endif
 1248 
 1249 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9
 1250 {
 1251     MPI2_CONFIG_PAGE_HEADER Header;                                 /* 0x00 */
 1252     U32                     Reserved1;                              /* 0x04 */
 1253     U32                     Reserved2;                              /* 0x08 */
 1254     U8                      NumSensors;                             /* 0x0C */
 1255     U8                      Reserved4;                              /* 0x0D */
 1256     U16                     Reserved3;                              /* 0x0E */
 1257     MPI2_IOUNIT9_SENSOR     Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
 1258 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
 1259   Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
 1260 
 1261 #define MPI2_IOUNITPAGE9_PAGEVERSION                    (0x00)
 1262 
 1263 
 1264 /* IO Unit Page 10 */
 1265 
 1266 typedef struct _MPI2_IOUNIT10_FUNCTION
 1267 {
 1268     U8                      CreditPercent;      /* 0x00 */
 1269     U8                      Reserved1;          /* 0x01 */
 1270     U16                     Reserved2;          /* 0x02 */
 1271 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
 1272   Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
 1273 
 1274 /*
 1275  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 1276  * one and check the value returned for NumFunctions at runtime.
 1277  */
 1278 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
 1279 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES      (1)
 1280 #endif
 1281 
 1282 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10
 1283 {
 1284     MPI2_CONFIG_PAGE_HEADER Header;                                         /* 0x00 */
 1285     U8                      NumFunctions;                                   /* 0x04 */
 1286     U8                      Reserved1;                                      /* 0x05 */
 1287     U16                     Reserved2;                                      /* 0x06 */
 1288     U32                     Reserved3;                                      /* 0x08 */
 1289     U32                     Reserved4;                                      /* 0x0C */
 1290     MPI2_IOUNIT10_FUNCTION  Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];   /* 0x10 */
 1291 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
 1292   Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
 1293 
 1294 #define MPI2_IOUNITPAGE10_PAGEVERSION                   (0x01)
 1295 
 1296 
 1297 /* IO Unit Page 11 (for MPI v2.6 and later) */
 1298 
 1299 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP
 1300 {
 1301     U8          MaxTargetSpinup;            /* 0x00 */
 1302     U8          SpinupDelay;                /* 0x01 */
 1303     U8          SpinupFlags;                /* 0x02 */
 1304     U8          Reserved1;                  /* 0x03 */
 1305 } MPI26_IOUNIT11_SPINUP_GROUP, MPI2_POINTER PTR_MPI26_IOUNIT11_SPINUP_GROUP,
 1306   Mpi26IOUnit11SpinupGroup_t, MPI2_POINTER pMpi26IOUnit11SpinupGroup_t;
 1307 
 1308 /* defines for IO Unit Page 11 SpinupFlags */
 1309 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG          (0x01)
 1310 
 1311 
 1312 /*
 1313  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 1314  * four and check the value returned for NumPhys at runtime.
 1315  */
 1316 #ifndef MPI26_IOUNITPAGE11_PHY_MAX
 1317 #define MPI26_IOUNITPAGE11_PHY_MAX        (4)
 1318 #endif
 1319 
 1320 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11
 1321 {
 1322     MPI2_CONFIG_PAGE_HEADER         Header;                         /* 0x00 */
 1323     U32                             Reserved1;                      /* 0x04 */
 1324     MPI26_IOUNIT11_SPINUP_GROUP     SpinupGroupParameters[4];       /* 0x08 */
 1325     U32                             Reserved2;                      /* 0x18 */
 1326     U32                             Reserved3;                      /* 0x1C */
 1327     U32                             Reserved4;                      /* 0x20 */
 1328     U8                              BootDeviceWaitTime;             /* 0x24 */
 1329     U8                              SATADeviceWaitTime;             /* 0x25 */
 1330     U16                             Reserved6;                      /* 0x26 */
 1331     U8                              NumPhys;                        /* 0x28 */
 1332     U8                              PEInitialSpinupDelay;           /* 0x29 */
 1333     U8                              PEReplyDelay;                   /* 0x2A */
 1334     U8                              Flags;                          /* 0x2B */
 1335     U8                              PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */
 1336 } MPI26_CONFIG_PAGE_IO_UNIT_11,
 1337   MPI2_POINTER PTR_MPI26_CONFIG_PAGE_IO_UNIT_11,
 1338   Mpi26IOUnitPage11_t, MPI2_POINTER pMpi26IOUnitPage11_t;
 1339 
 1340 #define MPI26_IOUNITPAGE11_PAGEVERSION                  (0x00)
 1341 
 1342 /* defines for Flags field */
 1343 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE        (0x01)
 1344 
 1345 /* defines for PHY field */
 1346 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK        (0x03)
 1347 
 1348 
 1349 
 1350 /****************************************************************************
 1351 *   IOC Config Pages
 1352 ****************************************************************************/
 1353 
 1354 /* IOC Page 0 */
 1355 
 1356 typedef struct _MPI2_CONFIG_PAGE_IOC_0
 1357 {
 1358     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 1359     U32                     Reserved1;                  /* 0x04 */
 1360     U32                     Reserved2;                  /* 0x08 */
 1361     U16                     VendorID;                   /* 0x0C */
 1362     U16                     DeviceID;                   /* 0x0E */
 1363     U8                      RevisionID;                 /* 0x10 */
 1364     U8                      Reserved3;                  /* 0x11 */
 1365     U16                     Reserved4;                  /* 0x12 */
 1366     U32                     ClassCode;                  /* 0x14 */
 1367     U16                     SubsystemVendorID;          /* 0x18 */
 1368     U16                     SubsystemID;                /* 0x1A */
 1369 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
 1370   Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
 1371 
 1372 #define MPI2_IOCPAGE0_PAGEVERSION                       (0x02)
 1373 
 1374 
 1375 /* IOC Page 1 */
 1376 
 1377 typedef struct _MPI2_CONFIG_PAGE_IOC_1
 1378 {
 1379     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 1380     U32                     Flags;                      /* 0x04 */
 1381     U32                     CoalescingTimeout;          /* 0x08 */
 1382     U8                      CoalescingDepth;            /* 0x0C */
 1383     U8                      PCISlotNum;                 /* 0x0D */
 1384     U8                      PCIBusNum;                  /* 0x0E */
 1385     U8                      PCIDomainSegment;           /* 0x0F */
 1386     U32                     Reserved1;                  /* 0x10 */
 1387     U32                     Reserved2;                  /* 0x14 */
 1388 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
 1389   Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
 1390 
 1391 #define MPI2_IOCPAGE1_PAGEVERSION                       (0x05)
 1392 
 1393 /* defines for IOC Page 1 Flags field */
 1394 #define MPI2_IOCPAGE1_REPLY_COALESCING                  (0x00000001)
 1395 
 1396 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN                (0xFF)
 1397 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN                 (0xFF)
 1398 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN                 (0xFF)
 1399 
 1400 /* IOC Page 6 */
 1401 
 1402 typedef struct _MPI2_CONFIG_PAGE_IOC_6
 1403 {
 1404     MPI2_CONFIG_PAGE_HEADER Header;                         /* 0x00 */
 1405     U32                     CapabilitiesFlags;              /* 0x04 */
 1406     U8                      MaxDrivesRAID0;                 /* 0x08 */
 1407     U8                      MaxDrivesRAID1;                 /* 0x09 */
 1408     U8                      MaxDrivesRAID1E;                /* 0x0A */
 1409     U8                      MaxDrivesRAID10;                /* 0x0B */
 1410     U8                      MinDrivesRAID0;                 /* 0x0C */
 1411     U8                      MinDrivesRAID1;                 /* 0x0D */
 1412     U8                      MinDrivesRAID1E;                /* 0x0E */
 1413     U8                      MinDrivesRAID10;                /* 0x0F */
 1414     U32                     Reserved1;                      /* 0x10 */
 1415     U8                      MaxGlobalHotSpares;             /* 0x14 */
 1416     U8                      MaxPhysDisks;                   /* 0x15 */
 1417     U8                      MaxVolumes;                     /* 0x16 */
 1418     U8                      MaxConfigs;                     /* 0x17 */
 1419     U8                      MaxOCEDisks;                    /* 0x18 */
 1420     U8                      Reserved2;                      /* 0x19 */
 1421     U16                     Reserved3;                      /* 0x1A */
 1422     U32                     SupportedStripeSizeMapRAID0;    /* 0x1C */
 1423     U32                     SupportedStripeSizeMapRAID1E;   /* 0x20 */
 1424     U32                     SupportedStripeSizeMapRAID10;   /* 0x24 */
 1425     U32                     Reserved4;                      /* 0x28 */
 1426     U32                     Reserved5;                      /* 0x2C */
 1427     U16                     DefaultMetadataSize;            /* 0x30 */
 1428     U16                     Reserved6;                      /* 0x32 */
 1429     U16                     MaxBadBlockTableEntries;        /* 0x34 */
 1430     U16                     Reserved7;                      /* 0x36 */
 1431     U32                     IRNvsramVersion;                /* 0x38 */
 1432 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
 1433   Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
 1434 
 1435 #define MPI2_IOCPAGE6_PAGEVERSION                       (0x05)
 1436 
 1437 /* defines for IOC Page 6 CapabilitiesFlags */
 1438 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT      (0x00000020)
 1439 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT          (0x00000010)
 1440 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT           (0x00000008)
 1441 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT          (0x00000004)
 1442 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT           (0x00000002)
 1443 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE        (0x00000001)
 1444 
 1445 
 1446 /* IOC Page 7 */
 1447 
 1448 #define MPI2_IOCPAGE7_EVENTMASK_WORDS       (4)
 1449 
 1450 typedef struct _MPI2_CONFIG_PAGE_IOC_7
 1451 {
 1452     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 1453     U32                     Reserved1;                  /* 0x04 */
 1454     U32                     EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
 1455     U16                     SASBroadcastPrimitiveMasks; /* 0x18 */
 1456     U16                     SASNotifyPrimitiveMasks;    /* 0x1A */
 1457     U32                     Reserved3;                  /* 0x1C */
 1458 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
 1459   Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
 1460 
 1461 #define MPI2_IOCPAGE7_PAGEVERSION                       (0x02)
 1462 
 1463 
 1464 /* IOC Page 8 */
 1465 
 1466 typedef struct _MPI2_CONFIG_PAGE_IOC_8
 1467 {
 1468     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 1469     U8                      NumDevsPerEnclosure;        /* 0x04 */
 1470     U8                      Reserved1;                  /* 0x05 */
 1471     U16                     Reserved2;                  /* 0x06 */
 1472     U16                     MaxPersistentEntries;       /* 0x08 */
 1473     U16                     MaxNumPhysicalMappedIDs;    /* 0x0A */
 1474     U16                     Flags;                      /* 0x0C */
 1475     U16                     Reserved3;                  /* 0x0E */
 1476     U16                     IRVolumeMappingFlags;       /* 0x10 */
 1477     U16                     Reserved4;                  /* 0x12 */
 1478     U32                     Reserved5;                  /* 0x14 */
 1479 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
 1480   Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
 1481 
 1482 #define MPI2_IOCPAGE8_PAGEVERSION                       (0x00)
 1483 
 1484 /* defines for IOC Page 8 Flags field */
 1485 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1             (0x00000020)
 1486 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0         (0x00000010)
 1487 
 1488 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE           (0x0000000E)
 1489 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING  (0x00000000)
 1490 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING      (0x00000002)
 1491 
 1492 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING  (0x00000001)
 1493 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING   (0x00000000)
 1494 
 1495 /* defines for IOC Page 8 IRVolumeMappingFlags */
 1496 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE  (0x00000003)
 1497 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING        (0x00000000)
 1498 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING       (0x00000001)
 1499 
 1500 
 1501 /****************************************************************************
 1502 *   BIOS Config Pages
 1503 ****************************************************************************/
 1504 
 1505 /* BIOS Page 1 */
 1506 
 1507 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
 1508 {
 1509     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 1510     U32                     BiosOptions;                /* 0x04 */
 1511     U32                     IOCSettings;                /* 0x08 */
 1512     U8                      SSUTimeout;                 /* 0x0C */
 1513     U8                      Reserved1;                  /* 0x0D */
 1514     U16                     Reserved2;                  /* 0x0E */
 1515     U32                     DeviceSettings;             /* 0x10 */
 1516     U16                     NumberOfDevices;            /* 0x14 */
 1517     U16                     UEFIVersion;                /* 0x16 */
 1518     U16                     IOTimeoutBlockDevicesNonRM; /* 0x18 */
 1519     U16                     IOTimeoutSequential;        /* 0x1A */
 1520     U16                     IOTimeoutOther;             /* 0x1C */
 1521     U16                     IOTimeoutBlockDevicesRM;    /* 0x1E */
 1522 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
 1523   Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
 1524 
 1525 #define MPI2_BIOSPAGE1_PAGEVERSION                      (0x07)
 1526 
 1527 /* values for BIOS Page 1 BiosOptions field */
 1528 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE    (0x00008000)
 1529 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG                  (0x00004000)
 1530 
 1531 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK                         (0x00003800)
 1532 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL                        (0x00000000)
 1533 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE                   (0x00000800)
 1534 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID                        (0x00001000)
 1535 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS                        (0x00001800)
 1536 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY                        (0x00002000)
 1537 
 1538 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS                 (0x00000400)
 1539 
 1540 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD       (0x00000300)
 1541 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD   (0x00000000)
 1542 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD       (0x00000100)
 1543 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD    (0x00000200)
 1544 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD    (0x00000300)
 1545 
 1546 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID                      (0x000000F0)
 1547 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID                       (0x00000000)
 1548 
 1549 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION       (0x00000006)
 1550 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII                  (0x00000000)
 1551 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII                 (0x00000002)
 1552 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII           (0x00000004)
 1553 
 1554 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS                     (0x00000001)
 1555 
 1556 /* values for BIOS Page 1 IOCSettings field */
 1557 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE      (0x00030000)
 1558 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT       (0x00000000)
 1559 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT          (0x00010000)
 1560 
 1561 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING           (0x000000C0)
 1562 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING           (0x00000000)
 1563 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING           (0x00000040)
 1564 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING          (0x00000080)
 1565 
 1566 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT      (0x00000030)
 1567 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT                (0x00000000)
 1568 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT              (0x00000010)
 1569 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT                (0x00000020)
 1570 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT               (0x00000030)
 1571 
 1572 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS             (0x00000008)
 1573 
 1574 /* values for BIOS Page 1 DeviceSettings field */
 1575 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING     (0x00000010)
 1576 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN           (0x00000008)
 1577 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN            (0x00000004)
 1578 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN        (0x00000002)
 1579 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN         (0x00000001)
 1580 
 1581 /* defines for BIOS Page 1 UEFIVersion field */
 1582 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK              (0xFF00)
 1583 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT             (8)
 1584 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK              (0x00FF)
 1585 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT             (0)
 1586 
 1587 
 1588 
 1589 /* BIOS Page 2 */
 1590 
 1591 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
 1592 {
 1593     U32         Reserved1;                              /* 0x00 */
 1594     U32         Reserved2;                              /* 0x04 */
 1595     U32         Reserved3;                              /* 0x08 */
 1596     U32         Reserved4;                              /* 0x0C */
 1597     U32         Reserved5;                              /* 0x10 */
 1598     U32         Reserved6;                              /* 0x14 */
 1599 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
 1600   MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
 1601   Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
 1602 
 1603 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
 1604 {
 1605     U64         SASAddress;                             /* 0x00 */
 1606     U8          LUN[8];                                 /* 0x08 */
 1607     U32         Reserved1;                              /* 0x10 */
 1608     U32         Reserved2;                              /* 0x14 */
 1609 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
 1610   Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
 1611 
 1612 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
 1613 {
 1614     U64         EnclosureLogicalID;                     /* 0x00 */
 1615     U32         Reserved1;                              /* 0x08 */
 1616     U32         Reserved2;                              /* 0x0C */
 1617     U16         SlotNumber;                             /* 0x10 */
 1618     U16         Reserved3;                              /* 0x12 */
 1619     U32         Reserved4;                              /* 0x14 */
 1620 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
 1621   MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
 1622   Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
 1623 
 1624 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
 1625 {
 1626     U64         DeviceName;                             /* 0x00 */
 1627     U8          LUN[8];                                 /* 0x08 */
 1628     U32         Reserved1;                              /* 0x10 */
 1629     U32         Reserved2;                              /* 0x14 */
 1630 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
 1631   Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
 1632 
 1633 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
 1634 {
 1635     MPI2_BOOT_DEVICE_ADAPTER_ORDER  AdapterOrder;
 1636     MPI2_BOOT_DEVICE_SAS_WWID       SasWwid;
 1637     MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
 1638     MPI2_BOOT_DEVICE_DEVICE_NAME    DeviceName;
 1639 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
 1640   Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
 1641 
 1642 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
 1643 {
 1644     MPI2_CONFIG_PAGE_HEADER     Header;                 /* 0x00 */
 1645     U32                         Reserved1;              /* 0x04 */
 1646     U32                         Reserved2;              /* 0x08 */
 1647     U32                         Reserved3;              /* 0x0C */
 1648     U32                         Reserved4;              /* 0x10 */
 1649     U32                         Reserved5;              /* 0x14 */
 1650     U32                         Reserved6;              /* 0x18 */
 1651     U8                          ReqBootDeviceForm;      /* 0x1C */
 1652     U8                          Reserved7;              /* 0x1D */
 1653     U16                         Reserved8;              /* 0x1E */
 1654     MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedBootDevice;    /* 0x20 */
 1655     U8                          ReqAltBootDeviceForm;   /* 0x38 */
 1656     U8                          Reserved9;              /* 0x39 */
 1657     U16                         Reserved10;             /* 0x3A */
 1658     MPI2_BIOSPAGE2_BOOT_DEVICE  RequestedAltBootDevice; /* 0x3C */
 1659     U8                          CurrentBootDeviceForm;  /* 0x58 */
 1660     U8                          Reserved11;             /* 0x59 */
 1661     U16                         Reserved12;             /* 0x5A */
 1662     MPI2_BIOSPAGE2_BOOT_DEVICE  CurrentBootDevice;      /* 0x58 */
 1663 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
 1664   Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
 1665 
 1666 #define MPI2_BIOSPAGE2_PAGEVERSION                      (0x04)
 1667 
 1668 /* values for BIOS Page 2 BootDeviceForm fields */
 1669 #define MPI2_BIOSPAGE2_FORM_MASK                        (0x0F)
 1670 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED         (0x00)
 1671 #define MPI2_BIOSPAGE2_FORM_SAS_WWID                    (0x05)
 1672 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT              (0x06)
 1673 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME                 (0x07)
 1674 
 1675 
 1676 /* BIOS Page 3 */
 1677 
 1678 #define MPI2_BIOSPAGE3_NUM_ADAPTER      (4)
 1679 
 1680 typedef struct _MPI2_ADAPTER_INFO
 1681 {
 1682     U8      PciBusNumber;                               /* 0x00 */
 1683     U8      PciDeviceAndFunctionNumber;                 /* 0x01 */
 1684     U16     AdapterFlags;                               /* 0x02 */
 1685 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
 1686   Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
 1687 
 1688 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED                (0x0001)
 1689 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS             (0x0002)
 1690 
 1691 typedef struct _MPI2_ADAPTER_ORDER_AUX
 1692 {
 1693     U64     WWID;                                       /* 0x00 */
 1694     U32     Reserved1;                                  /* 0x08 */
 1695     U32     Reserved2;                                  /* 0x0C */
 1696 } MPI2_ADAPTER_ORDER_AUX, MPI2_POINTER PTR_MPI2_ADAPTER_ORDER_AUX,
 1697   Mpi2AdapterOrderAux_t, MPI2_POINTER pMpi2AdapterOrderAux_t;
 1698 
 1699 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
 1700 {
 1701     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 1702     U32                     GlobalFlags;                /* 0x04 */
 1703     U32                     BiosVersion;                /* 0x08 */
 1704     MPI2_ADAPTER_INFO       AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */
 1705     U32                     Reserved1;                  /* 0x1C */
 1706     MPI2_ADAPTER_ORDER_AUX  AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and newer */
 1707 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
 1708   Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
 1709 
 1710 #define MPI2_BIOSPAGE3_PAGEVERSION                      (0x01)
 1711 
 1712 /* values for BIOS Page 3 GlobalFlags */
 1713 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR             (0x00000002)
 1714 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE             (0x00000004)
 1715 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE        (0x00000010)
 1716 
 1717 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK      (0x000000E0)
 1718 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY      (0x00000000)
 1719 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY            (0x00000020)
 1720 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY        (0x00000040)
 1721 
 1722 
 1723 /* BIOS Page 4 */
 1724 
 1725 /*
 1726  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 1727  * one and check the value returned for NumPhys at runtime.
 1728  */
 1729 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
 1730 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES        (1)
 1731 #endif
 1732 
 1733 typedef struct _MPI2_BIOS4_ENTRY
 1734 {
 1735     U64                     ReassignmentWWID;       /* 0x00 */
 1736     U64                     ReassignmentDeviceName; /* 0x08 */
 1737 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
 1738   Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
 1739 
 1740 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
 1741 {
 1742     MPI2_CONFIG_PAGE_HEADER Header;                             /* 0x00 */
 1743     U8                      NumPhys;                            /* 0x04 */
 1744     U8                      Reserved1;                          /* 0x05 */
 1745     U16                     Reserved2;                          /* 0x06 */
 1746     MPI2_BIOS4_ENTRY        Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES];  /* 0x08 */
 1747 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
 1748   Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
 1749 
 1750 #define MPI2_BIOSPAGE4_PAGEVERSION                      (0x01)
 1751 
 1752 
 1753 /****************************************************************************
 1754 *   RAID Volume Config Pages
 1755 ****************************************************************************/
 1756 
 1757 /* RAID Volume Page 0 */
 1758 
 1759 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
 1760 {
 1761     U8                      RAIDSetNum;                 /* 0x00 */
 1762     U8                      PhysDiskMap;                /* 0x01 */
 1763     U8                      PhysDiskNum;                /* 0x02 */
 1764     U8                      Reserved;                   /* 0x03 */
 1765 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
 1766   Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
 1767 
 1768 /* defines for the PhysDiskMap field */
 1769 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY                  (0x01)
 1770 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY                (0x02)
 1771 
 1772 typedef struct _MPI2_RAIDVOL0_SETTINGS
 1773 {
 1774     U16                     Settings;                   /* 0x00 */
 1775     U8                      HotSparePool;               /* 0x01 */
 1776     U8                      Reserved;                   /* 0x02 */
 1777 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
 1778   Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
 1779 
 1780 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
 1781 #define MPI2_RAID_HOT_SPARE_POOL_0                      (0x01)
 1782 #define MPI2_RAID_HOT_SPARE_POOL_1                      (0x02)
 1783 #define MPI2_RAID_HOT_SPARE_POOL_2                      (0x04)
 1784 #define MPI2_RAID_HOT_SPARE_POOL_3                      (0x08)
 1785 #define MPI2_RAID_HOT_SPARE_POOL_4                      (0x10)
 1786 #define MPI2_RAID_HOT_SPARE_POOL_5                      (0x20)
 1787 #define MPI2_RAID_HOT_SPARE_POOL_6                      (0x40)
 1788 #define MPI2_RAID_HOT_SPARE_POOL_7                      (0x80)
 1789 
 1790 /* RAID Volume Page 0 VolumeSettings defines */
 1791 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX     (0x0008)
 1792 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
 1793 
 1794 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING        (0x0003)
 1795 #define MPI2_RAIDVOL0_SETTING_UNCHANGED                 (0x0000)
 1796 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING     (0x0001)
 1797 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING      (0x0002)
 1798 
 1799 /*
 1800  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 1801  * one and check the value returned for NumPhysDisks at runtime.
 1802  */
 1803 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
 1804 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX       (1)
 1805 #endif
 1806 
 1807 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
 1808 {
 1809     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 1810     U16                     DevHandle;                  /* 0x04 */
 1811     U8                      VolumeState;                /* 0x06 */
 1812     U8                      VolumeType;                 /* 0x07 */
 1813     U32                     VolumeStatusFlags;          /* 0x08 */
 1814     MPI2_RAIDVOL0_SETTINGS  VolumeSettings;             /* 0x0C */
 1815     U64                     MaxLBA;                     /* 0x10 */
 1816     U32                     StripeSize;                 /* 0x18 */
 1817     U16                     BlockSize;                  /* 0x1C */
 1818     U16                     Reserved1;                  /* 0x1E */
 1819     U8                      SupportedPhysDisks;         /* 0x20 */
 1820     U8                      ResyncRate;                 /* 0x21 */
 1821     U16                     DataScrubDuration;          /* 0x22 */
 1822     U8                      NumPhysDisks;               /* 0x24 */
 1823     U8                      Reserved2;                  /* 0x25 */
 1824     U8                      Reserved3;                  /* 0x26 */
 1825     U8                      InactiveStatus;             /* 0x27 */
 1826     MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
 1827 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
 1828   Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
 1829 
 1830 #define MPI2_RAIDVOLPAGE0_PAGEVERSION           (0x0A)
 1831 
 1832 /* values for RAID VolumeState */
 1833 #define MPI2_RAID_VOL_STATE_MISSING                         (0x00)
 1834 #define MPI2_RAID_VOL_STATE_FAILED                          (0x01)
 1835 #define MPI2_RAID_VOL_STATE_INITIALIZING                    (0x02)
 1836 #define MPI2_RAID_VOL_STATE_ONLINE                          (0x03)
 1837 #define MPI2_RAID_VOL_STATE_DEGRADED                        (0x04)
 1838 #define MPI2_RAID_VOL_STATE_OPTIMAL                         (0x05)
 1839 
 1840 /* values for RAID VolumeType */
 1841 #define MPI2_RAID_VOL_TYPE_RAID0                            (0x00)
 1842 #define MPI2_RAID_VOL_TYPE_RAID1E                           (0x01)
 1843 #define MPI2_RAID_VOL_TYPE_RAID1                            (0x02)
 1844 #define MPI2_RAID_VOL_TYPE_RAID10                           (0x05)
 1845 #define MPI2_RAID_VOL_TYPE_UNKNOWN                          (0xFF)
 1846 
 1847 /* values for RAID Volume Page 0 VolumeStatusFlags field */
 1848 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC            (0x02000000)
 1849 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING        (0x01000000)
 1850 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING               (0x00800000)
 1851 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING      (0x00400000)
 1852 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT      (0x00200000)
 1853 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB                (0x00100000)
 1854 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK         (0x00080000)
 1855 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION        (0x00040000)
 1856 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT           (0x00020000)
 1857 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS        (0x00010000)
 1858 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT        (0x00000080)
 1859 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED               (0x00000040)
 1860 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE              (0x00000020)
 1861 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR          (0x00000000)
 1862 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR        (0x00000010)
 1863 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL      (0x00000008)
 1864 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE           (0x00000004)
 1865 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED                  (0x00000002)
 1866 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED                   (0x00000001)
 1867 
 1868 /* values for RAID Volume Page 0 SupportedPhysDisks field */
 1869 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS             (0x08)
 1870 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS                    (0x04)
 1871 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL                  (0x02)
 1872 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL                 (0x01)
 1873 
 1874 /* values for RAID Volume Page 0 InactiveStatus field */
 1875 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE                  (0x00)
 1876 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE           (0x01)
 1877 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE           (0x02)
 1878 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE    (0x03)
 1879 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE             (0x04)
 1880 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE    (0x05)
 1881 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED                (0x06)
 1882 
 1883 
 1884 /* RAID Volume Page 1 */
 1885 
 1886 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
 1887 {
 1888     MPI2_CONFIG_PAGE_HEADER Header;                     /* 0x00 */
 1889     U16                     DevHandle;                  /* 0x04 */
 1890     U16                     Reserved0;                  /* 0x06 */
 1891     U8                      GUID[24];                   /* 0x08 */
 1892     U8                      Name[16];                   /* 0x20 */
 1893     U64                     WWID;                       /* 0x30 */
 1894     U32                     Reserved1;                  /* 0x38 */
 1895     U32                     Reserved2;                  /* 0x3C */
 1896 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
 1897   Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
 1898 
 1899 #define MPI2_RAIDVOLPAGE1_PAGEVERSION           (0x03)
 1900 
 1901 
 1902 /****************************************************************************
 1903 *   RAID Physical Disk Config Pages
 1904 ****************************************************************************/
 1905 
 1906 /* RAID Physical Disk Page 0 */
 1907 
 1908 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
 1909 {
 1910     U16                     Reserved1;                  /* 0x00 */
 1911     U8                      HotSparePool;               /* 0x02 */
 1912     U8                      Reserved2;                  /* 0x03 */
 1913 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
 1914   Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
 1915 
 1916 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
 1917 
 1918 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
 1919 {
 1920     U8                      VendorID[8];                /* 0x00 */
 1921     U8                      ProductID[16];              /* 0x08 */
 1922     U8                      ProductRevLevel[4];         /* 0x18 */
 1923     U8                      SerialNum[32];              /* 0x1C */
 1924 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
 1925   MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
 1926   Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
 1927 
 1928 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
 1929 {
 1930     MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
 1931     U16                             DevHandle;                  /* 0x04 */
 1932     U8                              Reserved1;                  /* 0x06 */
 1933     U8                              PhysDiskNum;                /* 0x07 */
 1934     MPI2_RAIDPHYSDISK0_SETTINGS     PhysDiskSettings;           /* 0x08 */
 1935     U32                             Reserved2;                  /* 0x0C */
 1936     MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData;                /* 0x10 */
 1937     U32                             Reserved3;                  /* 0x4C */
 1938     U8                              PhysDiskState;              /* 0x50 */
 1939     U8                              OfflineReason;              /* 0x51 */
 1940     U8                              IncompatibleReason;         /* 0x52 */
 1941     U8                              PhysDiskAttributes;         /* 0x53 */
 1942     U32                             PhysDiskStatusFlags;        /* 0x54 */
 1943     U64                             DeviceMaxLBA;               /* 0x58 */
 1944     U64                             HostMaxLBA;                 /* 0x60 */
 1945     U64                             CoercedMaxLBA;              /* 0x68 */
 1946     U16                             BlockSize;                  /* 0x70 */
 1947     U16                             Reserved5;                  /* 0x72 */
 1948     U32                             Reserved6;                  /* 0x74 */
 1949 } MPI2_CONFIG_PAGE_RD_PDISK_0,
 1950   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
 1951   Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
 1952 
 1953 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION          (0x05)
 1954 
 1955 /* PhysDiskState defines */
 1956 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED               (0x00)
 1957 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE               (0x01)
 1958 #define MPI2_RAID_PD_STATE_OFFLINE                      (0x02)
 1959 #define MPI2_RAID_PD_STATE_ONLINE                       (0x03)
 1960 #define MPI2_RAID_PD_STATE_HOT_SPARE                    (0x04)
 1961 #define MPI2_RAID_PD_STATE_DEGRADED                     (0x05)
 1962 #define MPI2_RAID_PD_STATE_REBUILDING                   (0x06)
 1963 #define MPI2_RAID_PD_STATE_OPTIMAL                      (0x07)
 1964 
 1965 /* OfflineReason defines */
 1966 #define MPI2_PHYSDISK0_ONLINE                           (0x00)
 1967 #define MPI2_PHYSDISK0_OFFLINE_MISSING                  (0x01)
 1968 #define MPI2_PHYSDISK0_OFFLINE_FAILED                   (0x03)
 1969 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING             (0x04)
 1970 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED                (0x05)
 1971 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED         (0x06)
 1972 #define MPI2_PHYSDISK0_OFFLINE_OTHER                    (0xFF)
 1973 
 1974 /* IncompatibleReason defines */
 1975 #define MPI2_PHYSDISK0_COMPATIBLE                       (0x00)
 1976 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL            (0x01)
 1977 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE           (0x02)
 1978 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA             (0x03)
 1979 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD   (0x04)
 1980 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA    (0x05)
 1981 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE          (0x06)
 1982 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN             (0xFF)
 1983 
 1984 /* PhysDiskAttributes defines */
 1985 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK                (0x0C)
 1986 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE         (0x08)
 1987 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE           (0x04)
 1988 
 1989 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK             (0x03)
 1990 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL              (0x02)
 1991 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL             (0x01)
 1992 
 1993 /* PhysDiskStatusFlags defines */
 1994 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED        (0x00000040)
 1995 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET           (0x00000020)
 1996 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED  (0x00000010)
 1997 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS     (0x00000000)
 1998 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
 1999 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME      (0x00000004)
 2000 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED             (0x00000002)
 2001 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC          (0x00000001)
 2002 
 2003 
 2004 /* RAID Physical Disk Page 1 */
 2005 
 2006 /*
 2007  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 2008  * one and check the value returned for NumPhysDiskPaths at runtime.
 2009  */
 2010 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
 2011 #define MPI2_RAID_PHYS_DISK1_PATH_MAX   (1)
 2012 #endif
 2013 
 2014 typedef struct _MPI2_RAIDPHYSDISK1_PATH
 2015 {
 2016     U16             DevHandle;          /* 0x00 */
 2017     U16             Reserved1;          /* 0x02 */
 2018     U64             WWID;               /* 0x04 */
 2019     U64             OwnerWWID;          /* 0x0C */
 2020     U8              OwnerIdentifier;    /* 0x14 */
 2021     U8              Reserved2;          /* 0x15 */
 2022     U16             Flags;              /* 0x16 */
 2023 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
 2024   Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
 2025 
 2026 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
 2027 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY        (0x0004)
 2028 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN         (0x0002)
 2029 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID        (0x0001)
 2030 
 2031 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
 2032 {
 2033     MPI2_CONFIG_PAGE_HEADER         Header;                     /* 0x00 */
 2034     U8                              NumPhysDiskPaths;           /* 0x04 */
 2035     U8                              PhysDiskNum;                /* 0x05 */
 2036     U16                             Reserved1;                  /* 0x06 */
 2037     U32                             Reserved2;                  /* 0x08 */
 2038     MPI2_RAIDPHYSDISK1_PATH         PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
 2039 } MPI2_CONFIG_PAGE_RD_PDISK_1,
 2040   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
 2041   Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
 2042 
 2043 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION          (0x02)
 2044 
 2045 
 2046 /****************************************************************************
 2047 *   values for fields used by several types of SAS Config Pages
 2048 ****************************************************************************/
 2049 
 2050 /* values for NegotiatedLinkRates fields */
 2051 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL             (0xF0)
 2052 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL            (4)
 2053 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL            (0x0F)
 2054 /* link rates used for Negotiated Physical and Logical Link Rate */
 2055 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE        (0x00)
 2056 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED             (0x01)
 2057 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED       (0x02)
 2058 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE        (0x03)
 2059 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR            (0x04)
 2060 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS    (0x05)
 2061 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY          (0x06)
 2062 #define MPI2_SAS_NEG_LINK_RATE_1_5                      (0x08)
 2063 #define MPI2_SAS_NEG_LINK_RATE_3_0                      (0x09)
 2064 #define MPI2_SAS_NEG_LINK_RATE_6_0                      (0x0A)
 2065 #define MPI25_SAS_NEG_LINK_RATE_12_0                    (0x0B)
 2066 #define MPI26_SAS_NEG_LINK_RATE_22_5                    (0x0C)
 2067 
 2068 
 2069 /* values for AttachedPhyInfo fields */
 2070 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT       (0x00000040)
 2071 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS        (0x00000020)
 2072 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE           (0x00000010)
 2073 
 2074 #define MPI2_SAS_APHYINFO_REASON_MASK                   (0x0000000F)
 2075 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN                (0x00000000)
 2076 #define MPI2_SAS_APHYINFO_REASON_POWER_ON               (0x00000001)
 2077 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET             (0x00000002)
 2078 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL        (0x00000003)
 2079 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC           (0x00000004)
 2080 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ       (0x00000005)
 2081 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER    (0x00000006)
 2082 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT          (0x00000007)
 2083 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED       (0x00000008)
 2084 
 2085 
 2086 /* values for PhyInfo fields */
 2087 #define MPI2_SAS_PHYINFO_PHY_VACANT                     (0x80000000)
 2088 
 2089 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK       (0x18000000)
 2090 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION      (27)
 2091 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE               (0x00000000)
 2092 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL              (0x08000000)
 2093 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER              (0x10000000)
 2094 
 2095 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS       (0x04000000)
 2096 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT        (0x02000000)
 2097 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS               (0x01000000)
 2098 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT          (0x00400000)
 2099 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS                   (0x00200000)
 2100 #define MPI2_SAS_PHYINFO_ZONING_ENABLED                 (0x00100000)
 2101 
 2102 #define MPI2_SAS_PHYINFO_REASON_MASK                    (0x000F0000)
 2103 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN                 (0x00000000)
 2104 #define MPI2_SAS_PHYINFO_REASON_POWER_ON                (0x00010000)
 2105 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET              (0x00020000)
 2106 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL         (0x00030000)
 2107 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC            (0x00040000)
 2108 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ        (0x00050000)
 2109 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER     (0x00060000)
 2110 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT           (0x00070000)
 2111 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED        (0x00080000)
 2112 
 2113 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED         (0x00008000)
 2114 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE               (0x00004000)
 2115 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT     (0x00002000)
 2116 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY                    (0x00001000)
 2117 
 2118 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME      (0x00000F00)
 2119 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME     (8)
 2120 
 2121 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE         (0x000000F0)
 2122 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING                 (0x00000000)
 2123 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING            (0x00000010)
 2124 #define MPI2_SAS_PHYINFO_TABLE_ROUTING                  (0x00000020)
 2125 
 2126 
 2127 /* values for SAS ProgrammedLinkRate fields */
 2128 #define MPI2_SAS_PRATE_MAX_RATE_MASK                    (0xF0)
 2129 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE        (0x00)
 2130 #define MPI2_SAS_PRATE_MAX_RATE_1_5                     (0x80)
 2131 #define MPI2_SAS_PRATE_MAX_RATE_3_0                     (0x90)
 2132 #define MPI2_SAS_PRATE_MAX_RATE_6_0                     (0xA0)
 2133 #define MPI25_SAS_PRATE_MAX_RATE_12_0                   (0xB0)
 2134 #define MPI26_SAS_PRATE_MAX_RATE_22_5                   (0xC0)
 2135 #define MPI2_SAS_PRATE_MIN_RATE_MASK                    (0x0F)
 2136 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE        (0x00)
 2137 #define MPI2_SAS_PRATE_MIN_RATE_1_5                     (0x08)
 2138 #define MPI2_SAS_PRATE_MIN_RATE_3_0                     (0x09)
 2139 #define MPI2_SAS_PRATE_MIN_RATE_6_0                     (0x0A)
 2140 #define MPI25_SAS_PRATE_MIN_RATE_12_0                   (0x0B)
 2141 #define MPI26_SAS_PRATE_MIN_RATE_22_5                   (0x0C)
 2142 
 2143 
 2144 /* values for SAS HwLinkRate fields */
 2145 #define MPI2_SAS_HWRATE_MAX_RATE_MASK                   (0xF0)
 2146 #define MPI2_SAS_HWRATE_MAX_RATE_1_5                    (0x80)
 2147 #define MPI2_SAS_HWRATE_MAX_RATE_3_0                    (0x90)
 2148 #define MPI2_SAS_HWRATE_MAX_RATE_6_0                    (0xA0)
 2149 #define MPI25_SAS_HWRATE_MAX_RATE_12_0                  (0xB0)
 2150 #define MPI26_SAS_HWRATE_MAX_RATE_22_5                  (0xC0)
 2151 #define MPI2_SAS_HWRATE_MIN_RATE_MASK                   (0x0F)
 2152 #define MPI2_SAS_HWRATE_MIN_RATE_1_5                    (0x08)
 2153 #define MPI2_SAS_HWRATE_MIN_RATE_3_0                    (0x09)
 2154 #define MPI2_SAS_HWRATE_MIN_RATE_6_0                    (0x0A)
 2155 #define MPI25_SAS_HWRATE_MIN_RATE_12_0                  (0x0B)
 2156 #define MPI26_SAS_HWRATE_MIN_RATE_22_5                  (0x0C)
 2157 
 2158 
 2159 
 2160 /****************************************************************************
 2161 *   SAS IO Unit Config Pages
 2162 ****************************************************************************/
 2163 
 2164 /* SAS IO Unit Page 0 */
 2165 
 2166 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
 2167 {
 2168     U8          Port;                   /* 0x00 */
 2169     U8          PortFlags;              /* 0x01 */
 2170     U8          PhyFlags;               /* 0x02 */
 2171     U8          NegotiatedLinkRate;     /* 0x03 */
 2172     U32         ControllerPhyDeviceInfo;/* 0x04 */
 2173     U16         AttachedDevHandle;      /* 0x08 */
 2174     U16         ControllerDevHandle;    /* 0x0A */
 2175     U32         DiscoveryStatus;        /* 0x0C */
 2176     U32         Reserved;               /* 0x10 */
 2177 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
 2178   Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
 2179 
 2180 /*
 2181  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 2182  * one and check the value returned for NumPhys at runtime.
 2183  */
 2184 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
 2185 #define MPI2_SAS_IOUNIT0_PHY_MAX        (1)
 2186 #endif
 2187 
 2188 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
 2189 {
 2190     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
 2191     U32                                 Reserved1;                          /* 0x08 */
 2192     U8                                  NumPhys;                            /* 0x0C */
 2193     U8                                  Reserved2;                          /* 0x0D */
 2194     U16                                 Reserved3;                          /* 0x0E */
 2195     MPI2_SAS_IO_UNIT0_PHY_DATA          PhyData[MPI2_SAS_IOUNIT0_PHY_MAX];  /* 0x10 */
 2196 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
 2197   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
 2198   Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
 2199 
 2200 #define MPI2_SASIOUNITPAGE0_PAGEVERSION                     (0x05)
 2201 
 2202 /* values for SAS IO Unit Page 0 PortFlags */
 2203 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS     (0x08)
 2204 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG          (0x01)
 2205 
 2206 /* values for SAS IO Unit Page 0 PhyFlags */
 2207 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT       (0x40)
 2208 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT       (0x20)
 2209 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED             (0x10)
 2210 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED               (0x08)
 2211 
 2212 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
 2213 
 2214 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
 2215 
 2216 /* values for SAS IO Unit Page 0 DiscoveryStatus */
 2217 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 2218 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 2219 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED               (0x20000000)
 2220 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 2221 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 2222 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 2223 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 2224 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN                (0x00002000)
 2225 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 2226 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE               (0x00000800)
 2227 #define MPI2_SASIOUNIT0_DS_TABLE_LINK                       (0x00000400)
 2228 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK                 (0x00000200)
 2229 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR                    (0x00000100)
 2230 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED              (0x00000080)
 2231 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST                  (0x00000040)
 2232 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 2233 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT                      (0x00000010)
 2234 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS                   (0x00000004)
 2235 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 2236 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED                    (0x00000001)
 2237 
 2238 
 2239 /* SAS IO Unit Page 1 */
 2240 
 2241 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
 2242 {
 2243     U8          Port;                       /* 0x00 */
 2244     U8          PortFlags;                  /* 0x01 */
 2245     U8          PhyFlags;                   /* 0x02 */
 2246     U8          MaxMinLinkRate;             /* 0x03 */
 2247     U32         ControllerPhyDeviceInfo;    /* 0x04 */
 2248     U16         MaxTargetPortConnectTime;   /* 0x08 */
 2249     U16         Reserved1;                  /* 0x0A */
 2250 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
 2251   Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
 2252 
 2253 /*
 2254  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 2255  * one and check the value returned for NumPhys at runtime.
 2256  */
 2257 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
 2258 #define MPI2_SAS_IOUNIT1_PHY_MAX        (1)
 2259 #endif
 2260 
 2261 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
 2262 {
 2263     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
 2264     U16                                 ControlFlags;                       /* 0x08 */
 2265     U16                                 SASNarrowMaxQueueDepth;             /* 0x0A */
 2266     U16                                 AdditionalControlFlags;             /* 0x0C */
 2267     U16                                 SASWideMaxQueueDepth;               /* 0x0E */
 2268     U8                                  NumPhys;                            /* 0x10 */
 2269     U8                                  SATAMaxQDepth;                      /* 0x11 */
 2270     U8                                  ReportDeviceMissingDelay;           /* 0x12 */
 2271     U8                                  IODeviceMissingDelay;               /* 0x13 */
 2272     MPI2_SAS_IO_UNIT1_PHY_DATA          PhyData[MPI2_SAS_IOUNIT1_PHY_MAX];  /* 0x14 */
 2273 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
 2274   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
 2275   Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
 2276 
 2277 #define MPI2_SASIOUNITPAGE1_PAGEVERSION     (0x09)
 2278 
 2279 /* values for SAS IO Unit Page 1 ControlFlags */
 2280 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST                    (0x8000)
 2281 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX                        (0x4000)
 2282 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX                        (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */
 2283 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE                    (0x1000)
 2284 
 2285 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT                    (0x0600)
 2286 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT                   (9)
 2287 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH                    (0x0)
 2288 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT                     (0x1)
 2289 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT                    (0x2)
 2290 
 2291 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED             (0x0080)
 2292 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED                 (0x0040)
 2293 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED                   (0x0020)
 2294 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED                   (0x0010)
 2295 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL           (0x0008)
 2296 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL                 (0x0004)
 2297 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY                 (0x0002)
 2298 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION                   (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */
 2299 
 2300 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
 2301 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT                 (0x0100)
 2302 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL          (0x0080)
 2303 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION    (0x0040)
 2304 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION        (0x0020)
 2305 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET   (0x0010)
 2306 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET  (0x0008)
 2307 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET   (0x0004)
 2308 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET     (0x0002)
 2309 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE               (0x0001)
 2310 
 2311 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
 2312 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK                 (0x7F)
 2313 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16                      (0x80)
 2314 
 2315 /* values for SAS IO Unit Page 1 PortFlags */
 2316 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG                 (0x01)
 2317 
 2318 /* values for SAS IO Unit Page 1 PhyFlags */
 2319 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT               (0x40)
 2320 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT               (0x20)
 2321 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE                      (0x10)
 2322 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE                        (0x08)
 2323 
 2324 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
 2325 #define MPI2_SASIOUNIT1_MAX_RATE_MASK                               (0xF0)
 2326 #define MPI2_SASIOUNIT1_MAX_RATE_1_5                                (0x80)
 2327 #define MPI2_SASIOUNIT1_MAX_RATE_3_0                                (0x90)
 2328 #define MPI2_SASIOUNIT1_MAX_RATE_6_0                                (0xA0)
 2329 #define MPI25_SASIOUNIT1_MAX_RATE_12_0                              (0xB0)
 2330 #define MPI26_SASIOUNIT1_MAX_RATE_22_5                              (0xC0)
 2331 #define MPI2_SASIOUNIT1_MIN_RATE_MASK                               (0x0F)
 2332 #define MPI2_SASIOUNIT1_MIN_RATE_1_5                                (0x08)
 2333 #define MPI2_SASIOUNIT1_MIN_RATE_3_0                                (0x09)
 2334 #define MPI2_SASIOUNIT1_MIN_RATE_6_0                                (0x0A)
 2335 #define MPI25_SASIOUNIT1_MIN_RATE_12_0                              (0x0B)
 2336 #define MPI26_SASIOUNIT1_MIN_RATE_22_5                              (0x0C)
 2337 
 2338 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
 2339 
 2340 
 2341 /* SAS IO Unit Page 4 (for MPI v2.5 and earlier) */
 2342 
 2343 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
 2344 {
 2345     U8          MaxTargetSpinup;            /* 0x00 */
 2346     U8          SpinupDelay;                /* 0x01 */
 2347     U8          SpinupFlags;                /* 0x02 */
 2348     U8          Reserved1;                  /* 0x03 */
 2349 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
 2350   Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
 2351 
 2352 /* defines for SAS IO Unit Page 4 SpinupFlags */
 2353 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG         (0x01)
 2354 
 2355 
 2356 /*
 2357  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 2358  * one and check the value returned for NumPhys at runtime.
 2359  */
 2360 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
 2361 #define MPI2_SAS_IOUNIT4_PHY_MAX        (4)
 2362 #endif
 2363 
 2364 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
 2365 {
 2366     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                         /* 0x00 */
 2367     MPI2_SAS_IOUNIT4_SPINUP_GROUP       SpinupGroupParameters[4];       /* 0x08 */
 2368     U32                                 Reserved1;                      /* 0x18 */
 2369     U32                                 Reserved2;                      /* 0x1C */
 2370     U32                                 Reserved3;                      /* 0x20 */
 2371     U8                                  BootDeviceWaitTime;             /* 0x24 */
 2372     U8                                  SATADeviceWaitTime;             /* 0x25 */
 2373     U16                                 Reserved5;                      /* 0x26 */
 2374     U8                                  NumPhys;                        /* 0x28 */
 2375     U8                                  PEInitialSpinupDelay;           /* 0x29 */
 2376     U8                                  PEReplyDelay;                   /* 0x2A */
 2377     U8                                  Flags;                          /* 0x2B */
 2378     U8                                  PHY[MPI2_SAS_IOUNIT4_PHY_MAX];  /* 0x2C */
 2379 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
 2380   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
 2381   Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
 2382 
 2383 #define MPI2_SASIOUNITPAGE4_PAGEVERSION     (0x02)
 2384 
 2385 /* defines for Flags field */
 2386 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE               (0x01)
 2387 
 2388 /* defines for PHY field */
 2389 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK               (0x03)
 2390 
 2391 
 2392 /* SAS IO Unit Page 5 */
 2393 
 2394 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
 2395 {
 2396     U8          ControlFlags;               /* 0x00 */
 2397     U8          PortWidthModGroup;          /* 0x01 */
 2398     U16         InactivityTimerExponent;    /* 0x02 */
 2399     U8          SATAPartialTimeout;         /* 0x04 */
 2400     U8          Reserved2;                  /* 0x05 */
 2401     U8          SATASlumberTimeout;         /* 0x06 */
 2402     U8          Reserved3;                  /* 0x07 */
 2403     U8          SASPartialTimeout;          /* 0x08 */
 2404     U8          Reserved4;                  /* 0x09 */
 2405     U8          SASSlumberTimeout;          /* 0x0A */
 2406     U8          Reserved5;                  /* 0x0B */
 2407 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
 2408   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
 2409   Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
 2410 
 2411 /* defines for ControlFlags field */
 2412 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE      (0x08)
 2413 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE      (0x04)
 2414 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE     (0x02)
 2415 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE     (0x01)
 2416 
 2417 /* defines for PortWidthModeGroup field */
 2418 #define MPI2_SASIOUNIT5_PWMG_DISABLE                    (0xFF)
 2419 
 2420 /* defines for InactivityTimerExponent field */
 2421 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER            (0x7000)
 2422 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER           (12)
 2423 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL            (0x0700)
 2424 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL           (8)
 2425 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER           (0x0070)
 2426 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER          (4)
 2427 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL           (0x0007)
 2428 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL          (0)
 2429 
 2430 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS                 (7)
 2431 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND                  (6)
 2432 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS        (5)
 2433 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS            (4)
 2434 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND             (3)
 2435 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS        (2)
 2436 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS            (1)
 2437 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND             (0)
 2438 
 2439 /*
 2440  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 2441  * one and check the value returned for NumPhys at runtime.
 2442  */
 2443 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
 2444 #define MPI2_SAS_IOUNIT5_PHY_MAX        (1)
 2445 #endif
 2446 
 2447 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5
 2448 {
 2449     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
 2450     U8                                  NumPhys;                            /* 0x08 */
 2451     U8                                  Reserved1;                          /* 0x09 */
 2452     U16                                 Reserved2;                          /* 0x0A */
 2453     U32                                 Reserved3;                          /* 0x0C */
 2454     MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS   SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];  /* 0x10 */
 2455 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
 2456   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
 2457   Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
 2458 
 2459 #define MPI2_SASIOUNITPAGE5_PAGEVERSION     (0x01)
 2460 
 2461 
 2462 /* SAS IO Unit Page 6 */
 2463 
 2464 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
 2465 {
 2466     U8          CurrentStatus;              /* 0x00 */
 2467     U8          CurrentModulation;          /* 0x01 */
 2468     U8          CurrentUtilization;         /* 0x02 */
 2469     U8          Reserved1;                  /* 0x03 */
 2470     U32         Reserved2;                  /* 0x04 */
 2471 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
 2472   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
 2473   Mpi2SasIOUnit6PortWidthModGroupStatus_t,
 2474   MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
 2475 
 2476 /* defines for CurrentStatus field */
 2477 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE                      (0x00)
 2478 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED                     (0x01)
 2479 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG                   (0x02)
 2480 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN                        (0x03)
 2481 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY                 (0x04)
 2482 #define MPI2_SASIOUNIT6_STATUS_INACTIVE                         (0x05)
 2483 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT                    (0x06)
 2484 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST                      (0x07)
 2485 
 2486 /* defines for CurrentModulation field */
 2487 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT                   (0x00)
 2488 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT                   (0x01)
 2489 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT                   (0x02)
 2490 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT                  (0x03)
 2491 
 2492 /*
 2493  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 2494  * one and check the value returned for NumGroups at runtime.
 2495  */
 2496 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
 2497 #define MPI2_SAS_IOUNIT6_GROUP_MAX      (1)
 2498 #endif
 2499 
 2500 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6
 2501 {
 2502     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 2503     U32                                 Reserved1;                  /* 0x08 */
 2504     U32                                 Reserved2;                  /* 0x0C */
 2505     U8                                  NumGroups;                  /* 0x10 */
 2506     U8                                  Reserved3;                  /* 0x11 */
 2507     U16                                 Reserved4;                  /* 0x12 */
 2508     MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
 2509         PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
 2510 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
 2511   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
 2512   Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
 2513 
 2514 #define MPI2_SASIOUNITPAGE6_PAGEVERSION     (0x00)
 2515 
 2516 
 2517 /* SAS IO Unit Page 7 */
 2518 
 2519 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
 2520 {
 2521     U8          Flags;                      /* 0x00 */
 2522     U8          Reserved1;                  /* 0x01 */
 2523     U16         Reserved2;                  /* 0x02 */
 2524     U8          Threshold75Pct;             /* 0x04 */
 2525     U8          Threshold50Pct;             /* 0x05 */
 2526     U8          Threshold25Pct;             /* 0x06 */
 2527     U8          Reserved3;                  /* 0x07 */
 2528 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
 2529   MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
 2530   Mpi2SasIOUnit7PortWidthModGroupSettings_t,
 2531   MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
 2532 
 2533 /* defines for Flags field */
 2534 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION  (0x01)
 2535 
 2536 
 2537 /*
 2538  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 2539  * one and check the value returned for NumGroups at runtime.
 2540  */
 2541 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
 2542 #define MPI2_SAS_IOUNIT7_GROUP_MAX      (1)
 2543 #endif
 2544 
 2545 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7
 2546 {
 2547     MPI2_CONFIG_EXTENDED_PAGE_HEADER            Header;             /* 0x00 */
 2548     U8                                          SamplingInterval;   /* 0x08 */
 2549     U8                                          WindowLength;       /* 0x09 */
 2550     U16                                         Reserved1;          /* 0x0A */
 2551     U32                                         Reserved2;          /* 0x0C */
 2552     U32                                         Reserved3;          /* 0x10 */
 2553     U8                                          NumGroups;          /* 0x14 */
 2554     U8                                          Reserved4;          /* 0x15 */
 2555     U16                                         Reserved5;          /* 0x16 */
 2556     MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
 2557         PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
 2558 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
 2559   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
 2560   Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
 2561 
 2562 #define MPI2_SASIOUNITPAGE7_PAGEVERSION     (0x00)
 2563 
 2564 
 2565 /* SAS IO Unit Page 8 */
 2566 
 2567 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8
 2568 {
 2569     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                         /* 0x00 */
 2570     U32                                 Reserved1;                      /* 0x08 */
 2571     U32                                 PowerManagementCapabilities;    /* 0x0C */
 2572     U8                                  TxRxSleepStatus;                /* 0x10 */ /* reserved in MPI 2.0 */
 2573     U8                                  Reserved2;                      /* 0x11 */
 2574     U16                                 Reserved3;                      /* 0x12 */
 2575 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
 2576   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
 2577   Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
 2578 
 2579 #define MPI2_SASIOUNITPAGE8_PAGEVERSION     (0x00)
 2580 
 2581 /* defines for PowerManagementCapabilities field */
 2582 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD          (0x00001000)
 2583 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE        (0x00000800)
 2584 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE        (0x00000400)
 2585 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE       (0x00000200)
 2586 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE       (0x00000100)
 2587 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD        (0x00000010)
 2588 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE      (0x00000008)
 2589 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE      (0x00000004)
 2590 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE     (0x00000002)
 2591 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE     (0x00000001)
 2592 
 2593 /* defines for TxRxSleepStatus field */
 2594 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED          (0x00)
 2595 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED           (0x01)
 2596 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE               (0x02)
 2597 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN             (0x03)
 2598 
 2599 
 2600 
 2601 /* SAS IO Unit Page 16 */
 2602 
 2603 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16
 2604 {
 2605     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
 2606     U64                                 TimeStamp;                          /* 0x08 */
 2607     U32                                 Reserved1;                          /* 0x10 */
 2608     U32                                 Reserved2;                          /* 0x14 */
 2609     U32                                 FastPathPendedRequests;             /* 0x18 */
 2610     U32                                 FastPathUnPendedRequests;           /* 0x1C */
 2611     U32                                 FastPathHostRequestStarts;          /* 0x20 */
 2612     U32                                 FastPathFirmwareRequestStarts;      /* 0x24 */
 2613     U32                                 FastPathHostCompletions;            /* 0x28 */
 2614     U32                                 FastPathFirmwareCompletions;        /* 0x2C */
 2615     U32                                 NonFastPathRequestStarts;           /* 0x30 */
 2616     U32                                 NonFastPathHostCompletions;         /* 0x30 */
 2617 } MPI2_CONFIG_PAGE_SASIOUNIT16,
 2618   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
 2619   Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t;
 2620 
 2621 #define MPI2_SASIOUNITPAGE16_PAGEVERSION    (0x00)
 2622 
 2623 
 2624 /****************************************************************************
 2625 *   SAS Expander Config Pages
 2626 ****************************************************************************/
 2627 
 2628 /* SAS Expander Page 0 */
 2629 
 2630 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
 2631 {
 2632     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 2633     U8                                  PhysicalPort;               /* 0x08 */
 2634     U8                                  ReportGenLength;            /* 0x09 */
 2635     U16                                 EnclosureHandle;            /* 0x0A */
 2636     U64                                 SASAddress;                 /* 0x0C */
 2637     U32                                 DiscoveryStatus;            /* 0x14 */
 2638     U16                                 DevHandle;                  /* 0x18 */
 2639     U16                                 ParentDevHandle;            /* 0x1A */
 2640     U16                                 ExpanderChangeCount;        /* 0x1C */
 2641     U16                                 ExpanderRouteIndexes;       /* 0x1E */
 2642     U8                                  NumPhys;                    /* 0x20 */
 2643     U8                                  SASLevel;                   /* 0x21 */
 2644     U16                                 Flags;                      /* 0x22 */
 2645     U16                                 STPBusInactivityTimeLimit;  /* 0x24 */
 2646     U16                                 STPMaxConnectTimeLimit;     /* 0x26 */
 2647     U16                                 STP_SMP_NexusLossTime;      /* 0x28 */
 2648     U16                                 MaxNumRoutedSasAddresses;   /* 0x2A */
 2649     U64                                 ActiveZoneManagerSASAddress;/* 0x2C */
 2650     U16                                 ZoneLockInactivityLimit;    /* 0x34 */
 2651     U16                                 Reserved1;                  /* 0x36 */
 2652     U8                                  TimeToReducedFunc;          /* 0x38 */
 2653     U8                                  InitialTimeToReducedFunc;   /* 0x39 */
 2654     U8                                  MaxReducedFuncTime;         /* 0x3A */
 2655     U8                                  Reserved2;                  /* 0x3B */
 2656 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
 2657   Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
 2658 
 2659 #define MPI2_SASEXPANDER0_PAGEVERSION       (0x06)
 2660 
 2661 /* values for SAS Expander Page 0 DiscoveryStatus field */
 2662 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED         (0x80000000)
 2663 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED          (0x40000000)
 2664 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED            (0x20000000)
 2665 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED          (0x10000000)
 2666 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR          (0x08000000)
 2667 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
 2668 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE         (0x00004000)
 2669 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN             (0x00002000)
 2670 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK     (0x00001000)
 2671 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE            (0x00000800)
 2672 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK                    (0x00000400)
 2673 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK              (0x00000200)
 2674 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR                 (0x00000100)
 2675 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED           (0x00000080)
 2676 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST               (0x00000040)
 2677 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES             (0x00000020)
 2678 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT                   (0x00000010)
 2679 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS                (0x00000004)
 2680 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE          (0x00000002)
 2681 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED                 (0x00000001)
 2682 
 2683 /* values for SAS Expander Page 0 Flags field */
 2684 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY      (0x2000)
 2685 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED                (0x1000)
 2686 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES    (0x0800)
 2687 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES     (0x0400)
 2688 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT             (0x0200)
 2689 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING             (0x0100)
 2690 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT     (0x0080)
 2691 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE       (0x0010)
 2692 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG              (0x0004)
 2693 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS         (0x0002)
 2694 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG         (0x0001)
 2695 
 2696 
 2697 /* SAS Expander Page 1 */
 2698 
 2699 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
 2700 {
 2701     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 2702     U8                                  PhysicalPort;               /* 0x08 */
 2703     U8                                  Reserved1;                  /* 0x09 */
 2704     U16                                 Reserved2;                  /* 0x0A */
 2705     U8                                  NumPhys;                    /* 0x0C */
 2706     U8                                  Phy;                        /* 0x0D */
 2707     U16                                 NumTableEntriesProgrammed;  /* 0x0E */
 2708     U8                                  ProgrammedLinkRate;         /* 0x10 */
 2709     U8                                  HwLinkRate;                 /* 0x11 */
 2710     U16                                 AttachedDevHandle;          /* 0x12 */
 2711     U32                                 PhyInfo;                    /* 0x14 */
 2712     U32                                 AttachedDeviceInfo;         /* 0x18 */
 2713     U16                                 ExpanderDevHandle;          /* 0x1C */
 2714     U8                                  ChangeCount;                /* 0x1E */
 2715     U8                                  NegotiatedLinkRate;         /* 0x1F */
 2716     U8                                  PhyIdentifier;              /* 0x20 */
 2717     U8                                  AttachedPhyIdentifier;      /* 0x21 */
 2718     U8                                  Reserved3;                  /* 0x22 */
 2719     U8                                  DiscoveryInfo;              /* 0x23 */
 2720     U32                                 AttachedPhyInfo;            /* 0x24 */
 2721     U8                                  ZoneGroup;                  /* 0x28 */
 2722     U8                                  SelfConfigStatus;           /* 0x29 */
 2723     U16                                 Reserved4;                  /* 0x2A */
 2724 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
 2725   Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
 2726 
 2727 #define MPI2_SASEXPANDER1_PAGEVERSION       (0x02)
 2728 
 2729 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
 2730 
 2731 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
 2732 
 2733 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
 2734 
 2735 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
 2736 
 2737 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
 2738 
 2739 /* values for SAS Expander Page 1 DiscoveryInfo field */
 2740 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED    (0x04)
 2741 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE  (0x02)
 2742 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES  (0x01)
 2743 
 2744 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
 2745 
 2746 
 2747 /****************************************************************************
 2748 *   SAS Device Config Pages
 2749 ****************************************************************************/
 2750 
 2751 /* SAS Device Page 0 */
 2752 
 2753 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
 2754 {
 2755     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
 2756     U16                                 Slot;                   /* 0x08 */
 2757     U16                                 EnclosureHandle;        /* 0x0A */
 2758     U64                                 SASAddress;             /* 0x0C */
 2759     U16                                 ParentDevHandle;        /* 0x14 */
 2760     U8                                  PhyNum;                 /* 0x16 */
 2761     U8                                  AccessStatus;           /* 0x17 */
 2762     U16                                 DevHandle;              /* 0x18 */
 2763     U8                                  AttachedPhyIdentifier;  /* 0x1A */
 2764     U8                                  ZoneGroup;              /* 0x1B */
 2765     U32                                 DeviceInfo;             /* 0x1C */
 2766     U16                                 Flags;                  /* 0x20 */
 2767     U8                                  PhysicalPort;           /* 0x22 */
 2768     U8                                  MaxPortConnections;     /* 0x23 */
 2769     U64                                 DeviceName;             /* 0x24 */
 2770     U8                                  PortGroups;             /* 0x2C */
 2771     U8                                  DmaGroup;               /* 0x2D */
 2772     U8                                  ControlGroup;           /* 0x2E */
 2773     U8                                  EnclosureLevel;         /* 0x2F */
 2774     U8                                  ConnectorName[4];       /* 0x30 */
 2775     U32                                 Reserved3;              /* 0x34 */
 2776 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
 2777   Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
 2778 
 2779 #define MPI2_SASDEVICE0_PAGEVERSION         (0x09)
 2780 
 2781 /* values for SAS Device Page 0 AccessStatus field */
 2782 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS                  (0x00)
 2783 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED           (0x01)
 2784 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED     (0x02)
 2785 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT  (0x03)
 2786 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION  (0x04)
 2787 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE      (0x05)
 2788 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE  (0x06)
 2789 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED             (0x07)
 2790 /* specific values for SATA Init failures */
 2791 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN                (0x10)
 2792 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT   (0x11)
 2793 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG                   (0x12)
 2794 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION         (0x13)
 2795 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER            (0x14)
 2796 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN                 (0x15)
 2797 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN                (0x16)
 2798 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN                (0x17)
 2799 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION       (0x18)
 2800 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE        (0x19)
 2801 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX                    (0x1F)
 2802 
 2803 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
 2804 
 2805 /* values for SAS Device Page 0 Flags field */
 2806 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE          (0x8000)
 2807 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH           (0x4000)
 2808 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE           (0x2000)
 2809 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE           (0x1000)
 2810 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE           (0x0800)
 2811 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY     (0x0400)
 2812 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE             (0x0200)
 2813 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE           (0x0100)
 2814 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED     (0x0080)
 2815 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED         (0x0040)
 2816 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED           (0x0020)
 2817 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED           (0x0010)
 2818 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH         (0x0008)
 2819 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE              (0x0004)
 2820 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID             (0x0002)
 2821 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT               (0x0001)
 2822 
 2823 /* SAS Device Page 1 */
 2824 
 2825 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
 2826 {
 2827     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
 2828     U32                                 Reserved1;              /* 0x08 */
 2829     U64                                 SASAddress;             /* 0x0C */
 2830     U32                                 Reserved2;              /* 0x14 */
 2831     U16                                 DevHandle;              /* 0x18 */
 2832     U16                                 Reserved3;              /* 0x1A */
 2833     U8                                  InitialRegDeviceFIS[20];/* 0x1C */
 2834 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
 2835   Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
 2836 
 2837 #define MPI2_SASDEVICE1_PAGEVERSION         (0x01)
 2838 
 2839 
 2840 /****************************************************************************
 2841 *   SAS PHY Config Pages
 2842 ****************************************************************************/
 2843 
 2844 /* SAS PHY Page 0 */
 2845 
 2846 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
 2847 {
 2848     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
 2849     U16                                 OwnerDevHandle;         /* 0x08 */
 2850     U16                                 Reserved1;              /* 0x0A */
 2851     U16                                 AttachedDevHandle;      /* 0x0C */
 2852     U8                                  AttachedPhyIdentifier;  /* 0x0E */
 2853     U8                                  Reserved2;              /* 0x0F */
 2854     U32                                 AttachedPhyInfo;        /* 0x10 */
 2855     U8                                  ProgrammedLinkRate;     /* 0x14 */
 2856     U8                                  HwLinkRate;             /* 0x15 */
 2857     U8                                  ChangeCount;            /* 0x16 */
 2858     U8                                  Flags;                  /* 0x17 */
 2859     U32                                 PhyInfo;                /* 0x18 */
 2860     U8                                  NegotiatedLinkRate;     /* 0x1C */
 2861     U8                                  Reserved3;              /* 0x1D */
 2862     U16                                 Reserved4;              /* 0x1E */
 2863 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
 2864   Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
 2865 
 2866 #define MPI2_SASPHY0_PAGEVERSION            (0x03)
 2867 
 2868 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
 2869 
 2870 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
 2871 
 2872 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
 2873 
 2874 /* values for SAS PHY Page 0 Flags field */
 2875 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC             (0x01)
 2876 
 2877 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
 2878 
 2879 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
 2880 
 2881 
 2882 /* SAS PHY Page 1 */
 2883 
 2884 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
 2885 {
 2886     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 2887     U32                                 Reserved1;                  /* 0x08 */
 2888     U32                                 InvalidDwordCount;          /* 0x0C */
 2889     U32                                 RunningDisparityErrorCount; /* 0x10 */
 2890     U32                                 LossDwordSynchCount;        /* 0x14 */
 2891     U32                                 PhyResetProblemCount;       /* 0x18 */
 2892 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
 2893   Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
 2894 
 2895 #define MPI2_SASPHY1_PAGEVERSION            (0x01)
 2896 
 2897 
 2898 /* SAS PHY Page 2 */
 2899 
 2900 typedef struct _MPI2_SASPHY2_PHY_EVENT
 2901 {
 2902     U8          PhyEventCode;       /* 0x00 */
 2903     U8          Reserved1;          /* 0x01 */
 2904     U16         Reserved2;          /* 0x02 */
 2905     U32         PhyEventInfo;       /* 0x04 */
 2906 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
 2907   Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
 2908 
 2909 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
 2910 
 2911 
 2912 /*
 2913  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 2914  * one and check the value returned for NumPhyEvents at runtime.
 2915  */
 2916 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
 2917 #define MPI2_SASPHY2_PHY_EVENT_MAX      (1)
 2918 #endif
 2919 
 2920 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2
 2921 {
 2922     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 2923     U32                                 Reserved1;                  /* 0x08 */
 2924     U8                                  NumPhyEvents;               /* 0x0C */
 2925     U8                                  Reserved2;                  /* 0x0D */
 2926     U16                                 Reserved3;                  /* 0x0E */
 2927     MPI2_SASPHY2_PHY_EVENT              PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */
 2928 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
 2929   Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
 2930 
 2931 #define MPI2_SASPHY2_PAGEVERSION            (0x00)
 2932 
 2933 
 2934 /* SAS PHY Page 3 */
 2935 
 2936 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG
 2937 {
 2938     U8          PhyEventCode;       /* 0x00 */
 2939     U8          Reserved1;          /* 0x01 */
 2940     U16         Reserved2;          /* 0x02 */
 2941     U8          CounterType;        /* 0x04 */
 2942     U8          ThresholdWindow;    /* 0x05 */
 2943     U8          TimeUnits;          /* 0x06 */
 2944     U8          Reserved3;          /* 0x07 */
 2945     U32         EventThreshold;     /* 0x08 */
 2946     U16         ThresholdFlags;     /* 0x0C */
 2947     U16         Reserved4;          /* 0x0E */
 2948 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
 2949   Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
 2950 
 2951 /* values for PhyEventCode field */
 2952 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT                    (0x00)
 2953 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD               (0x01)
 2954 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR     (0x02)
 2955 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC             (0x03)
 2956 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM           (0x04)
 2957 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW     (0x05)
 2958 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR                    (0x06)
 2959 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR         (0x20)
 2960 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT           (0x21)
 2961 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT           (0x22)
 2962 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT           (0x23)
 2963 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT           (0x24)
 2964 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON   (0x25)
 2965 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON   (0x26)
 2966 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK                    (0x27)
 2967 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK                    (0x28)
 2968 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT               (0x29)
 2969 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION                  (0x2A)
 2970 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED      (0x2B)
 2971 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME        (0x2C)
 2972 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME          (0x2D)
 2973 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME           (0x2E)
 2974 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES               (0x40)
 2975 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES               (0x41)
 2976 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES         (0x42)
 2977 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES         (0x43)
 2978 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED           (0x44)
 2979 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED           (0x45)
 2980 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES              (0x50)
 2981 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES              (0x51)
 2982 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW               (0x52)
 2983 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES               (0x60)
 2984 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES               (0x61)
 2985 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES         (0x63)
 2986 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT             (0xD0)
 2987 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE    (0xD1)
 2988 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP                      (0xD2)
 2989 /* Following codes are product specific and in MPI v2.6 and later */
 2990 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME             (0xD3)
 2991 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME    (0xD4)
 2992 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME                 (0xD5)
 2993 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT       (0xD6)
 2994 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START               (0xD7)
 2995 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT        (0xD8)
 2996 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN           (0xD9)
 2997 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE        (0xDA)
 2998 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE       (0xDB)
 2999 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE        (0xDC)
 3000 
 3001 /* values for the CounterType field */
 3002 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING                  (0x00)
 3003 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING                (0x01)
 3004 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE                (0x02)
 3005 
 3006 /* values for the TimeUnits field */
 3007 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS             (0x00)
 3008 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS            (0x01)
 3009 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND               (0x02)
 3010 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS             (0x03)
 3011 
 3012 /* values for the ThresholdFlags field */
 3013 #define MPI2_SASPHY3_TFLAGS_PHY_RESET                       (0x0002)
 3014 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY                    (0x0001)
 3015 
 3016 /*
 3017  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 3018  * one and check the value returned for NumPhyEvents at runtime.
 3019  */
 3020 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
 3021 #define MPI2_SASPHY3_PHY_EVENT_MAX      (1)
 3022 #endif
 3023 
 3024 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3
 3025 {
 3026     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3027     U32                                 Reserved1;                  /* 0x08 */
 3028     U8                                  NumPhyEvents;               /* 0x0C */
 3029     U8                                  Reserved2;                  /* 0x0D */
 3030     U16                                 Reserved3;                  /* 0x0E */
 3031     MPI2_SASPHY3_PHY_EVENT_CONFIG       PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
 3032 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
 3033   Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
 3034 
 3035 #define MPI2_SASPHY3_PAGEVERSION            (0x00)
 3036 
 3037 
 3038 /* SAS PHY Page 4 */
 3039 
 3040 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4
 3041 {
 3042     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3043     U16                                 Reserved1;                  /* 0x08 */
 3044     U8                                  Reserved2;                  /* 0x0A */
 3045     U8                                  Flags;                      /* 0x0B */
 3046     U8                                  InitialFrame[28];           /* 0x0C */
 3047 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
 3048   Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
 3049 
 3050 #define MPI2_SASPHY4_PAGEVERSION            (0x00)
 3051 
 3052 /* values for the Flags field */
 3053 #define MPI2_SASPHY4_FLAGS_FRAME_VALID        (0x02)
 3054 #define MPI2_SASPHY4_FLAGS_SATA_FRAME         (0x01)
 3055 
 3056 
 3057 
 3058 
 3059 /****************************************************************************
 3060 *   SAS Port Config Pages
 3061 ****************************************************************************/
 3062 
 3063 /* SAS Port Page 0 */
 3064 
 3065 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
 3066 {
 3067     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3068     U8                                  PortNumber;                 /* 0x08 */
 3069     U8                                  PhysicalPort;               /* 0x09 */
 3070     U8                                  PortWidth;                  /* 0x0A */
 3071     U8                                  PhysicalPortWidth;          /* 0x0B */
 3072     U8                                  ZoneGroup;                  /* 0x0C */
 3073     U8                                  Reserved1;                  /* 0x0D */
 3074     U16                                 Reserved2;                  /* 0x0E */
 3075     U64                                 SASAddress;                 /* 0x10 */
 3076     U32                                 DeviceInfo;                 /* 0x18 */
 3077     U32                                 Reserved3;                  /* 0x1C */
 3078     U32                                 Reserved4;                  /* 0x20 */
 3079 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
 3080   Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
 3081 
 3082 #define MPI2_SASPORT0_PAGEVERSION           (0x00)
 3083 
 3084 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
 3085 
 3086 
 3087 /****************************************************************************
 3088 *   SAS Enclosure Config Pages
 3089 ****************************************************************************/
 3090 
 3091 /* SAS Enclosure Page 0, Enclosure Page 0 */
 3092 
 3093 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
 3094 {
 3095     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3096     U32                                 Reserved1;                  /* 0x08 */
 3097     U64                                 EnclosureLogicalID;         /* 0x0C */
 3098     U16                                 Flags;                      /* 0x14 */
 3099     U16                                 EnclosureHandle;            /* 0x16 */
 3100     U16                                 NumSlots;                   /* 0x18 */
 3101     U16                                 StartSlot;                  /* 0x1A */
 3102     U8                                  ChassisSlot;                /* 0x1C */
 3103     U8                                  EnclosureLevel;             /* 0x1D */
 3104     U16                                 SEPDevHandle;               /* 0x1E */
 3105     U32                                 Reserved2;                  /* 0x20 */
 3106     U32                                 Reserved3;                  /* 0x24 */
 3107 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
 3108   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
 3109   Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t,
 3110   MPI26_CONFIG_PAGE_ENCLOSURE_0,
 3111   MPI2_POINTER PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0,
 3112   Mpi26EnclosurePage0_t, MPI2_POINTER pMpi26EnclosurePage0_t;
 3113 
 3114 #define MPI2_SASENCLOSURE0_PAGEVERSION      (0x04)
 3115 
 3116 /* values for SAS Enclosure Page 0 Flags field */
 3117 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID    (0x0020)
 3118 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID      (0x0010)
 3119 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK              (0x000F)
 3120 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN           (0x0000)
 3121 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES           (0x0001)
 3122 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO         (0x0002)
 3123 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO         (0x0003)
 3124 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE     (0x0004)
 3125 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO          (0x0005)
 3126 
 3127 #define MPI26_ENCLOSURE0_PAGEVERSION        (0x04)
 3128 
 3129 /* Values for Enclosure Page 0 Flags field */
 3130 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID       (0x0020)
 3131 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID         (0x0010)
 3132 #define MPI26_ENCLS0_FLAGS_MNG_MASK                 (0x000F)
 3133 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN              (0x0000)
 3134 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES              (0x0001)
 3135 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO            (0x0002)
 3136 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO            (0x0003)
 3137 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE        (0x0004)
 3138 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO             (0x0005)
 3139 
 3140 /****************************************************************************
 3141 *   Log Config Page
 3142 ****************************************************************************/
 3143 
 3144 /* Log Page 0 */
 3145 
 3146 /*
 3147  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 3148  * one and check the value returned for NumLogEntries at runtime.
 3149  */
 3150 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
 3151 #define MPI2_LOG_0_NUM_LOG_ENTRIES          (1)
 3152 #endif
 3153 
 3154 #define MPI2_LOG_0_LOG_DATA_LENGTH          (0x1C)
 3155 
 3156 typedef struct _MPI2_LOG_0_ENTRY
 3157 {
 3158     U64         TimeStamp;                          /* 0x00 */
 3159     U32         Reserved1;                          /* 0x08 */
 3160     U16         LogSequence;                        /* 0x0C */
 3161     U16         LogEntryQualifier;                  /* 0x0E */
 3162     U8          VP_ID;                              /* 0x10 */
 3163     U8          VF_ID;                              /* 0x11 */
 3164     U16         Reserved2;                          /* 0x12 */
 3165     U8          LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
 3166 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
 3167   Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
 3168 
 3169 /* values for Log Page 0 LogEntry LogEntryQualifier field */
 3170 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED          (0x0000)
 3171 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET        (0x0001)
 3172 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE      (0x0002)
 3173 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC    (0x8000)
 3174 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC    (0xFFFF)
 3175 
 3176 typedef struct _MPI2_CONFIG_PAGE_LOG_0
 3177 {
 3178     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3179     U32                                 Reserved1;                  /* 0x08 */
 3180     U32                                 Reserved2;                  /* 0x0C */
 3181     U16                                 NumLogEntries;              /* 0x10 */
 3182     U16                                 Reserved3;                  /* 0x12 */
 3183     MPI2_LOG_0_ENTRY                    LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
 3184 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
 3185   Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
 3186 
 3187 #define MPI2_LOG_0_PAGEVERSION              (0x02)
 3188 
 3189 
 3190 /****************************************************************************
 3191 *   RAID Config Page
 3192 ****************************************************************************/
 3193 
 3194 /* RAID Page 0 */
 3195 
 3196 /*
 3197  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 3198  * one and check the value returned for NumElements at runtime.
 3199  */
 3200 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
 3201 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS       (1)
 3202 #endif
 3203 
 3204 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
 3205 {
 3206     U16                     ElementFlags;               /* 0x00 */
 3207     U16                     VolDevHandle;               /* 0x02 */
 3208     U8                      HotSparePool;               /* 0x04 */
 3209     U8                      PhysDiskNum;                /* 0x05 */
 3210     U16                     PhysDiskDevHandle;          /* 0x06 */
 3211 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
 3212   MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
 3213   Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
 3214 
 3215 /* values for the ElementFlags field */
 3216 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE       (0x000F)
 3217 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT          (0x0000)
 3218 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT   (0x0001)
 3219 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT       (0x0002)
 3220 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT             (0x0003)
 3221 
 3222 
 3223 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
 3224 {
 3225     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3226     U8                                  NumHotSpares;               /* 0x08 */
 3227     U8                                  NumPhysDisks;               /* 0x09 */
 3228     U8                                  NumVolumes;                 /* 0x0A */
 3229     U8                                  ConfigNum;                  /* 0x0B */
 3230     U32                                 Flags;                      /* 0x0C */
 3231     U8                                  ConfigGUID[24];             /* 0x10 */
 3232     U32                                 Reserved1;                  /* 0x28 */
 3233     U8                                  NumElements;                /* 0x2C */
 3234     U8                                  Reserved2;                  /* 0x2D */
 3235     U16                                 Reserved3;                  /* 0x2E */
 3236     MPI2_RAIDCONFIG0_CONFIG_ELEMENT     ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
 3237 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
 3238   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
 3239   Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
 3240 
 3241 #define MPI2_RAIDCONFIG0_PAGEVERSION            (0x00)
 3242 
 3243 /* values for RAID Configuration Page 0 Flags field */
 3244 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG        (0x00000001)
 3245 
 3246 
 3247 /****************************************************************************
 3248 *   Driver Persistent Mapping Config Pages
 3249 ****************************************************************************/
 3250 
 3251 /* Driver Persistent Mapping Page 0 */
 3252 
 3253 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
 3254 {
 3255     U64                                 PhysicalIdentifier;         /* 0x00 */
 3256     U16                                 MappingInformation;         /* 0x08 */
 3257     U16                                 DeviceIndex;                /* 0x0A */
 3258     U32                                 PhysicalBitsMapping;        /* 0x0C */
 3259     U32                                 Reserved1;                  /* 0x10 */
 3260 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
 3261   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
 3262   Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
 3263 
 3264 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
 3265 {
 3266     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3267     MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY  Entry;                      /* 0x08 */
 3268 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
 3269   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
 3270   Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
 3271 
 3272 #define MPI2_DRIVERMAPPING0_PAGEVERSION         (0x00)
 3273 
 3274 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
 3275 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK              (0x07F0)
 3276 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT             (4)
 3277 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK           (0x000F)
 3278 
 3279 
 3280 /****************************************************************************
 3281 *   Ethernet Config Pages
 3282 ****************************************************************************/
 3283 
 3284 /* Ethernet Page 0 */
 3285 
 3286 /* IP address (union of IPv4 and IPv6) */
 3287 typedef union _MPI2_ETHERNET_IP_ADDR
 3288 {
 3289     U32     IPv4Addr;
 3290     U32     IPv6Addr[4];
 3291 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
 3292   Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
 3293 
 3294 #define MPI2_ETHERNET_HOST_NAME_LENGTH          (32)
 3295 
 3296 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0
 3297 {
 3298     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
 3299     U8                                  NumInterfaces;          /* 0x08 */
 3300     U8                                  Reserved0;              /* 0x09 */
 3301     U16                                 Reserved1;              /* 0x0A */
 3302     U32                                 Status;                 /* 0x0C */
 3303     U8                                  MediaState;             /* 0x10 */
 3304     U8                                  Reserved2;              /* 0x11 */
 3305     U16                                 Reserved3;              /* 0x12 */
 3306     U8                                  MacAddress[6];          /* 0x14 */
 3307     U8                                  Reserved4;              /* 0x1A */
 3308     U8                                  Reserved5;              /* 0x1B */
 3309     MPI2_ETHERNET_IP_ADDR               IpAddress;              /* 0x1C */
 3310     MPI2_ETHERNET_IP_ADDR               SubnetMask;             /* 0x2C */
 3311     MPI2_ETHERNET_IP_ADDR               GatewayIpAddress;       /* 0x3C */
 3312     MPI2_ETHERNET_IP_ADDR               DNS1IpAddress;          /* 0x4C */
 3313     MPI2_ETHERNET_IP_ADDR               DNS2IpAddress;          /* 0x5C */
 3314     MPI2_ETHERNET_IP_ADDR               DhcpIpAddress;          /* 0x6C */
 3315     U8                                  HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
 3316 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
 3317   Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
 3318 
 3319 #define MPI2_ETHERNETPAGE0_PAGEVERSION   (0x00)
 3320 
 3321 /* values for Ethernet Page 0 Status field */
 3322 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE             (0x80000000)
 3323 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE             (0x40000000)
 3324 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED        (0x20000000)
 3325 #define MPI2_ETHPG0_STATUS_DEFAULT_IF               (0x00000100)
 3326 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED         (0x00000080)
 3327 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED           (0x00000040)
 3328 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED             (0x00000020)
 3329 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED      (0x00000010)
 3330 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED             (0x00000008)
 3331 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED             (0x00000004)
 3332 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES           (0x00000002)
 3333 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED           (0x00000001)
 3334 
 3335 /* values for Ethernet Page 0 MediaState field */
 3336 #define MPI2_ETHPG0_MS_DUPLEX_MASK                  (0x80)
 3337 #define MPI2_ETHPG0_MS_HALF_DUPLEX                  (0x00)
 3338 #define MPI2_ETHPG0_MS_FULL_DUPLEX                  (0x80)
 3339 
 3340 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK           (0x07)
 3341 #define MPI2_ETHPG0_MS_NOT_CONNECTED                (0x00)
 3342 #define MPI2_ETHPG0_MS_10MBIT                       (0x01)
 3343 #define MPI2_ETHPG0_MS_100MBIT                      (0x02)
 3344 #define MPI2_ETHPG0_MS_1GBIT                        (0x03)
 3345 
 3346 
 3347 /* Ethernet Page 1 */
 3348 
 3349 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1
 3350 {
 3351     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
 3352     U32                                 Reserved0;              /* 0x08 */
 3353     U32                                 Flags;                  /* 0x0C */
 3354     U8                                  MediaState;             /* 0x10 */
 3355     U8                                  Reserved1;              /* 0x11 */
 3356     U16                                 Reserved2;              /* 0x12 */
 3357     U8                                  MacAddress[6];          /* 0x14 */
 3358     U8                                  Reserved3;              /* 0x1A */
 3359     U8                                  Reserved4;              /* 0x1B */
 3360     MPI2_ETHERNET_IP_ADDR               StaticIpAddress;        /* 0x1C */
 3361     MPI2_ETHERNET_IP_ADDR               StaticSubnetMask;       /* 0x2C */
 3362     MPI2_ETHERNET_IP_ADDR               StaticGatewayIpAddress; /* 0x3C */
 3363     MPI2_ETHERNET_IP_ADDR               StaticDNS1IpAddress;    /* 0x4C */
 3364     MPI2_ETHERNET_IP_ADDR               StaticDNS2IpAddress;    /* 0x5C */
 3365     U32                                 Reserved5;              /* 0x6C */
 3366     U32                                 Reserved6;              /* 0x70 */
 3367     U32                                 Reserved7;              /* 0x74 */
 3368     U32                                 Reserved8;              /* 0x78 */
 3369     U8                                  HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
 3370 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
 3371   Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
 3372 
 3373 #define MPI2_ETHERNETPAGE1_PAGEVERSION   (0x00)
 3374 
 3375 /* values for Ethernet Page 1 Flags field */
 3376 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF             (0x00000100)
 3377 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD         (0x00000080)
 3378 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET              (0x00000040)
 3379 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2                (0x00000020)
 3380 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT         (0x00000010)
 3381 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6                (0x00000008)
 3382 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4                (0x00000004)
 3383 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES         (0x00000002)
 3384 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF              (0x00000001)
 3385 
 3386 /* values for Ethernet Page 1 MediaState field */
 3387 #define MPI2_ETHPG1_MS_DUPLEX_MASK                  (0x80)
 3388 #define MPI2_ETHPG1_MS_HALF_DUPLEX                  (0x00)
 3389 #define MPI2_ETHPG1_MS_FULL_DUPLEX                  (0x80)
 3390 
 3391 #define MPI2_ETHPG1_MS_DATA_RATE_MASK               (0x07)
 3392 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO               (0x00)
 3393 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT             (0x01)
 3394 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT            (0x02)
 3395 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT              (0x03)
 3396 
 3397 
 3398 /****************************************************************************
 3399 *   Extended Manufacturing Config Pages
 3400 ****************************************************************************/
 3401 
 3402 /*
 3403  * Generic structure to use for product-specific extended manufacturing pages
 3404  * (currently Extended Manufacturing Page 40 through Extended Manufacturing
 3405  * Page 60).
 3406  */
 3407 
 3408 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS
 3409 {
 3410     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
 3411     U32                                 ProductSpecificInfo;    /* 0x08 */
 3412 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
 3413   MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
 3414   Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
 3415 
 3416 /* PageVersion should be provided by product-specific code */
 3417 
 3418 
 3419 /****************************************************************************
 3420 *   values for fields used by several types of PCIe Config Pages
 3421 ****************************************************************************/
 3422 
 3423 /* values for NegotiatedLinkRates fields */
 3424 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL          (0x0F)
 3425 /* link rates used for Negotiated Physical Link Rate */
 3426 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN                (0x00)
 3427 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED           (0x01)
 3428 #define MPI26_PCIE_NEG_LINK_RATE_2_5                    (0x02)
 3429 #define MPI26_PCIE_NEG_LINK_RATE_5_0                    (0x03)
 3430 #define MPI26_PCIE_NEG_LINK_RATE_8_0                    (0x04)
 3431 #define MPI26_PCIE_NEG_LINK_RATE_16_0                   (0x05)
 3432 
 3433 
 3434 /****************************************************************************
 3435 *   PCIe IO Unit Config Pages (MPI v2.6 and later)
 3436 ****************************************************************************/
 3437 
 3438 /* PCIe IO Unit Page 0 */
 3439 
 3440 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA
 3441 {
 3442     U8          Link;                   /* 0x00 */
 3443     U8          LinkFlags;              /* 0x01 */
 3444     U8          PhyFlags;               /* 0x02 */
 3445     U8          NegotiatedLinkRate;     /* 0x03 */
 3446     U32         ControllerPhyDeviceInfo;/* 0x04 */
 3447     U16         AttachedDevHandle;      /* 0x08 */
 3448     U16         ControllerDevHandle;    /* 0x0A */
 3449     U32         EnumerationStatus;      /* 0x0C */
 3450     U32         Reserved1;              /* 0x10 */
 3451 } MPI26_PCIE_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA,
 3452   Mpi26PCIeIOUnit0PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit0PhyData_t;
 3453 
 3454 /*
 3455  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 3456  * one and check the value returned for NumPhys at runtime.
 3457  */
 3458 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX
 3459 #define MPI26_PCIE_IOUNIT0_PHY_MAX      (1)
 3460 #endif
 3461 
 3462 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0
 3463 {
 3464     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                                 /* 0x00 */
 3465     U32                                 Reserved1;                              /* 0x08 */
 3466     U8                                  NumPhys;                                /* 0x0C */
 3467     U8                                  InitStatus;                             /* 0x0D */
 3468     U16                                 Reserved3;                              /* 0x0E */
 3469     MPI26_PCIE_IO_UNIT0_PHY_DATA        PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX];    /* 0x10 */
 3470 } MPI26_CONFIG_PAGE_PIOUNIT_0,
 3471   MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_0,
 3472   Mpi26PCIeIOUnitPage0_t, MPI2_POINTER pMpi26PCIeIOUnitPage0_t;
 3473 
 3474 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION                   (0x00)
 3475 
 3476 /* values for PCIe IO Unit Page 0 LinkFlags */
 3477 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08)
 3478 
 3479 /* values for PCIe IO Unit Page 0 PhyFlags */
 3480 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED             (0x08)
 3481 
 3482 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
 3483 
 3484 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */
 3485 
 3486 /* values for PCIe IO Unit Page 0 EnumerationStatus */
 3487 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED          (0x40000000)
 3488 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED           (0x20000000)
 3489 
 3490 
 3491 /* PCIe IO Unit Page 1 */
 3492 
 3493 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA
 3494 {
 3495     U8          Link;                       /* 0x00 */
 3496     U8          LinkFlags;                  /* 0x01 */
 3497     U8          PhyFlags;                   /* 0x02 */
 3498     U8          MaxMinLinkRate;             /* 0x03 */
 3499     U32         ControllerPhyDeviceInfo;    /* 0x04 */
 3500     U32         Reserved1;                  /* 0x08 */
 3501 } MPI26_PCIE_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA,
 3502   Mpi26PCIeIOUnit1PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit1PhyData_t;
 3503 
 3504 /* values for LinkFlags */
 3505 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS    (0x00)
 3506 #define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS     (0x01)
 3507 
 3508 /*
 3509  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 3510  * one and check the value returned for NumPhys at runtime.
 3511  */
 3512 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX
 3513 #define MPI26_PCIE_IOUNIT1_PHY_MAX      (1)
 3514 #endif
 3515 
 3516 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1
 3517 {
 3518     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                             /* 0x00 */
 3519     U16                                 ControlFlags;                       /* 0x08 */
 3520     U16                                 Reserved;                           /* 0x0A */
 3521     U16                                 AdditionalControlFlags;             /* 0x0C */
 3522     U16                                 NVMeMaxQueueDepth;                  /* 0x0E */
 3523     U8                                  NumPhys;                            /* 0x10 */
 3524     U8                                  Reserved1;                          /* 0x11 */
 3525     U16                                 Reserved2;                          /* 0x12 */
 3526     MPI26_PCIE_IO_UNIT1_PHY_DATA        PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/* 0x14 */
 3527 } MPI26_CONFIG_PAGE_PIOUNIT_1,
 3528   MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_1,
 3529   Mpi26PCIeIOUnitPage1_t, MPI2_POINTER pMpi26PCIeIOUnitPage1_t;
 3530 
 3531 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION   (0x00)
 3532 
 3533 /* values for PCIe IO Unit Page 1 PhyFlags */
 3534 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE                      (0x08)
 3535 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY                    (0x01)
 3536 
 3537 /* values for PCIe IO Unit Page 1 MaxMinLinkRate */
 3538 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK                             (0xF0)
 3539 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT                            (4)
 3540 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5                              (0x20)
 3541 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0                              (0x30)
 3542 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0                              (0x40)
 3543 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0                             (0x50)
 3544 
 3545 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */
 3546 
 3547 
 3548 /****************************************************************************
 3549 *   PCIe Switch Config Pages (MPI v2.6 and later)
 3550 ****************************************************************************/
 3551 
 3552 /* PCIe Switch Page 0 */
 3553 
 3554 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0
 3555 {
 3556     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3557     U8                                  PhysicalPort;               /* 0x08 */
 3558     U8                                  Reserved1;                  /* 0x09 */
 3559     U16                                 Reserved2;                  /* 0x0A */
 3560     U16                                 DevHandle;                  /* 0x0C */
 3561     U16                                 ParentDevHandle;            /* 0x0E */
 3562     U8                                  NumPorts;                   /* 0x10 */
 3563     U8                                  PCIeLevel;                  /* 0x11 */
 3564     U16                                 Reserved3;                  /* 0x12 */
 3565     U32                                 Reserved4;                  /* 0x14 */
 3566     U32                                 Reserved5;                  /* 0x18 */
 3567     U32                                 Reserved6;                  /* 0x1C */
 3568 } MPI26_CONFIG_PAGE_PSWITCH_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_0,
 3569   Mpi26PCIeSwitchPage0_t, MPI2_POINTER pMpi26PCIeSwitchPage0_t;
 3570 
 3571 #define MPI26_PCIESWITCH0_PAGEVERSION       (0x00)
 3572 
 3573 
 3574 /* PCIe Switch Page 1 */
 3575 
 3576 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1
 3577 {
 3578     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3579     U8                                  PhysicalPort;               /* 0x08 */
 3580     U8                                  Reserved1;                  /* 0x09 */
 3581     U16                                 Reserved2;                  /* 0x0A */
 3582     U8                                  NumPorts;                   /* 0x0C */
 3583     U8                                  PortNum;                    /* 0x0D */
 3584     U16                                 AttachedDevHandle;          /* 0x0E */
 3585     U16                                 SwitchDevHandle;            /* 0x10 */
 3586     U8                                  NegotiatedPortWidth;        /* 0x12 */
 3587     U8                                  NegotiatedLinkRate;         /* 0x13 */
 3588     U32                                 Reserved4;                  /* 0x14 */
 3589     U32                                 Reserved5;                  /* 0x18 */
 3590 } MPI26_CONFIG_PAGE_PSWITCH_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_1,
 3591   Mpi26PCIeSwitchPage1_t, MPI2_POINTER pMpi26PCIeSwitchPage1_t;
 3592 
 3593 #define MPI26_PCIESWITCH1_PAGEVERSION       (0x00)
 3594 
 3595 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
 3596 
 3597 
 3598 /****************************************************************************
 3599 *   PCIe Device Config Pages (MPI v2.6 and later)
 3600 ****************************************************************************/
 3601 
 3602 /* PCIe Device Page 0 */
 3603 
 3604 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0
 3605 {
 3606     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
 3607     U16                                 Slot;                   /* 0x08 */
 3608     U16                                 EnclosureHandle;        /* 0x0A */
 3609     U64                                 WWID;                   /* 0x0C */
 3610     U16                                 ParentDevHandle;        /* 0x14 */
 3611     U8                                  PortNum;                /* 0x16 */
 3612     U8                                  AccessStatus;           /* 0x17 */
 3613     U16                                 DevHandle;              /* 0x18 */
 3614     U8                                  PhysicalPort;           /* 0x1A */
 3615     U8                                  Reserved1;              /* 0x1B */
 3616     U32                                 DeviceInfo;             /* 0x1C */
 3617     U32                                 Flags;                  /* 0x20 */
 3618     U8                                  SupportedLinkRates;     /* 0x24 */
 3619     U8                                  MaxPortWidth;           /* 0x25 */
 3620     U8                                  NegotiatedPortWidth;    /* 0x26 */
 3621     U8                                  NegotiatedLinkRate;     /* 0x27 */
 3622     U8                                  EnclosureLevel;         /* 0x28 */
 3623     U8                                  Reserved2;              /* 0x29 */
 3624     U16                                 Reserved3;              /* 0x2A */
 3625     U8                                  ConnectorName[4];       /* 0x2C */
 3626     U32                                 Reserved4;              /* 0x30 */
 3627     U32                                 Reserved5;              /* 0x34 */
 3628 } MPI26_CONFIG_PAGE_PCIEDEV_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_0,
 3629   Mpi26PCIeDevicePage0_t, MPI2_POINTER pMpi26PCIeDevicePage0_t;
 3630 
 3631 #define MPI26_PCIEDEVICE0_PAGEVERSION       (0x01)
 3632 
 3633 /* values for PCIe Device Page 0 AccessStatus field */
 3634 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS                    (0x00)
 3635 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION         (0x04)
 3636 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED            (0x02)
 3637 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED               (0x07)
 3638 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED   (0x08)
 3639 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE           (0x09)
 3640 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED                (0x0A)
 3641 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN                      (0x10)
 3642 
 3643 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT           (0x30)
 3644 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED      (0x31)
 3645 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED         (0x32)
 3646 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED          (0x33)
 3647 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED        (0x34)
 3648 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED         (0x35)
 3649 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36)
 3650 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT            (0x37)
 3651 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS          (0x38)
 3652 
 3653 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX                (0x3F)
 3654 
 3655 /* see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo field */
 3656 
 3657 /* values for PCIe Device Page 0 Flags field */
 3658 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE            (0x8000)
 3659 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH              (0x4000)
 3660 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE              (0x2000)
 3661 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION      (0x0400)
 3662 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION            (0x0200)
 3663 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE             (0x0100)
 3664 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED        (0x0080)
 3665 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED            (0x0040)
 3666 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED              (0x0020)
 3667 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED              (0x0010)
 3668 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID               (0x0002)
 3669 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT                 (0x0001)
 3670 
 3671 /* values for PCIe Device Page 0 SupportedLinkRates field */
 3672 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED             (0x08)
 3673 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED              (0x04)
 3674 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED              (0x02)
 3675 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED              (0x01)
 3676 
 3677 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
 3678 
 3679 
 3680 /* PCIe Device Page 2 */
 3681 
 3682 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2
 3683 {
 3684     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                 /* 0x00 */
 3685     U16                                 DevHandle;              /* 0x08 */
 3686     U16                                 Reserved1;              /* 0x0A */
 3687     U32                                 MaximumDataTransferSize;/* 0x0C */
 3688     U32                                 Capabilities;           /* 0x10 */
 3689     U32                                 Reserved2;              /* 0x14 */
 3690 } MPI26_CONFIG_PAGE_PCIEDEV_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_2,
 3691   Mpi26PCIeDevicePage2_t, MPI2_POINTER pMpi26PCIeDevicePage2_t;
 3692 
 3693 #define MPI26_PCIEDEVICE2_PAGEVERSION       (0x00)
 3694 
 3695 /* defines for PCIe Device Page 2 Capabilities field */
 3696 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT                  (0x00000004)
 3697 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT          (0x00000002)
 3698 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT                 (0x00000001)
 3699 
 3700 
 3701 /****************************************************************************
 3702 *   PCIe Link Config Pages (MPI v2.6 and later)
 3703 ****************************************************************************/
 3704 
 3705 /* PCIe Link Page 1 */
 3706 
 3707 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1
 3708 {
 3709     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3710     U8                                  Link;                       /* 0x08 */
 3711     U8                                  Reserved1;                  /* 0x09 */
 3712     U16                                 Reserved2;                  /* 0x0A */
 3713     U32                                 CorrectableErrorCount;      /* 0x0C */
 3714     U16                                 NonFatalErrorCount;         /* 0x10 */
 3715     U16                                 Reserved3;                  /* 0x12 */
 3716     U16                                 FatalErrorCount;            /* 0x14 */
 3717     U16                                 Reserved4;                  /* 0x16 */
 3718 } MPI26_CONFIG_PAGE_PCIELINK_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_1,
 3719   Mpi26PcieLinkPage1_t, MPI2_POINTER pMpi26PcieLinkPage1_t;
 3720 
 3721 #define MPI26_PCIELINK1_PAGEVERSION            (0x00)
 3722 
 3723 /* PCIe Link Page 2 */
 3724 
 3725 typedef struct _MPI26_PCIELINK2_LINK_EVENT
 3726 {
 3727     U8          LinkEventCode;      /* 0x00 */
 3728     U8          Reserved1;          /* 0x01 */
 3729     U16         Reserved2;          /* 0x02 */
 3730     U32         LinkEventInfo;      /* 0x04 */
 3731 } MPI26_PCIELINK2_LINK_EVENT, MPI2_POINTER PTR_MPI26_PCIELINK2_LINK_EVENT,
 3732   Mpi26PcieLink2LinkEvent_t, MPI2_POINTER pMpi26PcieLink2LinkEvent_t;
 3733 
 3734 /* use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */
 3735 
 3736 
 3737 /*
 3738  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 3739  * one and check the value returned for NumLinkEvents at runtime.
 3740  */
 3741 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX
 3742 #define MPI26_PCIELINK2_LINK_EVENT_MAX      (1)
 3743 #endif
 3744 
 3745 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2
 3746 {
 3747     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3748     U8                                  Link;                       /* 0x08 */
 3749     U8                                  Reserved1;                  /* 0x09 */
 3750     U16                                 Reserved2;                  /* 0x0A */
 3751     U8                                  NumLinkEvents;              /* 0x0C */
 3752     U8                                  Reserved3;                  /* 0x0D */
 3753     U16                                 Reserved4;                  /* 0x0E */
 3754     MPI26_PCIELINK2_LINK_EVENT          LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /* 0x10 */
 3755 } MPI26_CONFIG_PAGE_PCIELINK_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_2,
 3756   Mpi26PcieLinkPage2_t, MPI2_POINTER pMpi26PcieLinkPage2_t;
 3757 
 3758 #define MPI26_PCIELINK2_PAGEVERSION            (0x00)
 3759 
 3760 
 3761 /* PCIe Link Page 3 */
 3762 
 3763 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG
 3764 {
 3765     U8          LinkEventCode;      /* 0x00 */
 3766     U8          Reserved1;          /* 0x01 */
 3767     U16         Reserved2;          /* 0x02 */
 3768     U8          CounterType;        /* 0x04 */
 3769     U8          ThresholdWindow;    /* 0x05 */
 3770     U8          TimeUnits;          /* 0x06 */
 3771     U8          Reserved3;          /* 0x07 */
 3772     U32         EventThreshold;     /* 0x08 */
 3773     U16         ThresholdFlags;     /* 0x0C */
 3774     U16         Reserved4;          /* 0x0E */
 3775 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, MPI2_POINTER PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG,
 3776   Mpi26PcieLink3LinkEventConfig_t, MPI2_POINTER pMpi26PcieLink3LinkEventConfig_t;
 3777 
 3778 /* values for LinkEventCode field */
 3779 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT                              (0x00)
 3780 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED            (0x01)
 3781 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED              (0x02)
 3782 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED                  (0x03)
 3783 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED              (0x04)
 3784 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED      (0x05)
 3785 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED               (0x06)
 3786 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP                          (0x07)
 3787 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP                     (0x08)
 3788 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP                         (0x09)
 3789 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE                  (0x0A)
 3790 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE                     (0x0B)
 3791 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE                     (0x0C)
 3792 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE                        (0x0D)
 3793 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE                  (0x0E)
 3794 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE                 (0x0F)
 3795 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR                          (0x10)
 3796 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR                          (0x11)
 3797 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR                       (0x12)
 3798 
 3799 /* values for the CounterType field */
 3800 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING               (0x00)
 3801 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING             (0x01)
 3802 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE             (0x02)
 3803 
 3804 /* values for the TimeUnits field */
 3805 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS            (0x00)
 3806 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS           (0x01)
 3807 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND              (0x02)
 3808 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS            (0x03)
 3809 
 3810 /* values for the ThresholdFlags field */
 3811 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY                 (0x0001)
 3812 
 3813 /*
 3814  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 3815  * one and check the value returned for NumLinkEvents at runtime.
 3816  */
 3817 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX
 3818 #define MPI26_PCIELINK3_LINK_EVENT_MAX      (1)
 3819 #endif
 3820 
 3821 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3
 3822 {
 3823     MPI2_CONFIG_EXTENDED_PAGE_HEADER    Header;                     /* 0x00 */
 3824     U8                                  Link;                       /* 0x08 */
 3825     U8                                  Reserved1;                  /* 0x09 */
 3826     U16                                 Reserved2;                  /* 0x0A */
 3827     U8                                  NumLinkEvents;              /* 0x0C */
 3828     U8                                  Reserved3;                  /* 0x0D */
 3829     U16                                 Reserved4;                  /* 0x0E */
 3830     MPI26_PCIELINK3_LINK_EVENT_CONFIG   LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /* 0x10 */
 3831 } MPI26_CONFIG_PAGE_PCIELINK_3, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_3,
 3832   Mpi26PcieLinkPage3_t, MPI2_POINTER pMpi26PcieLinkPage3_t;
 3833 
 3834 #define MPI26_PCIELINK3_PAGEVERSION            (0x00)
 3835 
 3836 
 3837 #endif
 3838 

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