mpi2_ioc.h

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    1 /*-
    2  *  Copyright 2000-2020 Broadcom Inc. All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  * 3. Neither the name of the author nor the names of any co-contributors
   13  *    may be used to endorse or promote products derived from this software
   14  *    without specific prior written permission.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD
   29  *
   30  * $FreeBSD$
   31  */
   32 
   33 /*
   34  *  Copyright 2000-2020 Broadcom Inc. All rights reserved.
   35  *
   36  *
   37  *           Name:  mpi2_ioc.h
   38  *          Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
   39  *  Creation Date:  October 11, 2006
   40  *
   41  *  mpi2_ioc.h Version:  02.00.36
   42  *
   43  *  NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
   44  *        prefix are for use only on MPI v2.5 products, and must not be used
   45  *        with MPI v2.0 products. Unless otherwise noted, names beginning with
   46  *        MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
   47  *
   48  *  Version History
   49  *  ---------------
   50  *
   51  *  Date      Version   Description
   52  *  --------  --------  ------------------------------------------------------
   53  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
   54  *  06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
   55  *                      MaxTargets.
   56  *                      Added TotalImageSize field to FWDownload Request.
   57  *                      Added reserved words to FWUpload Request.
   58  *  06-26-07  02.00.02  Added IR Configuration Change List Event.
   59  *  08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
   60  *                      request and replaced it with
   61  *                      ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
   62  *                      Replaced the MinReplyQueueDepth field of the IOCFacts
   63  *                      reply with MaxReplyDescriptorPostQueueDepth.
   64  *                      Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
   65  *                      depth for the Reply Descriptor Post Queue.
   66  *                      Added SASAddress field to Initiator Device Table
   67  *                      Overflow Event data.
   68  *  10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
   69  *                      for SAS Initiator Device Status Change Event data.
   70  *                      Modified Reason Code defines for SAS Topology Change
   71  *                      List Event data, including adding a bit for PHY Vacant
   72  *                      status, and adding a mask for the Reason Code.
   73  *                      Added define for
   74  *                      MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
   75  *                      Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
   76  *  12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
   77  *                      the IOCFacts Reply.
   78  *                      Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
   79  *                      Moved MPI2_VERSION_UNION to mpi2.h.
   80  *                      Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
   81  *                      instead of enables, and added SASBroadcastPrimitiveMasks
   82  *                      field.
   83  *                      Added Log Entry Added Event and related structure.
   84  *  02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
   85  *                      Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
   86  *                      Added MaxVolumes and MaxPersistentEntries fields to
   87  *                      IOCFacts reply.
   88  *                      Added ProtocalFlags and IOCCapabilities fields to
   89  *                      MPI2_FW_IMAGE_HEADER.
   90  *                      Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
   91  *  03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
   92  *                      a U16 (from a U32).
   93  *                      Removed extra 's' from EventMasks name.
   94  *  06-27-08  02.00.08  Fixed an offset in a comment.
   95  *  10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
   96  *                      Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
   97  *                      renamed MinReplyFrameSize to ReplyFrameSize.
   98  *                      Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
   99  *                      Added two new RAIDOperation values for Integrated RAID
  100  *                      Operations Status Event data.
  101  *                      Added four new IR Configuration Change List Event data
  102  *                      ReasonCode values.
  103  *                      Added two new ReasonCode defines for SAS Device Status
  104  *                      Change Event data.
  105  *                      Added three new DiscoveryStatus bits for the SAS
  106  *                      Discovery event data.
  107  *                      Added Multiplexing Status Change bit to the PhyStatus
  108  *                      field of the SAS Topology Change List event data.
  109  *                      Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  110  *                      BootFlags are now product-specific.
  111  *                      Added defines for the indivdual signature bytes
  112  *                      for MPI2_INIT_IMAGE_FOOTER.
  113  *  01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  114  *                      Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  115  *                      define.
  116  *                      Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  117  *                      define.
  118  *                      Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  119  *  05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  120  *                      Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  121  *                      Added two new reason codes for SAS Device Status Change
  122  *                      Event.
  123  *                      Added new event: SAS PHY Counter.
  124  *  07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
  125  *                      Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  126  *                      Added new product id family for 2208.
  127  *  10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  128  *                      Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  129  *                      Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  130  *                      Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  131  *                      Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
  132  *                      Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
  133  *                      Added Host Based Discovery Phy Event data.
  134  *                      Added defines for ProductID Product field
  135  *                      (MPI2_FW_HEADER_PID_).
  136  *                      Modified values for SAS ProductID Family
  137  *                      (MPI2_FW_HEADER_PID_FAMILY_).
  138  *  02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
  139  *                      Added PowerManagementControl Request structures and
  140  *                      defines.
  141  *  05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
  142  *                      Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
  143  *  11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
  144  *  02-23-11  02.00.17  Added SAS NOTIFY Primitive event, and added
  145  *                      SASNotifyPrimitiveMasks field to
  146  *                      MPI2_EVENT_NOTIFICATION_REQUEST.
  147  *                      Added Temperature Threshold Event.
  148  *                      Added Host Message Event.
  149  *                      Added Send Host Message request and reply.
  150  *  05-25-11  02.00.18  For Extended Image Header, added
  151  *                      MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
  152  *                      MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
  153  *                      Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
  154  *  08-24-11  02.00.19  Added PhysicalPort field to
  155  *                      MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
  156  *                      Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
  157  *  11-18-11  02.00.20  Incorporating additions for MPI v2.5.
  158  *  03-29-12  02.00.21  Added a product specific range to event values.
  159  *  07-26-12  02.00.22  Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
  160  *                      Added ElapsedSeconds field to
  161  *                      MPI2_EVENT_DATA_IR_OPERATION_STATUS.
  162  *  08-19-13  02.00.23  For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
  163  *                      and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
  164  *                      Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
  165  *                      Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
  166  *                      Added Encrypted Hash Extended Image.
  167  *  12-05-13  02.00.24  Added MPI25_HASH_IMAGE_TYPE_BIOS.
  168  *  11-18-14  02.00.25  Updated copyright information.
  169  *  03-16-15  02.00.26  Updated for MPI v2.6.
  170  *                      Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
  171  *                      MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
  172  *                      Added MPI2_EVENT_PCIE_LINK_COUNTER and
  173  *                      MPI26_EVENT_DATA_PCIE_LINK_COUNTER.
  174  *                      Added MPI26_CTRL_OP_SHUTDOWN.
  175  *                      Added MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG
  176  *                      Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
  177  *                      MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
  178  *  08-25-15  02.00.27  Added IC ARCH Class based signature defines.
  179  *                      Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event.
  180  *                      Added ConigurationFlags field to IOCInit message to
  181  *                      support NVMe SGL format control.
  182  *                      Added PCIe SRIOV support.
  183  * 02-17-16   02.00.28  Added SAS 4 22.5 gbs speed support.
  184  *                      Added PCIe 4 16.0 GT/sec speec support.
  185  *                      Removed AHCI support.
  186  *                      Removed SOP support.
  187  * 07-01-16   02.00.29  Added Archclass for 4008 product.
  188  *                      Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED
  189  * 08-23-16   02.00.30  Added new defines for the ImageType field of FWDownload
  190  *                      Request Message.
  191  *                      Added new defines for the ImageType field of FWUpload
  192  *                      Request Message.
  193  *                      Added new values for the RegionType field in the Layout
  194  *                      Data sections of the FLASH Layout Extended Image Data.
  195  *                      Added new defines for the ReasonCode field of
  196  *                      Active Cable Exception Event.
  197  *                      Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and
  198  *                      MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE.
  199  * 11-23-16   02.00.31  Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and
  200  *                      MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR.
  201  * 02-02-17   02.00.32  Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP.
  202  *                      Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related
  203  *                      defines for the ReasonCode field.
  204  * 06-13-17   02.00.33  Added MPI2_FW_DOWNLOAD_ITYPE_CPLD.
  205  * 09-29-17   02.00.34  Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED
  206  *                      to the ReasonCode field in PCIe Device Status Change
  207  *                      Event Data.
  208  * 07-22-18   02.00.35  Added FW_DOWNLOAD_ITYPE_CPLD and _PSOC.
  209  *                      Moved FW image definitions ionto new mpi2_image,h
  210  * 08-14-18   02.00.36  Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
  211  *  --------------------------------------------------------------------------
  212  */
  213 
  214 #ifndef MPI2_IOC_H
  215 #define MPI2_IOC_H
  216 
  217 /*****************************************************************************
  218 *
  219 *               IOC Messages
  220 *
  221 *****************************************************************************/
  222 
  223 /****************************************************************************
  224 *  IOCInit message
  225 ****************************************************************************/
  226 
  227 /* IOCInit Request message */
  228 typedef struct _MPI2_IOC_INIT_REQUEST
  229 {
  230     U8                      WhoInit;                        /* 0x00 */
  231     U8                      Reserved1;                      /* 0x01 */
  232     U8                      ChainOffset;                    /* 0x02 */
  233     U8                      Function;                       /* 0x03 */
  234     U16                     Reserved2;                      /* 0x04 */
  235     U8                      Reserved3;                      /* 0x06 */
  236     U8                      MsgFlags;                       /* 0x07 */
  237     U8                      VP_ID;                          /* 0x08 */
  238     U8                      VF_ID;                          /* 0x09 */
  239     U16                     Reserved4;                      /* 0x0A */
  240     U16                     MsgVersion;                     /* 0x0C */
  241     U16                     HeaderVersion;                  /* 0x0E */
  242     U32                     Reserved5;                      /* 0x10 */
  243     U16                     ConfigurationFlags;             /* 0x14 */
  244     U8                      HostPageSize;                   /* 0x16 */
  245     U8                      HostMSIxVectors;                /* 0x17 */
  246     U16                     Reserved8;                      /* 0x18 */
  247     U16                     SystemRequestFrameSize;         /* 0x1A */
  248     U16                     ReplyDescriptorPostQueueDepth;  /* 0x1C */
  249     U16                     ReplyFreeQueueDepth;            /* 0x1E */
  250     U32                     SenseBufferAddressHigh;         /* 0x20 */
  251     U32                     SystemReplyAddressHigh;         /* 0x24 */
  252     U64                     SystemRequestFrameBaseAddress;  /* 0x28 */
  253     U64                     ReplyDescriptorPostQueueAddress;/* 0x30 */
  254     U64                     ReplyFreeQueueAddress;          /* 0x38 */
  255     U64                     TimeStamp;                      /* 0x40 */
  256 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
  257   Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
  258 
  259 /* WhoInit values */
  260 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
  261 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
  262 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
  263 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
  264 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
  265 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
  266 
  267 /* MsgFlags */
  268 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE    (0x01)
  269 
  270 /* MsgVersion */
  271 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
  272 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
  273 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
  274 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
  275 
  276 /* HeaderVersion */
  277 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
  278 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
  279 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
  280 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
  281 
  282 /* ConfigurationFlags */
  283 #define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT  (0x0001)
  284 
  285 /* minimum depth for a Reply Descriptor Post Queue */
  286 #define MPI2_RDPQ_DEPTH_MIN                     (16)
  287 
  288 /* Reply Descriptor Post Queue Array Entry */
  289 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY
  290 {
  291     U64                 RDPQBaseAddress;                    /* 0x00 */
  292     U32                 Reserved1;                          /* 0x08 */
  293     U32                 Reserved2;                          /* 0x0C */
  294 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
  295   MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
  296   Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry;
  297 
  298 /* IOCInit Reply message */
  299 typedef struct _MPI2_IOC_INIT_REPLY
  300 {
  301     U8                      WhoInit;                        /* 0x00 */
  302     U8                      Reserved1;                      /* 0x01 */
  303     U8                      MsgLength;                      /* 0x02 */
  304     U8                      Function;                       /* 0x03 */
  305     U16                     Reserved2;                      /* 0x04 */
  306     U8                      Reserved3;                      /* 0x06 */
  307     U8                      MsgFlags;                       /* 0x07 */
  308     U8                      VP_ID;                          /* 0x08 */
  309     U8                      VF_ID;                          /* 0x09 */
  310     U16                     Reserved4;                      /* 0x0A */
  311     U16                     Reserved5;                      /* 0x0C */
  312     U16                     IOCStatus;                      /* 0x0E */
  313     U32                     IOCLogInfo;                     /* 0x10 */
  314 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
  315   Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
  316 
  317 /****************************************************************************
  318 *  IOCFacts message
  319 ****************************************************************************/
  320 
  321 /* IOCFacts Request message */
  322 typedef struct _MPI2_IOC_FACTS_REQUEST
  323 {
  324     U16                     Reserved1;                      /* 0x00 */
  325     U8                      ChainOffset;                    /* 0x02 */
  326     U8                      Function;                       /* 0x03 */
  327     U16                     Reserved2;                      /* 0x04 */
  328     U8                      Reserved3;                      /* 0x06 */
  329     U8                      MsgFlags;                       /* 0x07 */
  330     U8                      VP_ID;                          /* 0x08 */
  331     U8                      VF_ID;                          /* 0x09 */
  332     U16                     Reserved4;                      /* 0x0A */
  333 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
  334   Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
  335 
  336 /* IOCFacts Reply message */
  337 typedef struct _MPI2_IOC_FACTS_REPLY
  338 {
  339     U16                     MsgVersion;                     /* 0x00 */
  340     U8                      MsgLength;                      /* 0x02 */
  341     U8                      Function;                       /* 0x03 */
  342     U16                     HeaderVersion;                  /* 0x04 */
  343     U8                      IOCNumber;                      /* 0x06 */
  344     U8                      MsgFlags;                       /* 0x07 */
  345     U8                      VP_ID;                          /* 0x08 */
  346     U8                      VF_ID;                          /* 0x09 */
  347     U16                     Reserved1;                      /* 0x0A */
  348     U16                     IOCExceptions;                  /* 0x0C */
  349     U16                     IOCStatus;                      /* 0x0E */
  350     U32                     IOCLogInfo;                     /* 0x10 */
  351     U8                      MaxChainDepth;                  /* 0x14 */
  352     U8                      WhoInit;                        /* 0x15 */
  353     U8                      NumberOfPorts;                  /* 0x16 */
  354     U8                      MaxMSIxVectors;                 /* 0x17 */
  355     U16                     RequestCredit;                  /* 0x18 */
  356     U16                     ProductID;                      /* 0x1A */
  357     U32                     IOCCapabilities;                /* 0x1C */
  358     MPI2_VERSION_UNION      FWVersion;                      /* 0x20 */
  359     U16                     IOCRequestFrameSize;            /* 0x24 */
  360     U16                     IOCMaxChainSegmentSize;         /* 0x26 */ /* MPI 2.5 only; Reserved in MPI 2.0 */
  361     U16                     MaxInitiators;                  /* 0x28 */
  362     U16                     MaxTargets;                     /* 0x2A */
  363     U16                     MaxSasExpanders;                /* 0x2C */
  364     U16                     MaxEnclosures;                  /* 0x2E */
  365     U16                     ProtocolFlags;                  /* 0x30 */
  366     U16                     HighPriorityCredit;             /* 0x32 */
  367     U16                     MaxReplyDescriptorPostQueueDepth; /* 0x34 */
  368     U8                      ReplyFrameSize;                 /* 0x36 */
  369     U8                      MaxVolumes;                     /* 0x37 */
  370     U16                     MaxDevHandle;                   /* 0x38 */
  371     U16                     MaxPersistentEntries;           /* 0x3A */
  372     U16                     MinDevHandle;                   /* 0x3C */
  373     U8                      CurrentHostPageSize;            /* 0x3E */
  374     U8                      Reserved4;                      /* 0x3F */
  375     U8                      SGEModifierMask;                /* 0x40 */
  376     U8                      SGEModifierValue;               /* 0x41 */
  377     U8                      SGEModifierShift;               /* 0x42 */
  378     U8                      Reserved5;                      /* 0x43 */
  379 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
  380   Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
  381 
  382 /* MsgVersion */
  383 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
  384 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
  385 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
  386 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
  387 
  388 /* HeaderVersion */
  389 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
  390 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
  391 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
  392 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
  393 
  394 /* IOCExceptions */
  395 #define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED              (0x0400)
  396 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE     (0x0200)
  397 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
  398 
  399 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
  400 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
  401 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
  402 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
  403 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
  404 
  405 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
  406 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
  407 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
  408 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
  409 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
  410 
  411 /* defines for WhoInit field are after the IOCInit Request */
  412 
  413 /* ProductID field uses MPI2_FW_HEADER_PID_ */
  414 
  415 /* IOCCapabilities */
  416 #define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV            (0x00100000)
  417 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ            (0x00080000)
  418 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE     (0x00040000)
  419 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE     (0x00020000)
  420 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
  421 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
  422 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
  423 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
  424 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
  425 #define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
  426 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
  427 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
  428 #define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
  429 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
  430 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
  431 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
  432 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
  433 
  434 /* ProtocolFlags */
  435 #define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES             (0x0008) /* MPI v2.6 and later */
  436 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
  437 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
  438 
  439 /****************************************************************************
  440 *  PortFacts message
  441 ****************************************************************************/
  442 
  443 /* PortFacts Request message */
  444 typedef struct _MPI2_PORT_FACTS_REQUEST
  445 {
  446     U16                     Reserved1;                      /* 0x00 */
  447     U8                      ChainOffset;                    /* 0x02 */
  448     U8                      Function;                       /* 0x03 */
  449     U16                     Reserved2;                      /* 0x04 */
  450     U8                      PortNumber;                     /* 0x06 */
  451     U8                      MsgFlags;                       /* 0x07 */
  452     U8                      VP_ID;                          /* 0x08 */
  453     U8                      VF_ID;                          /* 0x09 */
  454     U16                     Reserved3;                      /* 0x0A */
  455 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
  456   Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
  457 
  458 /* PortFacts Reply message */
  459 typedef struct _MPI2_PORT_FACTS_REPLY
  460 {
  461     U16                     Reserved1;                      /* 0x00 */
  462     U8                      MsgLength;                      /* 0x02 */
  463     U8                      Function;                       /* 0x03 */
  464     U16                     Reserved2;                      /* 0x04 */
  465     U8                      PortNumber;                     /* 0x06 */
  466     U8                      MsgFlags;                       /* 0x07 */
  467     U8                      VP_ID;                          /* 0x08 */
  468     U8                      VF_ID;                          /* 0x09 */
  469     U16                     Reserved3;                      /* 0x0A */
  470     U16                     Reserved4;                      /* 0x0C */
  471     U16                     IOCStatus;                      /* 0x0E */
  472     U32                     IOCLogInfo;                     /* 0x10 */
  473     U8                      Reserved5;                      /* 0x14 */
  474     U8                      PortType;                       /* 0x15 */
  475     U16                     Reserved6;                      /* 0x16 */
  476     U16                     MaxPostedCmdBuffers;            /* 0x18 */
  477     U16                     Reserved7;                      /* 0x1A */
  478 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
  479   Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
  480 
  481 /* PortType values */
  482 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
  483 #define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
  484 #define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
  485 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
  486 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
  487 #define MPI2_PORTFACTS_PORTTYPE_TRI_MODE            (0x40) /* MPI v2.6 and later */
  488 
  489 /****************************************************************************
  490 *  PortEnable message
  491 ****************************************************************************/
  492 
  493 /* PortEnable Request message */
  494 typedef struct _MPI2_PORT_ENABLE_REQUEST
  495 {
  496     U16                     Reserved1;                      /* 0x00 */
  497     U8                      ChainOffset;                    /* 0x02 */
  498     U8                      Function;                       /* 0x03 */
  499     U8                      Reserved2;                      /* 0x04 */
  500     U8                      PortFlags;                      /* 0x05 */
  501     U8                      Reserved3;                      /* 0x06 */
  502     U8                      MsgFlags;                       /* 0x07 */
  503     U8                      VP_ID;                          /* 0x08 */
  504     U8                      VF_ID;                          /* 0x09 */
  505     U16                     Reserved4;                      /* 0x0A */
  506 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
  507   Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
  508 
  509 /* PortEnable Reply message */
  510 typedef struct _MPI2_PORT_ENABLE_REPLY
  511 {
  512     U16                     Reserved1;                      /* 0x00 */
  513     U8                      MsgLength;                      /* 0x02 */
  514     U8                      Function;                       /* 0x03 */
  515     U8                      Reserved2;                      /* 0x04 */
  516     U8                      PortFlags;                      /* 0x05 */
  517     U8                      Reserved3;                      /* 0x06 */
  518     U8                      MsgFlags;                       /* 0x07 */
  519     U8                      VP_ID;                          /* 0x08 */
  520     U8                      VF_ID;                          /* 0x09 */
  521     U16                     Reserved4;                      /* 0x0A */
  522     U16                     Reserved5;                      /* 0x0C */
  523     U16                     IOCStatus;                      /* 0x0E */
  524     U32                     IOCLogInfo;                     /* 0x10 */
  525 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
  526   Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
  527 
  528 /****************************************************************************
  529 *  EventNotification message
  530 ****************************************************************************/
  531 
  532 /* EventNotification Request message */
  533 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
  534 
  535 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
  536 {
  537     U16                     Reserved1;                      /* 0x00 */
  538     U8                      ChainOffset;                    /* 0x02 */
  539     U8                      Function;                       /* 0x03 */
  540     U16                     Reserved2;                      /* 0x04 */
  541     U8                      Reserved3;                      /* 0x06 */
  542     U8                      MsgFlags;                       /* 0x07 */
  543     U8                      VP_ID;                          /* 0x08 */
  544     U8                      VF_ID;                          /* 0x09 */
  545     U16                     Reserved4;                      /* 0x0A */
  546     U32                     Reserved5;                      /* 0x0C */
  547     U32                     Reserved6;                      /* 0x10 */
  548     U32                     EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
  549     U16                     SASBroadcastPrimitiveMasks;     /* 0x24 */
  550     U16                     SASNotifyPrimitiveMasks;        /* 0x26 */
  551     U32                     Reserved8;                      /* 0x28 */
  552 } MPI2_EVENT_NOTIFICATION_REQUEST,
  553   MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
  554   Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
  555 
  556 /* EventNotification Reply message */
  557 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
  558 {
  559     U16                     EventDataLength;                /* 0x00 */
  560     U8                      MsgLength;                      /* 0x02 */
  561     U8                      Function;                       /* 0x03 */
  562     U16                     Reserved1;                      /* 0x04 */
  563     U8                      AckRequired;                    /* 0x06 */
  564     U8                      MsgFlags;                       /* 0x07 */
  565     U8                      VP_ID;                          /* 0x08 */
  566     U8                      VF_ID;                          /* 0x09 */
  567     U16                     Reserved2;                      /* 0x0A */
  568     U16                     Reserved3;                      /* 0x0C */
  569     U16                     IOCStatus;                      /* 0x0E */
  570     U32                     IOCLogInfo;                     /* 0x10 */
  571     U16                     Event;                          /* 0x14 */
  572     U16                     Reserved4;                      /* 0x16 */
  573     U32                     EventContext;                   /* 0x18 */
  574     U32                     EventData[1];                   /* 0x1C */
  575 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
  576   Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
  577 
  578 /* AckRequired */
  579 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
  580 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
  581 
  582 /* Event */
  583 #define MPI2_EVENT_LOG_DATA                         (0x0001)
  584 #define MPI2_EVENT_STATE_CHANGE                     (0x0002)
  585 #define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
  586 #define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
  587 #define MPI2_EVENT_TASK_SET_FULL                    (0x000E) /* obsolete */
  588 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
  589 #define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
  590 #define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
  591 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
  592 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
  593 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
  594 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
  595 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
  596 #define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE        (0x001D) /* MPI v2.6 and later */
  597 #define MPI2_EVENT_IR_VOLUME                        (0x001E)
  598 #define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
  599 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
  600 #define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
  601 #define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
  602 #define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
  603 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
  604 #define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
  605 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE             (0x0026)
  606 #define MPI2_EVENT_TEMP_THRESHOLD                   (0x0027)
  607 #define MPI2_EVENT_HOST_MESSAGE                     (0x0028)
  608 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE         (0x0029)
  609 #define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE        (0x0030) /* MPI v2.6 and later */
  610 #define MPI2_EVENT_PCIE_ENUMERATION                 (0x0031) /* MPI v2.6 and later */
  611 #define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST        (0x0032) /* MPI v2.6 and later */
  612 #define MPI2_EVENT_PCIE_LINK_COUNTER                (0x0033) /* MPI v2.6 and later */
  613 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION           (0x0034) /* MPI v2.6 and later */
  614 #define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR       (0x0035) /* MPI v2.5 and later */
  615 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC             (0x006E)
  616 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC             (0x007F)
  617 
  618 /* Log Entry Added Event data */
  619 
  620 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
  621 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
  622 
  623 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
  624 {
  625     U64         TimeStamp;                          /* 0x00 */
  626     U32         Reserved1;                          /* 0x08 */
  627     U16         LogSequence;                        /* 0x0C */
  628     U16         LogEntryQualifier;                  /* 0x0E */
  629     U8          VP_ID;                              /* 0x10 */
  630     U8          VF_ID;                              /* 0x11 */
  631     U16         Reserved2;                          /* 0x12 */
  632     U8          LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
  633 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
  634   MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
  635   Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
  636 
  637 /* GPIO Interrupt Event data */
  638 
  639 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT
  640 {
  641     U8          GPIONum;                            /* 0x00 */
  642     U8          Reserved1;                          /* 0x01 */
  643     U16         Reserved2;                          /* 0x02 */
  644 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
  645   MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
  646   Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
  647 
  648 /* Temperature Threshold Event data */
  649 
  650 typedef struct _MPI2_EVENT_DATA_TEMPERATURE
  651 {
  652     U16         Status;                             /* 0x00 */
  653     U8          SensorNum;                          /* 0x02 */
  654     U8          Reserved1;                          /* 0x03 */
  655     U16         CurrentTemperature;                 /* 0x04 */
  656     U16         Reserved2;                          /* 0x06 */
  657     U32         Reserved3;                          /* 0x08 */
  658     U32         Reserved4;                          /* 0x0C */
  659 } MPI2_EVENT_DATA_TEMPERATURE,
  660   MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
  661   Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
  662 
  663 /* Temperature Threshold Event data Status bits */
  664 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED            (0x0008)
  665 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED            (0x0004)
  666 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED            (0x0002)
  667 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED            (0x0001)
  668 
  669 /* Host Message Event data */
  670 
  671 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE
  672 {
  673     U8          SourceVF_ID;                        /* 0x00 */
  674     U8          Reserved1;                          /* 0x01 */
  675     U16         Reserved2;                          /* 0x02 */
  676     U32         Reserved3;                          /* 0x04 */
  677     U32         HostData[1];                        /* 0x08 */
  678 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
  679   Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
  680 
  681 /* Power Performance Change Event data */
  682 
  683 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE
  684 {
  685     U8          CurrentPowerMode;                   /* 0x00 */
  686     U8          PreviousPowerMode;                  /* 0x01 */
  687     U16         Reserved1;                          /* 0x02 */
  688 } MPI2_EVENT_DATA_POWER_PERF_CHANGE,
  689   MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
  690   Mpi2EventDataPowerPerfChange_t, MPI2_POINTER pMpi2EventDataPowerPerfChange_t;
  691 
  692 /* defines for CurrentPowerMode and PreviousPowerMode fields */
  693 #define MPI2_EVENT_PM_INIT_MASK              (0xC0)
  694 #define MPI2_EVENT_PM_INIT_UNAVAILABLE       (0x00)
  695 #define MPI2_EVENT_PM_INIT_HOST              (0x40)
  696 #define MPI2_EVENT_PM_INIT_IO_UNIT           (0x80)
  697 #define MPI2_EVENT_PM_INIT_PCIE_DPA          (0xC0)
  698 
  699 #define MPI2_EVENT_PM_MODE_MASK              (0x07)
  700 #define MPI2_EVENT_PM_MODE_UNAVAILABLE       (0x00)
  701 #define MPI2_EVENT_PM_MODE_UNKNOWN           (0x01)
  702 #define MPI2_EVENT_PM_MODE_FULL_POWER        (0x04)
  703 #define MPI2_EVENT_PM_MODE_REDUCED_POWER     (0x05)
  704 #define MPI2_EVENT_PM_MODE_STANDBY           (0x06)
  705 
  706 /* Active Cable Exception Event data */
  707 
  708 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT
  709 {
  710     U32         ActiveCablePowerRequirement;        /* 0x00 */
  711     U8          ReasonCode;                         /* 0x04 */
  712     U8          ReceptacleID;                       /* 0x05 */
  713     U16         Reserved1;                          /* 0x06 */
  714 } MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
  715   MPI2_POINTER PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
  716   Mpi25EventDataActiveCableExcept_t,
  717   MPI2_POINTER pMpi25EventDataActiveCableExcept_t,
  718   MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
  719   MPI2_POINTER PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
  720   Mpi26EventDataActiveCableExcept_t,
  721   MPI2_POINTER pMpi26EventDataActiveCableExcept_t;
  722 
  723 /* MPI2.5 defines for the ReasonCode field */
  724 #define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER     (0x00)
  725 #define MPI25_EVENT_ACTIVE_CABLE_PRESENT                (0x01)
  726 #define MPI25_EVENT_ACTIVE_CABLE_DEGRADED               (0x02)
  727 
  728 /* MPI2.6 defines for the ReasonCode field */
  729 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER     (0x00)
  730 #define MPI26_EVENT_ACTIVE_CABLE_PRESENT                (0x01)
  731 #define MPI26_EVENT_ACTIVE_CABLE_DEGRADED               (0x02)
  732 
  733 /* Hard Reset Received Event data */
  734 
  735 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
  736 {
  737     U8                      Reserved1;                      /* 0x00 */
  738     U8                      Port;                           /* 0x01 */
  739     U16                     Reserved2;                      /* 0x02 */
  740 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
  741   MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
  742   Mpi2EventDataHardResetReceived_t,
  743   MPI2_POINTER pMpi2EventDataHardResetReceived_t;
  744 
  745 /* Task Set Full Event data */
  746 /*   this event is obsolete */
  747 
  748 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
  749 {
  750     U16                     DevHandle;                      /* 0x00 */
  751     U16                     CurrentDepth;                   /* 0x02 */
  752 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
  753   Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
  754 
  755 /* SAS Device Status Change Event data */
  756 
  757 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
  758 {
  759     U16                     TaskTag;                        /* 0x00 */
  760     U8                      ReasonCode;                     /* 0x02 */
  761     U8                      PhysicalPort;                   /* 0x03 */
  762     U8                      ASC;                            /* 0x04 */
  763     U8                      ASCQ;                           /* 0x05 */
  764     U16                     DevHandle;                      /* 0x06 */
  765     U32                     Reserved2;                      /* 0x08 */
  766     U64                     SASAddress;                     /* 0x0C */
  767     U8                      LUN[8];                         /* 0x14 */
  768 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
  769   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
  770   Mpi2EventDataSasDeviceStatusChange_t,
  771   MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
  772 
  773 /* SAS Device Status Change Event data ReasonCode values */
  774 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
  775 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
  776 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
  777 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
  778 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
  779 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
  780 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
  781 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
  782 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
  783 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
  784 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
  785 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
  786 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
  787 
  788 /* Integrated RAID Operation Status Event data */
  789 
  790 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
  791 {
  792     U16                     VolDevHandle;               /* 0x00 */
  793     U16                     Reserved1;                  /* 0x02 */
  794     U8                      RAIDOperation;              /* 0x04 */
  795     U8                      PercentComplete;            /* 0x05 */
  796     U16                     Reserved2;                  /* 0x06 */
  797     U32                     ElapsedSeconds;             /* 0x08 */
  798 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
  799   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
  800   Mpi2EventDataIrOperationStatus_t,
  801   MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
  802 
  803 /* Integrated RAID Operation Status Event data RAIDOperation values */
  804 #define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
  805 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
  806 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
  807 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
  808 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
  809 
  810 /* Integrated RAID Volume Event data */
  811 
  812 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
  813 {
  814     U16                     VolDevHandle;               /* 0x00 */
  815     U8                      ReasonCode;                 /* 0x02 */
  816     U8                      Reserved1;                  /* 0x03 */
  817     U32                     NewValue;                   /* 0x04 */
  818     U32                     PreviousValue;              /* 0x08 */
  819 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
  820   Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
  821 
  822 /* Integrated RAID Volume Event data ReasonCode values */
  823 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
  824 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
  825 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
  826 
  827 /* Integrated RAID Physical Disk Event data */
  828 
  829 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
  830 {
  831     U16                     Reserved1;                  /* 0x00 */
  832     U8                      ReasonCode;                 /* 0x02 */
  833     U8                      PhysDiskNum;                /* 0x03 */
  834     U16                     PhysDiskDevHandle;          /* 0x04 */
  835     U16                     Reserved2;                  /* 0x06 */
  836     U16                     Slot;                       /* 0x08 */
  837     U16                     EnclosureHandle;            /* 0x0A */
  838     U32                     NewValue;                   /* 0x0C */
  839     U32                     PreviousValue;              /* 0x10 */
  840 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
  841   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
  842   Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
  843 
  844 /* Integrated RAID Physical Disk Event data ReasonCode values */
  845 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
  846 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
  847 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
  848 
  849 /* Integrated RAID Configuration Change List Event data */
  850 
  851 /*
  852  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
  853  * one and check NumElements at runtime.
  854  */
  855 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
  856 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
  857 #endif
  858 
  859 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
  860 {
  861     U16                     ElementFlags;               /* 0x00 */
  862     U16                     VolDevHandle;               /* 0x02 */
  863     U8                      ReasonCode;                 /* 0x04 */
  864     U8                      PhysDiskNum;                /* 0x05 */
  865     U16                     PhysDiskDevHandle;          /* 0x06 */
  866 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
  867   Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
  868 
  869 /* IR Configuration Change List Event data ElementFlags values */
  870 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
  871 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
  872 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
  873 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
  874 
  875 /* IR Configuration Change List Event data ReasonCode values */
  876 #define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
  877 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
  878 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
  879 #define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
  880 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
  881 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
  882 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
  883 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
  884 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
  885 
  886 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
  887 {
  888     U8                              NumElements;        /* 0x00 */
  889     U8                              Reserved1;          /* 0x01 */
  890     U8                              Reserved2;          /* 0x02 */
  891     U8                              ConfigNum;          /* 0x03 */
  892     U32                             Flags;              /* 0x04 */
  893     MPI2_EVENT_IR_CONFIG_ELEMENT    ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];    /* 0x08 */
  894 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
  895   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
  896   Mpi2EventDataIrConfigChangeList_t,
  897   MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
  898 
  899 /* IR Configuration Change List Event data Flags values */
  900 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
  901 
  902 /* SAS Discovery Event data */
  903 
  904 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
  905 {
  906     U8                      Flags;                      /* 0x00 */
  907     U8                      ReasonCode;                 /* 0x01 */
  908     U8                      PhysicalPort;               /* 0x02 */
  909     U8                      Reserved1;                  /* 0x03 */
  910     U32                     DiscoveryStatus;            /* 0x04 */
  911 } MPI2_EVENT_DATA_SAS_DISCOVERY,
  912   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
  913   Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
  914 
  915 /* SAS Discovery Event data Flags values */
  916 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
  917 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
  918 
  919 /* SAS Discovery Event data ReasonCode values */
  920 #define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
  921 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
  922 
  923 /* SAS Discovery Event data DiscoveryStatus values */
  924 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
  925 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
  926 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
  927 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
  928 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
  929 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
  930 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
  931 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
  932 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
  933 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
  934 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
  935 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
  936 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
  937 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
  938 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
  939 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
  940 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
  941 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
  942 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
  943 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
  944 
  945 /* SAS Broadcast Primitive Event data */
  946 
  947 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
  948 {
  949     U8                      PhyNum;                     /* 0x00 */
  950     U8                      Port;                       /* 0x01 */
  951     U8                      PortWidth;                  /* 0x02 */
  952     U8                      Primitive;                  /* 0x03 */
  953 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
  954   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
  955   Mpi2EventDataSasBroadcastPrimitive_t,
  956   MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
  957 
  958 /* defines for the Primitive field */
  959 #define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
  960 #define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
  961 #define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
  962 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
  963 #define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
  964 #define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
  965 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
  966 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
  967 
  968 /* SAS Notify Primitive Event data */
  969 
  970 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE
  971 {
  972     U8                      PhyNum;                     /* 0x00 */
  973     U8                      Port;                       /* 0x01 */
  974     U8                      Reserved1;                  /* 0x02 */
  975     U8                      Primitive;                  /* 0x03 */
  976 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
  977   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
  978   Mpi2EventDataSasNotifyPrimitive_t,
  979   MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
  980 
  981 /* defines for the Primitive field */
  982 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP                     (0x01)
  983 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED               (0x02)
  984 #define MPI2_EVENT_NOTIFY_RESERVED1                         (0x03)
  985 #define MPI2_EVENT_NOTIFY_RESERVED2                         (0x04)
  986 
  987 /* SAS Initiator Device Status Change Event data */
  988 
  989 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
  990 {
  991     U8                      ReasonCode;                 /* 0x00 */
  992     U8                      PhysicalPort;               /* 0x01 */
  993     U16                     DevHandle;                  /* 0x02 */
  994     U64                     SASAddress;                 /* 0x04 */
  995 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
  996   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
  997   Mpi2EventDataSasInitDevStatusChange_t,
  998   MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
  999 
 1000 /* SAS Initiator Device Status Change event ReasonCode values */
 1001 #define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 1002 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 1003 
 1004 /* SAS Initiator Device Table Overflow Event data */
 1005 
 1006 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
 1007 {
 1008     U16                     MaxInit;                    /* 0x00 */
 1009     U16                     CurrentInit;                /* 0x02 */
 1010     U64                     SASAddress;                 /* 0x04 */
 1011 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 1012   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 1013   Mpi2EventDataSasInitTableOverflow_t,
 1014   MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
 1015 
 1016 /* SAS Topology Change List Event data */
 1017 
 1018 /*
 1019  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 1020  * one and check NumEntries at runtime.
 1021  */
 1022 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 1023 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 1024 #endif
 1025 
 1026 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 1027 {
 1028     U16                     AttachedDevHandle;          /* 0x00 */
 1029     U8                      LinkRate;                   /* 0x02 */
 1030     U8                      PhyStatus;                  /* 0x03 */
 1031 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 1032   Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
 1033 
 1034 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
 1035 {
 1036     U16                             EnclosureHandle;            /* 0x00 */
 1037     U16                             ExpanderDevHandle;          /* 0x02 */
 1038     U8                              NumPhys;                    /* 0x04 */
 1039     U8                              Reserved1;                  /* 0x05 */
 1040     U16                             Reserved2;                  /* 0x06 */
 1041     U8                              NumEntries;                 /* 0x08 */
 1042     U8                              StartPhyNum;                /* 0x09 */
 1043     U8                              ExpStatus;                  /* 0x0A */
 1044     U8                              PhysicalPort;               /* 0x0B */
 1045     MPI2_EVENT_SAS_TOPO_PHY_ENTRY   PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
 1046 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 1047   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 1048   Mpi2EventDataSasTopologyChangeList_t,
 1049   MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
 1050 
 1051 /* values for the ExpStatus field */
 1052 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 1053 #define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 1054 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 1055 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 1056 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 1057 
 1058 /* defines for the LinkRate field */
 1059 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 1060 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 1061 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
 1062 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 1063 
 1064 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 1065 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 1066 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 1067 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 1068 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 1069 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 1070 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
 1071 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
 1072 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
 1073 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
 1074 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0                   (0x0B)
 1075 #define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5                   (0x0C)
 1076 
 1077 /* values for the PhyStatus field */
 1078 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
 1079 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
 1080 /* values for the PhyStatus ReasonCode sub-field */
 1081 #define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
 1082 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
 1083 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
 1084 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
 1085 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
 1086 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
 1087 
 1088 /* SAS Enclosure Device Status Change Event data */
 1089 
 1090 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
 1091 {
 1092     U16                     EnclosureHandle;            /* 0x00 */
 1093     U8                      ReasonCode;                 /* 0x02 */
 1094     U8                      PhysicalPort;               /* 0x03 */
 1095     U64                     EnclosureLogicalID;         /* 0x04 */
 1096     U16                     NumSlots;                   /* 0x0C */
 1097     U16                     StartSlot;                  /* 0x0E */
 1098     U32                     PhyBits;                    /* 0x10 */
 1099 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 1100   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 1101   Mpi2EventDataSasEnclDevStatusChange_t,
 1102   MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t,
 1103   MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
 1104   MPI2_POINTER PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
 1105   Mpi26EventDataEnclDevStatusChange_t,
 1106   MPI2_POINTER pMpi26EventDataEnclDevStatusChange_t;
 1107 
 1108 /* SAS Enclosure Device Status Change event ReasonCode values */
 1109 #define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
 1110 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
 1111 
 1112 /* Enclosure Device Status Change event ReasonCode values */
 1113 #define MPI26_EVENT_ENCL_RC_ADDED                   (0x01)
 1114 #define MPI26_EVENT_ENCL_RC_NOT_RESPONDING          (0x02)
 1115 
 1116 /* SAS PHY Counter Event data */
 1117 
 1118 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER
 1119 {
 1120     U64         TimeStamp;          /* 0x00 */
 1121     U32         Reserved1;          /* 0x08 */
 1122     U8          PhyEventCode;       /* 0x0C */
 1123     U8          PhyNum;             /* 0x0D */
 1124     U16         Reserved2;          /* 0x0E */
 1125     U32         PhyEventInfo;       /* 0x10 */
 1126     U8          CounterType;        /* 0x14 */
 1127     U8          ThresholdWindow;    /* 0x15 */
 1128     U8          TimeUnits;          /* 0x16 */
 1129     U8          Reserved3;          /* 0x17 */
 1130     U32         EventThreshold;     /* 0x18 */
 1131     U16         ThresholdFlags;     /* 0x1C */
 1132     U16         Reserved4;          /* 0x1E */
 1133 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 1134   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 1135   Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
 1136 
 1137 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
 1138 
 1139 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
 1140 
 1141 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
 1142 
 1143 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
 1144 
 1145 /* SAS Quiesce Event data */
 1146 
 1147 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE
 1148 {
 1149     U8                      ReasonCode;                 /* 0x00 */
 1150     U8                      Reserved1;                  /* 0x01 */
 1151     U16                     Reserved2;                  /* 0x02 */
 1152     U32                     Reserved3;                  /* 0x04 */
 1153 } MPI2_EVENT_DATA_SAS_QUIESCE,
 1154   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
 1155   Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
 1156 
 1157 /* SAS Quiesce Event data ReasonCode values */
 1158 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
 1159 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
 1160 
 1161 typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR
 1162 {
 1163     U16         DevHandle;                  /* 0x00 */
 1164     U8          ReasonCode;                 /* 0x02 */
 1165     U8          PhysicalPort;               /* 0x03 */
 1166     U32         Reserved1[2];               /* 0x04 */
 1167     U64         SASAddress;                 /* 0x0C */
 1168     U32         Reserved2[2];               /* 0x14 */
 1169 } MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
 1170   MPI2_POINTER PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
 1171   Mpi25EventDataSasDeviceDiscoveryError_t,
 1172   MPI2_POINTER pMpi25EventDataSasDeviceDiscoveryError_t;
 1173 
 1174 /* SAS Device Discovery Error Event data ReasonCode values */
 1175 #define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED         (0x01)
 1176 #define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT        (0x02)
 1177 
 1178 /* Host Based Discovery Phy Event data */
 1179 
 1180 typedef struct _MPI2_EVENT_HBD_PHY_SAS
 1181 {
 1182     U8          Flags;                      /* 0x00 */
 1183     U8          NegotiatedLinkRate;         /* 0x01 */
 1184     U8          PhyNum;                     /* 0x02 */
 1185     U8          PhysicalPort;               /* 0x03 */
 1186     U32         Reserved1;                  /* 0x04 */
 1187     U8          InitialFrame[28];           /* 0x08 */
 1188 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
 1189   Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
 1190 
 1191 /* values for the Flags field */
 1192 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
 1193 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
 1194 
 1195 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */
 1196 
 1197 typedef union _MPI2_EVENT_HBD_DESCRIPTOR
 1198 {
 1199     MPI2_EVENT_HBD_PHY_SAS      Sas;
 1200 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
 1201   Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
 1202 
 1203 typedef struct _MPI2_EVENT_DATA_HBD_PHY
 1204 {
 1205     U8                          DescriptorType;     /* 0x00 */
 1206     U8                          Reserved1;          /* 0x01 */
 1207     U16                         Reserved2;          /* 0x02 */
 1208     U32                         Reserved3;          /* 0x04 */
 1209     MPI2_EVENT_HBD_DESCRIPTOR   Descriptor;         /* 0x08 */
 1210 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
 1211   Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
 1212 
 1213 /* values for the DescriptorType field */
 1214 #define MPI2_EVENT_HBD_DT_SAS               (0x01)
 1215 
 1216 /* PCIe Device Status Change Event data (MPI v2.6 and later) */
 1217 
 1218 typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE
 1219 {
 1220     U16                     TaskTag;                        /* 0x00 */
 1221     U8                      ReasonCode;                     /* 0x02 */
 1222     U8                      PhysicalPort;                   /* 0x03 */
 1223     U8                      ASC;                            /* 0x04 */
 1224     U8                      ASCQ;                           /* 0x05 */
 1225     U16                     DevHandle;                      /* 0x06 */
 1226     U32                     Reserved2;                      /* 0x08 */
 1227     U64                     WWID;                           /* 0x0C */
 1228     U8                      LUN[8];                         /* 0x14 */
 1229 } MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
 1230   MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
 1231   Mpi26EventDataPCIeDeviceStatusChange_t,
 1232   MPI2_POINTER pMpi26EventDataPCIeDeviceStatusChange_t;
 1233 
 1234 /* PCIe Device Status Change Event data ReasonCode values */
 1235 #define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA                           (0x05)
 1236 #define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED                          (0x07)
 1237 #define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 1238 #define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 1239 #define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 1240 #define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 1241 #define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 1242 #define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 1243 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 1244 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 1245 #define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE                     (0x10)
 1246 #define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED                (0x11)
 1247 
 1248 /* PCIe Enumeration Event data (MPI v2.6 and later) */
 1249 
 1250 typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION
 1251 {
 1252     U8                      Flags;                      /* 0x00 */
 1253     U8                      ReasonCode;                 /* 0x01 */
 1254     U8                      PhysicalPort;               /* 0x02 */
 1255     U8                      Reserved1;                  /* 0x03 */
 1256     U32                     EnumerationStatus;          /* 0x04 */
 1257 } MPI26_EVENT_DATA_PCIE_ENUMERATION,
 1258   MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION,
 1259   Mpi26EventDataPCIeEnumeration_t,
 1260   MPI2_POINTER pMpi26EventDataPCIeEnumeration_t;
 1261 
 1262 /* PCIe Enumeration Event data Flags values */
 1263 #define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE                 (0x02)
 1264 #define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS                   (0x01)
 1265 
 1266 /* PCIe Enumeration Event data ReasonCode values */
 1267 #define MPI26_EVENT_PCIE_ENUM_RC_STARTED                    (0x01)
 1268 #define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED                  (0x02)
 1269 
 1270 /* PCIe Enumeration Event data EnumerationStatus values */
 1271 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED            (0x40000000)
 1272 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED             (0x20000000)
 1273 #define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED            (0x10000000)
 1274 
 1275 /* PCIe Topology Change List Event data (MPI v2.6 and later) */
 1276 
 1277 /*
 1278  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 1279  * one and check NumEntries at runtime.
 1280  */
 1281 #ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT
 1282 #define MPI26_EVENT_PCIE_TOPO_PORT_COUNT        (1)
 1283 #endif
 1284 
 1285 typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY
 1286 {
 1287     U16         AttachedDevHandle;      /* 0x00 */
 1288     U8          PortStatus;             /* 0x02 */
 1289     U8          Reserved1;              /* 0x03 */
 1290     U8          CurrentPortInfo;        /* 0x04 */
 1291     U8          Reserved2;              /* 0x05 */
 1292     U8          PreviousPortInfo;       /* 0x06 */
 1293     U8          Reserved3;              /* 0x07 */
 1294 } MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
 1295   MPI2_POINTER PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
 1296   Mpi26EventPCIeTopoPortEntry_t,
 1297   MPI2_POINTER pMpi26EventPCIeTopoPortEntry_t;
 1298 
 1299 /* PCIe Topology Change List Event data PortStatus values */
 1300 #define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED                  (0x01)
 1301 #define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING             (0x02)
 1302 #define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED               (0x03)
 1303 #define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE                  (0x04)
 1304 #define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING       (0x05)
 1305 
 1306 /* PCIe Topology Change List Event data defines for CurrentPortInfo and PreviousPortInfo */
 1307 #define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK                  (0xF0)
 1308 #define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN              (0x00)
 1309 #define MPI26_EVENT_PCIE_TOPO_PI_1_LANE                     (0x10)
 1310 #define MPI26_EVENT_PCIE_TOPO_PI_2_LANES                    (0x20)
 1311 #define MPI26_EVENT_PCIE_TOPO_PI_4_LANES                    (0x30)
 1312 #define MPI26_EVENT_PCIE_TOPO_PI_8_LANES                    (0x40)
 1313 
 1314 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK                  (0x0F)
 1315 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN               (0x00)
 1316 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED              (0x01)
 1317 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5                   (0x02)
 1318 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0                   (0x03)
 1319 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0                   (0x04)
 1320 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0                  (0x05)
 1321 
 1322 typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST
 1323 {
 1324     U16                                 EnclosureHandle;        /* 0x00 */
 1325     U16                                 SwitchDevHandle;        /* 0x02 */
 1326     U8                                  NumPorts;               /* 0x04 */
 1327     U8                                  Reserved1;              /* 0x05 */
 1328     U16                                 Reserved2;              /* 0x06 */
 1329     U8                                  NumEntries;             /* 0x08 */
 1330     U8                                  StartPortNum;           /* 0x09 */
 1331     U8                                  SwitchStatus;           /* 0x0A */
 1332     U8                                  PhysicalPort;           /* 0x0B */
 1333     MPI26_EVENT_PCIE_TOPO_PORT_ENTRY    PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /* 0x0C */
 1334 } MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
 1335   MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
 1336   Mpi26EventDataPCIeTopologyChangeList_t,
 1337   MPI2_POINTER pMpi26EventDataPCIeTopologyChangeList_t;
 1338 
 1339 /* PCIe Topology Change List Event data SwitchStatus values */
 1340 #define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH             (0x00)
 1341 #define MPI26_EVENT_PCIE_TOPO_SS_ADDED                      (0x01)
 1342 #define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING             (0x02)
 1343 #define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING                 (0x03)
 1344 #define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING       (0x04)
 1345 
 1346 /* PCIe Link Counter Event data (MPI v2.6 and later) */
 1347 
 1348 typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER
 1349 {
 1350     U64         TimeStamp;          /* 0x00 */
 1351     U32         Reserved1;          /* 0x08 */
 1352     U8          LinkEventCode;      /* 0x0C */
 1353     U8          LinkNum;            /* 0x0D */
 1354     U16         Reserved2;          /* 0x0E */
 1355     U32         LinkEventInfo;      /* 0x10 */
 1356     U8          CounterType;        /* 0x14 */
 1357     U8          ThresholdWindow;    /* 0x15 */
 1358     U8          TimeUnits;          /* 0x16 */
 1359     U8          Reserved3;          /* 0x17 */
 1360     U32         EventThreshold;     /* 0x18 */
 1361     U16         ThresholdFlags;     /* 0x1C */
 1362     U16         Reserved4;          /* 0x1E */
 1363 } MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
 1364   MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
 1365   Mpi26EventDataPcieLinkCounter_t, MPI2_POINTER pMpi26EventDataPcieLinkCounter_t;
 1366 
 1367 /* use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode field */
 1368 
 1369 /* use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
 1370 
 1371 /* use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
 1372 
 1373 /* use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
 1374 
 1375 /****************************************************************************
 1376 *  EventAck message
 1377 ****************************************************************************/
 1378 
 1379 /* EventAck Request message */
 1380 typedef struct _MPI2_EVENT_ACK_REQUEST
 1381 {
 1382     U16                     Reserved1;                      /* 0x00 */
 1383     U8                      ChainOffset;                    /* 0x02 */
 1384     U8                      Function;                       /* 0x03 */
 1385     U16                     Reserved2;                      /* 0x04 */
 1386     U8                      Reserved3;                      /* 0x06 */
 1387     U8                      MsgFlags;                       /* 0x07 */
 1388     U8                      VP_ID;                          /* 0x08 */
 1389     U8                      VF_ID;                          /* 0x09 */
 1390     U16                     Reserved4;                      /* 0x0A */
 1391     U16                     Event;                          /* 0x0C */
 1392     U16                     Reserved5;                      /* 0x0E */
 1393     U32                     EventContext;                   /* 0x10 */
 1394 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
 1395   Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
 1396 
 1397 /* EventAck Reply message */
 1398 typedef struct _MPI2_EVENT_ACK_REPLY
 1399 {
 1400     U16                     Reserved1;                      /* 0x00 */
 1401     U8                      MsgLength;                      /* 0x02 */
 1402     U8                      Function;                       /* 0x03 */
 1403     U16                     Reserved2;                      /* 0x04 */
 1404     U8                      Reserved3;                      /* 0x06 */
 1405     U8                      MsgFlags;                       /* 0x07 */
 1406     U8                      VP_ID;                          /* 0x08 */
 1407     U8                      VF_ID;                          /* 0x09 */
 1408     U16                     Reserved4;                      /* 0x0A */
 1409     U16                     Reserved5;                      /* 0x0C */
 1410     U16                     IOCStatus;                      /* 0x0E */
 1411     U32                     IOCLogInfo;                     /* 0x10 */
 1412 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
 1413   Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
 1414 
 1415 /****************************************************************************
 1416 *  SendHostMessage message
 1417 ****************************************************************************/
 1418 
 1419 /* SendHostMessage Request message */
 1420 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST
 1421 {
 1422     U16                     HostDataLength;                 /* 0x00 */
 1423     U8                      ChainOffset;                    /* 0x02 */
 1424     U8                      Function;                       /* 0x03 */
 1425     U16                     Reserved1;                      /* 0x04 */
 1426     U8                      Reserved2;                      /* 0x06 */
 1427     U8                      MsgFlags;                       /* 0x07 */
 1428     U8                      VP_ID;                          /* 0x08 */
 1429     U8                      VF_ID;                          /* 0x09 */
 1430     U16                     Reserved3;                      /* 0x0A */
 1431     U8                      Reserved4;                      /* 0x0C */
 1432     U8                      DestVF_ID;                      /* 0x0D */
 1433     U16                     Reserved5;                      /* 0x0E */
 1434     U32                     Reserved6;                      /* 0x10 */
 1435     U32                     Reserved7;                      /* 0x14 */
 1436     U32                     Reserved8;                      /* 0x18 */
 1437     U32                     Reserved9;                      /* 0x1C */
 1438     U32                     Reserved10;                     /* 0x20 */
 1439     U32                     HostData[1];                    /* 0x24 */
 1440 } MPI2_SEND_HOST_MESSAGE_REQUEST,
 1441   MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
 1442   Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
 1443 
 1444 /* SendHostMessage Reply message */
 1445 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY
 1446 {
 1447     U16                     HostDataLength;                 /* 0x00 */
 1448     U8                      MsgLength;                      /* 0x02 */
 1449     U8                      Function;                       /* 0x03 */
 1450     U16                     Reserved1;                      /* 0x04 */
 1451     U8                      Reserved2;                      /* 0x06 */
 1452     U8                      MsgFlags;                       /* 0x07 */
 1453     U8                      VP_ID;                          /* 0x08 */
 1454     U8                      VF_ID;                          /* 0x09 */
 1455     U16                     Reserved3;                      /* 0x0A */
 1456     U16                     Reserved4;                      /* 0x0C */
 1457     U16                     IOCStatus;                      /* 0x0E */
 1458     U32                     IOCLogInfo;                     /* 0x10 */
 1459 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
 1460   Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
 1461 
 1462 /****************************************************************************
 1463 *  FWDownload message
 1464 ****************************************************************************/
 1465 
 1466 /* MPI v2.0 FWDownload Request message */
 1467 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
 1468 {
 1469     U8                      ImageType;                  /* 0x00 */
 1470     U8                      Reserved1;                  /* 0x01 */
 1471     U8                      ChainOffset;                /* 0x02 */
 1472     U8                      Function;                   /* 0x03 */
 1473     U16                     Reserved2;                  /* 0x04 */
 1474     U8                      Reserved3;                  /* 0x06 */
 1475     U8                      MsgFlags;                   /* 0x07 */
 1476     U8                      VP_ID;                      /* 0x08 */
 1477     U8                      VF_ID;                      /* 0x09 */
 1478     U16                     Reserved4;                  /* 0x0A */
 1479     U32                     TotalImageSize;             /* 0x0C */
 1480     U32                     Reserved5;                  /* 0x10 */
 1481     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
 1482 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
 1483   Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
 1484 
 1485 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
 1486 
 1487 #define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
 1488 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
 1489 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
 1490 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
 1491 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
 1492 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
 1493 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
 1494 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
 1495 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY           (0x0C) /* MPI v2.5 and newer */
 1496 #define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP           (0x0D)
 1497 #define MPI2_FW_DOWNLOAD_ITYPE_SBR                  (0x0E)
 1498 #define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP           (0x0F)
 1499 #define MPI2_FW_DOWNLOAD_ITYPE_HIIM                 (0x10)
 1500 #define MPI2_FW_DOWNLOAD_ITYPE_HIIA                 (0x11)
 1501 #define MPI2_FW_DOWNLOAD_ITYPE_CTLR                 (0x12)
 1502 #define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE         (0x13)
 1503 #define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA            (0x14)
 1504 #define MPI2_FW_DOWNLOAD_ITYPE_CPLD                 (0x15) /* MPI v2.6 and newer */
 1505 #define MPI2_FW_DOWNLOAD_ITYPE_PSOC                 (0x16) /* MPI v2.6 and newer */
 1506 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
 1507 #define MPI2_FW_DOWNLOAD_ITYPE_TERMINATE            (0xFF) /* MPI v2.6 and newer */
 1508 
 1509 /* MPI v2.0 FWDownload TransactionContext Element */
 1510 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
 1511 {
 1512     U8                      Reserved1;                  /* 0x00 */
 1513     U8                      ContextSize;                /* 0x01 */
 1514     U8                      DetailsLength;              /* 0x02 */
 1515     U8                      Flags;                      /* 0x03 */
 1516     U32                     Reserved2;                  /* 0x04 */
 1517     U32                     ImageOffset;                /* 0x08 */
 1518     U32                     ImageSize;                  /* 0x0C */
 1519 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
 1520   Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
 1521 
 1522 /* MPI v2.5 FWDownload Request message */
 1523 typedef struct _MPI25_FW_DOWNLOAD_REQUEST
 1524 {
 1525     U8                      ImageType;                  /* 0x00 */
 1526     U8                      Reserved1;                  /* 0x01 */
 1527     U8                      ChainOffset;                /* 0x02 */
 1528     U8                      Function;                   /* 0x03 */
 1529     U16                     Reserved2;                  /* 0x04 */
 1530     U8                      Reserved3;                  /* 0x06 */
 1531     U8                      MsgFlags;                   /* 0x07 */
 1532     U8                      VP_ID;                      /* 0x08 */
 1533     U8                      VF_ID;                      /* 0x09 */
 1534     U16                     Reserved4;                  /* 0x0A */
 1535     U32                     TotalImageSize;             /* 0x0C */
 1536     U32                     Reserved5;                  /* 0x10 */
 1537     U32                     Reserved6;                  /* 0x14 */
 1538     U32                     ImageOffset;                /* 0x18 */
 1539     U32                     ImageSize;                  /* 0x1C */
 1540     MPI25_SGE_IO_UNION      SGL;                        /* 0x20 */
 1541 } MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST,
 1542   Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest;
 1543 
 1544 /* FWDownload Reply message */
 1545 typedef struct _MPI2_FW_DOWNLOAD_REPLY
 1546 {
 1547     U8                      ImageType;                  /* 0x00 */
 1548     U8                      Reserved1;                  /* 0x01 */
 1549     U8                      MsgLength;                  /* 0x02 */
 1550     U8                      Function;                   /* 0x03 */
 1551     U16                     Reserved2;                  /* 0x04 */
 1552     U8                      Reserved3;                  /* 0x06 */
 1553     U8                      MsgFlags;                   /* 0x07 */
 1554     U8                      VP_ID;                      /* 0x08 */
 1555     U8                      VF_ID;                      /* 0x09 */
 1556     U16                     Reserved4;                  /* 0x0A */
 1557     U16                     Reserved5;                  /* 0x0C */
 1558     U16                     IOCStatus;                  /* 0x0E */
 1559     U32                     IOCLogInfo;                 /* 0x10 */
 1560 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
 1561   Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
 1562 
 1563 /****************************************************************************
 1564 *  FWUpload message
 1565 ****************************************************************************/
 1566 
 1567 /* MPI v2.0 FWUpload Request message */
 1568 typedef struct _MPI2_FW_UPLOAD_REQUEST
 1569 {
 1570     U8                      ImageType;                  /* 0x00 */
 1571     U8                      Reserved1;                  /* 0x01 */
 1572     U8                      ChainOffset;                /* 0x02 */
 1573     U8                      Function;                   /* 0x03 */
 1574     U16                     Reserved2;                  /* 0x04 */
 1575     U8                      Reserved3;                  /* 0x06 */
 1576     U8                      MsgFlags;                   /* 0x07 */
 1577     U8                      VP_ID;                      /* 0x08 */
 1578     U8                      VF_ID;                      /* 0x09 */
 1579     U16                     Reserved4;                  /* 0x0A */
 1580     U32                     Reserved5;                  /* 0x0C */
 1581     U32                     Reserved6;                  /* 0x10 */
 1582     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
 1583 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
 1584   Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
 1585 
 1586 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
 1587 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
 1588 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
 1589 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
 1590 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
 1591 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
 1592 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
 1593 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
 1594 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
 1595 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
 1596 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP         (0x0D)
 1597 #define MPI2_FW_UPLOAD_ITYPE_SBR                (0x0E)
 1598 #define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP         (0x0F)
 1599 #define MPI2_FW_UPLOAD_ITYPE_HIIM               (0x10)
 1600 #define MPI2_FW_UPLOAD_ITYPE_HIIA               (0x11)
 1601 #define MPI2_FW_UPLOAD_ITYPE_CTLR               (0x12)
 1602 #define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE       (0x13)
 1603 #define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA          (0x14)
 1604 
 1605 /* MPI v2.0 FWUpload TransactionContext Element */
 1606 typedef struct _MPI2_FW_UPLOAD_TCSGE
 1607 {
 1608     U8                      Reserved1;                  /* 0x00 */
 1609     U8                      ContextSize;                /* 0x01 */
 1610     U8                      DetailsLength;              /* 0x02 */
 1611     U8                      Flags;                      /* 0x03 */
 1612     U32                     Reserved2;                  /* 0x04 */
 1613     U32                     ImageOffset;                /* 0x08 */
 1614     U32                     ImageSize;                  /* 0x0C */
 1615 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
 1616   Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
 1617 
 1618 /* MPI v2.5 FWUpload Request message */
 1619 typedef struct _MPI25_FW_UPLOAD_REQUEST
 1620 {
 1621     U8                      ImageType;                  /* 0x00 */
 1622     U8                      Reserved1;                  /* 0x01 */
 1623     U8                      ChainOffset;                /* 0x02 */
 1624     U8                      Function;                   /* 0x03 */
 1625     U16                     Reserved2;                  /* 0x04 */
 1626     U8                      Reserved3;                  /* 0x06 */
 1627     U8                      MsgFlags;                   /* 0x07 */
 1628     U8                      VP_ID;                      /* 0x08 */
 1629     U8                      VF_ID;                      /* 0x09 */
 1630     U16                     Reserved4;                  /* 0x0A */
 1631     U32                     Reserved5;                  /* 0x0C */
 1632     U32                     Reserved6;                  /* 0x10 */
 1633     U32                     Reserved7;                  /* 0x14 */
 1634     U32                     ImageOffset;                /* 0x18 */
 1635     U32                     ImageSize;                  /* 0x1C */
 1636     MPI25_SGE_IO_UNION      SGL;                        /* 0x20 */
 1637 } MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST,
 1638   Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t;
 1639 
 1640 /* FWUpload Reply message */
 1641 typedef struct _MPI2_FW_UPLOAD_REPLY
 1642 {
 1643     U8                      ImageType;                  /* 0x00 */
 1644     U8                      Reserved1;                  /* 0x01 */
 1645     U8                      MsgLength;                  /* 0x02 */
 1646     U8                      Function;                   /* 0x03 */
 1647     U16                     Reserved2;                  /* 0x04 */
 1648     U8                      Reserved3;                  /* 0x06 */
 1649     U8                      MsgFlags;                   /* 0x07 */
 1650     U8                      VP_ID;                      /* 0x08 */
 1651     U8                      VF_ID;                      /* 0x09 */
 1652     U16                     Reserved4;                  /* 0x0A */
 1653     U16                     Reserved5;                  /* 0x0C */
 1654     U16                     IOCStatus;                  /* 0x0E */
 1655     U32                     IOCLogInfo;                 /* 0x10 */
 1656     U32                     ActualImageSize;            /* 0x14 */
 1657 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
 1658   Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
 1659 
 1660 /****************************************************************************
 1661 *  PowerManagementControl message
 1662 ****************************************************************************/
 1663 
 1664 /* PowerManagementControl Request message */
 1665 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST
 1666 {
 1667     U8                      Feature;                    /* 0x00 */
 1668     U8                      Reserved1;                  /* 0x01 */
 1669     U8                      ChainOffset;                /* 0x02 */
 1670     U8                      Function;                   /* 0x03 */
 1671     U16                     Reserved2;                  /* 0x04 */
 1672     U8                      Reserved3;                  /* 0x06 */
 1673     U8                      MsgFlags;                   /* 0x07 */
 1674     U8                      VP_ID;                      /* 0x08 */
 1675     U8                      VF_ID;                      /* 0x09 */
 1676     U16                     Reserved4;                  /* 0x0A */
 1677     U8                      Parameter1;                 /* 0x0C */
 1678     U8                      Parameter2;                 /* 0x0D */
 1679     U8                      Parameter3;                 /* 0x0E */
 1680     U8                      Parameter4;                 /* 0x0F */
 1681     U32                     Reserved5;                  /* 0x10 */
 1682     U32                     Reserved6;                  /* 0x14 */
 1683 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
 1684   Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
 1685 
 1686 /* defines for the Feature field */
 1687 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
 1688 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
 1689 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03) /* obsolete */
 1690 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
 1691 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE    (0x05) /* reserved in MPI 2.0 */
 1692 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
 1693 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
 1694 
 1695 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
 1696 /* Parameter1 contains a PHY number */
 1697 /* Parameter2 indicates power condition action using these defines */
 1698 #define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
 1699 #define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
 1700 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
 1701 /* Parameter3 and Parameter4 are reserved */
 1702 
 1703 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */
 1704 /* Parameter1 contains SAS port width modulation group number */
 1705 /* Parameter2 indicates IOC action using these defines */
 1706 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
 1707 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
 1708 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
 1709 /* Parameter3 indicates desired modulation level using these defines */
 1710 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
 1711 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
 1712 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
 1713 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
 1714 /* Parameter4 is reserved */
 1715 
 1716 /* this next set (_PCIE_LINK) is obsolete */
 1717 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
 1718 /* Parameter1 indicates desired PCIe link speed using these defines */
 1719 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00) /* obsolete */
 1720 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01) /* obsolete */
 1721 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02) /* obsolete */
 1722 /* Parameter2 indicates desired PCIe link width using these defines */
 1723 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01) /* obsolete */
 1724 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02) /* obsolete */
 1725 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04) /* obsolete */
 1726 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08) /* obsolete */
 1727 /* Parameter3 and Parameter4 are reserved */
 1728 
 1729 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
 1730 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
 1731 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
 1732 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
 1733 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
 1734 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
 1735 /* Parameter2, Parameter3, and Parameter4 are reserved */
 1736 
 1737 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature */
 1738 /* Parameter1 indicates host action regarding global power management mode */
 1739 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL             (0x01)
 1740 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE       (0x02)
 1741 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL          (0x03)
 1742 /* Parameter2 indicates the requested global power management mode */
 1743 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF            (0x01)
 1744 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF         (0x08)
 1745 #define MPI2_PM_CONTROL_PARAM2_STANDBY                  (0x40)
 1746 /* Parameter3 and Parameter4 are reserved */
 1747 
 1748 /* PowerManagementControl Reply message */
 1749 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY
 1750 {
 1751     U8                      Feature;                    /* 0x00 */
 1752     U8                      Reserved1;                  /* 0x01 */
 1753     U8                      MsgLength;                  /* 0x02 */
 1754     U8                      Function;                   /* 0x03 */
 1755     U16                     Reserved2;                  /* 0x04 */
 1756     U8                      Reserved3;                  /* 0x06 */
 1757     U8                      MsgFlags;                   /* 0x07 */
 1758     U8                      VP_ID;                      /* 0x08 */
 1759     U8                      VF_ID;                      /* 0x09 */
 1760     U16                     Reserved4;                  /* 0x0A */
 1761     U16                     Reserved5;                  /* 0x0C */
 1762     U16                     IOCStatus;                  /* 0x0E */
 1763     U32                     IOCLogInfo;                 /* 0x10 */
 1764 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
 1765   Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
 1766 
 1767 /****************************************************************************
 1768 *  IO Unit Control messages (MPI v2.6 and later only.)
 1769 ****************************************************************************/
 1770 
 1771 /* IO Unit Control Request Message */
 1772 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST
 1773 {
 1774     U8                      Operation;          /* 0x00 */
 1775     U8                      Reserved1;          /* 0x01 */
 1776     U8                      ChainOffset;        /* 0x02 */
 1777     U8                      Function;           /* 0x03 */
 1778     U16                     DevHandle;          /* 0x04 */
 1779     U8                      IOCParameter;       /* 0x06 */
 1780     U8                      MsgFlags;           /* 0x07 */
 1781     U8                      VP_ID;              /* 0x08 */
 1782     U8                      VF_ID;              /* 0x09 */
 1783     U16                     Reserved3;          /* 0x0A */
 1784     U16                     Reserved4;          /* 0x0C */
 1785     U8                      PhyNum;             /* 0x0E */
 1786     U8                      PrimFlags;          /* 0x0F */
 1787     U32                     Primitive;          /* 0x10 */
 1788     U8                      LookupMethod;       /* 0x14 */
 1789     U8                      Reserved5;          /* 0x15 */
 1790     U16                     SlotNumber;         /* 0x16 */
 1791     U64                     LookupAddress;      /* 0x18 */
 1792     U32                     IOCParameterValue;  /* 0x20 */
 1793     U32                     Reserved7;          /* 0x24 */
 1794     U32                     Reserved8;          /* 0x28 */
 1795 } MPI26_IOUNIT_CONTROL_REQUEST,
 1796   MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REQUEST,
 1797   Mpi26IoUnitControlRequest_t, MPI2_POINTER pMpi26IoUnitControlRequest_t;
 1798 
 1799 /* values for the Operation field */
 1800 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT              (0x02)
 1801 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET                (0x06)
 1802 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET                (0x07)
 1803 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG               (0x08)
 1804 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG              (0x09)
 1805 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE                (0x0A)
 1806 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY              (0x0B)
 1807 #define MPI26_CTRL_OP_REMOVE_DEVICE                     (0x0D)
 1808 #define MPI26_CTRL_OP_LOOKUP_MAPPING                    (0x0E)
 1809 #define MPI26_CTRL_OP_SET_IOC_PARAMETER                 (0x0F)
 1810 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE                  (0x10)
 1811 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE                 (0x11)
 1812 #define MPI26_CTRL_OP_ENABLE_FP_ALL                     (0x12)
 1813 #define MPI26_CTRL_OP_DISABLE_FP_ALL                    (0x13)
 1814 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ                    (0x14)
 1815 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ                   (0x15)
 1816 #define MPI26_CTRL_OP_SHUTDOWN                          (0x16)
 1817 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION     (0x17)
 1818 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION    (0x18)
 1819 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION      (0x19)
 1820 #define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT            (0x1A)
 1821 #define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT           (0x1B)
 1822 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN              (0x80)
 1823 
 1824 /* values for the PrimFlags field */
 1825 #define MPI26_CTRL_PRIMFLAGS_SINGLE                     (0x08)
 1826 #define MPI26_CTRL_PRIMFLAGS_TRIPLE                     (0x02)
 1827 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT                  (0x01)
 1828 
 1829 /* values for the LookupMethod field */
 1830 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS           (0x01)
 1831 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT         (0x02)
 1832 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME        (0x03)
 1833 
 1834 /* IO Unit Control Reply Message */
 1835 typedef struct _MPI26_IOUNIT_CONTROL_REPLY
 1836 {
 1837     U8                      Operation;          /* 0x00 */
 1838     U8                      Reserved1;          /* 0x01 */
 1839     U8                      MsgLength;          /* 0x02 */
 1840     U8                      Function;           /* 0x03 */
 1841     U16                     DevHandle;          /* 0x04 */
 1842     U8                      IOCParameter;       /* 0x06 */
 1843     U8                      MsgFlags;           /* 0x07 */
 1844     U8                      VP_ID;              /* 0x08 */
 1845     U8                      VF_ID;              /* 0x09 */
 1846     U16                     Reserved3;          /* 0x0A */
 1847     U16                     Reserved4;          /* 0x0C */
 1848     U16                     IOCStatus;          /* 0x0E */
 1849     U32                     IOCLogInfo;         /* 0x10 */
 1850 } MPI26_IOUNIT_CONTROL_REPLY, MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REPLY,
 1851   Mpi26IoUnitControlReply_t, MPI2_POINTER pMpi26IoUnitControlReply_t;
 1852 
 1853 #endif
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FreeBSD/Linux Kernel Cross Reference sys/dev/mpr/mpi/mpi2_ioc.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/mpr/mpi/mpi2_ioc.h
