1 /*-
2 * Copyright (c) 2012-2015 LSI Corp.
3 * Copyright (c) 2013-2016 Avago Technologies
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. Neither the name of the author nor the names of any co-contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
31 *
32 * $FreeBSD$
33 */
34
35 /*
36 * Copyright (c) 2000-2015 LSI Corporation.
37 * Copyright (c) 2013-2016 Avago Technologies
38 * All rights reserved.
39 *
40 *
41 * Name: mpi2_ioc.h
42 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
43 * Creation Date: October 11, 2006
44 *
45 * mpi2_ioc.h Version: 02.00.32
46 *
47 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
48 * prefix are for use only on MPI v2.5 products, and must not be used
49 * with MPI v2.0 products. Unless otherwise noted, names beginning with
50 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
51 *
52 * Version History
53 * ---------------
54 *
55 * Date Version Description
56 * -------- -------- ------------------------------------------------------
57 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
58 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
59 * MaxTargets.
60 * Added TotalImageSize field to FWDownload Request.
61 * Added reserved words to FWUpload Request.
62 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
63 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
64 * request and replaced it with
65 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
66 * Replaced the MinReplyQueueDepth field of the IOCFacts
67 * reply with MaxReplyDescriptorPostQueueDepth.
68 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
69 * depth for the Reply Descriptor Post Queue.
70 * Added SASAddress field to Initiator Device Table
71 * Overflow Event data.
72 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
73 * for SAS Initiator Device Status Change Event data.
74 * Modified Reason Code defines for SAS Topology Change
75 * List Event data, including adding a bit for PHY Vacant
76 * status, and adding a mask for the Reason Code.
77 * Added define for
78 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
79 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
80 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
81 * the IOCFacts Reply.
82 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
83 * Moved MPI2_VERSION_UNION to mpi2.h.
84 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
85 * instead of enables, and added SASBroadcastPrimitiveMasks
86 * field.
87 * Added Log Entry Added Event and related structure.
88 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
89 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
90 * Added MaxVolumes and MaxPersistentEntries fields to
91 * IOCFacts reply.
92 * Added ProtocalFlags and IOCCapabilities fields to
93 * MPI2_FW_IMAGE_HEADER.
94 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
95 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
96 * a U16 (from a U32).
97 * Removed extra 's' from EventMasks name.
98 * 06-27-08 02.00.08 Fixed an offset in a comment.
99 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
100 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
101 * renamed MinReplyFrameSize to ReplyFrameSize.
102 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
103 * Added two new RAIDOperation values for Integrated RAID
104 * Operations Status Event data.
105 * Added four new IR Configuration Change List Event data
106 * ReasonCode values.
107 * Added two new ReasonCode defines for SAS Device Status
108 * Change Event data.
109 * Added three new DiscoveryStatus bits for the SAS
110 * Discovery event data.
111 * Added Multiplexing Status Change bit to the PhyStatus
112 * field of the SAS Topology Change List event data.
113 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
114 * BootFlags are now product-specific.
115 * Added defines for the indivdual signature bytes
116 * for MPI2_INIT_IMAGE_FOOTER.
117 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
118 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
119 * define.
120 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
121 * define.
122 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
123 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
124 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
125 * Added two new reason codes for SAS Device Status Change
126 * Event.
127 * Added new event: SAS PHY Counter.
128 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
129 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
130 * Added new product id family for 2208.
131 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
132 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
133 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
134 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
135 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
136 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
137 * Added Host Based Discovery Phy Event data.
138 * Added defines for ProductID Product field
139 * (MPI2_FW_HEADER_PID_).
140 * Modified values for SAS ProductID Family
141 * (MPI2_FW_HEADER_PID_FAMILY_).
142 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
143 * Added PowerManagementControl Request structures and
144 * defines.
145 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
146 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
147 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
148 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
149 * SASNotifyPrimitiveMasks field to
150 * MPI2_EVENT_NOTIFICATION_REQUEST.
151 * Added Temperature Threshold Event.
152 * Added Host Message Event.
153 * Added Send Host Message request and reply.
154 * 05-25-11 02.00.18 For Extended Image Header, added
155 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
156 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
157 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
158 * 08-24-11 02.00.19 Added PhysicalPort field to
159 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
160 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
161 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5.
162 * 03-29-12 02.00.21 Added a product specific range to event values.
163 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
164 * Added ElapsedSeconds field to
165 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
166 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
167 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
168 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
169 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
170 * Added Encrypted Hash Extended Image.
171 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.
172 * 11-18-14 02.00.25 Updated copyright information.
173 * 03-16-15 02.00.26 Updated for MPI v2.6.
174 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
175 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
176 * Added MPI2_EVENT_PCIE_LINK_COUNTER and
177 * MPI26_EVENT_DATA_PCIE_LINK_COUNTER.
178 * Added MPI26_CTRL_OP_SHUTDOWN.
179 * Added MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG
180 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
181 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
182 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines.
183 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event.
184 * Added ConigurationFlags field to IOCInit message to
185 * support NVMe SGL format control.
186 * Added PCIe SRIOV support.
187 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support.
188 * Added PCIe 4 16.0 GT/sec speec support.
189 * Removed AHCI support.
190 * Removed SOP support.
191 * 07-01-16 02.00.29 Added Archclass for 4008 product.
192 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED
193 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload
194 * Request Message.
195 * Added new defines for the ImageType field of FWUpload
196 * Request Message.
197 * Added new values for the RegionType field in the Layout
198 * Data sections of the FLASH Layout Extended Image Data.
199 * Added new defines for the ReasonCode field of
200 * Active Cable Exception Event.
201 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and
202 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE.
203 * 11-23-16 02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and
204 * MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR.
205 * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP.
206 * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related
207 * defines for the ReasonCode field.
208 * --------------------------------------------------------------------------
209 */
210
211 #ifndef MPI2_IOC_H
212 #define MPI2_IOC_H
213
214 /*****************************************************************************
215 *
216 * IOC Messages
217 *
218 *****************************************************************************/
219
220 /****************************************************************************
221 * IOCInit message
222 ****************************************************************************/
223
224 /* IOCInit Request message */
225 typedef struct _MPI2_IOC_INIT_REQUEST
226 {
227 U8 WhoInit; /* 0x00 */
228 U8 Reserved1; /* 0x01 */
229 U8 ChainOffset; /* 0x02 */
230 U8 Function; /* 0x03 */
231 U16 Reserved2; /* 0x04 */
232 U8 Reserved3; /* 0x06 */
233 U8 MsgFlags; /* 0x07 */
234 U8 VP_ID; /* 0x08 */
235 U8 VF_ID; /* 0x09 */
236 U16 Reserved4; /* 0x0A */
237 U16 MsgVersion; /* 0x0C */
238 U16 HeaderVersion; /* 0x0E */
239 U32 Reserved5; /* 0x10 */
240 U16 ConfigurationFlags; /* 0x14 */
241 U8 HostPageSize; /* 0x16 */
242 U8 HostMSIxVectors; /* 0x17 */
243 U16 Reserved8; /* 0x18 */
244 U16 SystemRequestFrameSize; /* 0x1A */
245 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */
246 U16 ReplyFreeQueueDepth; /* 0x1E */
247 U32 SenseBufferAddressHigh; /* 0x20 */
248 U32 SystemReplyAddressHigh; /* 0x24 */
249 U64 SystemRequestFrameBaseAddress; /* 0x28 */
250 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */
251 U64 ReplyFreeQueueAddress; /* 0x38 */
252 U64 TimeStamp; /* 0x40 */
253 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
254 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
255
256 /* WhoInit values */
257 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
258 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
259 #define MPI2_WHOINIT_ROM_BIOS (0x02)
260 #define MPI2_WHOINIT_PCI_PEER (0x03)
261 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
262 #define MPI2_WHOINIT_MANUFACTURER (0x05)
263
264 /* MsgFlags */
265 #define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
266
267 /* MsgVersion */
268 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
269 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
270 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
271 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
272
273 /* HeaderVersion */
274 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
275 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
276 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
277 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
278
279 /* ConfigurationFlags */
280 #define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001)
281
282 /* minimum depth for a Reply Descriptor Post Queue */
283 #define MPI2_RDPQ_DEPTH_MIN (16)
284
285 /* Reply Descriptor Post Queue Array Entry */
286 typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY
287 {
288 U64 RDPQBaseAddress; /* 0x00 */
289 U32 Reserved1; /* 0x08 */
290 U32 Reserved2; /* 0x0C */
291 } MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
292 MPI2_POINTER PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
293 Mpi2IOCInitRDPQArrayEntry, MPI2_POINTER pMpi2IOCInitRDPQArrayEntry;
294
295 /* IOCInit Reply message */
296 typedef struct _MPI2_IOC_INIT_REPLY
297 {
298 U8 WhoInit; /* 0x00 */
299 U8 Reserved1; /* 0x01 */
300 U8 MsgLength; /* 0x02 */
301 U8 Function; /* 0x03 */
302 U16 Reserved2; /* 0x04 */
303 U8 Reserved3; /* 0x06 */
304 U8 MsgFlags; /* 0x07 */
305 U8 VP_ID; /* 0x08 */
306 U8 VF_ID; /* 0x09 */
307 U16 Reserved4; /* 0x0A */
308 U16 Reserved5; /* 0x0C */
309 U16 IOCStatus; /* 0x0E */
310 U32 IOCLogInfo; /* 0x10 */
311 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
312 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
313
314
315 /****************************************************************************
316 * IOCFacts message
317 ****************************************************************************/
318
319 /* IOCFacts Request message */
320 typedef struct _MPI2_IOC_FACTS_REQUEST
321 {
322 U16 Reserved1; /* 0x00 */
323 U8 ChainOffset; /* 0x02 */
324 U8 Function; /* 0x03 */
325 U16 Reserved2; /* 0x04 */
326 U8 Reserved3; /* 0x06 */
327 U8 MsgFlags; /* 0x07 */
328 U8 VP_ID; /* 0x08 */
329 U8 VF_ID; /* 0x09 */
330 U16 Reserved4; /* 0x0A */
331 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
332 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
333
334
335 /* IOCFacts Reply message */
336 typedef struct _MPI2_IOC_FACTS_REPLY
337 {
338 U16 MsgVersion; /* 0x00 */
339 U8 MsgLength; /* 0x02 */
340 U8 Function; /* 0x03 */
341 U16 HeaderVersion; /* 0x04 */
342 U8 IOCNumber; /* 0x06 */
343 U8 MsgFlags; /* 0x07 */
344 U8 VP_ID; /* 0x08 */
345 U8 VF_ID; /* 0x09 */
346 U16 Reserved1; /* 0x0A */
347 U16 IOCExceptions; /* 0x0C */
348 U16 IOCStatus; /* 0x0E */
349 U32 IOCLogInfo; /* 0x10 */
350 U8 MaxChainDepth; /* 0x14 */
351 U8 WhoInit; /* 0x15 */
352 U8 NumberOfPorts; /* 0x16 */
353 U8 MaxMSIxVectors; /* 0x17 */
354 U16 RequestCredit; /* 0x18 */
355 U16 ProductID; /* 0x1A */
356 U32 IOCCapabilities; /* 0x1C */
357 MPI2_VERSION_UNION FWVersion; /* 0x20 */
358 U16 IOCRequestFrameSize; /* 0x24 */
359 U16 IOCMaxChainSegmentSize; /* 0x26 */ /* MPI 2.5 only; Reserved in MPI 2.0 */
360 U16 MaxInitiators; /* 0x28 */
361 U16 MaxTargets; /* 0x2A */
362 U16 MaxSasExpanders; /* 0x2C */
363 U16 MaxEnclosures; /* 0x2E */
364 U16 ProtocolFlags; /* 0x30 */
365 U16 HighPriorityCredit; /* 0x32 */
366 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */
367 U8 ReplyFrameSize; /* 0x36 */
368 U8 MaxVolumes; /* 0x37 */
369 U16 MaxDevHandle; /* 0x38 */
370 U16 MaxPersistentEntries; /* 0x3A */
371 U16 MinDevHandle; /* 0x3C */
372 U8 CurrentHostPageSize; /* 0x3E */
373 U8 Reserved4; /* 0x3F */
374 U8 SGEModifierMask; /* 0x40 */
375 U8 SGEModifierValue; /* 0x41 */
376 U8 SGEModifierShift; /* 0x42 */
377 U8 Reserved5; /* 0x43 */
378 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
379 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
380
381 /* MsgVersion */
382 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
383 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
384 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
385 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
386
387 /* HeaderVersion */
388 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
389 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
390 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
391 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
392
393 /* IOCExceptions */
394 #define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400)
395 #define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)
396 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
397
398 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
399 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
400 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
401 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
402 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
403
404 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
405 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
406 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
407 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
408 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
409
410 /* defines for WhoInit field are after the IOCInit Request */
411
412 /* ProductID field uses MPI2_FW_HEADER_PID_ */
413
414 /* IOCCapabilities */
415 #define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000)
416 #define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000)
417 #define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)
418 #define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
419 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
420 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
421 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
422 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
423 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
424 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
425 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
426 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
427 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
428 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
429 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
430 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
431 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
432
433 /* ProtocolFlags */
434 #define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008) /* MPI v2.6 and later */
435 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
436 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
437
438
439 /****************************************************************************
440 * PortFacts message
441 ****************************************************************************/
442
443 /* PortFacts Request message */
444 typedef struct _MPI2_PORT_FACTS_REQUEST
445 {
446 U16 Reserved1; /* 0x00 */
447 U8 ChainOffset; /* 0x02 */
448 U8 Function; /* 0x03 */
449 U16 Reserved2; /* 0x04 */
450 U8 PortNumber; /* 0x06 */
451 U8 MsgFlags; /* 0x07 */
452 U8 VP_ID; /* 0x08 */
453 U8 VF_ID; /* 0x09 */
454 U16 Reserved3; /* 0x0A */
455 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
456 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
457
458 /* PortFacts Reply message */
459 typedef struct _MPI2_PORT_FACTS_REPLY
460 {
461 U16 Reserved1; /* 0x00 */
462 U8 MsgLength; /* 0x02 */
463 U8 Function; /* 0x03 */
464 U16 Reserved2; /* 0x04 */
465 U8 PortNumber; /* 0x06 */
466 U8 MsgFlags; /* 0x07 */
467 U8 VP_ID; /* 0x08 */
468 U8 VF_ID; /* 0x09 */
469 U16 Reserved3; /* 0x0A */
470 U16 Reserved4; /* 0x0C */
471 U16 IOCStatus; /* 0x0E */
472 U32 IOCLogInfo; /* 0x10 */
473 U8 Reserved5; /* 0x14 */
474 U8 PortType; /* 0x15 */
475 U16 Reserved6; /* 0x16 */
476 U16 MaxPostedCmdBuffers; /* 0x18 */
477 U16 Reserved7; /* 0x1A */
478 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
479 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
480
481 /* PortType values */
482 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
483 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
484 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
485 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
486 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
487 #define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40) /* MPI v2.6 and later */
488
489
490 /****************************************************************************
491 * PortEnable message
492 ****************************************************************************/
493
494 /* PortEnable Request message */
495 typedef struct _MPI2_PORT_ENABLE_REQUEST
496 {
497 U16 Reserved1; /* 0x00 */
498 U8 ChainOffset; /* 0x02 */
499 U8 Function; /* 0x03 */
500 U8 Reserved2; /* 0x04 */
501 U8 PortFlags; /* 0x05 */
502 U8 Reserved3; /* 0x06 */
503 U8 MsgFlags; /* 0x07 */
504 U8 VP_ID; /* 0x08 */
505 U8 VF_ID; /* 0x09 */
506 U16 Reserved4; /* 0x0A */
507 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
508 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
509
510
511 /* PortEnable Reply message */
512 typedef struct _MPI2_PORT_ENABLE_REPLY
513 {
514 U16 Reserved1; /* 0x00 */
515 U8 MsgLength; /* 0x02 */
516 U8 Function; /* 0x03 */
517 U8 Reserved2; /* 0x04 */
518 U8 PortFlags; /* 0x05 */
519 U8 Reserved3; /* 0x06 */
520 U8 MsgFlags; /* 0x07 */
521 U8 VP_ID; /* 0x08 */
522 U8 VF_ID; /* 0x09 */
523 U16 Reserved4; /* 0x0A */
524 U16 Reserved5; /* 0x0C */
525 U16 IOCStatus; /* 0x0E */
526 U32 IOCLogInfo; /* 0x10 */
527 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
528 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
529
530
531 /****************************************************************************
532 * EventNotification message
533 ****************************************************************************/
534
535 /* EventNotification Request message */
536 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
537
538 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
539 {
540 U16 Reserved1; /* 0x00 */
541 U8 ChainOffset; /* 0x02 */
542 U8 Function; /* 0x03 */
543 U16 Reserved2; /* 0x04 */
544 U8 Reserved3; /* 0x06 */
545 U8 MsgFlags; /* 0x07 */
546 U8 VP_ID; /* 0x08 */
547 U8 VF_ID; /* 0x09 */
548 U16 Reserved4; /* 0x0A */
549 U32 Reserved5; /* 0x0C */
550 U32 Reserved6; /* 0x10 */
551 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
552 U16 SASBroadcastPrimitiveMasks; /* 0x24 */
553 U16 SASNotifyPrimitiveMasks; /* 0x26 */
554 U32 Reserved8; /* 0x28 */
555 } MPI2_EVENT_NOTIFICATION_REQUEST,
556 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
557 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
558
559
560 /* EventNotification Reply message */
561 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
562 {
563 U16 EventDataLength; /* 0x00 */
564 U8 MsgLength; /* 0x02 */
565 U8 Function; /* 0x03 */
566 U16 Reserved1; /* 0x04 */
567 U8 AckRequired; /* 0x06 */
568 U8 MsgFlags; /* 0x07 */
569 U8 VP_ID; /* 0x08 */
570 U8 VF_ID; /* 0x09 */
571 U16 Reserved2; /* 0x0A */
572 U16 Reserved3; /* 0x0C */
573 U16 IOCStatus; /* 0x0E */
574 U32 IOCLogInfo; /* 0x10 */
575 U16 Event; /* 0x14 */
576 U16 Reserved4; /* 0x16 */
577 U32 EventContext; /* 0x18 */
578 U32 EventData[1]; /* 0x1C */
579 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
580 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
581
582 /* AckRequired */
583 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
584 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
585
586 /* Event */
587 #define MPI2_EVENT_LOG_DATA (0x0001)
588 #define MPI2_EVENT_STATE_CHANGE (0x0002)
589 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
590 #define MPI2_EVENT_EVENT_CHANGE (0x000A)
591 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */
592 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
593 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
594 #define MPI2_EVENT_SAS_DISCOVERY (0x0016)
595 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
596 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
597 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
598 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
599 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
600 #define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D) /* MPI v2.6 and later */
601 #define MPI2_EVENT_IR_VOLUME (0x001E)
602 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
603 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
604 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
605 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
606 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
607 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
608 #define MPI2_EVENT_SAS_QUIESCE (0x0025)
609 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
610 #define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
611 #define MPI2_EVENT_HOST_MESSAGE (0x0028)
612 #define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
613 #define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030) /* MPI v2.6 and later */
614 #define MPI2_EVENT_PCIE_ENUMERATION (0x0031) /* MPI v2.6 and later */
615 #define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032) /* MPI v2.6 and later */
616 #define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033) /* MPI v2.6 and later */
617 #define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034) /* MPI v2.6 and later */
618 #define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x0035) /* MPI v2.5 and later */
619 #define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
620 #define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
621
622
623 /* Log Entry Added Event data */
624
625 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
626 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
627
628 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
629 {
630 U64 TimeStamp; /* 0x00 */
631 U32 Reserved1; /* 0x08 */
632 U16 LogSequence; /* 0x0C */
633 U16 LogEntryQualifier; /* 0x0E */
634 U8 VP_ID; /* 0x10 */
635 U8 VF_ID; /* 0x11 */
636 U16 Reserved2; /* 0x12 */
637 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
638 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
639 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
640 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
641
642
643 /* GPIO Interrupt Event data */
644
645 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT
646 {
647 U8 GPIONum; /* 0x00 */
648 U8 Reserved1; /* 0x01 */
649 U16 Reserved2; /* 0x02 */
650 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
651 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
652 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
653
654
655 /* Temperature Threshold Event data */
656
657 typedef struct _MPI2_EVENT_DATA_TEMPERATURE
658 {
659 U16 Status; /* 0x00 */
660 U8 SensorNum; /* 0x02 */
661 U8 Reserved1; /* 0x03 */
662 U16 CurrentTemperature; /* 0x04 */
663 U16 Reserved2; /* 0x06 */
664 U32 Reserved3; /* 0x08 */
665 U32 Reserved4; /* 0x0C */
666 } MPI2_EVENT_DATA_TEMPERATURE,
667 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
668 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
669
670 /* Temperature Threshold Event data Status bits */
671 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
672 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
673 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
674 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
675
676
677 /* Host Message Event data */
678
679 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE
680 {
681 U8 SourceVF_ID; /* 0x00 */
682 U8 Reserved1; /* 0x01 */
683 U16 Reserved2; /* 0x02 */
684 U32 Reserved3; /* 0x04 */
685 U32 HostData[1]; /* 0x08 */
686 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
687 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
688
689
690 /* Power Performance Change Event data */
691
692 typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE
693 {
694 U8 CurrentPowerMode; /* 0x00 */
695 U8 PreviousPowerMode; /* 0x01 */
696 U16 Reserved1; /* 0x02 */
697 } MPI2_EVENT_DATA_POWER_PERF_CHANGE,
698 MPI2_POINTER PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
699 Mpi2EventDataPowerPerfChange_t, MPI2_POINTER pMpi2EventDataPowerPerfChange_t;
700
701 /* defines for CurrentPowerMode and PreviousPowerMode fields */
702 #define MPI2_EVENT_PM_INIT_MASK (0xC0)
703 #define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00)
704 #define MPI2_EVENT_PM_INIT_HOST (0x40)
705 #define MPI2_EVENT_PM_INIT_IO_UNIT (0x80)
706 #define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0)
707
708 #define MPI2_EVENT_PM_MODE_MASK (0x07)
709 #define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
710 #define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
711 #define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
712 #define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
713 #define MPI2_EVENT_PM_MODE_STANDBY (0x06)
714
715
716 /* Active Cable Exception Event data */
717
718 typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT
719 {
720 U32 ActiveCablePowerRequirement; /* 0x00 */
721 U8 ReasonCode; /* 0x04 */
722 U8 ReceptacleID; /* 0x05 */
723 U16 Reserved1; /* 0x06 */
724 } MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
725 MPI2_POINTER PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
726 Mpi25EventDataActiveCableExcept_t,
727 MPI2_POINTER pMpi25EventDataActiveCableExcept_t,
728 MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
729 MPI2_POINTER PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
730 Mpi26EventDataActiveCableExcept_t,
731 MPI2_POINTER pMpi26EventDataActiveCableExcept_t;
732
733 /* MPI2.5 defines for the ReasonCode field */
734 #define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
735 #define MPI25_EVENT_ACTIVE_CABLE_PRESENT (0x01)
736 #define MPI25_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
737
738 /* MPI2.6 defines for the ReasonCode field */
739 #define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
740 #define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01)
741 #define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
742
743 /* Hard Reset Received Event data */
744
745 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
746 {
747 U8 Reserved1; /* 0x00 */
748 U8 Port; /* 0x01 */
749 U16 Reserved2; /* 0x02 */
750 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
751 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
752 Mpi2EventDataHardResetReceived_t,
753 MPI2_POINTER pMpi2EventDataHardResetReceived_t;
754
755
756 /* Task Set Full Event data */
757 /* this event is obsolete */
758
759 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
760 {
761 U16 DevHandle; /* 0x00 */
762 U16 CurrentDepth; /* 0x02 */
763 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
764 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
765
766
767 /* SAS Device Status Change Event data */
768
769 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
770 {
771 U16 TaskTag; /* 0x00 */
772 U8 ReasonCode; /* 0x02 */
773 U8 PhysicalPort; /* 0x03 */
774 U8 ASC; /* 0x04 */
775 U8 ASCQ; /* 0x05 */
776 U16 DevHandle; /* 0x06 */
777 U32 Reserved2; /* 0x08 */
778 U64 SASAddress; /* 0x0C */
779 U8 LUN[8]; /* 0x14 */
780 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
781 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
782 Mpi2EventDataSasDeviceStatusChange_t,
783 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
784
785 /* SAS Device Status Change Event data ReasonCode values */
786 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
787 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
788 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
789 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
790 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
791 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
792 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
793 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
794 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
795 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
796 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
797 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
798 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
799
800
801 /* Integrated RAID Operation Status Event data */
802
803 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
804 {
805 U16 VolDevHandle; /* 0x00 */
806 U16 Reserved1; /* 0x02 */
807 U8 RAIDOperation; /* 0x04 */
808 U8 PercentComplete; /* 0x05 */
809 U16 Reserved2; /* 0x06 */
810 U32 ElapsedSeconds; /* 0x08 */
811 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
812 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
813 Mpi2EventDataIrOperationStatus_t,
814 MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
815
816 /* Integrated RAID Operation Status Event data RAIDOperation values */
817 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
818 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
819 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
820 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
821 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
822
823
824 /* Integrated RAID Volume Event data */
825
826 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
827 {
828 U16 VolDevHandle; /* 0x00 */
829 U8 ReasonCode; /* 0x02 */
830 U8 Reserved1; /* 0x03 */
831 U32 NewValue; /* 0x04 */
832 U32 PreviousValue; /* 0x08 */
833 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
834 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
835
836 /* Integrated RAID Volume Event data ReasonCode values */
837 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
838 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
839 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
840
841
842 /* Integrated RAID Physical Disk Event data */
843
844 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
845 {
846 U16 Reserved1; /* 0x00 */
847 U8 ReasonCode; /* 0x02 */
848 U8 PhysDiskNum; /* 0x03 */
849 U16 PhysDiskDevHandle; /* 0x04 */
850 U16 Reserved2; /* 0x06 */
851 U16 Slot; /* 0x08 */
852 U16 EnclosureHandle; /* 0x0A */
853 U32 NewValue; /* 0x0C */
854 U32 PreviousValue; /* 0x10 */
855 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
856 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
857 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
858
859 /* Integrated RAID Physical Disk Event data ReasonCode values */
860 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
861 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
862 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
863
864
865 /* Integrated RAID Configuration Change List Event data */
866
867 /*
868 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
869 * one and check NumElements at runtime.
870 */
871 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
872 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
873 #endif
874
875 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
876 {
877 U16 ElementFlags; /* 0x00 */
878 U16 VolDevHandle; /* 0x02 */
879 U8 ReasonCode; /* 0x04 */
880 U8 PhysDiskNum; /* 0x05 */
881 U16 PhysDiskDevHandle; /* 0x06 */
882 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
883 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
884
885 /* IR Configuration Change List Event data ElementFlags values */
886 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
887 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
888 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
889 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
890
891 /* IR Configuration Change List Event data ReasonCode values */
892 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
893 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
894 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
895 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
896 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
897 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
898 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
899 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
900 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
901
902 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
903 {
904 U8 NumElements; /* 0x00 */
905 U8 Reserved1; /* 0x01 */
906 U8 Reserved2; /* 0x02 */
907 U8 ConfigNum; /* 0x03 */
908 U32 Flags; /* 0x04 */
909 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */
910 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
911 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
912 Mpi2EventDataIrConfigChangeList_t,
913 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
914
915 /* IR Configuration Change List Event data Flags values */
916 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
917
918
919 /* SAS Discovery Event data */
920
921 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
922 {
923 U8 Flags; /* 0x00 */
924 U8 ReasonCode; /* 0x01 */
925 U8 PhysicalPort; /* 0x02 */
926 U8 Reserved1; /* 0x03 */
927 U32 DiscoveryStatus; /* 0x04 */
928 } MPI2_EVENT_DATA_SAS_DISCOVERY,
929 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
930 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
931
932 /* SAS Discovery Event data Flags values */
933 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
934 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
935
936 /* SAS Discovery Event data ReasonCode values */
937 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
938 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
939
940 /* SAS Discovery Event data DiscoveryStatus values */
941 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
942 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
943 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
944 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
945 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
946 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
947 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
948 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
949 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
950 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
951 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
952 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
953 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
954 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
955 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
956 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
957 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
958 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
959 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
960 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
961
962
963 /* SAS Broadcast Primitive Event data */
964
965 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
966 {
967 U8 PhyNum; /* 0x00 */
968 U8 Port; /* 0x01 */
969 U8 PortWidth; /* 0x02 */
970 U8 Primitive; /* 0x03 */
971 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
972 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
973 Mpi2EventDataSasBroadcastPrimitive_t,
974 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
975
976 /* defines for the Primitive field */
977 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
978 #define MPI2_EVENT_PRIMITIVE_SES (0x02)
979 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
980 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
981 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
982 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
983 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
984 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
985
986
987 /* SAS Notify Primitive Event data */
988
989 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE
990 {
991 U8 PhyNum; /* 0x00 */
992 U8 Port; /* 0x01 */
993 U8 Reserved1; /* 0x02 */
994 U8 Primitive; /* 0x03 */
995 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
996 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
997 Mpi2EventDataSasNotifyPrimitive_t,
998 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
999
1000 /* defines for the Primitive field */
1001 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
1002 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
1003 #define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
1004 #define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
1005
1006
1007 /* SAS Initiator Device Status Change Event data */
1008
1009 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
1010 {
1011 U8 ReasonCode; /* 0x00 */
1012 U8 PhysicalPort; /* 0x01 */
1013 U16 DevHandle; /* 0x02 */
1014 U64 SASAddress; /* 0x04 */
1015 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
1016 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
1017 Mpi2EventDataSasInitDevStatusChange_t,
1018 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
1019
1020 /* SAS Initiator Device Status Change event ReasonCode values */
1021 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
1022 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
1023
1024
1025 /* SAS Initiator Device Table Overflow Event data */
1026
1027 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
1028 {
1029 U16 MaxInit; /* 0x00 */
1030 U16 CurrentInit; /* 0x02 */
1031 U64 SASAddress; /* 0x04 */
1032 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
1033 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
1034 Mpi2EventDataSasInitTableOverflow_t,
1035 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
1036
1037
1038 /* SAS Topology Change List Event data */
1039
1040 /*
1041 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1042 * one and check NumEntries at runtime.
1043 */
1044 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
1045 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
1046 #endif
1047
1048 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
1049 {
1050 U16 AttachedDevHandle; /* 0x00 */
1051 U8 LinkRate; /* 0x02 */
1052 U8 PhyStatus; /* 0x03 */
1053 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
1054 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
1055
1056 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
1057 {
1058 U16 EnclosureHandle; /* 0x00 */
1059 U16 ExpanderDevHandle; /* 0x02 */
1060 U8 NumPhys; /* 0x04 */
1061 U8 Reserved1; /* 0x05 */
1062 U16 Reserved2; /* 0x06 */
1063 U8 NumEntries; /* 0x08 */
1064 U8 StartPhyNum; /* 0x09 */
1065 U8 ExpStatus; /* 0x0A */
1066 U8 PhysicalPort; /* 0x0B */
1067 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
1068 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
1069 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
1070 Mpi2EventDataSasTopologyChangeList_t,
1071 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
1072
1073 /* values for the ExpStatus field */
1074 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
1075 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
1076 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
1077 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
1078 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
1079
1080 /* defines for the LinkRate field */
1081 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
1082 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
1083 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
1084 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
1085
1086 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
1087 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
1088 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
1089 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
1090 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
1091 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
1092 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
1093 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
1094 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
1095 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
1096 #define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
1097 #define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C)
1098
1099 /* values for the PhyStatus field */
1100 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
1101 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
1102 /* values for the PhyStatus ReasonCode sub-field */
1103 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
1104 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
1105 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
1106 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
1107 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
1108 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
1109
1110
1111 /* SAS Enclosure Device Status Change Event data */
1112
1113 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
1114 {
1115 U16 EnclosureHandle; /* 0x00 */
1116 U8 ReasonCode; /* 0x02 */
1117 U8 PhysicalPort; /* 0x03 */
1118 U64 EnclosureLogicalID; /* 0x04 */
1119 U16 NumSlots; /* 0x0C */
1120 U16 StartSlot; /* 0x0E */
1121 U32 PhyBits; /* 0x10 */
1122 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1123 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1124 Mpi2EventDataSasEnclDevStatusChange_t,
1125 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t,
1126 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1127 MPI2_POINTER PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1128 Mpi26EventDataEnclDevStatusChange_t,
1129 MPI2_POINTER pMpi26EventDataEnclDevStatusChange_t;
1130
1131 /* SAS Enclosure Device Status Change event ReasonCode values */
1132 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
1133 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
1134
1135 /* Enclosure Device Status Change event ReasonCode values */
1136 #define MPI26_EVENT_ENCL_RC_ADDED (0x01)
1137 #define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02)
1138
1139 /* SAS PHY Counter Event data */
1140
1141 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER
1142 {
1143 U64 TimeStamp; /* 0x00 */
1144 U32 Reserved1; /* 0x08 */
1145 U8 PhyEventCode; /* 0x0C */
1146 U8 PhyNum; /* 0x0D */
1147 U16 Reserved2; /* 0x0E */
1148 U32 PhyEventInfo; /* 0x10 */
1149 U8 CounterType; /* 0x14 */
1150 U8 ThresholdWindow; /* 0x15 */
1151 U8 TimeUnits; /* 0x16 */
1152 U8 Reserved3; /* 0x17 */
1153 U32 EventThreshold; /* 0x18 */
1154 U16 ThresholdFlags; /* 0x1C */
1155 U16 Reserved4; /* 0x1E */
1156 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1157 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1158 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
1159
1160 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */
1161
1162 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
1163
1164 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
1165
1166 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
1167
1168
1169 /* SAS Quiesce Event data */
1170
1171 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE
1172 {
1173 U8 ReasonCode; /* 0x00 */
1174 U8 Reserved1; /* 0x01 */
1175 U16 Reserved2; /* 0x02 */
1176 U32 Reserved3; /* 0x04 */
1177 } MPI2_EVENT_DATA_SAS_QUIESCE,
1178 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1179 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
1180
1181 /* SAS Quiesce Event data ReasonCode values */
1182 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
1183 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
1184
1185
1186 typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR
1187 {
1188 U16 DevHandle; /* 0x00 */
1189 U8 ReasonCode; /* 0x02 */
1190 U8 PhysicalPort; /* 0x03 */
1191 U32 Reserved1[2]; /* 0x04 */
1192 U64 SASAddress; /* 0x0C */
1193 U32 Reserved2[2]; /* 0x14 */
1194 } MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1195 MPI2_POINTER PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1196 Mpi25EventDataSasDeviceDiscoveryError_t,
1197 MPI2_POINTER pMpi25EventDataSasDeviceDiscoveryError_t;
1198
1199 /* SAS Device Discovery Error Event data ReasonCode values */
1200 #define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED (0x01)
1201 #define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT (0x02)
1202
1203
1204 /* Host Based Discovery Phy Event data */
1205
1206 typedef struct _MPI2_EVENT_HBD_PHY_SAS
1207 {
1208 U8 Flags; /* 0x00 */
1209 U8 NegotiatedLinkRate; /* 0x01 */
1210 U8 PhyNum; /* 0x02 */
1211 U8 PhysicalPort; /* 0x03 */
1212 U32 Reserved1; /* 0x04 */
1213 U8 InitialFrame[28]; /* 0x08 */
1214 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
1215 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
1216
1217 /* values for the Flags field */
1218 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1219 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1220
1221 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */
1222
1223 typedef union _MPI2_EVENT_HBD_DESCRIPTOR
1224 {
1225 MPI2_EVENT_HBD_PHY_SAS Sas;
1226 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1227 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
1228
1229 typedef struct _MPI2_EVENT_DATA_HBD_PHY
1230 {
1231 U8 DescriptorType; /* 0x00 */
1232 U8 Reserved1; /* 0x01 */
1233 U16 Reserved2; /* 0x02 */
1234 U32 Reserved3; /* 0x04 */
1235 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */
1236 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1237 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1238
1239 /* values for the DescriptorType field */
1240 #define MPI2_EVENT_HBD_DT_SAS (0x01)
1241
1242
1243 /* PCIe Device Status Change Event data (MPI v2.6 and later) */
1244
1245 typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE
1246 {
1247 U16 TaskTag; /* 0x00 */
1248 U8 ReasonCode; /* 0x02 */
1249 U8 PhysicalPort; /* 0x03 */
1250 U8 ASC; /* 0x04 */
1251 U8 ASCQ; /* 0x05 */
1252 U16 DevHandle; /* 0x06 */
1253 U32 Reserved2; /* 0x08 */
1254 U64 WWID; /* 0x0C */
1255 U8 LUN[8]; /* 0x14 */
1256 } MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1257 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1258 Mpi26EventDataPCIeDeviceStatusChange_t,
1259 MPI2_POINTER pMpi26EventDataPCIeDeviceStatusChange_t;
1260
1261 /* PCIe Device Status Change Event data ReasonCode values */
1262 #define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05)
1263 #define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07)
1264 #define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
1265 #define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
1266 #define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
1267 #define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
1268 #define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
1269 #define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
1270 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
1271 #define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
1272 #define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10)
1273
1274
1275 /* PCIe Enumeration Event data (MPI v2.6 and later) */
1276
1277 typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION
1278 {
1279 U8 Flags; /* 0x00 */
1280 U8 ReasonCode; /* 0x01 */
1281 U8 PhysicalPort; /* 0x02 */
1282 U8 Reserved1; /* 0x03 */
1283 U32 EnumerationStatus; /* 0x04 */
1284 } MPI26_EVENT_DATA_PCIE_ENUMERATION,
1285 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION,
1286 Mpi26EventDataPCIeEnumeration_t,
1287 MPI2_POINTER pMpi26EventDataPCIeEnumeration_t;
1288
1289 /* PCIe Enumeration Event data Flags values */
1290 #define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02)
1291 #define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01)
1292
1293 /* PCIe Enumeration Event data ReasonCode values */
1294 #define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01)
1295 #define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)
1296
1297 /* PCIe Enumeration Event data EnumerationStatus values */
1298 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)
1299 #define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)
1300 #define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)
1301
1302
1303 /* PCIe Topology Change List Event data (MPI v2.6 and later) */
1304
1305 /*
1306 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1307 * one and check NumEntries at runtime.
1308 */
1309 #ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT
1310 #define MPI26_EVENT_PCIE_TOPO_PORT_COUNT (1)
1311 #endif
1312
1313 typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY
1314 {
1315 U16 AttachedDevHandle; /* 0x00 */
1316 U8 PortStatus; /* 0x02 */
1317 U8 Reserved1; /* 0x03 */
1318 U8 CurrentPortInfo; /* 0x04 */
1319 U8 Reserved2; /* 0x05 */
1320 U8 PreviousPortInfo; /* 0x06 */
1321 U8 Reserved3; /* 0x07 */
1322 } MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1323 MPI2_POINTER PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1324 Mpi26EventPCIeTopoPortEntry_t,
1325 MPI2_POINTER pMpi26EventPCIeTopoPortEntry_t;
1326
1327 /* PCIe Topology Change List Event data PortStatus values */
1328 #define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01)
1329 #define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)
1330 #define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)
1331 #define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)
1332 #define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
1333
1334 /* PCIe Topology Change List Event data defines for CurrentPortInfo and PreviousPortInfo */
1335 #define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0)
1336 #define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
1337 #define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10)
1338 #define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20)
1339 #define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30)
1340 #define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40)
1341
1342 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F)
1343 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
1344 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
1345 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
1346 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)
1347 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)
1348 #define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)
1349
1350 typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST
1351 {
1352 U16 EnclosureHandle; /* 0x00 */
1353 U16 SwitchDevHandle; /* 0x02 */
1354 U8 NumPorts; /* 0x04 */
1355 U8 Reserved1; /* 0x05 */
1356 U16 Reserved2; /* 0x06 */
1357 U8 NumEntries; /* 0x08 */
1358 U8 StartPortNum; /* 0x09 */
1359 U8 SwitchStatus; /* 0x0A */
1360 U8 PhysicalPort; /* 0x0B */
1361 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /* 0x0C */
1362 } MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1363 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1364 Mpi26EventDataPCIeTopologyChangeList_t,
1365 MPI2_POINTER pMpi26EventDataPCIeTopologyChangeList_t;
1366
1367 /* PCIe Topology Change List Event data SwitchStatus values */
1368 #define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)
1369 #define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01)
1370 #define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
1371 #define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
1372 #define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
1373
1374 /* PCIe Link Counter Event data (MPI v2.6 and later) */
1375
1376 typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER
1377 {
1378 U64 TimeStamp; /* 0x00 */
1379 U32 Reserved1; /* 0x08 */
1380 U8 LinkEventCode; /* 0x0C */
1381 U8 LinkNum; /* 0x0D */
1382 U16 Reserved2; /* 0x0E */
1383 U32 LinkEventInfo; /* 0x10 */
1384 U8 CounterType; /* 0x14 */
1385 U8 ThresholdWindow; /* 0x15 */
1386 U8 TimeUnits; /* 0x16 */
1387 U8 Reserved3; /* 0x17 */
1388 U32 EventThreshold; /* 0x18 */
1389 U16 ThresholdFlags; /* 0x1C */
1390 U16 Reserved4; /* 0x1E */
1391 } MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1392 MPI2_POINTER PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1393 Mpi26EventDataPcieLinkCounter_t, MPI2_POINTER pMpi26EventDataPcieLinkCounter_t;
1394
1395
1396 /* use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode field */
1397
1398 /* use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */
1399
1400 /* use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */
1401
1402 /* use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */
1403
1404 /****************************************************************************
1405 * EventAck message
1406 ****************************************************************************/
1407
1408 /* EventAck Request message */
1409 typedef struct _MPI2_EVENT_ACK_REQUEST
1410 {
1411 U16 Reserved1; /* 0x00 */
1412 U8 ChainOffset; /* 0x02 */
1413 U8 Function; /* 0x03 */
1414 U16 Reserved2; /* 0x04 */
1415 U8 Reserved3; /* 0x06 */
1416 U8 MsgFlags; /* 0x07 */
1417 U8 VP_ID; /* 0x08 */
1418 U8 VF_ID; /* 0x09 */
1419 U16 Reserved4; /* 0x0A */
1420 U16 Event; /* 0x0C */
1421 U16 Reserved5; /* 0x0E */
1422 U32 EventContext; /* 0x10 */
1423 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1424 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
1425
1426
1427 /* EventAck Reply message */
1428 typedef struct _MPI2_EVENT_ACK_REPLY
1429 {
1430 U16 Reserved1; /* 0x00 */
1431 U8 MsgLength; /* 0x02 */
1432 U8 Function; /* 0x03 */
1433 U16 Reserved2; /* 0x04 */
1434 U8 Reserved3; /* 0x06 */
1435 U8 MsgFlags; /* 0x07 */
1436 U8 VP_ID; /* 0x08 */
1437 U8 VF_ID; /* 0x09 */
1438 U16 Reserved4; /* 0x0A */
1439 U16 Reserved5; /* 0x0C */
1440 U16 IOCStatus; /* 0x0E */
1441 U32 IOCLogInfo; /* 0x10 */
1442 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1443 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1444
1445
1446 /****************************************************************************
1447 * SendHostMessage message
1448 ****************************************************************************/
1449
1450 /* SendHostMessage Request message */
1451 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST
1452 {
1453 U16 HostDataLength; /* 0x00 */
1454 U8 ChainOffset; /* 0x02 */
1455 U8 Function; /* 0x03 */
1456 U16 Reserved1; /* 0x04 */
1457 U8 Reserved2; /* 0x06 */
1458 U8 MsgFlags; /* 0x07 */
1459 U8 VP_ID; /* 0x08 */
1460 U8 VF_ID; /* 0x09 */
1461 U16 Reserved3; /* 0x0A */
1462 U8 Reserved4; /* 0x0C */
1463 U8 DestVF_ID; /* 0x0D */
1464 U16 Reserved5; /* 0x0E */
1465 U32 Reserved6; /* 0x10 */
1466 U32 Reserved7; /* 0x14 */
1467 U32 Reserved8; /* 0x18 */
1468 U32 Reserved9; /* 0x1C */
1469 U32 Reserved10; /* 0x20 */
1470 U32 HostData[1]; /* 0x24 */
1471 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1472 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1473 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
1474
1475
1476 /* SendHostMessage Reply message */
1477 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY
1478 {
1479 U16 HostDataLength; /* 0x00 */
1480 U8 MsgLength; /* 0x02 */
1481 U8 Function; /* 0x03 */
1482 U16 Reserved1; /* 0x04 */
1483 U8 Reserved2; /* 0x06 */
1484 U8 MsgFlags; /* 0x07 */
1485 U8 VP_ID; /* 0x08 */
1486 U8 VF_ID; /* 0x09 */
1487 U16 Reserved3; /* 0x0A */
1488 U16 Reserved4; /* 0x0C */
1489 U16 IOCStatus; /* 0x0E */
1490 U32 IOCLogInfo; /* 0x10 */
1491 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1492 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
1493
1494
1495 /****************************************************************************
1496 * FWDownload message
1497 ****************************************************************************/
1498
1499 /* MPI v2.0 FWDownload Request message */
1500 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1501 {
1502 U8 ImageType; /* 0x00 */
1503 U8 Reserved1; /* 0x01 */
1504 U8 ChainOffset; /* 0x02 */
1505 U8 Function; /* 0x03 */
1506 U16 Reserved2; /* 0x04 */
1507 U8 Reserved3; /* 0x06 */
1508 U8 MsgFlags; /* 0x07 */
1509 U8 VP_ID; /* 0x08 */
1510 U8 VF_ID; /* 0x09 */
1511 U16 Reserved4; /* 0x0A */
1512 U32 TotalImageSize; /* 0x0C */
1513 U32 Reserved5; /* 0x10 */
1514 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1515 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1516 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1517
1518 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1519
1520 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1521 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1522 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1523 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1524 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1525 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1526 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1527 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1528 #define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C) /* MPI v2.5 and newer */
1529 #define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP (0x0D)
1530 #define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E)
1531 #define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F)
1532 #define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10)
1533 #define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11)
1534 #define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12)
1535 #define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13)
1536 #define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14)
1537 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1538
1539 /* MPI v2.0 FWDownload TransactionContext Element */
1540 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1541 {
1542 U8 Reserved1; /* 0x00 */
1543 U8 ContextSize; /* 0x01 */
1544 U8 DetailsLength; /* 0x02 */
1545 U8 Flags; /* 0x03 */
1546 U32 Reserved2; /* 0x04 */
1547 U32 ImageOffset; /* 0x08 */
1548 U32 ImageSize; /* 0x0C */
1549 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1550 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1551
1552
1553 /* MPI v2.5 FWDownload Request message */
1554 typedef struct _MPI25_FW_DOWNLOAD_REQUEST
1555 {
1556 U8 ImageType; /* 0x00 */
1557 U8 Reserved1; /* 0x01 */
1558 U8 ChainOffset; /* 0x02 */
1559 U8 Function; /* 0x03 */
1560 U16 Reserved2; /* 0x04 */
1561 U8 Reserved3; /* 0x06 */
1562 U8 MsgFlags; /* 0x07 */
1563 U8 VP_ID; /* 0x08 */
1564 U8 VF_ID; /* 0x09 */
1565 U16 Reserved4; /* 0x0A */
1566 U32 TotalImageSize; /* 0x0C */
1567 U32 Reserved5; /* 0x10 */
1568 U32 Reserved6; /* 0x14 */
1569 U32 ImageOffset; /* 0x18 */
1570 U32 ImageSize; /* 0x1C */
1571 MPI25_SGE_IO_UNION SGL; /* 0x20 */
1572 } MPI25_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_DOWNLOAD_REQUEST,
1573 Mpi25FWDownloadRequest, MPI2_POINTER pMpi25FWDownloadRequest;
1574
1575
1576 /* FWDownload Reply message */
1577 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1578 {
1579 U8 ImageType; /* 0x00 */
1580 U8 Reserved1; /* 0x01 */
1581 U8 MsgLength; /* 0x02 */
1582 U8 Function; /* 0x03 */
1583 U16 Reserved2; /* 0x04 */
1584 U8 Reserved3; /* 0x06 */
1585 U8 MsgFlags; /* 0x07 */
1586 U8 VP_ID; /* 0x08 */
1587 U8 VF_ID; /* 0x09 */
1588 U16 Reserved4; /* 0x0A */
1589 U16 Reserved5; /* 0x0C */
1590 U16 IOCStatus; /* 0x0E */
1591 U32 IOCLogInfo; /* 0x10 */
1592 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1593 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1594
1595
1596 /****************************************************************************
1597 * FWUpload message
1598 ****************************************************************************/
1599
1600 /* MPI v2.0 FWUpload Request message */
1601 typedef struct _MPI2_FW_UPLOAD_REQUEST
1602 {
1603 U8 ImageType; /* 0x00 */
1604 U8 Reserved1; /* 0x01 */
1605 U8 ChainOffset; /* 0x02 */
1606 U8 Function; /* 0x03 */
1607 U16 Reserved2; /* 0x04 */
1608 U8 Reserved3; /* 0x06 */
1609 U8 MsgFlags; /* 0x07 */
1610 U8 VP_ID; /* 0x08 */
1611 U8 VF_ID; /* 0x09 */
1612 U16 Reserved4; /* 0x0A */
1613 U32 Reserved5; /* 0x0C */
1614 U32 Reserved6; /* 0x10 */
1615 MPI2_MPI_SGE_UNION SGL; /* 0x14 */
1616 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1617 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1618
1619 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1620 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1621 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1622 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1623 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1624 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1625 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1626 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1627 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1628 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1629 #define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D)
1630 #define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E)
1631 #define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F)
1632 #define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10)
1633 #define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11)
1634 #define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12)
1635 #define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13)
1636 #define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14)
1637
1638 /* MPI v2.0 FWUpload TransactionContext Element */
1639 typedef struct _MPI2_FW_UPLOAD_TCSGE
1640 {
1641 U8 Reserved1; /* 0x00 */
1642 U8 ContextSize; /* 0x01 */
1643 U8 DetailsLength; /* 0x02 */
1644 U8 Flags; /* 0x03 */
1645 U32 Reserved2; /* 0x04 */
1646 U32 ImageOffset; /* 0x08 */
1647 U32 ImageSize; /* 0x0C */
1648 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1649 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1650
1651
1652 /* MPI v2.5 FWUpload Request message */
1653 typedef struct _MPI25_FW_UPLOAD_REQUEST
1654 {
1655 U8 ImageType; /* 0x00 */
1656 U8 Reserved1; /* 0x01 */
1657 U8 ChainOffset; /* 0x02 */
1658 U8 Function; /* 0x03 */
1659 U16 Reserved2; /* 0x04 */
1660 U8 Reserved3; /* 0x06 */
1661 U8 MsgFlags; /* 0x07 */
1662 U8 VP_ID; /* 0x08 */
1663 U8 VF_ID; /* 0x09 */
1664 U16 Reserved4; /* 0x0A */
1665 U32 Reserved5; /* 0x0C */
1666 U32 Reserved6; /* 0x10 */
1667 U32 Reserved7; /* 0x14 */
1668 U32 ImageOffset; /* 0x18 */
1669 U32 ImageSize; /* 0x1C */
1670 MPI25_SGE_IO_UNION SGL; /* 0x20 */
1671 } MPI25_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI25_FW_UPLOAD_REQUEST,
1672 Mpi25FWUploadRequest_t, MPI2_POINTER pMpi25FWUploadRequest_t;
1673
1674
1675 /* FWUpload Reply message */
1676 typedef struct _MPI2_FW_UPLOAD_REPLY
1677 {
1678 U8 ImageType; /* 0x00 */
1679 U8 Reserved1; /* 0x01 */
1680 U8 MsgLength; /* 0x02 */
1681 U8 Function; /* 0x03 */
1682 U16 Reserved2; /* 0x04 */
1683 U8 Reserved3; /* 0x06 */
1684 U8 MsgFlags; /* 0x07 */
1685 U8 VP_ID; /* 0x08 */
1686 U8 VF_ID; /* 0x09 */
1687 U16 Reserved4; /* 0x0A */
1688 U16 Reserved5; /* 0x0C */
1689 U16 IOCStatus; /* 0x0E */
1690 U32 IOCLogInfo; /* 0x10 */
1691 U32 ActualImageSize; /* 0x14 */
1692 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1693 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1694
1695
1696 /* FW Image Header */
1697 typedef struct _MPI2_FW_IMAGE_HEADER
1698 {
1699 U32 Signature; /* 0x00 */
1700 U32 Signature0; /* 0x04 */
1701 U32 Signature1; /* 0x08 */
1702 U32 Signature2; /* 0x0C */
1703 MPI2_VERSION_UNION MPIVersion; /* 0x10 */
1704 MPI2_VERSION_UNION FWVersion; /* 0x14 */
1705 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */
1706 MPI2_VERSION_UNION PackageVersion; /* 0x1C */
1707 U16 VendorID; /* 0x20 */
1708 U16 ProductID; /* 0x22 */
1709 U16 ProtocolFlags; /* 0x24 */
1710 U16 Reserved26; /* 0x26 */
1711 U32 IOCCapabilities; /* 0x28 */
1712 U32 ImageSize; /* 0x2C */
1713 U32 NextImageHeaderOffset; /* 0x30 */
1714 U32 Checksum; /* 0x34 */
1715 U32 Reserved38; /* 0x38 */
1716 U32 Reserved3C; /* 0x3C */
1717 U32 Reserved40; /* 0x40 */
1718 U32 Reserved44; /* 0x44 */
1719 U32 Reserved48; /* 0x48 */
1720 U32 Reserved4C; /* 0x4C */
1721 U32 Reserved50; /* 0x50 */
1722 U32 Reserved54; /* 0x54 */
1723 U32 Reserved58; /* 0x58 */
1724 U32 Reserved5C; /* 0x5C */
1725 U32 BootFlags; /* 0x60 */ /* reserved in MPI v2.5 and earlier */
1726 U32 FirmwareVersionNameWhat; /* 0x64 */
1727 U8 FirmwareVersionName[32]; /* 0x68 */
1728 U32 VendorNameWhat; /* 0x88 */
1729 U8 VendorName[32]; /* 0x8C */
1730 U32 PackageNameWhat; /* 0x88 */
1731 U8 PackageName[32]; /* 0x8C */
1732 U32 ReservedD0; /* 0xD0 */
1733 U32 ReservedD4; /* 0xD4 */
1734 U32 ReservedD8; /* 0xD8 */
1735 U32 ReservedDC; /* 0xDC */
1736 U32 ReservedE0; /* 0xE0 */
1737 U32 ReservedE4; /* 0xE4 */
1738 U32 ReservedE8; /* 0xE8 */
1739 U32 ReservedEC; /* 0xEC */
1740 U32 ReservedF0; /* 0xF0 */
1741 U32 ReservedF4; /* 0xF4 */
1742 U32 ReservedF8; /* 0xF8 */
1743 U32 ReservedFC; /* 0xFC */
1744 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1745 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1746
1747 /* Signature field */
1748 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1749 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1750 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1751 #define MPI26_FW_HEADER_SIGNATURE (0xEB000000)
1752
1753 /* Signature0 field */
1754 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1755 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1756 #define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500) /* Last byte is defined by architecture */
1757 #define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A)
1758 #define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00)
1759 #define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01)
1760 #define MPI26_FW_HEADER_SIGNATURE0_ARC_3 (0x02)
1761 #define MPI26_FW_HEADER_SIGNATURE0 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0) // legacy (0x5AEAA55A)
1762 #define MPI26_FW_HEADER_SIGNATURE0_3516 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1)
1763 #define MPI26_FW_HEADER_SIGNATURE0_4008 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_3)
1764
1765 /* Signature1 field */
1766 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1767 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1768 #define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5)
1769
1770 /* Signature2 field */
1771 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1772 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1773 #define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA)
1774
1775
1776 /* defines for using the ProductID field */
1777 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1778 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1779
1780 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1781 #define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1782 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1783 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1784
1785
1786 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1787 /* SAS ProductID Family bits */
1788 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1789 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1790 #define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1791 #define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028)
1792 #define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031)
1793
1794 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1795
1796 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1797
1798
1799 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1800 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1801 #define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60)
1802 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1803
1804 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1805
1806 #define MPI2_FW_HEADER_SIZE (0x100)
1807
1808
1809 /* Extended Image Header */
1810 typedef struct _MPI2_EXT_IMAGE_HEADER
1811
1812 {
1813 U8 ImageType; /* 0x00 */
1814 U8 Reserved1; /* 0x01 */
1815 U16 Reserved2; /* 0x02 */
1816 U32 Checksum; /* 0x04 */
1817 U32 ImageSize; /* 0x08 */
1818 U32 NextImageHeaderOffset; /* 0x0C */
1819 U32 PackageVersion; /* 0x10 */
1820 U32 Reserved3; /* 0x14 */
1821 U32 Reserved4; /* 0x18 */
1822 U32 Reserved5; /* 0x1C */
1823 U8 IdentifyString[32]; /* 0x20 */
1824 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1825 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1826
1827 /* useful offsets */
1828 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1829 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1830 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1831
1832 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1833
1834 /* defines for the ImageType field */
1835 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1836 #define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1837 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1838 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1839 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1840 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1841 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1842 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1843 #define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09) /* MPI v2.5 and newer */
1844 #define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
1845 #define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
1846
1847 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC) /* deprecated */
1848
1849
1850
1851 /* FLASH Layout Extended Image Data */
1852
1853 /*
1854 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1855 * one and check RegionsPerLayout at runtime.
1856 */
1857 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1858 #define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1859 #endif
1860
1861 /*
1862 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1863 * one and check NumberOfLayouts at runtime.
1864 */
1865 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1866 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1867 #endif
1868
1869 typedef struct _MPI2_FLASH_REGION
1870 {
1871 U8 RegionType; /* 0x00 */
1872 U8 Reserved1; /* 0x01 */
1873 U16 Reserved2; /* 0x02 */
1874 U32 RegionOffset; /* 0x04 */
1875 U32 RegionSize; /* 0x08 */
1876 U32 Reserved3; /* 0x0C */
1877 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1878 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1879
1880 typedef struct _MPI2_FLASH_LAYOUT
1881 {
1882 U32 FlashSize; /* 0x00 */
1883 U32 Reserved1; /* 0x04 */
1884 U32 Reserved2; /* 0x08 */
1885 U32 Reserved3; /* 0x0C */
1886 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1887 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1888 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1889
1890 typedef struct _MPI2_FLASH_LAYOUT_DATA
1891 {
1892 U8 ImageRevision; /* 0x00 */
1893 U8 Reserved1; /* 0x01 */
1894 U8 SizeOfRegion; /* 0x02 */
1895 U8 Reserved2; /* 0x03 */
1896 U16 NumberOfLayouts; /* 0x04 */
1897 U16 RegionsPerLayout; /* 0x06 */
1898 U16 MinimumSectorAlignment; /* 0x08 */
1899 U16 Reserved3; /* 0x0A */
1900 U32 Reserved4; /* 0x0C */
1901 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1902 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1903 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1904
1905 /* defines for the RegionType field */
1906 #define MPI2_FLASH_REGION_UNUSED (0x00)
1907 #define MPI2_FLASH_REGION_FIRMWARE (0x01)
1908 #define MPI2_FLASH_REGION_BIOS (0x02)
1909 #define MPI2_FLASH_REGION_NVDATA (0x03)
1910 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1911 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1912 #define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1913 #define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1914 #define MPI2_FLASH_REGION_MEGARAID (0x09)
1915 #define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A)
1916 #define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK) /* older name */
1917 #define MPI2_FLASH_REGION_CBB_BACKUP (0x0D)
1918 #define MPI2_FLASH_REGION_SBR (0x0E)
1919 #define MPI2_FLASH_REGION_SBR_BACKUP (0x0F)
1920 #define MPI2_FLASH_REGION_HIIM (0x10)
1921 #define MPI2_FLASH_REGION_HIIA (0x11)
1922 #define MPI2_FLASH_REGION_CTLR (0x12)
1923 #define MPI2_FLASH_REGION_IMR_FIRMWARE (0x13)
1924 #define MPI2_FLASH_REGION_MR_NVDATA (0x14)
1925
1926 /* ImageRevision */
1927 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1928
1929
1930
1931 /* Supported Devices Extended Image Data */
1932
1933 /*
1934 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1935 * one and check NumberOfDevices at runtime.
1936 */
1937 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1938 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1939 #endif
1940
1941 typedef struct _MPI2_SUPPORTED_DEVICE
1942 {
1943 U16 DeviceID; /* 0x00 */
1944 U16 VendorID; /* 0x02 */
1945 U16 DeviceIDMask; /* 0x04 */
1946 U16 Reserved1; /* 0x06 */
1947 U8 LowPCIRev; /* 0x08 */
1948 U8 HighPCIRev; /* 0x09 */
1949 U16 Reserved2; /* 0x0A */
1950 U32 Reserved3; /* 0x0C */
1951 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1952 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1953
1954 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1955 {
1956 U8 ImageRevision; /* 0x00 */
1957 U8 Reserved1; /* 0x01 */
1958 U8 NumberOfDevices; /* 0x02 */
1959 U8 Reserved2; /* 0x03 */
1960 U32 Reserved3; /* 0x04 */
1961 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1962 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1963 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1964
1965 /* ImageRevision */
1966 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1967
1968
1969 /* Init Extended Image Data */
1970
1971 typedef struct _MPI2_INIT_IMAGE_FOOTER
1972
1973 {
1974 U32 BootFlags; /* 0x00 */
1975 U32 ImageSize; /* 0x04 */
1976 U32 Signature0; /* 0x08 */
1977 U32 Signature1; /* 0x0C */
1978 U32 Signature2; /* 0x10 */
1979 U32 ResetVector; /* 0x14 */
1980 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1981 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1982
1983 /* defines for the BootFlags field */
1984 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1985
1986 /* defines for the ImageSize field */
1987 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1988
1989 /* defines for the Signature0 field */
1990 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1991 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1992
1993 /* defines for the Signature1 field */
1994 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1995 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1996
1997 /* defines for the Signature2 field */
1998 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1999 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
2000
2001 /* Signature fields as individual bytes */
2002 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
2003 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
2004 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
2005 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
2006
2007 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
2008 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
2009 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
2010 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
2011
2012 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
2013 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
2014 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
2015 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
2016
2017 /* defines for the ResetVector field */
2018 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
2019
2020
2021 /* Encrypted Hash Extended Image Data */
2022
2023 typedef struct _MPI25_ENCRYPTED_HASH_ENTRY
2024 {
2025 U8 HashImageType; /* 0x00 */
2026 U8 HashAlgorithm; /* 0x01 */
2027 U8 EncryptionAlgorithm; /* 0x02 */
2028 U8 Reserved1; /* 0x03 */
2029 U32 Reserved2; /* 0x04 */
2030 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */
2031 } MPI25_ENCRYPTED_HASH_ENTRY, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_ENTRY,
2032 Mpi25EncryptedHashEntry_t, MPI2_POINTER pMpi25EncryptedHashEntry_t;
2033
2034 /* values for HashImageType */
2035 #define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00)
2036 #define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01)
2037 #define MPI25_HASH_IMAGE_TYPE_BIOS (0x02)
2038
2039 /* values for HashAlgorithm */
2040 #define MPI25_HASH_ALGORITHM_UNUSED (0x00)
2041 #define MPI25_HASH_ALGORITHM_SHA256 (0x01)
2042
2043 /* values for EncryptionAlgorithm */
2044 #define MPI25_ENCRYPTION_ALG_UNUSED (0x00)
2045 #define MPI25_ENCRYPTION_ALG_RSA256 (0x01)
2046
2047 typedef struct _MPI25_ENCRYPTED_HASH_DATA
2048 {
2049 U8 ImageVersion; /* 0x00 */
2050 U8 NumHash; /* 0x01 */
2051 U16 Reserved1; /* 0x02 */
2052 U32 Reserved2; /* 0x04 */
2053 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */ /* variable number of entries */
2054 } MPI25_ENCRYPTED_HASH_DATA, MPI2_POINTER PTR_MPI25_ENCRYPTED_HASH_DATA,
2055 Mpi25EncryptedHashData_t, MPI2_POINTER pMpi25EncryptedHashData_t;
2056
2057 /****************************************************************************
2058 * PowerManagementControl message
2059 ****************************************************************************/
2060
2061 /* PowerManagementControl Request message */
2062 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST
2063 {
2064 U8 Feature; /* 0x00 */
2065 U8 Reserved1; /* 0x01 */
2066 U8 ChainOffset; /* 0x02 */
2067 U8 Function; /* 0x03 */
2068 U16 Reserved2; /* 0x04 */
2069 U8 Reserved3; /* 0x06 */
2070 U8 MsgFlags; /* 0x07 */
2071 U8 VP_ID; /* 0x08 */
2072 U8 VF_ID; /* 0x09 */
2073 U16 Reserved4; /* 0x0A */
2074 U8 Parameter1; /* 0x0C */
2075 U8 Parameter2; /* 0x0D */
2076 U8 Parameter3; /* 0x0E */
2077 U8 Parameter4; /* 0x0F */
2078 U32 Reserved5; /* 0x10 */
2079 U32 Reserved6; /* 0x14 */
2080 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
2081 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
2082
2083 /* defines for the Feature field */
2084 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
2085 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
2086 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /* obsolete */
2087 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
2088 #define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05) /* reserved in MPI 2.0 */
2089 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
2090 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
2091
2092 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
2093 /* Parameter1 contains a PHY number */
2094 /* Parameter2 indicates power condition action using these defines */
2095 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
2096 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
2097 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
2098 /* Parameter3 and Parameter4 are reserved */
2099
2100 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */
2101 /* Parameter1 contains SAS port width modulation group number */
2102 /* Parameter2 indicates IOC action using these defines */
2103 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
2104 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
2105 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
2106 /* Parameter3 indicates desired modulation level using these defines */
2107 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
2108 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
2109 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
2110 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
2111 /* Parameter4 is reserved */
2112
2113 /* this next set (_PCIE_LINK) is obsolete */
2114 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
2115 /* Parameter1 indicates desired PCIe link speed using these defines */
2116 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /* obsolete */
2117 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /* obsolete */
2118 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /* obsolete */
2119 /* Parameter2 indicates desired PCIe link width using these defines */
2120 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /* obsolete */
2121 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /* obsolete */
2122 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /* obsolete */
2123 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /* obsolete */
2124 /* Parameter3 and Parameter4 are reserved */
2125
2126 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
2127 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
2128 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
2129 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
2130 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
2131 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
2132 /* Parameter2, Parameter3, and Parameter4 are reserved */
2133
2134 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature */
2135 /* Parameter1 indicates host action regarding global power management mode */
2136 #define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01)
2137 #define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02)
2138 #define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03)
2139 /* Parameter2 indicates the requested global power management mode */
2140 #define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01)
2141 #define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08)
2142 #define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40)
2143 /* Parameter3 and Parameter4 are reserved */
2144
2145
2146 /* PowerManagementControl Reply message */
2147 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY
2148 {
2149 U8 Feature; /* 0x00 */
2150 U8 Reserved1; /* 0x01 */
2151 U8 MsgLength; /* 0x02 */
2152 U8 Function; /* 0x03 */
2153 U16 Reserved2; /* 0x04 */
2154 U8 Reserved3; /* 0x06 */
2155 U8 MsgFlags; /* 0x07 */
2156 U8 VP_ID; /* 0x08 */
2157 U8 VF_ID; /* 0x09 */
2158 U16 Reserved4; /* 0x0A */
2159 U16 Reserved5; /* 0x0C */
2160 U16 IOCStatus; /* 0x0E */
2161 U32 IOCLogInfo; /* 0x10 */
2162 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
2163 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
2164
2165
2166 /****************************************************************************
2167 * IO Unit Control messages (MPI v2.6 and later only.)
2168 ****************************************************************************/
2169
2170 /* IO Unit Control Request Message */
2171 typedef struct _MPI26_IOUNIT_CONTROL_REQUEST
2172 {
2173 U8 Operation; /* 0x00 */
2174 U8 Reserved1; /* 0x01 */
2175 U8 ChainOffset; /* 0x02 */
2176 U8 Function; /* 0x03 */
2177 U16 DevHandle; /* 0x04 */
2178 U8 IOCParameter; /* 0x06 */
2179 U8 MsgFlags; /* 0x07 */
2180 U8 VP_ID; /* 0x08 */
2181 U8 VF_ID; /* 0x09 */
2182 U16 Reserved3; /* 0x0A */
2183 U16 Reserved4; /* 0x0C */
2184 U8 PhyNum; /* 0x0E */
2185 U8 PrimFlags; /* 0x0F */
2186 U32 Primitive; /* 0x10 */
2187 U8 LookupMethod; /* 0x14 */
2188 U8 Reserved5; /* 0x15 */
2189 U16 SlotNumber; /* 0x16 */
2190 U64 LookupAddress; /* 0x18 */
2191 U32 IOCParameterValue; /* 0x20 */
2192 U32 Reserved7; /* 0x24 */
2193 U32 Reserved8; /* 0x28 */
2194 } MPI26_IOUNIT_CONTROL_REQUEST,
2195 MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REQUEST,
2196 Mpi26IoUnitControlRequest_t, MPI2_POINTER pMpi26IoUnitControlRequest_t;
2197
2198 /* values for the Operation field */
2199 #define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02)
2200 #define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06)
2201 #define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07)
2202 #define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08)
2203 #define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09)
2204 #define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A)
2205 #define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B)
2206 #define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D)
2207 #define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E)
2208 #define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F)
2209 #define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10)
2210 #define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11)
2211 #define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12)
2212 #define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13)
2213 #define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14)
2214 #define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15)
2215 #define MPI26_CTRL_OP_SHUTDOWN (0x16)
2216 #define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17)
2217 #define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18)
2218 #define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19)
2219 #define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A)
2220 #define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B)
2221 #define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80)
2222
2223 /* values for the PrimFlags field */
2224 #define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08)
2225 #define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02)
2226 #define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01)
2227
2228 /* values for the LookupMethod field */
2229 #define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
2230 #define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
2231 #define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
2232
2233
2234 /* IO Unit Control Reply Message */
2235 typedef struct _MPI26_IOUNIT_CONTROL_REPLY
2236 {
2237 U8 Operation; /* 0x00 */
2238 U8 Reserved1; /* 0x01 */
2239 U8 MsgLength; /* 0x02 */
2240 U8 Function; /* 0x03 */
2241 U16 DevHandle; /* 0x04 */
2242 U8 IOCParameter; /* 0x06 */
2243 U8 MsgFlags; /* 0x07 */
2244 U8 VP_ID; /* 0x08 */
2245 U8 VF_ID; /* 0x09 */
2246 U16 Reserved3; /* 0x0A */
2247 U16 Reserved4; /* 0x0C */
2248 U16 IOCStatus; /* 0x0E */
2249 U32 IOCLogInfo; /* 0x10 */
2250 } MPI26_IOUNIT_CONTROL_REPLY, MPI2_POINTER PTR_MPI26_IOUNIT_CONTROL_REPLY,
2251 Mpi26IoUnitControlReply_t, MPI2_POINTER pMpi26IoUnitControlReply_t;
2252
2253
2254 #endif
2255
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