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sys/dev/mps/mpi/mpi2_ioc.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006-2015 LSI Corp. 5 * Copyright (c) 2013-2015 Avago Technologies 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 30 * 31 * $FreeBSD$ 32 */ 33 34 /* 35 * Copyright (c) 2006-2015 LSI Corporation. 36 * Copyright (c) 2013-2015 Avago Technologies 37 * 38 * 39 * Name: mpi2_ioc.h 40 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 41 * Creation Date: October 11, 2006 42 * 43 * mpi2_ioc.h Version: 02.00.16 44 * 45 * Version History 46 * --------------- 47 * 48 * Date Version Description 49 * -------- -------- ------------------------------------------------------ 50 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 51 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 52 * MaxTargets. 53 * Added TotalImageSize field to FWDownload Request. 54 * Added reserved words to FWUpload Request. 55 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 56 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 57 * request and replaced it with 58 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 59 * Replaced the MinReplyQueueDepth field of the IOCFacts 60 * reply with MaxReplyDescriptorPostQueueDepth. 61 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 62 * depth for the Reply Descriptor Post Queue. 63 * Added SASAddress field to Initiator Device Table 64 * Overflow Event data. 65 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 66 * for SAS Initiator Device Status Change Event data. 67 * Modified Reason Code defines for SAS Topology Change 68 * List Event data, including adding a bit for PHY Vacant 69 * status, and adding a mask for the Reason Code. 70 * Added define for 71 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 72 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 73 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 74 * the IOCFacts Reply. 75 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 76 * Moved MPI2_VERSION_UNION to mpi2.h. 77 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 78 * instead of enables, and added SASBroadcastPrimitiveMasks 79 * field. 80 * Added Log Entry Added Event and related structure. 81 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 82 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 83 * Added MaxVolumes and MaxPersistentEntries fields to 84 * IOCFacts reply. 85 * Added ProtocalFlags and IOCCapabilities fields to 86 * MPI2_FW_IMAGE_HEADER. 87 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 88 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 89 * a U16 (from a U32). 90 * Removed extra 's' from EventMasks name. 91 * 06-27-08 02.00.08 Fixed an offset in a comment. 92 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 93 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 94 * renamed MinReplyFrameSize to ReplyFrameSize. 95 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 96 * Added two new RAIDOperation values for Integrated RAID 97 * Operations Status Event data. 98 * Added four new IR Configuration Change List Event data 99 * ReasonCode values. 100 * Added two new ReasonCode defines for SAS Device Status 101 * Change Event data. 102 * Added three new DiscoveryStatus bits for the SAS 103 * Discovery event data. 104 * Added Multiplexing Status Change bit to the PhyStatus 105 * field of the SAS Topology Change List event data. 106 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 107 * BootFlags are now product-specific. 108 * Added defines for the indivdual signature bytes 109 * for MPI2_INIT_IMAGE_FOOTER. 110 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 111 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 112 * define. 113 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 114 * define. 115 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 116 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 117 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 118 * Added two new reason codes for SAS Device Status Change 119 * Event. 120 * Added new event: SAS PHY Counter. 121 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 122 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 123 * Added new product id family for 2208. 124 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 125 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 126 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 127 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 128 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 129 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 130 * Added Host Based Discovery Phy Event data. 131 * Added defines for ProductID Product field 132 * (MPI2_FW_HEADER_PID_). 133 * Modified values for SAS ProductID Family 134 * (MPI2_FW_HEADER_PID_FAMILY_). 135 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 136 * Added PowerManagementControl Request structures and 137 * defines. 138 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 139 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 140 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 141 * -------------------------------------------------------------------------- 142 */ 143 144 #ifndef MPI2_IOC_H 145 #define MPI2_IOC_H 146 147 /***************************************************************************** 148 * 149 * IOC Messages 150 * 151 *****************************************************************************/ 152 153 /**************************************************************************** 154 * IOCInit message 155 ****************************************************************************/ 156 157 /* IOCInit Request message */ 158 typedef struct _MPI2_IOC_INIT_REQUEST 159 { 160 U8 WhoInit; /* 0x00 */ 161 U8 Reserved1; /* 0x01 */ 162 U8 ChainOffset; /* 0x02 */ 163 U8 Function; /* 0x03 */ 164 U16 Reserved2; /* 0x04 */ 165 U8 Reserved3; /* 0x06 */ 166 U8 MsgFlags; /* 0x07 */ 167 U8 VP_ID; /* 0x08 */ 168 U8 VF_ID; /* 0x09 */ 169 U16 Reserved4; /* 0x0A */ 170 U16 MsgVersion; /* 0x0C */ 171 U16 HeaderVersion; /* 0x0E */ 172 U32 Reserved5; /* 0x10 */ 173 U16 Reserved6; /* 0x14 */ 174 U8 Reserved7; /* 0x16 */ 175 U8 HostMSIxVectors; /* 0x17 */ 176 U16 Reserved8; /* 0x18 */ 177 U16 SystemRequestFrameSize; /* 0x1A */ 178 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 179 U16 ReplyFreeQueueDepth; /* 0x1E */ 180 U32 SenseBufferAddressHigh; /* 0x20 */ 181 U32 SystemReplyAddressHigh; /* 0x24 */ 182 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 183 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 184 U64 ReplyFreeQueueAddress; /* 0x38 */ 185 U64 TimeStamp; /* 0x40 */ 186 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 187 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 188 189 /* WhoInit values */ 190 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 191 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 192 #define MPI2_WHOINIT_ROM_BIOS (0x02) 193 #define MPI2_WHOINIT_PCI_PEER (0x03) 194 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 195 #define MPI2_WHOINIT_MANUFACTURER (0x05) 196 197 /* MsgVersion */ 198 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 199 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 200 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 201 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 202 203 /* HeaderVersion */ 204 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 205 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 206 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 207 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 208 209 /* minimum depth for the Reply Descriptor Post Queue */ 210 #define MPI2_RDPQ_DEPTH_MIN (16) 211 212 /* IOCInit Reply message */ 213 typedef struct _MPI2_IOC_INIT_REPLY 214 { 215 U8 WhoInit; /* 0x00 */ 216 U8 Reserved1; /* 0x01 */ 217 U8 MsgLength; /* 0x02 */ 218 U8 Function; /* 0x03 */ 219 U16 Reserved2; /* 0x04 */ 220 U8 Reserved3; /* 0x06 */ 221 U8 MsgFlags; /* 0x07 */ 222 U8 VP_ID; /* 0x08 */ 223 U8 VF_ID; /* 0x09 */ 224 U16 Reserved4; /* 0x0A */ 225 U16 Reserved5; /* 0x0C */ 226 U16 IOCStatus; /* 0x0E */ 227 U32 IOCLogInfo; /* 0x10 */ 228 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 229 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 230 231 /**************************************************************************** 232 * IOCFacts message 233 ****************************************************************************/ 234 235 /* IOCFacts Request message */ 236 typedef struct _MPI2_IOC_FACTS_REQUEST 237 { 238 U16 Reserved1; /* 0x00 */ 239 U8 ChainOffset; /* 0x02 */ 240 U8 Function; /* 0x03 */ 241 U16 Reserved2; /* 0x04 */ 242 U8 Reserved3; /* 0x06 */ 243 U8 MsgFlags; /* 0x07 */ 244 U8 VP_ID; /* 0x08 */ 245 U8 VF_ID; /* 0x09 */ 246 U16 Reserved4; /* 0x0A */ 247 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 248 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 249 250 /* IOCFacts Reply message */ 251 typedef struct _MPI2_IOC_FACTS_REPLY 252 { 253 U16 MsgVersion; /* 0x00 */ 254 U8 MsgLength; /* 0x02 */ 255 U8 Function; /* 0x03 */ 256 U16 HeaderVersion; /* 0x04 */ 257 U8 IOCNumber; /* 0x06 */ 258 U8 MsgFlags; /* 0x07 */ 259 U8 VP_ID; /* 0x08 */ 260 U8 VF_ID; /* 0x09 */ 261 U16 Reserved1; /* 0x0A */ 262 U16 IOCExceptions; /* 0x0C */ 263 U16 IOCStatus; /* 0x0E */ 264 U32 IOCLogInfo; /* 0x10 */ 265 U8 MaxChainDepth; /* 0x14 */ 266 U8 WhoInit; /* 0x15 */ 267 U8 NumberOfPorts; /* 0x16 */ 268 U8 MaxMSIxVectors; /* 0x17 */ 269 U16 RequestCredit; /* 0x18 */ 270 U16 ProductID; /* 0x1A */ 271 U32 IOCCapabilities; /* 0x1C */ 272 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 273 U16 IOCRequestFrameSize; /* 0x24 */ 274 U16 Reserved3; /* 0x26 */ 275 U16 MaxInitiators; /* 0x28 */ 276 U16 MaxTargets; /* 0x2A */ 277 U16 MaxSasExpanders; /* 0x2C */ 278 U16 MaxEnclosures; /* 0x2E */ 279 U16 ProtocolFlags; /* 0x30 */ 280 U16 HighPriorityCredit; /* 0x32 */ 281 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 282 U8 ReplyFrameSize; /* 0x36 */ 283 U8 MaxVolumes; /* 0x37 */ 284 U16 MaxDevHandle; /* 0x38 */ 285 U16 MaxPersistentEntries; /* 0x3A */ 286 U16 MinDevHandle; /* 0x3C */ 287 U16 Reserved4; /* 0x3E */ 288 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 289 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 290 291 /* MsgVersion */ 292 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 293 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 294 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 295 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 296 297 /* HeaderVersion */ 298 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 299 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 300 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 301 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 302 303 /* IOCExceptions */ 304 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 305 306 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 307 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 308 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 309 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 310 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 311 312 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 313 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 314 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 315 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 316 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 317 318 /* defines for WhoInit field are after the IOCInit Request */ 319 320 /* ProductID field uses MPI2_FW_HEADER_PID_ */ 321 322 /* IOCCapabilities */ 323 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 324 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 325 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 326 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 327 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 328 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 329 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 330 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 331 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 332 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 333 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 334 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 335 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 336 337 /* ProtocolFlags */ 338 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 339 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 340 341 /**************************************************************************** 342 * PortFacts message 343 ****************************************************************************/ 344 345 /* PortFacts Request message */ 346 typedef struct _MPI2_PORT_FACTS_REQUEST 347 { 348 U16 Reserved1; /* 0x00 */ 349 U8 ChainOffset; /* 0x02 */ 350 U8 Function; /* 0x03 */ 351 U16 Reserved2; /* 0x04 */ 352 U8 PortNumber; /* 0x06 */ 353 U8 MsgFlags; /* 0x07 */ 354 U8 VP_ID; /* 0x08 */ 355 U8 VF_ID; /* 0x09 */ 356 U16 Reserved3; /* 0x0A */ 357 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 358 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 359 360 /* PortFacts Reply message */ 361 typedef struct _MPI2_PORT_FACTS_REPLY 362 { 363 U16 Reserved1; /* 0x00 */ 364 U8 MsgLength; /* 0x02 */ 365 U8 Function; /* 0x03 */ 366 U16 Reserved2; /* 0x04 */ 367 U8 PortNumber; /* 0x06 */ 368 U8 MsgFlags; /* 0x07 */ 369 U8 VP_ID; /* 0x08 */ 370 U8 VF_ID; /* 0x09 */ 371 U16 Reserved3; /* 0x0A */ 372 U16 Reserved4; /* 0x0C */ 373 U16 IOCStatus; /* 0x0E */ 374 U32 IOCLogInfo; /* 0x10 */ 375 U8 Reserved5; /* 0x14 */ 376 U8 PortType; /* 0x15 */ 377 U16 Reserved6; /* 0x16 */ 378 U16 MaxPostedCmdBuffers; /* 0x18 */ 379 U16 Reserved7; /* 0x1A */ 380 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 381 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 382 383 /* PortType values */ 384 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 385 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 386 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 387 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 388 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 389 390 /**************************************************************************** 391 * PortEnable message 392 ****************************************************************************/ 393 394 /* PortEnable Request message */ 395 typedef struct _MPI2_PORT_ENABLE_REQUEST 396 { 397 U16 Reserved1; /* 0x00 */ 398 U8 ChainOffset; /* 0x02 */ 399 U8 Function; /* 0x03 */ 400 U8 Reserved2; /* 0x04 */ 401 U8 PortFlags; /* 0x05 */ 402 U8 Reserved3; /* 0x06 */ 403 U8 MsgFlags; /* 0x07 */ 404 U8 VP_ID; /* 0x08 */ 405 U8 VF_ID; /* 0x09 */ 406 U16 Reserved4; /* 0x0A */ 407 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 408 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 409 410 /* PortEnable Reply message */ 411 typedef struct _MPI2_PORT_ENABLE_REPLY 412 { 413 U16 Reserved1; /* 0x00 */ 414 U8 MsgLength; /* 0x02 */ 415 U8 Function; /* 0x03 */ 416 U8 Reserved2; /* 0x04 */ 417 U8 PortFlags; /* 0x05 */ 418 U8 Reserved3; /* 0x06 */ 419 U8 MsgFlags; /* 0x07 */ 420 U8 VP_ID; /* 0x08 */ 421 U8 VF_ID; /* 0x09 */ 422 U16 Reserved4; /* 0x0A */ 423 U16 Reserved5; /* 0x0C */ 424 U16 IOCStatus; /* 0x0E */ 425 U32 IOCLogInfo; /* 0x10 */ 426 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 427 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 428 429 /**************************************************************************** 430 * EventNotification message 431 ****************************************************************************/ 432 433 /* EventNotification Request message */ 434 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 435 436 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 437 { 438 U16 Reserved1; /* 0x00 */ 439 U8 ChainOffset; /* 0x02 */ 440 U8 Function; /* 0x03 */ 441 U16 Reserved2; /* 0x04 */ 442 U8 Reserved3; /* 0x06 */ 443 U8 MsgFlags; /* 0x07 */ 444 U8 VP_ID; /* 0x08 */ 445 U8 VF_ID; /* 0x09 */ 446 U16 Reserved4; /* 0x0A */ 447 U32 Reserved5; /* 0x0C */ 448 U32 Reserved6; /* 0x10 */ 449 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 450 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 451 U16 Reserved7; /* 0x26 */ 452 U32 Reserved8; /* 0x28 */ 453 } MPI2_EVENT_NOTIFICATION_REQUEST, 454 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 455 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 456 457 /* EventNotification Reply message */ 458 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 459 { 460 U16 EventDataLength; /* 0x00 */ 461 U8 MsgLength; /* 0x02 */ 462 U8 Function; /* 0x03 */ 463 U16 Reserved1; /* 0x04 */ 464 U8 AckRequired; /* 0x06 */ 465 U8 MsgFlags; /* 0x07 */ 466 U8 VP_ID; /* 0x08 */ 467 U8 VF_ID; /* 0x09 */ 468 U16 Reserved2; /* 0x0A */ 469 U16 Reserved3; /* 0x0C */ 470 U16 IOCStatus; /* 0x0E */ 471 U32 IOCLogInfo; /* 0x10 */ 472 U16 Event; /* 0x14 */ 473 U16 Reserved4; /* 0x16 */ 474 U32 EventContext; /* 0x18 */ 475 U32 EventData[1]; /* 0x1C */ 476 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 477 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 478 479 /* AckRequired */ 480 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 481 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 482 483 /* Event */ 484 #define MPI2_EVENT_LOG_DATA (0x0001) 485 #define MPI2_EVENT_STATE_CHANGE (0x0002) 486 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 487 #define MPI2_EVENT_EVENT_CHANGE (0x000A) 488 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 489 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 490 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 491 #define MPI2_EVENT_SAS_DISCOVERY (0x0016) 492 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 493 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 494 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 495 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 496 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 497 #define MPI2_EVENT_IR_VOLUME (0x001E) 498 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 499 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 500 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 501 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 502 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 503 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 504 #define MPI2_EVENT_SAS_QUIESCE (0x0025) 505 506 /* Log Entry Added Event data */ 507 508 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 509 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 510 511 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 512 { 513 U64 TimeStamp; /* 0x00 */ 514 U32 Reserved1; /* 0x08 */ 515 U16 LogSequence; /* 0x0C */ 516 U16 LogEntryQualifier; /* 0x0E */ 517 U8 VP_ID; /* 0x10 */ 518 U8 VF_ID; /* 0x11 */ 519 U16 Reserved2; /* 0x12 */ 520 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 521 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 522 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 523 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 524 525 /* GPIO Interrupt Event data */ 526 527 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 528 { 529 U8 GPIONum; /* 0x00 */ 530 U8 Reserved1; /* 0x01 */ 531 U16 Reserved2; /* 0x02 */ 532 } MPI2_EVENT_DATA_GPIO_INTERRUPT, 533 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 534 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 535 536 /* Hard Reset Received Event data */ 537 538 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 539 { 540 U8 Reserved1; /* 0x00 */ 541 U8 Port; /* 0x01 */ 542 U16 Reserved2; /* 0x02 */ 543 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 544 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 545 Mpi2EventDataHardResetReceived_t, 546 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 547 548 /* Task Set Full Event data */ 549 /* this event is obsolete */ 550 551 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 552 { 553 U16 DevHandle; /* 0x00 */ 554 U16 CurrentDepth; /* 0x02 */ 555 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 556 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 557 558 /* SAS Device Status Change Event data */ 559 560 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 561 { 562 U16 TaskTag; /* 0x00 */ 563 U8 ReasonCode; /* 0x02 */ 564 U8 Reserved1; /* 0x03 */ 565 U8 ASC; /* 0x04 */ 566 U8 ASCQ; /* 0x05 */ 567 U16 DevHandle; /* 0x06 */ 568 U32 Reserved2; /* 0x08 */ 569 U64 SASAddress; /* 0x0C */ 570 U8 LUN[8]; /* 0x14 */ 571 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 572 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 573 Mpi2EventDataSasDeviceStatusChange_t, 574 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 575 576 /* SAS Device Status Change Event data ReasonCode values */ 577 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 578 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 579 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 580 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 581 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 582 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 583 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 584 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 585 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 586 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 587 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 588 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 589 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 590 591 /* Integrated RAID Operation Status Event data */ 592 593 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 594 { 595 U16 VolDevHandle; /* 0x00 */ 596 U16 Reserved1; /* 0x02 */ 597 U8 RAIDOperation; /* 0x04 */ 598 U8 PercentComplete; /* 0x05 */ 599 U16 Reserved2; /* 0x06 */ 600 U32 Resereved3; /* 0x08 */ 601 } MPI2_EVENT_DATA_IR_OPERATION_STATUS, 602 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 603 Mpi2EventDataIrOperationStatus_t, 604 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 605 606 /* Integrated RAID Operation Status Event data RAIDOperation values */ 607 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 608 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 609 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 610 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 611 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 612 613 /* Integrated RAID Volume Event data */ 614 615 typedef struct _MPI2_EVENT_DATA_IR_VOLUME 616 { 617 U16 VolDevHandle; /* 0x00 */ 618 U8 ReasonCode; /* 0x02 */ 619 U8 Reserved1; /* 0x03 */ 620 U32 NewValue; /* 0x04 */ 621 U32 PreviousValue; /* 0x08 */ 622 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 623 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 624 625 /* Integrated RAID Volume Event data ReasonCode values */ 626 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 627 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 628 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 629 630 /* Integrated RAID Physical Disk Event data */ 631 632 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 633 { 634 U16 Reserved1; /* 0x00 */ 635 U8 ReasonCode; /* 0x02 */ 636 U8 PhysDiskNum; /* 0x03 */ 637 U16 PhysDiskDevHandle; /* 0x04 */ 638 U16 Reserved2; /* 0x06 */ 639 U16 Slot; /* 0x08 */ 640 U16 EnclosureHandle; /* 0x0A */ 641 U32 NewValue; /* 0x0C */ 642 U32 PreviousValue; /* 0x10 */ 643 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 644 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 645 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 646 647 /* Integrated RAID Physical Disk Event data ReasonCode values */ 648 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 649 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 650 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 651 652 /* Integrated RAID Configuration Change List Event data */ 653 654 /* 655 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 656 * one and check NumElements at runtime. 657 */ 658 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 659 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 660 #endif 661 662 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 663 { 664 U16 ElementFlags; /* 0x00 */ 665 U16 VolDevHandle; /* 0x02 */ 666 U8 ReasonCode; /* 0x04 */ 667 U8 PhysDiskNum; /* 0x05 */ 668 U16 PhysDiskDevHandle; /* 0x06 */ 669 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 670 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 671 672 /* IR Configuration Change List Event data ElementFlags values */ 673 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 674 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 675 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 676 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 677 678 /* IR Configuration Change List Event data ReasonCode values */ 679 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 680 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 681 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 682 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 683 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 684 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 685 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 686 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 687 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 688 689 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 690 { 691 U8 NumElements; /* 0x00 */ 692 U8 Reserved1; /* 0x01 */ 693 U8 Reserved2; /* 0x02 */ 694 U8 ConfigNum; /* 0x03 */ 695 U32 Flags; /* 0x04 */ 696 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 697 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 698 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 699 Mpi2EventDataIrConfigChangeList_t, 700 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 701 702 /* IR Configuration Change List Event data Flags values */ 703 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 704 705 /* SAS Discovery Event data */ 706 707 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 708 { 709 U8 Flags; /* 0x00 */ 710 U8 ReasonCode; /* 0x01 */ 711 U8 PhysicalPort; /* 0x02 */ 712 U8 Reserved1; /* 0x03 */ 713 U32 DiscoveryStatus; /* 0x04 */ 714 } MPI2_EVENT_DATA_SAS_DISCOVERY, 715 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 716 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 717 718 /* SAS Discovery Event data Flags values */ 719 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 720 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 721 722 /* SAS Discovery Event data ReasonCode values */ 723 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 724 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 725 726 /* SAS Discovery Event data DiscoveryStatus values */ 727 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 728 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 729 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 730 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 731 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 732 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 733 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 734 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 735 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 736 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 737 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 738 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 739 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 740 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 741 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 742 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 743 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 744 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 745 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 746 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 747 748 /* SAS Broadcast Primitive Event data */ 749 750 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 751 { 752 U8 PhyNum; /* 0x00 */ 753 U8 Port; /* 0x01 */ 754 U8 PortWidth; /* 0x02 */ 755 U8 Primitive; /* 0x03 */ 756 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 757 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 758 Mpi2EventDataSasBroadcastPrimitive_t, 759 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 760 761 /* defines for the Primitive field */ 762 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 763 #define MPI2_EVENT_PRIMITIVE_SES (0x02) 764 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 765 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 766 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 767 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 768 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 769 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 770 771 /* SAS Initiator Device Status Change Event data */ 772 773 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 774 { 775 U8 ReasonCode; /* 0x00 */ 776 U8 PhysicalPort; /* 0x01 */ 777 U16 DevHandle; /* 0x02 */ 778 U64 SASAddress; /* 0x04 */ 779 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 780 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 781 Mpi2EventDataSasInitDevStatusChange_t, 782 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 783 784 /* SAS Initiator Device Status Change event ReasonCode values */ 785 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 786 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 787 788 /* SAS Initiator Device Table Overflow Event data */ 789 790 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 791 { 792 U16 MaxInit; /* 0x00 */ 793 U16 CurrentInit; /* 0x02 */ 794 U64 SASAddress; /* 0x04 */ 795 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 796 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 797 Mpi2EventDataSasInitTableOverflow_t, 798 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 799 800 /* SAS Topology Change List Event data */ 801 802 /* 803 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 804 * one and check NumEntries at runtime. 805 */ 806 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 807 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 808 #endif 809 810 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 811 { 812 U16 AttachedDevHandle; /* 0x00 */ 813 U8 LinkRate; /* 0x02 */ 814 U8 PhyStatus; /* 0x03 */ 815 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 816 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 817 818 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 819 { 820 U16 EnclosureHandle; /* 0x00 */ 821 U16 ExpanderDevHandle; /* 0x02 */ 822 U8 NumPhys; /* 0x04 */ 823 U8 Reserved1; /* 0x05 */ 824 U16 Reserved2; /* 0x06 */ 825 U8 NumEntries; /* 0x08 */ 826 U8 StartPhyNum; /* 0x09 */ 827 U8 ExpStatus; /* 0x0A */ 828 U8 PhysicalPort; /* 0x0B */ 829 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 830 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 831 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 832 Mpi2EventDataSasTopologyChangeList_t, 833 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 834 835 /* values for the ExpStatus field */ 836 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 837 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 838 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 839 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 840 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 841 842 /* defines for the LinkRate field */ 843 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 844 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 845 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 846 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 847 848 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 849 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 850 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 851 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 852 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 853 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 854 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 855 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 856 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 857 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 858 859 /* values for the PhyStatus field */ 860 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 861 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 862 /* values for the PhyStatus ReasonCode sub-field */ 863 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 864 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 865 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 866 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 867 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 868 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 869 870 /* SAS Enclosure Device Status Change Event data */ 871 872 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 873 { 874 U16 EnclosureHandle; /* 0x00 */ 875 U8 ReasonCode; /* 0x02 */ 876 U8 PhysicalPort; /* 0x03 */ 877 U64 EnclosureLogicalID; /* 0x04 */ 878 U16 NumSlots; /* 0x0C */ 879 U16 StartSlot; /* 0x0E */ 880 U32 PhyBits; /* 0x10 */ 881 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 882 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 883 Mpi2EventDataSasEnclDevStatusChange_t, 884 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; 885 886 /* SAS Enclosure Device Status Change event ReasonCode values */ 887 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 888 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 889 890 /* SAS PHY Counter Event data */ 891 892 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 893 { 894 U64 TimeStamp; /* 0x00 */ 895 U32 Reserved1; /* 0x08 */ 896 U8 PhyEventCode; /* 0x0C */ 897 U8 PhyNum; /* 0x0D */ 898 U16 Reserved2; /* 0x0E */ 899 U32 PhyEventInfo; /* 0x10 */ 900 U8 CounterType; /* 0x14 */ 901 U8 ThresholdWindow; /* 0x15 */ 902 U8 TimeUnits; /* 0x16 */ 903 U8 Reserved3; /* 0x17 */ 904 U32 EventThreshold; /* 0x18 */ 905 U16 ThresholdFlags; /* 0x1C */ 906 U16 Reserved4; /* 0x1E */ 907 } MPI2_EVENT_DATA_SAS_PHY_COUNTER, 908 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 909 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 910 911 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 912 913 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 914 915 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 916 917 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 918 919 /* SAS Quiesce Event data */ 920 921 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 922 { 923 U8 ReasonCode; /* 0x00 */ 924 U8 Reserved1; /* 0x01 */ 925 U16 Reserved2; /* 0x02 */ 926 U32 Reserved3; /* 0x04 */ 927 } MPI2_EVENT_DATA_SAS_QUIESCE, 928 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 929 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 930 931 /* SAS Quiesce Event data ReasonCode values */ 932 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 933 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 934 935 /* Host Based Discovery Phy Event data */ 936 937 typedef struct _MPI2_EVENT_HBD_PHY_SAS 938 { 939 U8 Flags; /* 0x00 */ 940 U8 NegotiatedLinkRate; /* 0x01 */ 941 U8 PhyNum; /* 0x02 */ 942 U8 PhysicalPort; /* 0x03 */ 943 U32 Reserved1; /* 0x04 */ 944 U8 InitialFrame[28]; /* 0x08 */ 945 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 946 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 947 948 /* values for the Flags field */ 949 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 950 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 951 952 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 953 954 typedef union _MPI2_EVENT_HBD_DESCRIPTOR 955 { 956 MPI2_EVENT_HBD_PHY_SAS Sas; 957 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 958 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 959 960 typedef struct _MPI2_EVENT_DATA_HBD_PHY 961 { 962 U8 DescriptorType; /* 0x00 */ 963 U8 Reserved1; /* 0x01 */ 964 U16 Reserved2; /* 0x02 */ 965 U32 Reserved3; /* 0x04 */ 966 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 967 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 968 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 969 970 /* values for the DescriptorType field */ 971 #define MPI2_EVENT_HBD_DT_SAS (0x01) 972 973 /**************************************************************************** 974 * EventAck message 975 ****************************************************************************/ 976 977 /* EventAck Request message */ 978 typedef struct _MPI2_EVENT_ACK_REQUEST 979 { 980 U16 Reserved1; /* 0x00 */ 981 U8 ChainOffset; /* 0x02 */ 982 U8 Function; /* 0x03 */ 983 U16 Reserved2; /* 0x04 */ 984 U8 Reserved3; /* 0x06 */ 985 U8 MsgFlags; /* 0x07 */ 986 U8 VP_ID; /* 0x08 */ 987 U8 VF_ID; /* 0x09 */ 988 U16 Reserved4; /* 0x0A */ 989 U16 Event; /* 0x0C */ 990 U16 Reserved5; /* 0x0E */ 991 U32 EventContext; /* 0x10 */ 992 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 993 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 994 995 /* EventAck Reply message */ 996 typedef struct _MPI2_EVENT_ACK_REPLY 997 { 998 U16 Reserved1; /* 0x00 */ 999 U8 MsgLength; /* 0x02 */ 1000 U8 Function; /* 0x03 */ 1001 U16 Reserved2; /* 0x04 */ 1002 U8 Reserved3; /* 0x06 */ 1003 U8 MsgFlags; /* 0x07 */ 1004 U8 VP_ID; /* 0x08 */ 1005 U8 VF_ID; /* 0x09 */ 1006 U16 Reserved4; /* 0x0A */ 1007 U16 Reserved5; /* 0x0C */ 1008 U16 IOCStatus; /* 0x0E */ 1009 U32 IOCLogInfo; /* 0x10 */ 1010 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1011 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1012 1013 /**************************************************************************** 1014 * FWDownload message 1015 ****************************************************************************/ 1016 1017 /* FWDownload Request message */ 1018 typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1019 { 1020 U8 ImageType; /* 0x00 */ 1021 U8 Reserved1; /* 0x01 */ 1022 U8 ChainOffset; /* 0x02 */ 1023 U8 Function; /* 0x03 */ 1024 U16 Reserved2; /* 0x04 */ 1025 U8 Reserved3; /* 0x06 */ 1026 U8 MsgFlags; /* 0x07 */ 1027 U8 VP_ID; /* 0x08 */ 1028 U8 VF_ID; /* 0x09 */ 1029 U16 Reserved4; /* 0x0A */ 1030 U32 TotalImageSize; /* 0x0C */ 1031 U32 Reserved5; /* 0x10 */ 1032 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1033 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1034 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1035 1036 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1037 1038 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1039 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1040 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1041 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1042 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1043 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1044 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1045 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1046 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1047 1048 /* FWDownload TransactionContext Element */ 1049 typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1050 { 1051 U8 Reserved1; /* 0x00 */ 1052 U8 ContextSize; /* 0x01 */ 1053 U8 DetailsLength; /* 0x02 */ 1054 U8 Flags; /* 0x03 */ 1055 U32 Reserved2; /* 0x04 */ 1056 U32 ImageOffset; /* 0x08 */ 1057 U32 ImageSize; /* 0x0C */ 1058 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1059 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1060 1061 /* FWDownload Reply message */ 1062 typedef struct _MPI2_FW_DOWNLOAD_REPLY 1063 { 1064 U8 ImageType; /* 0x00 */ 1065 U8 Reserved1; /* 0x01 */ 1066 U8 MsgLength; /* 0x02 */ 1067 U8 Function; /* 0x03 */ 1068 U16 Reserved2; /* 0x04 */ 1069 U8 Reserved3; /* 0x06 */ 1070 U8 MsgFlags; /* 0x07 */ 1071 U8 VP_ID; /* 0x08 */ 1072 U8 VF_ID; /* 0x09 */ 1073 U16 Reserved4; /* 0x0A */ 1074 U16 Reserved5; /* 0x0C */ 1075 U16 IOCStatus; /* 0x0E */ 1076 U32 IOCLogInfo; /* 0x10 */ 1077 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1078 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1079 1080 /**************************************************************************** 1081 * FWUpload message 1082 ****************************************************************************/ 1083 1084 /* FWUpload Request message */ 1085 typedef struct _MPI2_FW_UPLOAD_REQUEST 1086 { 1087 U8 ImageType; /* 0x00 */ 1088 U8 Reserved1; /* 0x01 */ 1089 U8 ChainOffset; /* 0x02 */ 1090 U8 Function; /* 0x03 */ 1091 U16 Reserved2; /* 0x04 */ 1092 U8 Reserved3; /* 0x06 */ 1093 U8 MsgFlags; /* 0x07 */ 1094 U8 VP_ID; /* 0x08 */ 1095 U8 VF_ID; /* 0x09 */ 1096 U16 Reserved4; /* 0x0A */ 1097 U32 Reserved5; /* 0x0C */ 1098 U32 Reserved6; /* 0x10 */ 1099 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1100 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1101 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1102 1103 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1104 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1105 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1106 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1107 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1108 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1109 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1110 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1111 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1112 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1113 1114 typedef struct _MPI2_FW_UPLOAD_TCSGE 1115 { 1116 U8 Reserved1; /* 0x00 */ 1117 U8 ContextSize; /* 0x01 */ 1118 U8 DetailsLength; /* 0x02 */ 1119 U8 Flags; /* 0x03 */ 1120 U32 Reserved2; /* 0x04 */ 1121 U32 ImageOffset; /* 0x08 */ 1122 U32 ImageSize; /* 0x0C */ 1123 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1124 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1125 1126 /* FWUpload Reply message */ 1127 typedef struct _MPI2_FW_UPLOAD_REPLY 1128 { 1129 U8 ImageType; /* 0x00 */ 1130 U8 Reserved1; /* 0x01 */ 1131 U8 MsgLength; /* 0x02 */ 1132 U8 Function; /* 0x03 */ 1133 U16 Reserved2; /* 0x04 */ 1134 U8 Reserved3; /* 0x06 */ 1135 U8 MsgFlags; /* 0x07 */ 1136 U8 VP_ID; /* 0x08 */ 1137 U8 VF_ID; /* 0x09 */ 1138 U16 Reserved4; /* 0x0A */ 1139 U16 Reserved5; /* 0x0C */ 1140 U16 IOCStatus; /* 0x0E */ 1141 U32 IOCLogInfo; /* 0x10 */ 1142 U32 ActualImageSize; /* 0x14 */ 1143 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1144 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1145 1146 /* FW Image Header */ 1147 typedef struct _MPI2_FW_IMAGE_HEADER 1148 { 1149 U32 Signature; /* 0x00 */ 1150 U32 Signature0; /* 0x04 */ 1151 U32 Signature1; /* 0x08 */ 1152 U32 Signature2; /* 0x0C */ 1153 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1154 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1155 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1156 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1157 U16 VendorID; /* 0x20 */ 1158 U16 ProductID; /* 0x22 */ 1159 U16 ProtocolFlags; /* 0x24 */ 1160 U16 Reserved26; /* 0x26 */ 1161 U32 IOCCapabilities; /* 0x28 */ 1162 U32 ImageSize; /* 0x2C */ 1163 U32 NextImageHeaderOffset; /* 0x30 */ 1164 U32 Checksum; /* 0x34 */ 1165 U32 Reserved38; /* 0x38 */ 1166 U32 Reserved3C; /* 0x3C */ 1167 U32 Reserved40; /* 0x40 */ 1168 U32 Reserved44; /* 0x44 */ 1169 U32 Reserved48; /* 0x48 */ 1170 U32 Reserved4C; /* 0x4C */ 1171 U32 Reserved50; /* 0x50 */ 1172 U32 Reserved54; /* 0x54 */ 1173 U32 Reserved58; /* 0x58 */ 1174 U32 Reserved5C; /* 0x5C */ 1175 U32 Reserved60; /* 0x60 */ 1176 U32 FirmwareVersionNameWhat; /* 0x64 */ 1177 U8 FirmwareVersionName[32]; /* 0x68 */ 1178 U32 VendorNameWhat; /* 0x88 */ 1179 U8 VendorName[32]; /* 0x8C */ 1180 U32 PackageNameWhat; /* 0x88 */ 1181 U8 PackageName[32]; /* 0x8C */ 1182 U32 ReservedD0; /* 0xD0 */ 1183 U32 ReservedD4; /* 0xD4 */ 1184 U32 ReservedD8; /* 0xD8 */ 1185 U32 ReservedDC; /* 0xDC */ 1186 U32 ReservedE0; /* 0xE0 */ 1187 U32 ReservedE4; /* 0xE4 */ 1188 U32 ReservedE8; /* 0xE8 */ 1189 U32 ReservedEC; /* 0xEC */ 1190 U32 ReservedF0; /* 0xF0 */ 1191 U32 ReservedF4; /* 0xF4 */ 1192 U32 ReservedF8; /* 0xF8 */ 1193 U32 ReservedFC; /* 0xFC */ 1194 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1195 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1196 1197 /* Signature field */ 1198 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1199 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1200 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1201 1202 /* Signature0 field */ 1203 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1204 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1205 1206 /* Signature1 field */ 1207 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1208 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1209 1210 /* Signature2 field */ 1211 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1212 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1213 1214 /* defines for using the ProductID field */ 1215 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1216 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1217 1218 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1219 #define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1220 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1221 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1222 1223 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1224 /* SAS */ 1225 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1226 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1227 1228 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1229 1230 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1231 1232 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1233 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1234 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1235 1236 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1237 1238 #define MPI2_FW_HEADER_SIZE (0x100) 1239 1240 /* Extended Image Header */ 1241 typedef struct _MPI2_EXT_IMAGE_HEADER 1242 1243 { 1244 U8 ImageType; /* 0x00 */ 1245 U8 Reserved1; /* 0x01 */ 1246 U16 Reserved2; /* 0x02 */ 1247 U32 Checksum; /* 0x04 */ 1248 U32 ImageSize; /* 0x08 */ 1249 U32 NextImageHeaderOffset; /* 0x0C */ 1250 U32 PackageVersion; /* 0x10 */ 1251 U32 Reserved3; /* 0x14 */ 1252 U32 Reserved4; /* 0x18 */ 1253 U32 Reserved5; /* 0x1C */ 1254 U8 IdentifyString[32]; /* 0x20 */ 1255 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1256 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1257 1258 /* useful offsets */ 1259 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1260 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1261 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1262 1263 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1264 1265 /* defines for the ImageType field */ 1266 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1267 #define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1268 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1269 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1270 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1271 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1272 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1273 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1274 1275 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID) 1276 1277 /* FLASH Layout Extended Image Data */ 1278 1279 /* 1280 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1281 * one and check RegionsPerLayout at runtime. 1282 */ 1283 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1284 #define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1285 #endif 1286 1287 /* 1288 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1289 * one and check NumberOfLayouts at runtime. 1290 */ 1291 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1292 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1293 #endif 1294 1295 typedef struct _MPI2_FLASH_REGION 1296 { 1297 U8 RegionType; /* 0x00 */ 1298 U8 Reserved1; /* 0x01 */ 1299 U16 Reserved2; /* 0x02 */ 1300 U32 RegionOffset; /* 0x04 */ 1301 U32 RegionSize; /* 0x08 */ 1302 U32 Reserved3; /* 0x0C */ 1303 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1304 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1305 1306 typedef struct _MPI2_FLASH_LAYOUT 1307 { 1308 U32 FlashSize; /* 0x00 */ 1309 U32 Reserved1; /* 0x04 */ 1310 U32 Reserved2; /* 0x08 */ 1311 U32 Reserved3; /* 0x0C */ 1312 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1313 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1314 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1315 1316 typedef struct _MPI2_FLASH_LAYOUT_DATA 1317 { 1318 U8 ImageRevision; /* 0x00 */ 1319 U8 Reserved1; /* 0x01 */ 1320 U8 SizeOfRegion; /* 0x02 */ 1321 U8 Reserved2; /* 0x03 */ 1322 U16 NumberOfLayouts; /* 0x04 */ 1323 U16 RegionsPerLayout; /* 0x06 */ 1324 U16 MinimumSectorAlignment; /* 0x08 */ 1325 U16 Reserved3; /* 0x0A */ 1326 U32 Reserved4; /* 0x0C */ 1327 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1328 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1329 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1330 1331 /* defines for the RegionType field */ 1332 #define MPI2_FLASH_REGION_UNUSED (0x00) 1333 #define MPI2_FLASH_REGION_FIRMWARE (0x01) 1334 #define MPI2_FLASH_REGION_BIOS (0x02) 1335 #define MPI2_FLASH_REGION_NVDATA (0x03) 1336 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1337 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1338 #define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1339 #define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1340 #define MPI2_FLASH_REGION_MEGARAID (0x09) 1341 #define MPI2_FLASH_REGION_INIT (0x0A) 1342 1343 /* ImageRevision */ 1344 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1345 1346 /* Supported Devices Extended Image Data */ 1347 1348 /* 1349 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1350 * one and check NumberOfDevices at runtime. 1351 */ 1352 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1353 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1354 #endif 1355 1356 typedef struct _MPI2_SUPPORTED_DEVICE 1357 { 1358 U16 DeviceID; /* 0x00 */ 1359 U16 VendorID; /* 0x02 */ 1360 U16 DeviceIDMask; /* 0x04 */ 1361 U16 Reserved1; /* 0x06 */ 1362 U8 LowPCIRev; /* 0x08 */ 1363 U8 HighPCIRev; /* 0x09 */ 1364 U16 Reserved2; /* 0x0A */ 1365 U32 Reserved3; /* 0x0C */ 1366 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1367 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1368 1369 typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1370 { 1371 U8 ImageRevision; /* 0x00 */ 1372 U8 Reserved1; /* 0x01 */ 1373 U8 NumberOfDevices; /* 0x02 */ 1374 U8 Reserved2; /* 0x03 */ 1375 U32 Reserved3; /* 0x04 */ 1376 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1377 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1378 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1379 1380 /* ImageRevision */ 1381 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1382 1383 /* Init Extended Image Data */ 1384 1385 typedef struct _MPI2_INIT_IMAGE_FOOTER 1386 1387 { 1388 U32 BootFlags; /* 0x00 */ 1389 U32 ImageSize; /* 0x04 */ 1390 U32 Signature0; /* 0x08 */ 1391 U32 Signature1; /* 0x0C */ 1392 U32 Signature2; /* 0x10 */ 1393 U32 ResetVector; /* 0x14 */ 1394 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1395 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1396 1397 /* defines for the BootFlags field */ 1398 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1399 1400 /* defines for the ImageSize field */ 1401 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1402 1403 /* defines for the Signature0 field */ 1404 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1405 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1406 1407 /* defines for the Signature1 field */ 1408 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1409 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1410 1411 /* defines for the Signature2 field */ 1412 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1413 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1414 1415 /* Signature fields as individual bytes */ 1416 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1417 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1418 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1419 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1420 1421 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1422 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1423 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1424 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1425 1426 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1427 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1428 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1429 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1430 1431 /* defines for the ResetVector field */ 1432 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1433 1434 /**************************************************************************** 1435 * PowerManagementControl message 1436 ****************************************************************************/ 1437 1438 /* PowerManagementControl Request message */ 1439 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 1440 { 1441 U8 Feature; /* 0x00 */ 1442 U8 Reserved1; /* 0x01 */ 1443 U8 ChainOffset; /* 0x02 */ 1444 U8 Function; /* 0x03 */ 1445 U16 Reserved2; /* 0x04 */ 1446 U8 Reserved3; /* 0x06 */ 1447 U8 MsgFlags; /* 0x07 */ 1448 U8 VP_ID; /* 0x08 */ 1449 U8 VF_ID; /* 0x09 */ 1450 U16 Reserved4; /* 0x0A */ 1451 U8 Parameter1; /* 0x0C */ 1452 U8 Parameter2; /* 0x0D */ 1453 U8 Parameter3; /* 0x0E */ 1454 U8 Parameter4; /* 0x0F */ 1455 U32 Reserved5; /* 0x10 */ 1456 U32 Reserved6; /* 0x14 */ 1457 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1458 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 1459 1460 /* defines for the Feature field */ 1461 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1462 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1463 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) 1464 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1465 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1466 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1467 1468 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1469 /* Parameter1 contains a PHY number */ 1470 /* Parameter2 indicates power condition action using these defines */ 1471 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1472 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1473 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1474 /* Parameter3 and Parameter4 are reserved */ 1475 1476 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 1477 /* Parameter1 contains SAS port width modulation group number */ 1478 /* Parameter2 indicates IOC action using these defines */ 1479 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1480 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1481 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1482 /* Parameter3 indicates desired modulation level using these defines */ 1483 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1484 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1485 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1486 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1487 /* Parameter4 is reserved */ 1488 1489 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1490 /* Parameter1 indicates desired PCIe link speed using these defines */ 1491 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) 1492 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) 1493 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) 1494 /* Parameter2 indicates desired PCIe link width using these defines */ 1495 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) 1496 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) 1497 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) 1498 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) 1499 /* Parameter3 and Parameter4 are reserved */ 1500 1501 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1502 /* Parameter1 indicates desired IOC hardware clock speed using these defines */ 1503 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1504 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1505 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1506 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1507 /* Parameter2, Parameter3, and Parameter4 are reserved */ 1508 1509 /* PowerManagementControl Reply message */ 1510 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 1511 { 1512 U8 Feature; /* 0x00 */ 1513 U8 Reserved1; /* 0x01 */ 1514 U8 MsgLength; /* 0x02 */ 1515 U8 Function; /* 0x03 */ 1516 U16 Reserved2; /* 0x04 */ 1517 U8 Reserved3; /* 0x06 */ 1518 U8 MsgFlags; /* 0x07 */ 1519 U8 VP_ID; /* 0x08 */ 1520 U8 VF_ID; /* 0x09 */ 1521 U16 Reserved4; /* 0x0A */ 1522 U16 Reserved5; /* 0x0C */ 1523 U16 IOCStatus; /* 0x0E */ 1524 U32 IOCLogInfo; /* 0x10 */ 1525 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1526 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 1527 1528 #endif
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