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1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-3-Clause 4 * 5 * Copyright (c) 2000-2010, LSI Logic Corporation and its contributors. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are 10 * met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon including 16 * a substantially similar Disclaimer requirement for further binary 17 * redistribution. 18 * 3. Neither the name of the LSI Logic Corporation nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 32 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * Name: mpi_ioc.h 35 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 36 * Creation Date: August 11, 2000 37 * 38 * mpi_ioc.h Version: 01.05.16 39 * 40 * Version History 41 * --------------- 42 * 43 * Date Version Description 44 * -------- -------- ------------------------------------------------------ 45 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 46 * 05-24-00 00.10.02 Added _MSG_IOC_INIT_REPLY structure. 47 * 06-06-00 01.00.01 Added CurReplyFrameSize field to _MSG_IOC_FACTS_REPLY. 48 * 06-12-00 01.00.02 Added _MSG_PORT_ENABLE_REPLY structure. 49 * Added _MSG_EVENT_ACK_REPLY structure. 50 * Added _MSG_FW_DOWNLOAD_REPLY structure. 51 * Added _MSG_TOOLBOX_REPLY structure. 52 * 06-30-00 01.00.03 Added MaxLanBuckets to _PORT_FACT_REPLY structure. 53 * 07-27-00 01.00.04 Added _EVENT_DATA structure definitions for _SCSI, 54 * _LINK_STATUS, _LOOP_STATE and _LOGOUT. 55 * 08-11-00 01.00.05 Switched positions of MsgLength and Function fields in 56 * _MSG_EVENT_ACK_REPLY structure to match specification. 57 * 11-02-00 01.01.01 Original release for post 1.0 work. 58 * Added a value for Manufacturer to WhoInit. 59 * 12-04-00 01.01.02 Modified IOCFacts reply, added FWUpload messages, and 60 * removed toolbox message. 61 * 01-09-01 01.01.03 Added event enabled and disabled defines. 62 * Added structures for FwHeader and DataHeader. 63 * Added ImageType to FwUpload reply. 64 * 02-20-01 01.01.04 Started using MPI_POINTER. 65 * 02-27-01 01.01.05 Added event for RAID status change and its event data. 66 * Added IocNumber field to MSG_IOC_FACTS_REPLY. 67 * 03-27-01 01.01.06 Added defines for ProductId field of MPI_FW_HEADER. 68 * Added structure offset comments. 69 * 04-09-01 01.01.07 Added structure EVENT_DATA_EVENT_CHANGE. 70 * 08-08-01 01.02.01 Original release for v1.2 work. 71 * New format for FWVersion and ProductId in 72 * MSG_IOC_FACTS_REPLY and MPI_FW_HEADER. 73 * 08-31-01 01.02.02 Addded event MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE and 74 * related structure and defines. 75 * Added event MPI_EVENT_ON_BUS_TIMER_EXPIRED. 76 * Added MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE. 77 * Replaced a reserved field in MSG_IOC_FACTS_REPLY with 78 * IOCExceptions and changed DataImageSize to reserved. 79 * Added MPI_FW_DOWNLOAD_ITYPE_NVSTORE_DATA and 80 * MPI_FW_UPLOAD_ITYPE_NVDATA. 81 * 09-28-01 01.02.03 Modified Event Data for Integrated RAID. 82 * 11-01-01 01.02.04 Added defines for MPI_EXT_IMAGE_HEADER ImageType field. 83 * 03-14-02 01.02.05 Added HeaderVersion field to MSG_IOC_FACTS_REPLY. 84 * 05-31-02 01.02.06 Added define for 85 * MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID. 86 * Added AliasIndex to EVENT_DATA_LOGOUT structure. 87 * 04-01-03 01.02.07 Added defines for MPI_FW_HEADER_SIGNATURE_. 88 * 06-26-03 01.02.08 Added new values to the product family defines. 89 * 04-29-04 01.02.09 Added IOCCapabilities field to MSG_IOC_FACTS_REPLY and 90 * added related defines. 91 * 05-11-04 01.03.01 Original release for MPI v1.3. 92 * 08-19-04 01.05.01 Added four new fields to MSG_IOC_INIT. 93 * Added three new fields to MSG_IOC_FACTS_REPLY. 94 * Defined four new bits for the IOCCapabilities field of 95 * the IOCFacts reply. 96 * Added two new PortTypes for the PortFacts reply. 97 * Added six new events along with their EventData 98 * structures. 99 * Added a new MsgFlag to the FwDownload request to 100 * indicate last segment. 101 * Defined a new image type of boot loader. 102 * Added FW family codes for SAS product families. 103 * 10-05-04 01.05.02 Added ReplyFifoHostSignalingAddr field to 104 * MSG_IOC_FACTS_REPLY. 105 * 12-07-04 01.05.03 Added more defines for SAS Discovery Error event. 106 * 12-09-04 01.05.04 Added Unsupported device to SAS Device event. 107 * 01-15-05 01.05.05 Added event data for SAS SES Event. 108 * 02-09-05 01.05.06 Added MPI_FW_UPLOAD_ITYPE_FW_BACKUP define. 109 * 02-22-05 01.05.07 Added Host Page Buffer Persistent flag to IOC Facts 110 * Reply and IOC Init Request. 111 * 03-11-05 01.05.08 Added family code for 1068E family. 112 * Removed IOCFacts Reply EEDP Capability bit. 113 * 06-24-05 01.05.09 Added 5 new IOCFacts Reply IOCCapabilities bits. 114 * Added Max SATA Targets to SAS Discovery Error event. 115 * 08-30-05 01.05.10 Added 4 new events and their event data structures. 116 * Added new ReasonCode value for SAS Device Status Change 117 * event. 118 * Added new family code for FC949E. 119 * 03-27-06 01.05.11 Added MPI_IOCFACTS_CAPABILITY_TLR. 120 * Added additional Reason Codes and more event data fields 121 * to EVENT_DATA_SAS_DEVICE_STATUS_CHANGE. 122 * Added EVENT_DATA_SAS_BROADCAST_PRIMITIVE structure and 123 * new event. 124 * Added MPI_EVENT_SAS_SMP_ERROR and event data structure. 125 * Added MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE and event 126 * data structure. 127 * Added MPI_EVENT_SAS_INIT_TABLE_OVERFLOW and event 128 * data structure. 129 * Added MPI_EXT_IMAGE_TYPE_INITIALIZATION. 130 * 10-11-06 01.05.12 Added MPI_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED. 131 * Added MaxInitiators field to PortFacts reply. 132 * Added SAS Device Status Change ReasonCode for 133 * asynchronous notificaiton. 134 * Added MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE and event 135 * data structure. 136 * Added new ImageType values for FWDownload and FWUpload 137 * requests. 138 * 02-28-07 01.05.13 Added MPI_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT for SAS 139 * Broadcast Event Data (replacing _RESERVED2). 140 * For Discovery Error Event Data DiscoveryStatus field, 141 * replaced _MULTPL_PATHS with _UNSUPPORTED_DEVICE and 142 * added _MULTI_PORT_DOMAIN. 143 * 05-24-07 01.05.14 Added Common Boot Block type to FWDownload Request. 144 * Added Common Boot Block type to FWUpload Request. 145 * 08-07-07 01.05.15 Added MPI_EVENT_SAS_INIT_RC_REMOVED define. 146 * Added MPI_EVENT_IR2_RC_DUAL_PORT_ADDED and 147 * MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED for IR2 event data. 148 * Added SASAddress field to SAS Initiator Device Table 149 * Overflow event data structure. 150 * 03-28-08 01.05.16 Added two new ReasonCode values to SAS Device Status 151 * Change Event data to indicate completion of internally 152 * generated task management. 153 * Added MPI_EVENT_DSCVRY_ERR_DS_SATA_INIT_FAILURE define. 154 * Added MPI_EVENT_SAS_INIT_RC_INACCESSIBLE define. 155 * -------------------------------------------------------------------------- 156 */ 157 158 #ifndef MPI_IOC_H 159 #define MPI_IOC_H 160 161 /***************************************************************************** 162 * 163 * I O C M e s s a g e s 164 * 165 *****************************************************************************/ 166 167 /****************************************************************************/ 168 /* IOCInit message */ 169 /****************************************************************************/ 170 171 typedef struct _MSG_IOC_INIT 172 { 173 U8 WhoInit; /* 00h */ 174 U8 Reserved; /* 01h */ 175 U8 ChainOffset; /* 02h */ 176 U8 Function; /* 03h */ 177 U8 Flags; /* 04h */ 178 U8 MaxDevices; /* 05h */ 179 U8 MaxBuses; /* 06h */ 180 U8 MsgFlags; /* 07h */ 181 U32 MsgContext; /* 08h */ 182 U16 ReplyFrameSize; /* 0Ch */ 183 U8 Reserved1[2]; /* 0Eh */ 184 U32 HostMfaHighAddr; /* 10h */ 185 U32 SenseBufferHighAddr; /* 14h */ 186 U32 ReplyFifoHostSignalingAddr; /* 18h */ 187 SGE_SIMPLE_UNION HostPageBufferSGE; /* 1Ch */ 188 U16 MsgVersion; /* 28h */ 189 U16 HeaderVersion; /* 2Ah */ 190 } MSG_IOC_INIT, MPI_POINTER PTR_MSG_IOC_INIT, 191 IOCInit_t, MPI_POINTER pIOCInit_t; 192 193 /* WhoInit values */ 194 #define MPI_WHOINIT_NO_ONE (0x00) 195 #define MPI_WHOINIT_SYSTEM_BIOS (0x01) 196 #define MPI_WHOINIT_ROM_BIOS (0x02) 197 #define MPI_WHOINIT_PCI_PEER (0x03) 198 #define MPI_WHOINIT_HOST_DRIVER (0x04) 199 #define MPI_WHOINIT_MANUFACTURER (0x05) 200 201 /* Flags values */ 202 #define MPI_IOCINIT_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (0x04) 203 #define MPI_IOCINIT_FLAGS_REPLY_FIFO_HOST_SIGNAL (0x02) 204 #define MPI_IOCINIT_FLAGS_DISCARD_FW_IMAGE (0x01) 205 206 /* MsgVersion */ 207 #define MPI_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 208 #define MPI_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 209 #define MPI_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 210 #define MPI_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 211 212 /* HeaderVersion */ 213 #define MPI_IOCINIT_HEADERVERSION_UNIT_MASK (0xFF00) 214 #define MPI_IOCINIT_HEADERVERSION_UNIT_SHIFT (8) 215 #define MPI_IOCINIT_HEADERVERSION_DEV_MASK (0x00FF) 216 #define MPI_IOCINIT_HEADERVERSION_DEV_SHIFT (0) 217 218 typedef struct _MSG_IOC_INIT_REPLY 219 { 220 U8 WhoInit; /* 00h */ 221 U8 Reserved; /* 01h */ 222 U8 MsgLength; /* 02h */ 223 U8 Function; /* 03h */ 224 U8 Flags; /* 04h */ 225 U8 MaxDevices; /* 05h */ 226 U8 MaxBuses; /* 06h */ 227 U8 MsgFlags; /* 07h */ 228 U32 MsgContext; /* 08h */ 229 U16 Reserved2; /* 0Ch */ 230 U16 IOCStatus; /* 0Eh */ 231 U32 IOCLogInfo; /* 10h */ 232 } MSG_IOC_INIT_REPLY, MPI_POINTER PTR_MSG_IOC_INIT_REPLY, 233 IOCInitReply_t, MPI_POINTER pIOCInitReply_t; 234 235 /****************************************************************************/ 236 /* IOC Facts message */ 237 /****************************************************************************/ 238 239 typedef struct _MSG_IOC_FACTS 240 { 241 U8 Reserved[2]; /* 00h */ 242 U8 ChainOffset; /* 01h */ 243 U8 Function; /* 02h */ 244 U8 Reserved1[3]; /* 03h */ 245 U8 MsgFlags; /* 04h */ 246 U32 MsgContext; /* 08h */ 247 } MSG_IOC_FACTS, MPI_POINTER PTR_IOC_FACTS, 248 IOCFacts_t, MPI_POINTER pIOCFacts_t; 249 250 typedef struct _MPI_FW_VERSION_STRUCT 251 { 252 U8 Dev; /* 00h */ 253 U8 Unit; /* 01h */ 254 U8 Minor; /* 02h */ 255 U8 Major; /* 03h */ 256 } MPI_FW_VERSION_STRUCT; 257 258 typedef union _MPI_FW_VERSION 259 { 260 MPI_FW_VERSION_STRUCT Struct; 261 U32 Word; 262 } MPI_FW_VERSION; 263 264 /* IOC Facts Reply */ 265 typedef struct _MSG_IOC_FACTS_REPLY 266 { 267 U16 MsgVersion; /* 00h */ 268 U8 MsgLength; /* 02h */ 269 U8 Function; /* 03h */ 270 U16 HeaderVersion; /* 04h */ 271 U8 IOCNumber; /* 06h */ 272 U8 MsgFlags; /* 07h */ 273 U32 MsgContext; /* 08h */ 274 U16 IOCExceptions; /* 0Ch */ 275 U16 IOCStatus; /* 0Eh */ 276 U32 IOCLogInfo; /* 10h */ 277 U8 MaxChainDepth; /* 14h */ 278 U8 WhoInit; /* 15h */ 279 U8 BlockSize; /* 16h */ 280 U8 Flags; /* 17h */ 281 U16 ReplyQueueDepth; /* 18h */ 282 U16 RequestFrameSize; /* 1Ah */ 283 U16 Reserved_0101_FWVersion; /* 1Ch */ /* obsolete 16-bit FWVersion */ 284 U16 ProductID; /* 1Eh */ 285 U32 CurrentHostMfaHighAddr; /* 20h */ 286 U16 GlobalCredits; /* 24h */ 287 U8 NumberOfPorts; /* 26h */ 288 U8 EventState; /* 27h */ 289 U32 CurrentSenseBufferHighAddr; /* 28h */ 290 U16 CurReplyFrameSize; /* 2Ch */ 291 U8 MaxDevices; /* 2Eh */ 292 U8 MaxBuses; /* 2Fh */ 293 U32 FWImageSize; /* 30h */ 294 U32 IOCCapabilities; /* 34h */ 295 MPI_FW_VERSION FWVersion; /* 38h */ 296 U16 HighPriorityQueueDepth; /* 3Ch */ 297 U16 Reserved2; /* 3Eh */ 298 SGE_SIMPLE_UNION HostPageBufferSGE; /* 40h */ 299 U32 ReplyFifoHostSignalingAddr; /* 4Ch */ 300 } MSG_IOC_FACTS_REPLY, MPI_POINTER PTR_MSG_IOC_FACTS_REPLY, 301 IOCFactsReply_t, MPI_POINTER pIOCFactsReply_t; 302 303 #define MPI_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 304 #define MPI_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 305 #define MPI_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 306 #define MPI_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 307 308 #define MPI_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 309 #define MPI_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 310 #define MPI_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 311 #define MPI_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 312 313 #define MPI_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 314 #define MPI_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 315 #define MPI_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 316 #define MPI_IOCFACTS_EXCEPT_PERSISTENT_TABLE_FULL (0x0008) 317 #define MPI_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 318 319 #define MPI_IOCFACTS_FLAGS_FW_DOWNLOAD_BOOT (0x01) 320 #define MPI_IOCFACTS_FLAGS_REPLY_FIFO_HOST_SIGNAL (0x02) 321 #define MPI_IOCFACTS_FLAGS_HOST_PAGE_BUFFER_PERSISTENT (0x04) 322 323 #define MPI_IOCFACTS_EVENTSTATE_DISABLED (0x00) 324 #define MPI_IOCFACTS_EVENTSTATE_ENABLED (0x01) 325 326 #define MPI_IOCFACTS_CAPABILITY_HIGH_PRI_Q (0x00000001) 327 #define MPI_IOCFACTS_CAPABILITY_REPLY_HOST_SIGNAL (0x00000002) 328 #define MPI_IOCFACTS_CAPABILITY_QUEUE_FULL_HANDLING (0x00000004) 329 #define MPI_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 330 #define MPI_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 331 #define MPI_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 332 #define MPI_IOCFACTS_CAPABILITY_EEDP (0x00000040) 333 #define MPI_IOCFACTS_CAPABILITY_BIDIRECTIONAL (0x00000080) 334 #define MPI_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 335 #define MPI_IOCFACTS_CAPABILITY_SCSIIO32 (0x00000200) 336 #define MPI_IOCFACTS_CAPABILITY_NO_SCSIIO16 (0x00000400) 337 #define MPI_IOCFACTS_CAPABILITY_TLR (0x00000800) 338 339 /***************************************************************************** 340 * 341 * P o r t M e s s a g e s 342 * 343 *****************************************************************************/ 344 345 /****************************************************************************/ 346 /* Port Facts message and Reply */ 347 /****************************************************************************/ 348 349 typedef struct _MSG_PORT_FACTS 350 { 351 U8 Reserved[2]; /* 00h */ 352 U8 ChainOffset; /* 02h */ 353 U8 Function; /* 03h */ 354 U8 Reserved1[2]; /* 04h */ 355 U8 PortNumber; /* 06h */ 356 U8 MsgFlags; /* 07h */ 357 U32 MsgContext; /* 08h */ 358 } MSG_PORT_FACTS, MPI_POINTER PTR_MSG_PORT_FACTS, 359 PortFacts_t, MPI_POINTER pPortFacts_t; 360 361 typedef struct _MSG_PORT_FACTS_REPLY 362 { 363 U16 Reserved; /* 00h */ 364 U8 MsgLength; /* 02h */ 365 U8 Function; /* 03h */ 366 U16 Reserved1; /* 04h */ 367 U8 PortNumber; /* 06h */ 368 U8 MsgFlags; /* 07h */ 369 U32 MsgContext; /* 08h */ 370 U16 Reserved2; /* 0Ch */ 371 U16 IOCStatus; /* 0Eh */ 372 U32 IOCLogInfo; /* 10h */ 373 U8 Reserved3; /* 14h */ 374 U8 PortType; /* 15h */ 375 U16 MaxDevices; /* 16h */ 376 U16 PortSCSIID; /* 18h */ 377 U16 ProtocolFlags; /* 1Ah */ 378 U16 MaxPostedCmdBuffers; /* 1Ch */ 379 U16 MaxPersistentIDs; /* 1Eh */ 380 U16 MaxLanBuckets; /* 20h */ 381 U8 MaxInitiators; /* 22h */ 382 U8 Reserved4; /* 23h */ 383 U32 Reserved5; /* 24h */ 384 } MSG_PORT_FACTS_REPLY, MPI_POINTER PTR_MSG_PORT_FACTS_REPLY, 385 PortFactsReply_t, MPI_POINTER pPortFactsReply_t; 386 387 /* PortTypes values */ 388 389 #define MPI_PORTFACTS_PORTTYPE_INACTIVE (0x00) 390 #define MPI_PORTFACTS_PORTTYPE_SCSI (0x01) 391 #define MPI_PORTFACTS_PORTTYPE_FC (0x10) 392 #define MPI_PORTFACTS_PORTTYPE_ISCSI (0x20) 393 #define MPI_PORTFACTS_PORTTYPE_SAS (0x30) 394 395 /* ProtocolFlags values */ 396 397 #define MPI_PORTFACTS_PROTOCOL_LOGBUSADDR (0x01) 398 #define MPI_PORTFACTS_PROTOCOL_LAN (0x02) 399 #define MPI_PORTFACTS_PROTOCOL_TARGET (0x04) 400 #define MPI_PORTFACTS_PROTOCOL_INITIATOR (0x08) 401 402 /****************************************************************************/ 403 /* Port Enable Message */ 404 /****************************************************************************/ 405 406 typedef struct _MSG_PORT_ENABLE 407 { 408 U8 Reserved[2]; /* 00h */ 409 U8 ChainOffset; /* 02h */ 410 U8 Function; /* 03h */ 411 U8 Reserved1[2]; /* 04h */ 412 U8 PortNumber; /* 06h */ 413 U8 MsgFlags; /* 07h */ 414 U32 MsgContext; /* 08h */ 415 } MSG_PORT_ENABLE, MPI_POINTER PTR_MSG_PORT_ENABLE, 416 PortEnable_t, MPI_POINTER pPortEnable_t; 417 418 typedef struct _MSG_PORT_ENABLE_REPLY 419 { 420 U8 Reserved[2]; /* 00h */ 421 U8 MsgLength; /* 02h */ 422 U8 Function; /* 03h */ 423 U8 Reserved1[2]; /* 04h */ 424 U8 PortNumber; /* 05h */ 425 U8 MsgFlags; /* 07h */ 426 U32 MsgContext; /* 08h */ 427 U16 Reserved2; /* 0Ch */ 428 U16 IOCStatus; /* 0Eh */ 429 U32 IOCLogInfo; /* 10h */ 430 } MSG_PORT_ENABLE_REPLY, MPI_POINTER PTR_MSG_PORT_ENABLE_REPLY, 431 PortEnableReply_t, MPI_POINTER pPortEnableReply_t; 432 433 /***************************************************************************** 434 * 435 * E v e n t M e s s a g e s 436 * 437 *****************************************************************************/ 438 439 /****************************************************************************/ 440 /* Event Notification messages */ 441 /****************************************************************************/ 442 443 typedef struct _MSG_EVENT_NOTIFY 444 { 445 U8 Switch; /* 00h */ 446 U8 Reserved; /* 01h */ 447 U8 ChainOffset; /* 02h */ 448 U8 Function; /* 03h */ 449 U8 Reserved1[3]; /* 04h */ 450 U8 MsgFlags; /* 07h */ 451 U32 MsgContext; /* 08h */ 452 } MSG_EVENT_NOTIFY, MPI_POINTER PTR_MSG_EVENT_NOTIFY, 453 EventNotification_t, MPI_POINTER pEventNotification_t; 454 455 /* Event Notification Reply */ 456 457 typedef struct _MSG_EVENT_NOTIFY_REPLY 458 { 459 U16 EventDataLength; /* 00h */ 460 U8 MsgLength; /* 02h */ 461 U8 Function; /* 03h */ 462 U8 Reserved1[2]; /* 04h */ 463 U8 AckRequired; /* 06h */ 464 U8 MsgFlags; /* 07h */ 465 U32 MsgContext; /* 08h */ 466 U8 Reserved2[2]; /* 0Ch */ 467 U16 IOCStatus; /* 0Eh */ 468 U32 IOCLogInfo; /* 10h */ 469 U32 Event; /* 14h */ 470 U32 EventContext; /* 18h */ 471 U32 Data[1]; /* 1Ch */ 472 } MSG_EVENT_NOTIFY_REPLY, MPI_POINTER PTR_MSG_EVENT_NOTIFY_REPLY, 473 EventNotificationReply_t, MPI_POINTER pEventNotificationReply_t; 474 475 /* Event Acknowledge */ 476 477 typedef struct _MSG_EVENT_ACK 478 { 479 U8 Reserved[2]; /* 00h */ 480 U8 ChainOffset; /* 02h */ 481 U8 Function; /* 03h */ 482 U8 Reserved1[3]; /* 04h */ 483 U8 MsgFlags; /* 07h */ 484 U32 MsgContext; /* 08h */ 485 U32 Event; /* 0Ch */ 486 U32 EventContext; /* 10h */ 487 } MSG_EVENT_ACK, MPI_POINTER PTR_MSG_EVENT_ACK, 488 EventAck_t, MPI_POINTER pEventAck_t; 489 490 typedef struct _MSG_EVENT_ACK_REPLY 491 { 492 U8 Reserved[2]; /* 00h */ 493 U8 MsgLength; /* 02h */ 494 U8 Function; /* 03h */ 495 U8 Reserved1[3]; /* 04h */ 496 U8 MsgFlags; /* 07h */ 497 U32 MsgContext; /* 08h */ 498 U16 Reserved2; /* 0Ch */ 499 U16 IOCStatus; /* 0Eh */ 500 U32 IOCLogInfo; /* 10h */ 501 } MSG_EVENT_ACK_REPLY, MPI_POINTER PTR_MSG_EVENT_ACK_REPLY, 502 EventAckReply_t, MPI_POINTER pEventAckReply_t; 503 504 /* Switch */ 505 506 #define MPI_EVENT_NOTIFICATION_SWITCH_OFF (0x00) 507 #define MPI_EVENT_NOTIFICATION_SWITCH_ON (0x01) 508 509 /* Event */ 510 511 #define MPI_EVENT_NONE (0x00000000) 512 #define MPI_EVENT_LOG_DATA (0x00000001) 513 #define MPI_EVENT_STATE_CHANGE (0x00000002) 514 #define MPI_EVENT_UNIT_ATTENTION (0x00000003) 515 #define MPI_EVENT_IOC_BUS_RESET (0x00000004) 516 #define MPI_EVENT_EXT_BUS_RESET (0x00000005) 517 #define MPI_EVENT_RESCAN (0x00000006) 518 #define MPI_EVENT_LINK_STATUS_CHANGE (0x00000007) 519 #define MPI_EVENT_LOOP_STATE_CHANGE (0x00000008) 520 #define MPI_EVENT_LOGOUT (0x00000009) 521 #define MPI_EVENT_EVENT_CHANGE (0x0000000A) 522 #define MPI_EVENT_INTEGRATED_RAID (0x0000000B) 523 #define MPI_EVENT_SCSI_DEVICE_STATUS_CHANGE (0x0000000C) 524 #define MPI_EVENT_ON_BUS_TIMER_EXPIRED (0x0000000D) 525 #define MPI_EVENT_QUEUE_FULL (0x0000000E) 526 #define MPI_EVENT_SAS_DEVICE_STATUS_CHANGE (0x0000000F) 527 #define MPI_EVENT_SAS_SES (0x00000010) 528 #define MPI_EVENT_PERSISTENT_TABLE_FULL (0x00000011) 529 #define MPI_EVENT_SAS_PHY_LINK_STATUS (0x00000012) 530 #define MPI_EVENT_SAS_DISCOVERY_ERROR (0x00000013) 531 #define MPI_EVENT_IR_RESYNC_UPDATE (0x00000014) 532 #define MPI_EVENT_IR2 (0x00000015) 533 #define MPI_EVENT_SAS_DISCOVERY (0x00000016) 534 #define MPI_EVENT_SAS_BROADCAST_PRIMITIVE (0x00000017) 535 #define MPI_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x00000018) 536 #define MPI_EVENT_SAS_INIT_TABLE_OVERFLOW (0x00000019) 537 #define MPI_EVENT_SAS_SMP_ERROR (0x0000001A) 538 #define MPI_EVENT_SAS_EXPANDER_STATUS_CHANGE (0x0000001B) 539 #define MPI_EVENT_LOG_ENTRY_ADDED (0x00000021) 540 541 /* AckRequired field values */ 542 543 #define MPI_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 544 #define MPI_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 545 546 /* EventChange Event data */ 547 548 typedef struct _EVENT_DATA_EVENT_CHANGE 549 { 550 U8 EventState; /* 00h */ 551 U8 Reserved; /* 01h */ 552 U16 Reserved1; /* 02h */ 553 } EVENT_DATA_EVENT_CHANGE, MPI_POINTER PTR_EVENT_DATA_EVENT_CHANGE, 554 EventDataEventChange_t, MPI_POINTER pEventDataEventChange_t; 555 556 /* LogEntryAdded Event data */ 557 558 /* this structure matches MPI_LOG_0_ENTRY in mpi_cnfg.h */ 559 #define MPI_EVENT_DATA_LOG_ENTRY_DATA_LENGTH (0x1C) 560 typedef struct _EVENT_DATA_LOG_ENTRY 561 { 562 U32 TimeStamp; /* 00h */ 563 U32 Reserved1; /* 04h */ 564 U16 LogSequence; /* 08h */ 565 U16 LogEntryQualifier; /* 0Ah */ 566 U8 LogData[MPI_EVENT_DATA_LOG_ENTRY_DATA_LENGTH]; /* 0Ch */ 567 } EVENT_DATA_LOG_ENTRY, MPI_POINTER PTR_EVENT_DATA_LOG_ENTRY, 568 MpiEventDataLogEntry_t, MPI_POINTER pMpiEventDataLogEntry_t; 569 570 typedef struct _EVENT_DATA_LOG_ENTRY_ADDED 571 { 572 U16 LogSequence; /* 00h */ 573 U16 Reserved1; /* 02h */ 574 U32 Reserved2; /* 04h */ 575 EVENT_DATA_LOG_ENTRY LogEntry; /* 08h */ 576 } EVENT_DATA_LOG_ENTRY_ADDED, MPI_POINTER PTR_EVENT_DATA_LOG_ENTRY_ADDED, 577 MpiEventDataLogEntryAdded_t, MPI_POINTER pMpiEventDataLogEntryAdded_t; 578 579 /* SCSI Event data for Port, Bus and Device forms */ 580 581 typedef struct _EVENT_DATA_SCSI 582 { 583 U8 TargetID; /* 00h */ 584 U8 BusPort; /* 01h */ 585 U16 Reserved; /* 02h */ 586 } EVENT_DATA_SCSI, MPI_POINTER PTR_EVENT_DATA_SCSI, 587 EventDataScsi_t, MPI_POINTER pEventDataScsi_t; 588 589 /* SCSI Device Status Change Event data */ 590 591 typedef struct _EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE 592 { 593 U8 TargetID; /* 00h */ 594 U8 Bus; /* 01h */ 595 U8 ReasonCode; /* 02h */ 596 U8 LUN; /* 03h */ 597 U8 ASC; /* 04h */ 598 U8 ASCQ; /* 05h */ 599 U16 Reserved; /* 06h */ 600 } EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 601 MPI_POINTER PTR_EVENT_DATA_SCSI_DEVICE_STATUS_CHANGE, 602 MpiEventDataScsiDeviceStatusChange_t, 603 MPI_POINTER pMpiEventDataScsiDeviceStatusChange_t; 604 605 /* MPI SCSI Device Status Change Event data ReasonCode values */ 606 #define MPI_EVENT_SCSI_DEV_STAT_RC_ADDED (0x03) 607 #define MPI_EVENT_SCSI_DEV_STAT_RC_NOT_RESPONDING (0x04) 608 #define MPI_EVENT_SCSI_DEV_STAT_RC_SMART_DATA (0x05) 609 610 /* SAS Device Status Change Event data */ 611 612 typedef struct _EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 613 { 614 U8 TargetID; /* 00h */ 615 U8 Bus; /* 01h */ 616 U8 ReasonCode; /* 02h */ 617 U8 Reserved; /* 03h */ 618 U8 ASC; /* 04h */ 619 U8 ASCQ; /* 05h */ 620 U16 DevHandle; /* 06h */ 621 U32 DeviceInfo; /* 08h */ 622 U16 ParentDevHandle; /* 0Ch */ 623 U8 PhyNum; /* 0Eh */ 624 U8 Reserved1; /* 0Fh */ 625 U64 SASAddress; /* 10h */ 626 U8 LUN[8]; /* 18h */ 627 U16 TaskTag; /* 20h */ 628 U16 Reserved2; /* 22h */ 629 } EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 630 MPI_POINTER PTR_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 631 MpiEventDataSasDeviceStatusChange_t, 632 MPI_POINTER pMpiEventDataSasDeviceStatusChange_t; 633 634 /* MPI SAS Device Status Change Event data ReasonCode values */ 635 #define MPI_EVENT_SAS_DEV_STAT_RC_ADDED (0x03) 636 #define MPI_EVENT_SAS_DEV_STAT_RC_NOT_RESPONDING (0x04) 637 #define MPI_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 638 #define MPI_EVENT_SAS_DEV_STAT_RC_NO_PERSIST_ADDED (0x06) 639 #define MPI_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 640 #define MPI_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 641 #define MPI_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 642 #define MPI_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 643 #define MPI_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 644 #define MPI_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 645 #define MPI_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 646 #define MPI_EVENT_SAS_DEV_STAT_RC_CMPL_INTERNAL_DEV_RESET (0x0E) 647 #define MPI_EVENT_SAS_DEV_STAT_RC_CMPL_TASK_ABORT_INTERNAL (0x0F) 648 649 /* SCSI Event data for Queue Full event */ 650 651 typedef struct _EVENT_DATA_QUEUE_FULL 652 { 653 U8 TargetID; /* 00h */ 654 U8 Bus; /* 01h */ 655 U16 CurrentDepth; /* 02h */ 656 } EVENT_DATA_QUEUE_FULL, MPI_POINTER PTR_EVENT_DATA_QUEUE_FULL, 657 EventDataQueueFull_t, MPI_POINTER pEventDataQueueFull_t; 658 659 /* MPI Integrated RAID Event data */ 660 661 typedef struct _EVENT_DATA_RAID 662 { 663 U8 VolumeID; /* 00h */ 664 U8 VolumeBus; /* 01h */ 665 U8 ReasonCode; /* 02h */ 666 U8 PhysDiskNum; /* 03h */ 667 U8 ASC; /* 04h */ 668 U8 ASCQ; /* 05h */ 669 U16 Reserved; /* 06h */ 670 U32 SettingsStatus; /* 08h */ 671 } EVENT_DATA_RAID, MPI_POINTER PTR_EVENT_DATA_RAID, 672 MpiEventDataRaid_t, MPI_POINTER pMpiEventDataRaid_t; 673 674 /* MPI Integrated RAID Event data ReasonCode values */ 675 #define MPI_EVENT_RAID_RC_VOLUME_CREATED (0x00) 676 #define MPI_EVENT_RAID_RC_VOLUME_DELETED (0x01) 677 #define MPI_EVENT_RAID_RC_VOLUME_SETTINGS_CHANGED (0x02) 678 #define MPI_EVENT_RAID_RC_VOLUME_STATUS_CHANGED (0x03) 679 #define MPI_EVENT_RAID_RC_VOLUME_PHYSDISK_CHANGED (0x04) 680 #define MPI_EVENT_RAID_RC_PHYSDISK_CREATED (0x05) 681 #define MPI_EVENT_RAID_RC_PHYSDISK_DELETED (0x06) 682 #define MPI_EVENT_RAID_RC_PHYSDISK_SETTINGS_CHANGED (0x07) 683 #define MPI_EVENT_RAID_RC_PHYSDISK_STATUS_CHANGED (0x08) 684 #define MPI_EVENT_RAID_RC_DOMAIN_VAL_NEEDED (0x09) 685 #define MPI_EVENT_RAID_RC_SMART_DATA (0x0A) 686 #define MPI_EVENT_RAID_RC_REPLACE_ACTION_STARTED (0x0B) 687 688 /* MPI Integrated RAID Resync Update Event data */ 689 690 typedef struct _MPI_EVENT_DATA_IR_RESYNC_UPDATE 691 { 692 U8 VolumeID; /* 00h */ 693 U8 VolumeBus; /* 01h */ 694 U8 ResyncComplete; /* 02h */ 695 U8 Reserved1; /* 03h */ 696 U32 Reserved2; /* 04h */ 697 } MPI_EVENT_DATA_IR_RESYNC_UPDATE, 698 MPI_POINTER PTR_MPI_EVENT_DATA_IR_RESYNC_UPDATE, 699 MpiEventDataIrResyncUpdate_t, MPI_POINTER pMpiEventDataIrResyncUpdate_t; 700 701 /* MPI IR2 Event data */ 702 703 /* MPI_LD_STATE or MPI_PD_STATE */ 704 typedef struct _IR2_STATE_CHANGED 705 { 706 U16 PreviousState; /* 00h */ 707 U16 NewState; /* 02h */ 708 } IR2_STATE_CHANGED, MPI_POINTER PTR_IR2_STATE_CHANGED; 709 710 typedef struct _IR2_PD_INFO 711 { 712 U16 DeviceHandle; /* 00h */ 713 U8 TruncEnclosureHandle; /* 02h */ 714 U8 TruncatedSlot; /* 03h */ 715 } IR2_PD_INFO, MPI_POINTER PTR_IR2_PD_INFO; 716 717 typedef union _MPI_IR2_RC_EVENT_DATA 718 { 719 IR2_STATE_CHANGED StateChanged; 720 U32 Lba; 721 IR2_PD_INFO PdInfo; 722 } MPI_IR2_RC_EVENT_DATA, MPI_POINTER PTR_MPI_IR2_RC_EVENT_DATA; 723 724 typedef struct _MPI_EVENT_DATA_IR2 725 { 726 U8 TargetID; /* 00h */ 727 U8 Bus; /* 01h */ 728 U8 ReasonCode; /* 02h */ 729 U8 PhysDiskNum; /* 03h */ 730 MPI_IR2_RC_EVENT_DATA IR2EventData; /* 04h */ 731 } MPI_EVENT_DATA_IR2, MPI_POINTER PTR_MPI_EVENT_DATA_IR2, 732 MpiEventDataIR2_t, MPI_POINTER pMpiEventDataIR2_t; 733 734 /* MPI IR2 Event data ReasonCode values */ 735 #define MPI_EVENT_IR2_RC_LD_STATE_CHANGED (0x01) 736 #define MPI_EVENT_IR2_RC_PD_STATE_CHANGED (0x02) 737 #define MPI_EVENT_IR2_RC_BAD_BLOCK_TABLE_FULL (0x03) 738 #define MPI_EVENT_IR2_RC_PD_INSERTED (0x04) 739 #define MPI_EVENT_IR2_RC_PD_REMOVED (0x05) 740 #define MPI_EVENT_IR2_RC_FOREIGN_CFG_DETECTED (0x06) 741 #define MPI_EVENT_IR2_RC_REBUILD_MEDIUM_ERROR (0x07) 742 #define MPI_EVENT_IR2_RC_DUAL_PORT_ADDED (0x08) 743 #define MPI_EVENT_IR2_RC_DUAL_PORT_REMOVED (0x09) 744 745 /* defines for logical disk states */ 746 #define MPI_LD_STATE_OPTIMAL (0x00) 747 #define MPI_LD_STATE_DEGRADED (0x01) 748 #define MPI_LD_STATE_FAILED (0x02) 749 #define MPI_LD_STATE_MISSING (0x03) 750 #define MPI_LD_STATE_OFFLINE (0x04) 751 752 /* defines for physical disk states */ 753 #define MPI_PD_STATE_ONLINE (0x00) 754 #define MPI_PD_STATE_MISSING (0x01) 755 #define MPI_PD_STATE_NOT_COMPATIBLE (0x02) 756 #define MPI_PD_STATE_FAILED (0x03) 757 #define MPI_PD_STATE_INITIALIZING (0x04) 758 #define MPI_PD_STATE_OFFLINE_AT_HOST_REQUEST (0x05) 759 #define MPI_PD_STATE_FAILED_AT_HOST_REQUEST (0x06) 760 #define MPI_PD_STATE_OFFLINE_FOR_ANOTHER_REASON (0xFF) 761 762 /* MPI Link Status Change Event data */ 763 764 typedef struct _EVENT_DATA_LINK_STATUS 765 { 766 U8 State; /* 00h */ 767 U8 Reserved; /* 01h */ 768 U16 Reserved1; /* 02h */ 769 U8 Reserved2; /* 04h */ 770 U8 Port; /* 05h */ 771 U16 Reserved3; /* 06h */ 772 } EVENT_DATA_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_LINK_STATUS, 773 EventDataLinkStatus_t, MPI_POINTER pEventDataLinkStatus_t; 774 775 #define MPI_EVENT_LINK_STATUS_FAILURE (0x00000000) 776 #define MPI_EVENT_LINK_STATUS_ACTIVE (0x00000001) 777 778 /* MPI Loop State Change Event data */ 779 780 typedef struct _EVENT_DATA_LOOP_STATE 781 { 782 U8 Character4; /* 00h */ 783 U8 Character3; /* 01h */ 784 U8 Type; /* 02h */ 785 U8 Reserved; /* 03h */ 786 U8 Reserved1; /* 04h */ 787 U8 Port; /* 05h */ 788 U16 Reserved2; /* 06h */ 789 } EVENT_DATA_LOOP_STATE, MPI_POINTER PTR_EVENT_DATA_LOOP_STATE, 790 EventDataLoopState_t, MPI_POINTER pEventDataLoopState_t; 791 792 #define MPI_EVENT_LOOP_STATE_CHANGE_LIP (0x0001) 793 #define MPI_EVENT_LOOP_STATE_CHANGE_LPE (0x0002) 794 #define MPI_EVENT_LOOP_STATE_CHANGE_LPB (0x0003) 795 796 /* MPI LOGOUT Event data */ 797 798 typedef struct _EVENT_DATA_LOGOUT 799 { 800 U32 NPortID; /* 00h */ 801 U8 AliasIndex; /* 04h */ 802 U8 Port; /* 05h */ 803 U16 Reserved1; /* 06h */ 804 } EVENT_DATA_LOGOUT, MPI_POINTER PTR_EVENT_DATA_LOGOUT, 805 EventDataLogout_t, MPI_POINTER pEventDataLogout_t; 806 807 #define MPI_EVENT_LOGOUT_ALL_ALIASES (0xFF) 808 809 /* SAS SES Event data */ 810 811 typedef struct _EVENT_DATA_SAS_SES 812 { 813 U8 PhyNum; /* 00h */ 814 U8 Port; /* 01h */ 815 U8 PortWidth; /* 02h */ 816 U8 Reserved1; /* 04h */ 817 } EVENT_DATA_SAS_SES, MPI_POINTER PTR_EVENT_DATA_SAS_SES, 818 MpiEventDataSasSes_t, MPI_POINTER pMpiEventDataSasSes_t; 819 820 /* SAS Broadcast Primitive Event data */ 821 822 typedef struct _EVENT_DATA_SAS_BROADCAST_PRIMITIVE 823 { 824 U8 PhyNum; /* 00h */ 825 U8 Port; /* 01h */ 826 U8 PortWidth; /* 02h */ 827 U8 Primitive; /* 04h */ 828 } EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 829 MPI_POINTER PTR_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 830 MpiEventDataSasBroadcastPrimitive_t, 831 MPI_POINTER pMpiEventDataSasBroadcastPrimitive_t; 832 833 #define MPI_EVENT_PRIMITIVE_CHANGE (0x01) 834 #define MPI_EVENT_PRIMITIVE_EXPANDER (0x03) 835 #define MPI_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 836 #define MPI_EVENT_PRIMITIVE_RESERVED3 (0x05) 837 #define MPI_EVENT_PRIMITIVE_RESERVED4 (0x06) 838 #define MPI_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 839 #define MPI_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 840 841 /* SAS Phy Link Status Event data */ 842 843 typedef struct _EVENT_DATA_SAS_PHY_LINK_STATUS 844 { 845 U8 PhyNum; /* 00h */ 846 U8 LinkRates; /* 01h */ 847 U16 DevHandle; /* 02h */ 848 U64 SASAddress; /* 04h */ 849 } EVENT_DATA_SAS_PHY_LINK_STATUS, MPI_POINTER PTR_EVENT_DATA_SAS_PHY_LINK_STATUS, 850 MpiEventDataSasPhyLinkStatus_t, MPI_POINTER pMpiEventDataSasPhyLinkStatus_t; 851 852 /* defines for the LinkRates field of the SAS PHY Link Status event */ 853 #define MPI_EVENT_SAS_PLS_LR_CURRENT_MASK (0xF0) 854 #define MPI_EVENT_SAS_PLS_LR_CURRENT_SHIFT (4) 855 #define MPI_EVENT_SAS_PLS_LR_PREVIOUS_MASK (0x0F) 856 #define MPI_EVENT_SAS_PLS_LR_PREVIOUS_SHIFT (0) 857 #define MPI_EVENT_SAS_PLS_LR_RATE_UNKNOWN (0x00) 858 #define MPI_EVENT_SAS_PLS_LR_RATE_PHY_DISABLED (0x01) 859 #define MPI_EVENT_SAS_PLS_LR_RATE_FAILED_SPEED_NEGOTIATION (0x02) 860 #define MPI_EVENT_SAS_PLS_LR_RATE_SATA_OOB_COMPLETE (0x03) 861 #define MPI_EVENT_SAS_PLS_LR_RATE_1_5 (0x08) 862 #define MPI_EVENT_SAS_PLS_LR_RATE_3_0 (0x09) 863 #define MPI_EVENT_SAS_PLS_LR_RATE_6_0 (0x0A) 864 865 /* SAS Discovery Event data */ 866 867 typedef struct _EVENT_DATA_SAS_DISCOVERY 868 { 869 U32 DiscoveryStatus; /* 00h */ 870 U32 Reserved1; /* 04h */ 871 } EVENT_DATA_SAS_DISCOVERY, MPI_POINTER PTR_EVENT_DATA_SAS_DISCOVERY, 872 EventDataSasDiscovery_t, MPI_POINTER pEventDataSasDiscovery_t; 873 874 #define MPI_EVENT_SAS_DSCVRY_COMPLETE (0x00000000) 875 #define MPI_EVENT_SAS_DSCVRY_IN_PROGRESS (0x00000001) 876 #define MPI_EVENT_SAS_DSCVRY_PHY_BITS_MASK (0xFFFF0000) 877 #define MPI_EVENT_SAS_DSCVRY_PHY_BITS_SHIFT (16) 878 879 /* SAS Discovery Errror Event data */ 880 881 typedef struct _EVENT_DATA_DISCOVERY_ERROR 882 { 883 U32 DiscoveryStatus; /* 00h */ 884 U8 Port; /* 04h */ 885 U8 Reserved1; /* 05h */ 886 U16 Reserved2; /* 06h */ 887 } EVENT_DATA_DISCOVERY_ERROR, MPI_POINTER PTR_EVENT_DATA_DISCOVERY_ERROR, 888 EventDataDiscoveryError_t, MPI_POINTER pEventDataDiscoveryError_t; 889 890 #define MPI_EVENT_DSCVRY_ERR_DS_LOOP_DETECTED (0x00000001) 891 #define MPI_EVENT_DSCVRY_ERR_DS_UNADDRESSABLE_DEVICE (0x00000002) 892 #define MPI_EVENT_DSCVRY_ERR_DS_MULTIPLE_PORTS (0x00000004) 893 #define MPI_EVENT_DSCVRY_ERR_DS_EXPANDER_ERR (0x00000008) 894 #define MPI_EVENT_DSCVRY_ERR_DS_SMP_TIMEOUT (0x00000010) 895 #define MPI_EVENT_DSCVRY_ERR_DS_OUT_ROUTE_ENTRIES (0x00000020) 896 #define MPI_EVENT_DSCVRY_ERR_DS_INDEX_NOT_EXIST (0x00000040) 897 #define MPI_EVENT_DSCVRY_ERR_DS_SMP_FUNCTION_FAILED (0x00000080) 898 #define MPI_EVENT_DSCVRY_ERR_DS_SMP_CRC_ERROR (0x00000100) 899 #define MPI_EVENT_DSCVRY_ERR_DS_MULTPL_SUBTRACTIVE (0x00000200) 900 #define MPI_EVENT_DSCVRY_ERR_DS_TABLE_TO_TABLE (0x00000400) 901 #define MPI_EVENT_DSCVRY_ERR_DS_UNSUPPORTED_DEVICE (0x00000800) 902 #define MPI_EVENT_DSCVRY_ERR_DS_MAX_SATA_TARGETS (0x00001000) 903 #define MPI_EVENT_DSCVRY_ERR_DS_MULTI_PORT_DOMAIN (0x00002000) 904 #define MPI_EVENT_DSCVRY_ERR_DS_SATA_INIT_FAILURE (0x00004000) 905 906 /* SAS SMP Error Event data */ 907 908 typedef struct _EVENT_DATA_SAS_SMP_ERROR 909 { 910 U8 Status; /* 00h */ 911 U8 Port; /* 01h */ 912 U8 SMPFunctionResult; /* 02h */ 913 U8 Reserved1; /* 03h */ 914 U64 SASAddress; /* 04h */ 915 } EVENT_DATA_SAS_SMP_ERROR, MPI_POINTER PTR_EVENT_DATA_SAS_SMP_ERROR, 916 MpiEventDataSasSmpError_t, MPI_POINTER pMpiEventDataSasSmpError_t; 917 918 /* defines for the Status field of the SAS SMP Error event */ 919 #define MPI_EVENT_SAS_SMP_FUNCTION_RESULT_VALID (0x00) 920 #define MPI_EVENT_SAS_SMP_CRC_ERROR (0x01) 921 #define MPI_EVENT_SAS_SMP_TIMEOUT (0x02) 922 #define MPI_EVENT_SAS_SMP_NO_DESTINATION (0x03) 923 #define MPI_EVENT_SAS_SMP_BAD_DESTINATION (0x04) 924 925 /* SAS Initiator Device Status Change Event data */ 926 927 typedef struct _EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 928 { 929 U8 ReasonCode; /* 00h */ 930 U8 Port; /* 01h */ 931 U16 DevHandle; /* 02h */ 932 U64 SASAddress; /* 04h */ 933 } EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 934 MPI_POINTER PTR_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 935 MpiEventDataSasInitDevStatusChange_t, 936 MPI_POINTER pMpiEventDataSasInitDevStatusChange_t; 937 938 /* defines for the ReasonCode field of the SAS Initiator Device Status Change event */ 939 #define MPI_EVENT_SAS_INIT_RC_ADDED (0x01) 940 #define MPI_EVENT_SAS_INIT_RC_REMOVED (0x02) 941 #define MPI_EVENT_SAS_INIT_RC_INACCESSIBLE (0x03) 942 943 /* SAS Initiator Device Table Overflow Event data */ 944 945 typedef struct _EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 946 { 947 U8 MaxInit; /* 00h */ 948 U8 CurrentInit; /* 01h */ 949 U16 Reserved1; /* 02h */ 950 U64 SASAddress; /* 04h */ 951 } EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 952 MPI_POINTER PTR_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 953 MpiEventDataSasInitTableOverflow_t, 954 MPI_POINTER pMpiEventDataSasInitTableOverflow_t; 955 956 /* SAS Expander Status Change Event data */ 957 958 typedef struct _EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE 959 { 960 U8 ReasonCode; /* 00h */ 961 U8 Reserved1; /* 01h */ 962 U16 Reserved2; /* 02h */ 963 U8 PhysicalPort; /* 04h */ 964 U8 Reserved3; /* 05h */ 965 U16 EnclosureHandle; /* 06h */ 966 U64 SASAddress; /* 08h */ 967 U32 DiscoveryStatus; /* 10h */ 968 U16 DevHandle; /* 14h */ 969 U16 ParentDevHandle; /* 16h */ 970 U16 ExpanderChangeCount; /* 18h */ 971 U16 ExpanderRouteIndexes; /* 1Ah */ 972 U8 NumPhys; /* 1Ch */ 973 U8 SASLevel; /* 1Dh */ 974 U8 Flags; /* 1Eh */ 975 U8 Reserved4; /* 1Fh */ 976 } EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE, 977 MPI_POINTER PTR_EVENT_DATA_SAS_EXPANDER_STATUS_CHANGE, 978 MpiEventDataSasExpanderStatusChange_t, 979 MPI_POINTER pMpiEventDataSasExpanderStatusChange_t; 980 981 /* values for ReasonCode field of SAS Expander Status Change Event data */ 982 #define MPI_EVENT_SAS_EXP_RC_ADDED (0x00) 983 #define MPI_EVENT_SAS_EXP_RC_NOT_RESPONDING (0x01) 984 985 /* values for DiscoveryStatus field of SAS Expander Status Change Event data */ 986 #define MPI_EVENT_SAS_EXP_DS_LOOP_DETECTED (0x00000001) 987 #define MPI_EVENT_SAS_EXP_DS_UNADDRESSABLE_DEVICE (0x00000002) 988 #define MPI_EVENT_SAS_EXP_DS_MULTIPLE_PORTS (0x00000004) 989 #define MPI_EVENT_SAS_EXP_DS_EXPANDER_ERR (0x00000008) 990 #define MPI_EVENT_SAS_EXP_DS_SMP_TIMEOUT (0x00000010) 991 #define MPI_EVENT_SAS_EXP_DS_OUT_ROUTE_ENTRIES (0x00000020) 992 #define MPI_EVENT_SAS_EXP_DS_INDEX_NOT_EXIST (0x00000040) 993 #define MPI_EVENT_SAS_EXP_DS_SMP_FUNCTION_FAILED (0x00000080) 994 #define MPI_EVENT_SAS_EXP_DS_SMP_CRC_ERROR (0x00000100) 995 #define MPI_EVENT_SAS_EXP_DS_SUBTRACTIVE_LINK (0x00000200) 996 #define MPI_EVENT_SAS_EXP_DS_TABLE_LINK (0x00000400) 997 #define MPI_EVENT_SAS_EXP_DS_UNSUPPORTED_DEVICE (0x00000800) 998 999 /* values for Flags field of SAS Expander Status Change Event data */ 1000 #define MPI_EVENT_SAS_EXP_FLAGS_ROUTE_TABLE_CONFIG (0x02) 1001 #define MPI_EVENT_SAS_EXP_FLAGS_CONFIG_IN_PROGRESS (0x01) 1002 1003 /***************************************************************************** 1004 * 1005 * F i r m w a r e L o a d M e s s a g e s 1006 * 1007 *****************************************************************************/ 1008 1009 /****************************************************************************/ 1010 /* Firmware Download message and associated structures */ 1011 /****************************************************************************/ 1012 1013 typedef struct _MSG_FW_DOWNLOAD 1014 { 1015 U8 ImageType; /* 00h */ 1016 U8 Reserved; /* 01h */ 1017 U8 ChainOffset; /* 02h */ 1018 U8 Function; /* 03h */ 1019 U8 Reserved1[3]; /* 04h */ 1020 U8 MsgFlags; /* 07h */ 1021 U32 MsgContext; /* 08h */ 1022 SGE_MPI_UNION SGL; /* 0Ch */ 1023 } MSG_FW_DOWNLOAD, MPI_POINTER PTR_MSG_FW_DOWNLOAD, 1024 FWDownload_t, MPI_POINTER pFWDownload_t; 1025 1026 #define MPI_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1027 1028 #define MPI_FW_DOWNLOAD_ITYPE_RESERVED (0x00) 1029 #define MPI_FW_DOWNLOAD_ITYPE_FW (0x01) 1030 #define MPI_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1031 #define MPI_FW_DOWNLOAD_ITYPE_NVDATA (0x03) 1032 #define MPI_FW_DOWNLOAD_ITYPE_BOOTLOADER (0x04) 1033 #define MPI_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1034 #define MPI_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1035 #define MPI_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1036 #define MPI_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1037 #define MPI_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1038 1039 typedef struct _FWDownloadTCSGE 1040 { 1041 U8 Reserved; /* 00h */ 1042 U8 ContextSize; /* 01h */ 1043 U8 DetailsLength; /* 02h */ 1044 U8 Flags; /* 03h */ 1045 U32 Reserved_0100_Checksum; /* 04h */ /* obsolete Checksum */ 1046 U32 ImageOffset; /* 08h */ 1047 U32 ImageSize; /* 0Ch */ 1048 } FW_DOWNLOAD_TCSGE, MPI_POINTER PTR_FW_DOWNLOAD_TCSGE, 1049 FWDownloadTCSGE_t, MPI_POINTER pFWDownloadTCSGE_t; 1050 1051 /* Firmware Download reply */ 1052 typedef struct _MSG_FW_DOWNLOAD_REPLY 1053 { 1054 U8 ImageType; /* 00h */ 1055 U8 Reserved; /* 01h */ 1056 U8 MsgLength; /* 02h */ 1057 U8 Function; /* 03h */ 1058 U8 Reserved1[3]; /* 04h */ 1059 U8 MsgFlags; /* 07h */ 1060 U32 MsgContext; /* 08h */ 1061 U16 Reserved2; /* 0Ch */ 1062 U16 IOCStatus; /* 0Eh */ 1063 U32 IOCLogInfo; /* 10h */ 1064 } MSG_FW_DOWNLOAD_REPLY, MPI_POINTER PTR_MSG_FW_DOWNLOAD_REPLY, 1065 FWDownloadReply_t, MPI_POINTER pFWDownloadReply_t; 1066 1067 /****************************************************************************/ 1068 /* Firmware Upload message and associated structures */ 1069 /****************************************************************************/ 1070 1071 typedef struct _MSG_FW_UPLOAD 1072 { 1073 U8 ImageType; /* 00h */ 1074 U8 Reserved; /* 01h */ 1075 U8 ChainOffset; /* 02h */ 1076 U8 Function; /* 03h */ 1077 U8 Reserved1[3]; /* 04h */ 1078 U8 MsgFlags; /* 07h */ 1079 U32 MsgContext; /* 08h */ 1080 SGE_MPI_UNION SGL; /* 0Ch */ 1081 } MSG_FW_UPLOAD, MPI_POINTER PTR_MSG_FW_UPLOAD, 1082 FWUpload_t, MPI_POINTER pFWUpload_t; 1083 1084 #define MPI_FW_UPLOAD_ITYPE_FW_IOC_MEM (0x00) 1085 #define MPI_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1086 #define MPI_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1087 #define MPI_FW_UPLOAD_ITYPE_NVDATA (0x03) 1088 #define MPI_FW_UPLOAD_ITYPE_BOOTLOADER (0x04) 1089 #define MPI_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1090 #define MPI_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1091 #define MPI_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1092 #define MPI_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1093 #define MPI_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1094 #define MPI_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1095 #define MPI_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1096 1097 typedef struct _FWUploadTCSGE 1098 { 1099 U8 Reserved; /* 00h */ 1100 U8 ContextSize; /* 01h */ 1101 U8 DetailsLength; /* 02h */ 1102 U8 Flags; /* 03h */ 1103 U32 Reserved1; /* 04h */ 1104 U32 ImageOffset; /* 08h */ 1105 U32 ImageSize; /* 0Ch */ 1106 } FW_UPLOAD_TCSGE, MPI_POINTER PTR_FW_UPLOAD_TCSGE, 1107 FWUploadTCSGE_t, MPI_POINTER pFWUploadTCSGE_t; 1108 1109 /* Firmware Upload reply */ 1110 typedef struct _MSG_FW_UPLOAD_REPLY 1111 { 1112 U8 ImageType; /* 00h */ 1113 U8 Reserved; /* 01h */ 1114 U8 MsgLength; /* 02h */ 1115 U8 Function; /* 03h */ 1116 U8 Reserved1[3]; /* 04h */ 1117 U8 MsgFlags; /* 07h */ 1118 U32 MsgContext; /* 08h */ 1119 U16 Reserved2; /* 0Ch */ 1120 U16 IOCStatus; /* 0Eh */ 1121 U32 IOCLogInfo; /* 10h */ 1122 U32 ActualImageSize; /* 14h */ 1123 } MSG_FW_UPLOAD_REPLY, MPI_POINTER PTR_MSG_FW_UPLOAD_REPLY, 1124 FWUploadReply_t, MPI_POINTER pFWUploadReply_t; 1125 1126 typedef struct _MPI_FW_HEADER 1127 { 1128 U32 ArmBranchInstruction0; /* 00h */ 1129 U32 Signature0; /* 04h */ 1130 U32 Signature1; /* 08h */ 1131 U32 Signature2; /* 0Ch */ 1132 U32 ArmBranchInstruction1; /* 10h */ 1133 U32 ArmBranchInstruction2; /* 14h */ 1134 U32 Reserved; /* 18h */ 1135 U32 Checksum; /* 1Ch */ 1136 U16 VendorId; /* 20h */ 1137 U16 ProductId; /* 22h */ 1138 MPI_FW_VERSION FWVersion; /* 24h */ 1139 U32 SeqCodeVersion; /* 28h */ 1140 U32 ImageSize; /* 2Ch */ 1141 U32 NextImageHeaderOffset; /* 30h */ 1142 U32 LoadStartAddress; /* 34h */ 1143 U32 IopResetVectorValue; /* 38h */ 1144 U32 IopResetRegAddr; /* 3Ch */ 1145 U32 VersionNameWhat; /* 40h */ 1146 U8 VersionName[32]; /* 44h */ 1147 U32 VendorNameWhat; /* 64h */ 1148 U8 VendorName[32]; /* 68h */ 1149 } MPI_FW_HEADER, MPI_POINTER PTR_MPI_FW_HEADER, 1150 MpiFwHeader_t, MPI_POINTER pMpiFwHeader_t; 1151 1152 #define MPI_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1153 1154 /* defines for using the ProductId field */ 1155 #define MPI_FW_HEADER_PID_TYPE_MASK (0xF000) 1156 #define MPI_FW_HEADER_PID_TYPE_SCSI (0x0000) 1157 #define MPI_FW_HEADER_PID_TYPE_FC (0x1000) 1158 #define MPI_FW_HEADER_PID_TYPE_SAS (0x2000) 1159 1160 #define MPI_FW_HEADER_SIGNATURE_0 (0x5AEAA55A) 1161 #define MPI_FW_HEADER_SIGNATURE_1 (0xA55AEAA5) 1162 #define MPI_FW_HEADER_SIGNATURE_2 (0x5AA55AEA) 1163 1164 #define MPI_FW_HEADER_PID_PROD_MASK (0x0F00) 1165 #define MPI_FW_HEADER_PID_PROD_INITIATOR_SCSI (0x0100) 1166 #define MPI_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1167 #define MPI_FW_HEADER_PID_PROD_TARGET_SCSI (0x0300) 1168 #define MPI_FW_HEADER_PID_PROD_IM_SCSI (0x0400) 1169 #define MPI_FW_HEADER_PID_PROD_IS_SCSI (0x0500) 1170 #define MPI_FW_HEADER_PID_PROD_CTX_SCSI (0x0600) 1171 #define MPI_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1172 1173 #define MPI_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1174 /* SCSI */ 1175 #define MPI_FW_HEADER_PID_FAMILY_1030A0_SCSI (0x0001) 1176 #define MPI_FW_HEADER_PID_FAMILY_1030B0_SCSI (0x0002) 1177 #define MPI_FW_HEADER_PID_FAMILY_1030B1_SCSI (0x0003) 1178 #define MPI_FW_HEADER_PID_FAMILY_1030C0_SCSI (0x0004) 1179 #define MPI_FW_HEADER_PID_FAMILY_1020A0_SCSI (0x0005) 1180 #define MPI_FW_HEADER_PID_FAMILY_1020B0_SCSI (0x0006) 1181 #define MPI_FW_HEADER_PID_FAMILY_1020B1_SCSI (0x0007) 1182 #define MPI_FW_HEADER_PID_FAMILY_1020C0_SCSI (0x0008) 1183 #define MPI_FW_HEADER_PID_FAMILY_1035A0_SCSI (0x0009) 1184 #define MPI_FW_HEADER_PID_FAMILY_1035B0_SCSI (0x000A) 1185 #define MPI_FW_HEADER_PID_FAMILY_1030TA0_SCSI (0x000B) 1186 #define MPI_FW_HEADER_PID_FAMILY_1020TA0_SCSI (0x000C) 1187 /* Fibre Channel */ 1188 #define MPI_FW_HEADER_PID_FAMILY_909_FC (0x0000) 1189 #define MPI_FW_HEADER_PID_FAMILY_919_FC (0x0001) /* 919 and 929 */ 1190 #define MPI_FW_HEADER_PID_FAMILY_919X_FC (0x0002) /* 919X and 929X */ 1191 #define MPI_FW_HEADER_PID_FAMILY_919XL_FC (0x0003) /* 919XL and 929XL */ 1192 #define MPI_FW_HEADER_PID_FAMILY_939X_FC (0x0004) /* 939X and 949X */ 1193 #define MPI_FW_HEADER_PID_FAMILY_959_FC (0x0005) 1194 #define MPI_FW_HEADER_PID_FAMILY_949E_FC (0x0006) 1195 /* SAS */ 1196 #define MPI_FW_HEADER_PID_FAMILY_1064_SAS (0x0001) 1197 #define MPI_FW_HEADER_PID_FAMILY_1068_SAS (0x0002) 1198 #define MPI_FW_HEADER_PID_FAMILY_1078_SAS (0x0003) 1199 #define MPI_FW_HEADER_PID_FAMILY_106xE_SAS (0x0004) /* 1068E, 1066E, and 1064E */ 1200 1201 typedef struct _MPI_EXT_IMAGE_HEADER 1202 { 1203 U8 ImageType; /* 00h */ 1204 U8 Reserved; /* 01h */ 1205 U16 Reserved1; /* 02h */ 1206 U32 Checksum; /* 04h */ 1207 U32 ImageSize; /* 08h */ 1208 U32 NextImageHeaderOffset; /* 0Ch */ 1209 U32 LoadStartAddress; /* 10h */ 1210 U32 Reserved2; /* 14h */ 1211 } MPI_EXT_IMAGE_HEADER, MPI_POINTER PTR_MPI_EXT_IMAGE_HEADER, 1212 MpiExtImageHeader_t, MPI_POINTER pMpiExtImageHeader_t; 1213 1214 /* defines for the ImageType field */ 1215 #define MPI_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1216 #define MPI_EXT_IMAGE_TYPE_FW (0x01) 1217 #define MPI_EXT_IMAGE_TYPE_NVDATA (0x03) 1218 #define MPI_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1219 #define MPI_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1220 1221 #endif
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