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sys/dev/msk/if_msk.c
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1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause 50 * 51 * Copyright (c) 1997, 1998, 1999, 2000 52 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 3. All advertising materials mentioning features or use of this software 63 * must display the following acknowledgement: 64 * This product includes software developed by Bill Paul. 65 * 4. Neither the name of the author nor the names of any co-contributors 66 * may be used to endorse or promote products derived from this software 67 * without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 70 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 72 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 73 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 74 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 75 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 76 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 77 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 78 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 79 * THE POSSIBILITY OF SUCH DAMAGE. 80 */ 81 /*- 82 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 83 * 84 * Permission to use, copy, modify, and distribute this software for any 85 * purpose with or without fee is hereby granted, provided that the above 86 * copyright notice and this permission notice appear in all copies. 87 * 88 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 89 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 90 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 91 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 92 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 93 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 94 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 95 */ 96 97 /* 98 * Device driver for the Marvell Yukon II Ethernet controller. 99 * Due to lack of documentation, this driver is based on the code from 100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 101 */ 102 103 #include <sys/cdefs.h> 104 __FBSDID("$FreeBSD$"); 105 106 #include <sys/param.h> 107 #include <sys/systm.h> 108 #include <sys/bus.h> 109 #include <sys/endian.h> 110 #include <sys/mbuf.h> 111 #include <sys/malloc.h> 112 #include <sys/kernel.h> 113 #include <sys/module.h> 114 #include <sys/socket.h> 115 #include <sys/sockio.h> 116 #include <sys/queue.h> 117 #include <sys/sysctl.h> 118 119 #include <net/bpf.h> 120 #include <net/ethernet.h> 121 #include <net/if.h> 122 #include <net/if_var.h> 123 #include <net/if_arp.h> 124 #include <net/if_dl.h> 125 #include <net/if_media.h> 126 #include <net/if_types.h> 127 #include <net/if_vlan_var.h> 128 129 #include <netinet/in.h> 130 #include <netinet/in_systm.h> 131 #include <netinet/ip.h> 132 #include <netinet/tcp.h> 133 #include <netinet/udp.h> 134 135 #include <machine/bus.h> 136 #include <machine/in_cksum.h> 137 #include <machine/resource.h> 138 #include <sys/rman.h> 139 140 #include <dev/mii/mii.h> 141 #include <dev/mii/miivar.h> 142 143 #include <dev/pci/pcireg.h> 144 #include <dev/pci/pcivar.h> 145 146 #include <dev/msk/if_mskreg.h> 147 148 MODULE_DEPEND(msk, pci, 1, 1, 1); 149 MODULE_DEPEND(msk, ether, 1, 1, 1); 150 MODULE_DEPEND(msk, miibus, 1, 1, 1); 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 /* Tunables. */ 156 static int msi_disable = 0; 157 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 158 static int legacy_intr = 0; 159 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 160 static int jumbo_disable = 0; 161 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 162 163 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 164 165 /* 166 * Devices supported by this driver. 167 */ 168 static const struct msk_product { 169 uint16_t msk_vendorid; 170 uint16_t msk_deviceid; 171 const char *msk_name; 172 } msk_products[] = { 173 { VENDORID_SK, DEVICEID_SK_YUKON2, 174 "SK-9Sxx Gigabit Ethernet" }, 175 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 176 "SK-9Exx Gigabit Ethernet"}, 177 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 178 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 179 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 180 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 181 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 182 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 183 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 184 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 185 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 186 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 187 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 188 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 189 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 190 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 191 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 192 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 193 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 194 "Marvell Yukon 88E8035 Fast Ethernet" }, 195 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 196 "Marvell Yukon 88E8036 Fast Ethernet" }, 197 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 198 "Marvell Yukon 88E8038 Fast Ethernet" }, 199 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 200 "Marvell Yukon 88E8039 Fast Ethernet" }, 201 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 202 "Marvell Yukon 88E8040 Fast Ethernet" }, 203 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 204 "Marvell Yukon 88E8040T Fast Ethernet" }, 205 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 206 "Marvell Yukon 88E8042 Fast Ethernet" }, 207 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 208 "Marvell Yukon 88E8048 Fast Ethernet" }, 209 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 210 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 211 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 212 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 213 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 214 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 215 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 216 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 217 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 218 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 219 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 220 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 221 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 222 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 223 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 224 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 225 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 226 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 227 { VENDORID_MARVELL, DEVICEID_MRVL_436D, 228 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 229 { VENDORID_MARVELL, DEVICEID_MRVL_4370, 230 "Marvell Yukon 88E8075 Gigabit Ethernet" }, 231 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 232 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 233 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 234 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 235 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 236 "D-Link 550SX Gigabit Ethernet" }, 237 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 238 "D-Link 560SX Gigabit Ethernet" }, 239 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 240 "D-Link 560T Gigabit Ethernet" } 241 }; 242 243 static const char *model_name[] = { 244 "Yukon XL", 245 "Yukon EC Ultra", 246 "Yukon EX", 247 "Yukon EC", 248 "Yukon FE", 249 "Yukon FE+", 250 "Yukon Supreme", 251 "Yukon Ultra 2", 252 "Yukon Unknown", 253 "Yukon Optima", 254 }; 255 256 static int mskc_probe(device_t); 257 static int mskc_attach(device_t); 258 static int mskc_detach(device_t); 259 static int mskc_shutdown(device_t); 260 static int mskc_setup_rambuffer(struct msk_softc *); 261 static int mskc_suspend(device_t); 262 static int mskc_resume(device_t); 263 static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t); 264 static void mskc_reset(struct msk_softc *); 265 266 static int msk_probe(device_t); 267 static int msk_attach(device_t); 268 static int msk_detach(device_t); 269 270 static void msk_tick(void *); 271 static void msk_intr(void *); 272 static void msk_intr_phy(struct msk_if_softc *); 273 static void msk_intr_gmac(struct msk_if_softc *); 274 static __inline void msk_rxput(struct msk_if_softc *); 275 static int msk_handle_events(struct msk_softc *); 276 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 277 static void msk_intr_hwerr(struct msk_softc *); 278 #ifndef __NO_STRICT_ALIGNMENT 279 static __inline void msk_fixup_rx(struct mbuf *); 280 #endif 281 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 282 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 283 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 284 static void msk_txeof(struct msk_if_softc *, int); 285 static int msk_encap(struct msk_if_softc *, struct mbuf **); 286 static void msk_start(struct ifnet *); 287 static void msk_start_locked(struct ifnet *); 288 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 289 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 290 static void msk_set_rambuffer(struct msk_if_softc *); 291 static void msk_set_tx_stfwd(struct msk_if_softc *); 292 static void msk_init(void *); 293 static void msk_init_locked(struct msk_if_softc *); 294 static void msk_stop(struct msk_if_softc *); 295 static void msk_watchdog(struct msk_if_softc *); 296 static int msk_mediachange(struct ifnet *); 297 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 298 static void msk_phy_power(struct msk_softc *, int); 299 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 300 static int msk_status_dma_alloc(struct msk_softc *); 301 static void msk_status_dma_free(struct msk_softc *); 302 static int msk_txrx_dma_alloc(struct msk_if_softc *); 303 static int msk_rx_dma_jalloc(struct msk_if_softc *); 304 static void msk_txrx_dma_free(struct msk_if_softc *); 305 static void msk_rx_dma_jfree(struct msk_if_softc *); 306 static int msk_rx_fill(struct msk_if_softc *, int); 307 static int msk_init_rx_ring(struct msk_if_softc *); 308 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 309 static void msk_init_tx_ring(struct msk_if_softc *); 310 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 311 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 312 static int msk_newbuf(struct msk_if_softc *, int); 313 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 314 315 static int msk_phy_readreg(struct msk_if_softc *, int, int); 316 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 317 static int msk_miibus_readreg(device_t, int, int); 318 static int msk_miibus_writereg(device_t, int, int, int); 319 static void msk_miibus_statchg(device_t); 320 321 static void msk_rxfilter(struct msk_if_softc *); 322 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 323 324 static void msk_stats_clear(struct msk_if_softc *); 325 static void msk_stats_update(struct msk_if_softc *); 326 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 327 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 328 static void msk_sysctl_node(struct msk_if_softc *); 329 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 330 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 331 332 static device_method_t mskc_methods[] = { 333 /* Device interface */ 334 DEVMETHOD(device_probe, mskc_probe), 335 DEVMETHOD(device_attach, mskc_attach), 336 DEVMETHOD(device_detach, mskc_detach), 337 DEVMETHOD(device_suspend, mskc_suspend), 338 DEVMETHOD(device_resume, mskc_resume), 339 DEVMETHOD(device_shutdown, mskc_shutdown), 340 341 DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag), 342 343 DEVMETHOD_END 344 }; 345 346 static driver_t mskc_driver = { 347 "mskc", 348 mskc_methods, 349 sizeof(struct msk_softc) 350 }; 351 352 static device_method_t msk_methods[] = { 353 /* Device interface */ 354 DEVMETHOD(device_probe, msk_probe), 355 DEVMETHOD(device_attach, msk_attach), 356 DEVMETHOD(device_detach, msk_detach), 357 DEVMETHOD(device_shutdown, bus_generic_shutdown), 358 359 /* MII interface */ 360 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 361 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 362 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 363 364 DEVMETHOD_END 365 }; 366 367 static driver_t msk_driver = { 368 "msk", 369 msk_methods, 370 sizeof(struct msk_if_softc) 371 }; 372 373 DRIVER_MODULE(mskc, pci, mskc_driver, NULL, NULL); 374 DRIVER_MODULE(msk, mskc, msk_driver, NULL, NULL); 375 DRIVER_MODULE(miibus, msk, miibus_driver, NULL, NULL); 376 377 static struct resource_spec msk_res_spec_io[] = { 378 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 379 { -1, 0, 0 } 380 }; 381 382 static struct resource_spec msk_res_spec_mem[] = { 383 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 384 { -1, 0, 0 } 385 }; 386 387 static struct resource_spec msk_irq_spec_legacy[] = { 388 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 389 { -1, 0, 0 } 390 }; 391 392 static struct resource_spec msk_irq_spec_msi[] = { 393 { SYS_RES_IRQ, 1, RF_ACTIVE }, 394 { -1, 0, 0 } 395 }; 396 397 static int 398 msk_miibus_readreg(device_t dev, int phy, int reg) 399 { 400 struct msk_if_softc *sc_if; 401 402 sc_if = device_get_softc(dev); 403 404 return (msk_phy_readreg(sc_if, phy, reg)); 405 } 406 407 static int 408 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 409 { 410 struct msk_softc *sc; 411 int i, val; 412 413 sc = sc_if->msk_softc; 414 415 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 416 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 417 418 for (i = 0; i < MSK_TIMEOUT; i++) { 419 DELAY(1); 420 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 421 if ((val & GM_SMI_CT_RD_VAL) != 0) { 422 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 423 break; 424 } 425 } 426 427 if (i == MSK_TIMEOUT) { 428 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 429 val = 0; 430 } 431 432 return (val); 433 } 434 435 static int 436 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 437 { 438 struct msk_if_softc *sc_if; 439 440 sc_if = device_get_softc(dev); 441 442 return (msk_phy_writereg(sc_if, phy, reg, val)); 443 } 444 445 static int 446 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 447 { 448 struct msk_softc *sc; 449 int i; 450 451 sc = sc_if->msk_softc; 452 453 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 454 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 455 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 456 for (i = 0; i < MSK_TIMEOUT; i++) { 457 DELAY(1); 458 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 459 GM_SMI_CT_BUSY) == 0) 460 break; 461 } 462 if (i == MSK_TIMEOUT) 463 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 464 465 return (0); 466 } 467 468 static void 469 msk_miibus_statchg(device_t dev) 470 { 471 struct msk_softc *sc; 472 struct msk_if_softc *sc_if; 473 struct mii_data *mii; 474 struct ifnet *ifp; 475 uint32_t gmac; 476 477 sc_if = device_get_softc(dev); 478 sc = sc_if->msk_softc; 479 480 MSK_IF_LOCK_ASSERT(sc_if); 481 482 mii = device_get_softc(sc_if->msk_miibus); 483 ifp = sc_if->msk_ifp; 484 if (mii == NULL || ifp == NULL || 485 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 486 return; 487 488 sc_if->msk_flags &= ~MSK_FLAG_LINK; 489 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 490 (IFM_AVALID | IFM_ACTIVE)) { 491 switch (IFM_SUBTYPE(mii->mii_media_active)) { 492 case IFM_10_T: 493 case IFM_100_TX: 494 sc_if->msk_flags |= MSK_FLAG_LINK; 495 break; 496 case IFM_1000_T: 497 case IFM_1000_SX: 498 case IFM_1000_LX: 499 case IFM_1000_CX: 500 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 501 sc_if->msk_flags |= MSK_FLAG_LINK; 502 break; 503 default: 504 break; 505 } 506 } 507 508 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 509 /* Enable Tx FIFO Underrun. */ 510 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 511 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 512 /* 513 * Because mii(4) notify msk(4) that it detected link status 514 * change, there is no need to enable automatic 515 * speed/flow-control/duplex updates. 516 */ 517 gmac = GM_GPCR_AU_ALL_DIS; 518 switch (IFM_SUBTYPE(mii->mii_media_active)) { 519 case IFM_1000_SX: 520 case IFM_1000_T: 521 gmac |= GM_GPCR_SPEED_1000; 522 break; 523 case IFM_100_TX: 524 gmac |= GM_GPCR_SPEED_100; 525 break; 526 case IFM_10_T: 527 break; 528 } 529 530 if ((IFM_OPTIONS(mii->mii_media_active) & 531 IFM_ETH_RXPAUSE) == 0) 532 gmac |= GM_GPCR_FC_RX_DIS; 533 if ((IFM_OPTIONS(mii->mii_media_active) & 534 IFM_ETH_TXPAUSE) == 0) 535 gmac |= GM_GPCR_FC_TX_DIS; 536 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 537 gmac |= GM_GPCR_DUP_FULL; 538 else 539 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 540 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 541 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 542 /* Read again to ensure writing. */ 543 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 544 gmac = GMC_PAUSE_OFF; 545 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 546 if ((IFM_OPTIONS(mii->mii_media_active) & 547 IFM_ETH_RXPAUSE) != 0) 548 gmac = GMC_PAUSE_ON; 549 } 550 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 551 552 /* Enable PHY interrupt for FIFO underrun/overflow. */ 553 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 554 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 555 } else { 556 /* 557 * Link state changed to down. 558 * Disable PHY interrupts. 559 */ 560 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 561 /* Disable Rx/Tx MAC. */ 562 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 563 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) { 564 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 565 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 566 /* Read again to ensure writing. */ 567 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 568 } 569 } 570 } 571 572 static u_int 573 msk_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 574 { 575 uint32_t *mchash = arg; 576 uint32_t crc; 577 578 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 579 /* Just want the 6 least significant bits. */ 580 crc &= 0x3f; 581 /* Set the corresponding bit in the hash table. */ 582 mchash[crc >> 5] |= 1 << (crc & 0x1f); 583 584 return (1); 585 } 586 587 static void 588 msk_rxfilter(struct msk_if_softc *sc_if) 589 { 590 struct msk_softc *sc; 591 struct ifnet *ifp; 592 uint32_t mchash[2]; 593 uint16_t mode; 594 595 sc = sc_if->msk_softc; 596 597 MSK_IF_LOCK_ASSERT(sc_if); 598 599 ifp = sc_if->msk_ifp; 600 601 bzero(mchash, sizeof(mchash)); 602 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 603 if ((ifp->if_flags & IFF_PROMISC) != 0) 604 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 605 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 606 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 607 mchash[0] = 0xffff; 608 mchash[1] = 0xffff; 609 } else { 610 mode |= GM_RXCR_UCF_ENA; 611 if_foreach_llmaddr(ifp, msk_hash_maddr, mchash); 612 if (mchash[0] != 0 || mchash[1] != 0) 613 mode |= GM_RXCR_MCF_ENA; 614 } 615 616 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 617 mchash[0] & 0xffff); 618 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 619 (mchash[0] >> 16) & 0xffff); 620 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 621 mchash[1] & 0xffff); 622 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 623 (mchash[1] >> 16) & 0xffff); 624 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 625 } 626 627 static void 628 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 629 { 630 struct msk_softc *sc; 631 632 sc = sc_if->msk_softc; 633 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 634 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 635 RX_VLAN_STRIP_ON); 636 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 637 TX_VLAN_TAG_ON); 638 } else { 639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 640 RX_VLAN_STRIP_OFF); 641 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 642 TX_VLAN_TAG_OFF); 643 } 644 } 645 646 static int 647 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 648 { 649 uint16_t idx; 650 int i; 651 652 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 653 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 654 /* Wait until controller executes OP_TCPSTART command. */ 655 for (i = 100; i > 0; i--) { 656 DELAY(100); 657 idx = CSR_READ_2(sc_if->msk_softc, 658 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 659 PREF_UNIT_GET_IDX_REG)); 660 if (idx != 0) 661 break; 662 } 663 if (i == 0) { 664 device_printf(sc_if->msk_if_dev, 665 "prefetch unit stuck?\n"); 666 return (ETIMEDOUT); 667 } 668 /* 669 * Fill consumed LE with free buffer. This can be done 670 * in Rx handler but we don't want to add special code 671 * in fast handler. 672 */ 673 if (jumbo > 0) { 674 if (msk_jumbo_newbuf(sc_if, 0) != 0) 675 return (ENOBUFS); 676 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 677 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 679 } else { 680 if (msk_newbuf(sc_if, 0) != 0) 681 return (ENOBUFS); 682 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 683 sc_if->msk_cdata.msk_rx_ring_map, 684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 685 } 686 sc_if->msk_cdata.msk_rx_prod = 0; 687 CSR_WRITE_2(sc_if->msk_softc, 688 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 689 sc_if->msk_cdata.msk_rx_prod); 690 } 691 return (0); 692 } 693 694 static int 695 msk_init_rx_ring(struct msk_if_softc *sc_if) 696 { 697 struct msk_ring_data *rd; 698 struct msk_rxdesc *rxd; 699 int i, nbuf, prod; 700 701 MSK_IF_LOCK_ASSERT(sc_if); 702 703 sc_if->msk_cdata.msk_rx_cons = 0; 704 sc_if->msk_cdata.msk_rx_prod = 0; 705 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 706 707 rd = &sc_if->msk_rdata; 708 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 709 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) { 710 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 711 rxd->rx_m = NULL; 712 rxd->rx_le = &rd->msk_rx_ring[prod]; 713 MSK_INC(prod, MSK_RX_RING_CNT); 714 } 715 nbuf = MSK_RX_BUF_CNT; 716 prod = 0; 717 /* Have controller know how to compute Rx checksum. */ 718 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 719 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 720 #ifdef MSK_64BIT_DMA 721 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 722 rxd->rx_m = NULL; 723 rxd->rx_le = &rd->msk_rx_ring[prod]; 724 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 725 ETHER_HDR_LEN); 726 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 727 MSK_INC(prod, MSK_RX_RING_CNT); 728 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 729 #endif 730 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 731 rxd->rx_m = NULL; 732 rxd->rx_le = &rd->msk_rx_ring[prod]; 733 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 734 ETHER_HDR_LEN); 735 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 736 MSK_INC(prod, MSK_RX_RING_CNT); 737 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 738 nbuf--; 739 } 740 for (i = 0; i < nbuf; i++) { 741 if (msk_newbuf(sc_if, prod) != 0) 742 return (ENOBUFS); 743 MSK_RX_INC(prod, MSK_RX_RING_CNT); 744 } 745 746 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 747 sc_if->msk_cdata.msk_rx_ring_map, 748 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 749 750 /* Update prefetch unit. */ 751 sc_if->msk_cdata.msk_rx_prod = prod; 752 CSR_WRITE_2(sc_if->msk_softc, 753 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 754 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) % 755 MSK_RX_RING_CNT); 756 if (msk_rx_fill(sc_if, 0) != 0) 757 return (ENOBUFS); 758 return (0); 759 } 760 761 static int 762 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 763 { 764 struct msk_ring_data *rd; 765 struct msk_rxdesc *rxd; 766 int i, nbuf, prod; 767 768 MSK_IF_LOCK_ASSERT(sc_if); 769 770 sc_if->msk_cdata.msk_rx_cons = 0; 771 sc_if->msk_cdata.msk_rx_prod = 0; 772 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 773 774 rd = &sc_if->msk_rdata; 775 bzero(rd->msk_jumbo_rx_ring, 776 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 777 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 778 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 779 rxd->rx_m = NULL; 780 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 781 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 782 } 783 nbuf = MSK_RX_BUF_CNT; 784 prod = 0; 785 /* Have controller know how to compute Rx checksum. */ 786 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 787 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 788 #ifdef MSK_64BIT_DMA 789 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 790 rxd->rx_m = NULL; 791 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 792 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 793 ETHER_HDR_LEN); 794 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 795 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 796 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 797 #endif 798 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 799 rxd->rx_m = NULL; 800 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 801 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 802 ETHER_HDR_LEN); 803 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 804 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 805 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 806 nbuf--; 807 } 808 for (i = 0; i < nbuf; i++) { 809 if (msk_jumbo_newbuf(sc_if, prod) != 0) 810 return (ENOBUFS); 811 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT); 812 } 813 814 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 815 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 816 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 817 818 /* Update prefetch unit. */ 819 sc_if->msk_cdata.msk_rx_prod = prod; 820 CSR_WRITE_2(sc_if->msk_softc, 821 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 822 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) % 823 MSK_JUMBO_RX_RING_CNT); 824 if (msk_rx_fill(sc_if, 1) != 0) 825 return (ENOBUFS); 826 return (0); 827 } 828 829 static void 830 msk_init_tx_ring(struct msk_if_softc *sc_if) 831 { 832 struct msk_ring_data *rd; 833 struct msk_txdesc *txd; 834 int i; 835 836 sc_if->msk_cdata.msk_tso_mtu = 0; 837 sc_if->msk_cdata.msk_last_csum = 0; 838 sc_if->msk_cdata.msk_tx_prod = 0; 839 sc_if->msk_cdata.msk_tx_cons = 0; 840 sc_if->msk_cdata.msk_tx_cnt = 0; 841 sc_if->msk_cdata.msk_tx_high_addr = 0; 842 843 rd = &sc_if->msk_rdata; 844 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 845 for (i = 0; i < MSK_TX_RING_CNT; i++) { 846 txd = &sc_if->msk_cdata.msk_txdesc[i]; 847 txd->tx_m = NULL; 848 txd->tx_le = &rd->msk_tx_ring[i]; 849 } 850 851 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 852 sc_if->msk_cdata.msk_tx_ring_map, 853 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 854 } 855 856 static __inline void 857 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 858 { 859 struct msk_rx_desc *rx_le; 860 struct msk_rxdesc *rxd; 861 struct mbuf *m; 862 863 #ifdef MSK_64BIT_DMA 864 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 865 rx_le = rxd->rx_le; 866 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 867 MSK_INC(idx, MSK_RX_RING_CNT); 868 #endif 869 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 870 m = rxd->rx_m; 871 rx_le = rxd->rx_le; 872 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 873 } 874 875 static __inline void 876 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 877 { 878 struct msk_rx_desc *rx_le; 879 struct msk_rxdesc *rxd; 880 struct mbuf *m; 881 882 #ifdef MSK_64BIT_DMA 883 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 884 rx_le = rxd->rx_le; 885 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 886 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 887 #endif 888 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 889 m = rxd->rx_m; 890 rx_le = rxd->rx_le; 891 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 892 } 893 894 static int 895 msk_newbuf(struct msk_if_softc *sc_if, int idx) 896 { 897 struct msk_rx_desc *rx_le; 898 struct msk_rxdesc *rxd; 899 struct mbuf *m; 900 bus_dma_segment_t segs[1]; 901 bus_dmamap_t map; 902 int nsegs; 903 904 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 905 if (m == NULL) 906 return (ENOBUFS); 907 908 m->m_len = m->m_pkthdr.len = MCLBYTES; 909 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 910 m_adj(m, ETHER_ALIGN); 911 #ifndef __NO_STRICT_ALIGNMENT 912 else 913 m_adj(m, MSK_RX_BUF_ALIGN); 914 #endif 915 916 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 917 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 918 BUS_DMA_NOWAIT) != 0) { 919 m_freem(m); 920 return (ENOBUFS); 921 } 922 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 923 924 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 925 #ifdef MSK_64BIT_DMA 926 rx_le = rxd->rx_le; 927 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 928 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 929 MSK_INC(idx, MSK_RX_RING_CNT); 930 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 931 #endif 932 if (rxd->rx_m != NULL) { 933 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 934 BUS_DMASYNC_POSTREAD); 935 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 936 rxd->rx_m = NULL; 937 } 938 map = rxd->rx_dmamap; 939 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 940 sc_if->msk_cdata.msk_rx_sparemap = map; 941 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 942 BUS_DMASYNC_PREREAD); 943 rxd->rx_m = m; 944 rx_le = rxd->rx_le; 945 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 946 rx_le->msk_control = 947 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 948 949 return (0); 950 } 951 952 static int 953 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 954 { 955 struct msk_rx_desc *rx_le; 956 struct msk_rxdesc *rxd; 957 struct mbuf *m; 958 bus_dma_segment_t segs[1]; 959 bus_dmamap_t map; 960 int nsegs; 961 962 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 963 if (m == NULL) 964 return (ENOBUFS); 965 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 966 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 967 m_adj(m, ETHER_ALIGN); 968 #ifndef __NO_STRICT_ALIGNMENT 969 else 970 m_adj(m, MSK_RX_BUF_ALIGN); 971 #endif 972 973 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 974 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 975 BUS_DMA_NOWAIT) != 0) { 976 m_freem(m); 977 return (ENOBUFS); 978 } 979 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 980 981 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 982 #ifdef MSK_64BIT_DMA 983 rx_le = rxd->rx_le; 984 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 985 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 986 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 987 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 988 #endif 989 if (rxd->rx_m != NULL) { 990 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 991 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 992 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 993 rxd->rx_dmamap); 994 rxd->rx_m = NULL; 995 } 996 map = rxd->rx_dmamap; 997 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 998 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 999 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 1000 BUS_DMASYNC_PREREAD); 1001 rxd->rx_m = m; 1002 rx_le = rxd->rx_le; 1003 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 1004 rx_le->msk_control = 1005 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 1006 1007 return (0); 1008 } 1009 1010 /* 1011 * Set media options. 1012 */ 1013 static int 1014 msk_mediachange(struct ifnet *ifp) 1015 { 1016 struct msk_if_softc *sc_if; 1017 struct mii_data *mii; 1018 int error; 1019 1020 sc_if = ifp->if_softc; 1021 1022 MSK_IF_LOCK(sc_if); 1023 mii = device_get_softc(sc_if->msk_miibus); 1024 error = mii_mediachg(mii); 1025 MSK_IF_UNLOCK(sc_if); 1026 1027 return (error); 1028 } 1029 1030 /* 1031 * Report current media status. 1032 */ 1033 static void 1034 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1035 { 1036 struct msk_if_softc *sc_if; 1037 struct mii_data *mii; 1038 1039 sc_if = ifp->if_softc; 1040 MSK_IF_LOCK(sc_if); 1041 if ((ifp->if_flags & IFF_UP) == 0) { 1042 MSK_IF_UNLOCK(sc_if); 1043 return; 1044 } 1045 mii = device_get_softc(sc_if->msk_miibus); 1046 1047 mii_pollstat(mii); 1048 ifmr->ifm_active = mii->mii_media_active; 1049 ifmr->ifm_status = mii->mii_media_status; 1050 MSK_IF_UNLOCK(sc_if); 1051 } 1052 1053 static int 1054 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1055 { 1056 struct msk_if_softc *sc_if; 1057 struct ifreq *ifr; 1058 struct mii_data *mii; 1059 int error, mask, reinit; 1060 1061 sc_if = ifp->if_softc; 1062 ifr = (struct ifreq *)data; 1063 error = 0; 1064 1065 switch(command) { 1066 case SIOCSIFMTU: 1067 MSK_IF_LOCK(sc_if); 1068 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1069 error = EINVAL; 1070 else if (ifp->if_mtu != ifr->ifr_mtu) { 1071 if (ifr->ifr_mtu > ETHERMTU) { 1072 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1073 error = EINVAL; 1074 MSK_IF_UNLOCK(sc_if); 1075 break; 1076 } 1077 if ((sc_if->msk_flags & 1078 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1079 ifp->if_hwassist &= 1080 ~(MSK_CSUM_FEATURES | CSUM_TSO); 1081 ifp->if_capenable &= 1082 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1083 VLAN_CAPABILITIES(ifp); 1084 } 1085 } 1086 ifp->if_mtu = ifr->ifr_mtu; 1087 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1088 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1089 msk_init_locked(sc_if); 1090 } 1091 } 1092 MSK_IF_UNLOCK(sc_if); 1093 break; 1094 case SIOCSIFFLAGS: 1095 MSK_IF_LOCK(sc_if); 1096 if ((ifp->if_flags & IFF_UP) != 0) { 1097 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1098 ((ifp->if_flags ^ sc_if->msk_if_flags) & 1099 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1100 msk_rxfilter(sc_if); 1101 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1102 msk_init_locked(sc_if); 1103 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1104 msk_stop(sc_if); 1105 sc_if->msk_if_flags = ifp->if_flags; 1106 MSK_IF_UNLOCK(sc_if); 1107 break; 1108 case SIOCADDMULTI: 1109 case SIOCDELMULTI: 1110 MSK_IF_LOCK(sc_if); 1111 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1112 msk_rxfilter(sc_if); 1113 MSK_IF_UNLOCK(sc_if); 1114 break; 1115 case SIOCGIFMEDIA: 1116 case SIOCSIFMEDIA: 1117 mii = device_get_softc(sc_if->msk_miibus); 1118 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1119 break; 1120 case SIOCSIFCAP: 1121 reinit = 0; 1122 MSK_IF_LOCK(sc_if); 1123 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1124 if ((mask & IFCAP_TXCSUM) != 0 && 1125 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1126 ifp->if_capenable ^= IFCAP_TXCSUM; 1127 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1128 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1129 else 1130 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1131 } 1132 if ((mask & IFCAP_RXCSUM) != 0 && 1133 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1134 ifp->if_capenable ^= IFCAP_RXCSUM; 1135 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1136 reinit = 1; 1137 } 1138 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1139 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1140 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1141 if ((mask & IFCAP_TSO4) != 0 && 1142 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1143 ifp->if_capenable ^= IFCAP_TSO4; 1144 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1145 ifp->if_hwassist |= CSUM_TSO; 1146 else 1147 ifp->if_hwassist &= ~CSUM_TSO; 1148 } 1149 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1150 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1151 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1152 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1153 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1154 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1155 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1156 ifp->if_capenable &= 1157 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1158 msk_setvlan(sc_if, ifp); 1159 } 1160 if (ifp->if_mtu > ETHERMTU && 1161 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1162 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1163 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1164 } 1165 VLAN_CAPABILITIES(ifp); 1166 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1167 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1168 msk_init_locked(sc_if); 1169 } 1170 MSK_IF_UNLOCK(sc_if); 1171 break; 1172 default: 1173 error = ether_ioctl(ifp, command, data); 1174 break; 1175 } 1176 1177 return (error); 1178 } 1179 1180 static int 1181 mskc_probe(device_t dev) 1182 { 1183 const struct msk_product *mp; 1184 uint16_t vendor, devid; 1185 int i; 1186 1187 vendor = pci_get_vendor(dev); 1188 devid = pci_get_device(dev); 1189 mp = msk_products; 1190 for (i = 0; i < nitems(msk_products); i++, mp++) { 1191 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1192 device_set_desc(dev, mp->msk_name); 1193 return (BUS_PROBE_DEFAULT); 1194 } 1195 } 1196 1197 return (ENXIO); 1198 } 1199 1200 static int 1201 mskc_setup_rambuffer(struct msk_softc *sc) 1202 { 1203 int next; 1204 int i; 1205 1206 /* Get adapter SRAM size. */ 1207 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1208 if (bootverbose) 1209 device_printf(sc->msk_dev, 1210 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1211 if (sc->msk_ramsize == 0) 1212 return (0); 1213 1214 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1215 /* 1216 * Give receiver 2/3 of memory and round down to the multiple 1217 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1218 * of 1024. 1219 */ 1220 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1221 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1222 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1223 sc->msk_rxqstart[i] = next; 1224 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1225 next = sc->msk_rxqend[i] + 1; 1226 sc->msk_txqstart[i] = next; 1227 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1228 next = sc->msk_txqend[i] + 1; 1229 if (bootverbose) { 1230 device_printf(sc->msk_dev, 1231 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1232 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1233 sc->msk_rxqend[i]); 1234 device_printf(sc->msk_dev, 1235 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1236 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1237 sc->msk_txqend[i]); 1238 } 1239 } 1240 1241 return (0); 1242 } 1243 1244 static void 1245 msk_phy_power(struct msk_softc *sc, int mode) 1246 { 1247 uint32_t our, val; 1248 int i; 1249 1250 switch (mode) { 1251 case MSK_PHY_POWERUP: 1252 /* Switch power to VCC (WA for VAUX problem). */ 1253 CSR_WRITE_1(sc, B0_POWER_CTRL, 1254 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1255 /* Disable Core Clock Division, set Clock Select to 0. */ 1256 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1257 1258 val = 0; 1259 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1260 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1261 /* Enable bits are inverted. */ 1262 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1263 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1264 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1265 } 1266 /* 1267 * Enable PCI & Core Clock, enable clock gating for both Links. 1268 */ 1269 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1270 1271 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1272 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1273 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1274 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1275 /* Deassert Low Power for 1st PHY. */ 1276 our |= PCI_Y2_PHY1_COMA; 1277 if (sc->msk_num_port > 1) 1278 our |= PCI_Y2_PHY2_COMA; 1279 } 1280 } 1281 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || 1282 sc->msk_hw_id == CHIP_ID_YUKON_EX || 1283 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { 1284 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1285 val &= (PCI_FORCE_ASPM_REQUEST | 1286 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | 1287 PCI_ASPM_CLKRUN_REQUEST); 1288 /* Set all bits to 0 except bits 15..12. */ 1289 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); 1290 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1291 val &= PCI_CTL_TIM_VMAIN_AV_MSK; 1292 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); 1293 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1294 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1295 /* 1296 * Disable status race, workaround for 1297 * Yukon EC Ultra & Yukon EX. 1298 */ 1299 val = CSR_READ_4(sc, B2_GP_IO); 1300 val |= GLB_GPIO_STAT_RACE_DIS; 1301 CSR_WRITE_4(sc, B2_GP_IO, val); 1302 CSR_READ_4(sc, B2_GP_IO); 1303 } 1304 /* Release PHY from PowerDown/COMA mode. */ 1305 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); 1306 1307 for (i = 0; i < sc->msk_num_port; i++) { 1308 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1309 GMLC_RST_SET); 1310 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1311 GMLC_RST_CLR); 1312 } 1313 break; 1314 case MSK_PHY_POWERDOWN: 1315 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1316 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1317 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1318 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1319 val &= ~PCI_Y2_PHY1_COMA; 1320 if (sc->msk_num_port > 1) 1321 val &= ~PCI_Y2_PHY2_COMA; 1322 } 1323 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1324 1325 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1326 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1327 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1328 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1329 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1330 /* Enable bits are inverted. */ 1331 val = 0; 1332 } 1333 /* 1334 * Disable PCI & Core Clock, disable clock gating for 1335 * both Links. 1336 */ 1337 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1338 CSR_WRITE_1(sc, B0_POWER_CTRL, 1339 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1340 break; 1341 default: 1342 break; 1343 } 1344 } 1345 1346 static void 1347 mskc_reset(struct msk_softc *sc) 1348 { 1349 bus_addr_t addr; 1350 uint16_t status; 1351 uint32_t val; 1352 int i, initram; 1353 1354 /* Disable ASF. */ 1355 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && 1356 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { 1357 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1358 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1359 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1360 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1361 /* Clear AHB bridge & microcontroller reset. */ 1362 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1363 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1364 /* Clear ASF microcontroller state. */ 1365 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1366 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; 1367 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1368 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1369 } else 1370 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1371 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1372 /* 1373 * Since we disabled ASF, S/W reset is required for 1374 * Power Management. 1375 */ 1376 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1377 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1378 } 1379 1380 /* Clear all error bits in the PCI status register. */ 1381 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1382 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1383 1384 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1385 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1386 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1387 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1388 1389 switch (sc->msk_bustype) { 1390 case MSK_PEX_BUS: 1391 /* Clear all PEX errors. */ 1392 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1393 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1394 if ((val & PEX_RX_OV) != 0) { 1395 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1396 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1397 } 1398 break; 1399 case MSK_PCI_BUS: 1400 case MSK_PCIX_BUS: 1401 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1402 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1403 if (val == 0) 1404 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1405 if (sc->msk_bustype == MSK_PCIX_BUS) { 1406 /* Set Cache Line Size opt. */ 1407 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1408 val |= PCI_CLS_OPT; 1409 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1410 } 1411 break; 1412 } 1413 /* Set PHY power state. */ 1414 msk_phy_power(sc, MSK_PHY_POWERUP); 1415 1416 /* Reset GPHY/GMAC Control */ 1417 for (i = 0; i < sc->msk_num_port; i++) { 1418 /* GPHY Control reset. */ 1419 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1420 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1421 /* GMAC Control reset. */ 1422 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1423 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1424 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1425 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1426 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 1427 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1428 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1429 GMC_BYP_RETR_ON); 1430 } 1431 1432 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR && 1433 sc->msk_hw_rev > CHIP_REV_YU_SU_B0) 1434 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS); 1435 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1436 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1437 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1438 } 1439 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1440 1441 /* LED On. */ 1442 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1443 1444 /* Clear TWSI IRQ. */ 1445 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1446 1447 /* Turn off hardware timer. */ 1448 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1449 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1450 1451 /* Turn off descriptor polling. */ 1452 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1453 1454 /* Turn off time stamps. */ 1455 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1456 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1457 1458 initram = 0; 1459 if (sc->msk_hw_id == CHIP_ID_YUKON_XL || 1460 sc->msk_hw_id == CHIP_ID_YUKON_EC || 1461 sc->msk_hw_id == CHIP_ID_YUKON_FE) 1462 initram++; 1463 1464 /* Configure timeout values. */ 1465 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) { 1466 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1467 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1468 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1469 MSK_RI_TO_53); 1470 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1471 MSK_RI_TO_53); 1472 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1473 MSK_RI_TO_53); 1474 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1475 MSK_RI_TO_53); 1476 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1477 MSK_RI_TO_53); 1478 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1479 MSK_RI_TO_53); 1480 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1481 MSK_RI_TO_53); 1482 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1483 MSK_RI_TO_53); 1484 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1485 MSK_RI_TO_53); 1486 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1487 MSK_RI_TO_53); 1488 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1489 MSK_RI_TO_53); 1490 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1491 MSK_RI_TO_53); 1492 } 1493 1494 /* Disable all interrupts. */ 1495 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1496 CSR_READ_4(sc, B0_HWE_IMSK); 1497 CSR_WRITE_4(sc, B0_IMSK, 0); 1498 CSR_READ_4(sc, B0_IMSK); 1499 1500 /* 1501 * On dual port PCI-X card, there is an problem where status 1502 * can be received out of order due to split transactions. 1503 */ 1504 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1505 uint16_t pcix_cmd; 1506 1507 pcix_cmd = pci_read_config(sc->msk_dev, 1508 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1509 /* Clear Max Outstanding Split Transactions. */ 1510 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1511 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1512 pci_write_config(sc->msk_dev, 1513 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1514 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1515 } 1516 if (sc->msk_expcap != 0) { 1517 /* Change Max. Read Request Size to 2048 bytes. */ 1518 if (pci_get_max_read_req(sc->msk_dev) == 512) 1519 pci_set_max_read_req(sc->msk_dev, 2048); 1520 } 1521 1522 /* Clear status list. */ 1523 bzero(sc->msk_stat_ring, 1524 sizeof(struct msk_stat_desc) * sc->msk_stat_count); 1525 sc->msk_stat_cons = 0; 1526 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1527 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1528 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1529 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1530 /* Set the status list base address. */ 1531 addr = sc->msk_stat_ring_paddr; 1532 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1533 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1534 /* Set the status list last index. */ 1535 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1); 1536 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1537 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1538 /* WA for dev. #4.3 */ 1539 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1540 /* WA for dev. #4.18 */ 1541 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1542 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1543 } else { 1544 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1545 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1546 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1547 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1548 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1549 else 1550 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1551 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1552 } 1553 /* 1554 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1555 */ 1556 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1557 1558 /* Enable status unit. */ 1559 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1560 1561 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1562 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1563 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1564 } 1565 1566 static int 1567 msk_probe(device_t dev) 1568 { 1569 struct msk_softc *sc; 1570 char desc[100]; 1571 1572 sc = device_get_softc(device_get_parent(dev)); 1573 /* 1574 * Not much to do here. We always know there will be 1575 * at least one GMAC present, and if there are two, 1576 * mskc_attach() will create a second device instance 1577 * for us. 1578 */ 1579 snprintf(desc, sizeof(desc), 1580 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1581 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1582 sc->msk_hw_rev); 1583 device_set_desc_copy(dev, desc); 1584 1585 return (BUS_PROBE_DEFAULT); 1586 } 1587 1588 static int 1589 msk_attach(device_t dev) 1590 { 1591 struct msk_softc *sc; 1592 struct msk_if_softc *sc_if; 1593 struct ifnet *ifp; 1594 struct msk_mii_data *mmd; 1595 int i, port, error; 1596 uint8_t eaddr[6]; 1597 1598 if (dev == NULL) 1599 return (EINVAL); 1600 1601 error = 0; 1602 sc_if = device_get_softc(dev); 1603 sc = device_get_softc(device_get_parent(dev)); 1604 mmd = device_get_ivars(dev); 1605 port = mmd->port; 1606 1607 sc_if->msk_if_dev = dev; 1608 sc_if->msk_port = port; 1609 sc_if->msk_softc = sc; 1610 sc_if->msk_flags = sc->msk_pflags; 1611 sc->msk_if[port] = sc_if; 1612 /* Setup Tx/Rx queue register offsets. */ 1613 if (port == MSK_PORT_A) { 1614 sc_if->msk_txq = Q_XA1; 1615 sc_if->msk_txsq = Q_XS1; 1616 sc_if->msk_rxq = Q_R1; 1617 } else { 1618 sc_if->msk_txq = Q_XA2; 1619 sc_if->msk_txsq = Q_XS2; 1620 sc_if->msk_rxq = Q_R2; 1621 } 1622 1623 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1624 msk_sysctl_node(sc_if); 1625 1626 if ((error = msk_txrx_dma_alloc(sc_if)) != 0) 1627 goto fail; 1628 msk_rx_dma_jalloc(sc_if); 1629 1630 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1631 if (ifp == NULL) { 1632 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1633 error = ENOSPC; 1634 goto fail; 1635 } 1636 ifp->if_softc = sc_if; 1637 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1638 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1639 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1640 /* 1641 * Enable Rx checksum offloading if controller supports 1642 * new descriptor formant and controller is not Yukon XL. 1643 */ 1644 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1645 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1646 ifp->if_capabilities |= IFCAP_RXCSUM; 1647 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1648 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1649 ifp->if_capabilities |= IFCAP_RXCSUM; 1650 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1651 ifp->if_capenable = ifp->if_capabilities; 1652 ifp->if_ioctl = msk_ioctl; 1653 ifp->if_start = msk_start; 1654 ifp->if_init = msk_init; 1655 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1656 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1657 IFQ_SET_READY(&ifp->if_snd); 1658 /* 1659 * Get station address for this interface. Note that 1660 * dual port cards actually come with three station 1661 * addresses: one for each port, plus an extra. The 1662 * extra one is used by the SysKonnect driver software 1663 * as a 'virtual' station address for when both ports 1664 * are operating in failover mode. Currently we don't 1665 * use this extra address. 1666 */ 1667 MSK_IF_LOCK(sc_if); 1668 for (i = 0; i < ETHER_ADDR_LEN; i++) 1669 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1670 1671 /* 1672 * Call MI attach routine. Can't hold locks when calling into ether_*. 1673 */ 1674 MSK_IF_UNLOCK(sc_if); 1675 ether_ifattach(ifp, eaddr); 1676 MSK_IF_LOCK(sc_if); 1677 1678 /* VLAN capability setup */ 1679 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1680 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1681 /* 1682 * Due to Tx checksum offload hardware bugs, msk(4) manually 1683 * computes checksum for short frames. For VLAN tagged frames 1684 * this workaround does not work so disable checksum offload 1685 * for VLAN interface. 1686 */ 1687 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1688 /* 1689 * Enable Rx checksum offloading for VLAN tagged frames 1690 * if controller support new descriptor format. 1691 */ 1692 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1693 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1694 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1695 } 1696 ifp->if_capenable = ifp->if_capabilities; 1697 /* 1698 * Disable RX checksum offloading on controllers that don't use 1699 * new descriptor format but give chance to enable it. 1700 */ 1701 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1702 ifp->if_capenable &= ~IFCAP_RXCSUM; 1703 1704 /* 1705 * Tell the upper layer(s) we support long frames. 1706 * Must appear after the call to ether_ifattach() because 1707 * ether_ifattach() sets ifi_hdrlen to the default value. 1708 */ 1709 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1710 1711 /* 1712 * Do miibus setup. 1713 */ 1714 MSK_IF_UNLOCK(sc_if); 1715 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1716 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1717 mmd->mii_flags); 1718 if (error != 0) { 1719 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1720 ether_ifdetach(ifp); 1721 error = ENXIO; 1722 goto fail; 1723 } 1724 1725 fail: 1726 if (error != 0) { 1727 /* Access should be ok even though lock has been dropped */ 1728 sc->msk_if[port] = NULL; 1729 msk_detach(dev); 1730 } 1731 1732 return (error); 1733 } 1734 1735 /* 1736 * Attach the interface. Allocate softc structures, do ifmedia 1737 * setup and ethernet/BPF attach. 1738 */ 1739 static int 1740 mskc_attach(device_t dev) 1741 { 1742 struct msk_softc *sc; 1743 struct msk_mii_data *mmd; 1744 int error, msic, msir, reg; 1745 1746 sc = device_get_softc(dev); 1747 sc->msk_dev = dev; 1748 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1749 MTX_DEF); 1750 1751 /* 1752 * Map control/status registers. 1753 */ 1754 pci_enable_busmaster(dev); 1755 1756 /* Allocate I/O resource */ 1757 #ifdef MSK_USEIOSPACE 1758 sc->msk_res_spec = msk_res_spec_io; 1759 #else 1760 sc->msk_res_spec = msk_res_spec_mem; 1761 #endif 1762 sc->msk_irq_spec = msk_irq_spec_legacy; 1763 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1764 if (error) { 1765 if (sc->msk_res_spec == msk_res_spec_mem) 1766 sc->msk_res_spec = msk_res_spec_io; 1767 else 1768 sc->msk_res_spec = msk_res_spec_mem; 1769 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1770 if (error) { 1771 device_printf(dev, "couldn't allocate %s resources\n", 1772 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1773 "I/O"); 1774 mtx_destroy(&sc->msk_mtx); 1775 return (ENXIO); 1776 } 1777 } 1778 1779 /* Enable all clocks before accessing any registers. */ 1780 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1781 1782 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1783 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1784 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1785 /* Bail out if chip is not recognized. */ 1786 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1787 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1788 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1789 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1790 sc->msk_hw_id, sc->msk_hw_rev); 1791 mtx_destroy(&sc->msk_mtx); 1792 return (ENXIO); 1793 } 1794 1795 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1796 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1797 OID_AUTO, "process_limit", 1798 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1799 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1800 "max number of Rx events to process"); 1801 1802 sc->msk_process_limit = MSK_PROC_DEFAULT; 1803 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1804 "process_limit", &sc->msk_process_limit); 1805 if (error == 0) { 1806 if (sc->msk_process_limit < MSK_PROC_MIN || 1807 sc->msk_process_limit > MSK_PROC_MAX) { 1808 device_printf(dev, "process_limit value out of range; " 1809 "using default: %d\n", MSK_PROC_DEFAULT); 1810 sc->msk_process_limit = MSK_PROC_DEFAULT; 1811 } 1812 } 1813 1814 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1815 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1816 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1817 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1818 "Maximum number of time to delay interrupts"); 1819 resource_int_value(device_get_name(dev), device_get_unit(dev), 1820 "int_holdoff", &sc->msk_int_holdoff); 1821 1822 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1823 /* Check number of MACs. */ 1824 sc->msk_num_port = 1; 1825 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1826 CFG_DUAL_MAC_MSK) { 1827 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1828 sc->msk_num_port++; 1829 } 1830 1831 /* Check bus type. */ 1832 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1833 sc->msk_bustype = MSK_PEX_BUS; 1834 sc->msk_expcap = reg; 1835 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1836 sc->msk_bustype = MSK_PCIX_BUS; 1837 sc->msk_pcixcap = reg; 1838 } else 1839 sc->msk_bustype = MSK_PCI_BUS; 1840 1841 switch (sc->msk_hw_id) { 1842 case CHIP_ID_YUKON_EC: 1843 sc->msk_clock = 125; /* 125 MHz */ 1844 sc->msk_pflags |= MSK_FLAG_JUMBO; 1845 break; 1846 case CHIP_ID_YUKON_EC_U: 1847 sc->msk_clock = 125; /* 125 MHz */ 1848 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1849 break; 1850 case CHIP_ID_YUKON_EX: 1851 sc->msk_clock = 125; /* 125 MHz */ 1852 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1853 MSK_FLAG_AUTOTX_CSUM; 1854 /* 1855 * Yukon Extreme seems to have silicon bug for 1856 * automatic Tx checksum calculation capability. 1857 */ 1858 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1859 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1860 /* 1861 * Yukon Extreme A0 could not use store-and-forward 1862 * for jumbo frames, so disable Tx checksum 1863 * offloading for jumbo frames. 1864 */ 1865 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1866 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1867 break; 1868 case CHIP_ID_YUKON_FE: 1869 sc->msk_clock = 100; /* 100 MHz */ 1870 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1871 break; 1872 case CHIP_ID_YUKON_FE_P: 1873 sc->msk_clock = 50; /* 50 MHz */ 1874 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1875 MSK_FLAG_AUTOTX_CSUM; 1876 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1877 /* 1878 * XXX 1879 * FE+ A0 has status LE writeback bug so msk(4) 1880 * does not rely on status word of received frame 1881 * in msk_rxeof() which in turn disables all 1882 * hardware assistance bits reported by the status 1883 * word as well as validity of the received frame. 1884 * Just pass received frames to upper stack with 1885 * minimal test and let upper stack handle them. 1886 */ 1887 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1888 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1889 } 1890 break; 1891 case CHIP_ID_YUKON_XL: 1892 sc->msk_clock = 156; /* 156 MHz */ 1893 sc->msk_pflags |= MSK_FLAG_JUMBO; 1894 break; 1895 case CHIP_ID_YUKON_SUPR: 1896 sc->msk_clock = 125; /* 125 MHz */ 1897 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1898 MSK_FLAG_AUTOTX_CSUM; 1899 break; 1900 case CHIP_ID_YUKON_UL_2: 1901 sc->msk_clock = 125; /* 125 MHz */ 1902 sc->msk_pflags |= MSK_FLAG_JUMBO; 1903 break; 1904 case CHIP_ID_YUKON_OPT: 1905 sc->msk_clock = 125; /* 125 MHz */ 1906 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1907 break; 1908 default: 1909 sc->msk_clock = 156; /* 156 MHz */ 1910 break; 1911 } 1912 1913 /* Allocate IRQ resources. */ 1914 msic = pci_msi_count(dev); 1915 if (bootverbose) 1916 device_printf(dev, "MSI count : %d\n", msic); 1917 if (legacy_intr != 0) 1918 msi_disable = 1; 1919 if (msi_disable == 0 && msic > 0) { 1920 msir = 1; 1921 if (pci_alloc_msi(dev, &msir) == 0) { 1922 if (msir == 1) { 1923 sc->msk_pflags |= MSK_FLAG_MSI; 1924 sc->msk_irq_spec = msk_irq_spec_msi; 1925 } else 1926 pci_release_msi(dev); 1927 } 1928 } 1929 1930 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1931 if (error) { 1932 device_printf(dev, "couldn't allocate IRQ resources\n"); 1933 goto fail; 1934 } 1935 1936 if ((error = msk_status_dma_alloc(sc)) != 0) 1937 goto fail; 1938 1939 /* Set base interrupt mask. */ 1940 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1941 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1942 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1943 1944 /* Reset the adapter. */ 1945 mskc_reset(sc); 1946 1947 if ((error = mskc_setup_rambuffer(sc)) != 0) 1948 goto fail; 1949 1950 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1951 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1952 device_printf(dev, "failed to add child for PORT_A\n"); 1953 error = ENXIO; 1954 goto fail; 1955 } 1956 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1957 mmd->port = MSK_PORT_A; 1958 mmd->pmd = sc->msk_pmd; 1959 mmd->mii_flags |= MIIF_DOPAUSE; 1960 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1961 mmd->mii_flags |= MIIF_HAVEFIBER; 1962 if (sc->msk_pmd == 'P') 1963 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1964 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1965 1966 if (sc->msk_num_port > 1) { 1967 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1968 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1969 device_printf(dev, "failed to add child for PORT_B\n"); 1970 error = ENXIO; 1971 goto fail; 1972 } 1973 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | 1974 M_ZERO); 1975 mmd->port = MSK_PORT_B; 1976 mmd->pmd = sc->msk_pmd; 1977 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1978 mmd->mii_flags |= MIIF_HAVEFIBER; 1979 if (sc->msk_pmd == 'P') 1980 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1981 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1982 } 1983 1984 error = bus_generic_attach(dev); 1985 if (error) { 1986 device_printf(dev, "failed to attach port(s)\n"); 1987 goto fail; 1988 } 1989 1990 /* Hook interrupt last to avoid having to lock softc. */ 1991 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1992 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1993 if (error != 0) { 1994 device_printf(dev, "couldn't set up interrupt handler\n"); 1995 goto fail; 1996 } 1997 fail: 1998 if (error != 0) 1999 mskc_detach(dev); 2000 2001 return (error); 2002 } 2003 2004 /* 2005 * Shutdown hardware and free up resources. This can be called any 2006 * time after the mutex has been initialized. It is called in both 2007 * the error case in attach and the normal detach case so it needs 2008 * to be careful about only freeing resources that have actually been 2009 * allocated. 2010 */ 2011 static int 2012 msk_detach(device_t dev) 2013 { 2014 struct msk_softc *sc; 2015 struct msk_if_softc *sc_if; 2016 struct ifnet *ifp; 2017 2018 sc_if = device_get_softc(dev); 2019 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 2020 ("msk mutex not initialized in msk_detach")); 2021 MSK_IF_LOCK(sc_if); 2022 2023 ifp = sc_if->msk_ifp; 2024 if (device_is_attached(dev)) { 2025 /* XXX */ 2026 sc_if->msk_flags |= MSK_FLAG_DETACH; 2027 msk_stop(sc_if); 2028 /* Can't hold locks while calling detach. */ 2029 MSK_IF_UNLOCK(sc_if); 2030 callout_drain(&sc_if->msk_tick_ch); 2031 if (ifp) 2032 ether_ifdetach(ifp); 2033 MSK_IF_LOCK(sc_if); 2034 } 2035 2036 /* 2037 * We're generally called from mskc_detach() which is using 2038 * device_delete_child() to get to here. It's already trashed 2039 * miibus for us, so don't do it here or we'll panic. 2040 * 2041 * if (sc_if->msk_miibus != NULL) { 2042 * device_delete_child(dev, sc_if->msk_miibus); 2043 * sc_if->msk_miibus = NULL; 2044 * } 2045 */ 2046 2047 msk_rx_dma_jfree(sc_if); 2048 msk_txrx_dma_free(sc_if); 2049 bus_generic_detach(dev); 2050 2051 sc = sc_if->msk_softc; 2052 sc->msk_if[sc_if->msk_port] = NULL; 2053 MSK_IF_UNLOCK(sc_if); 2054 if (ifp) 2055 if_free(ifp); 2056 2057 return (0); 2058 } 2059 2060 static int 2061 mskc_detach(device_t dev) 2062 { 2063 struct msk_softc *sc; 2064 2065 sc = device_get_softc(dev); 2066 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2067 2068 if (device_is_alive(dev)) { 2069 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2070 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2071 M_DEVBUF); 2072 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2073 } 2074 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2075 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2076 M_DEVBUF); 2077 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2078 } 2079 bus_generic_detach(dev); 2080 } 2081 2082 /* Disable all interrupts. */ 2083 CSR_WRITE_4(sc, B0_IMSK, 0); 2084 CSR_READ_4(sc, B0_IMSK); 2085 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2086 CSR_READ_4(sc, B0_HWE_IMSK); 2087 2088 /* LED Off. */ 2089 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2090 2091 /* Put hardware reset. */ 2092 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2093 2094 msk_status_dma_free(sc); 2095 2096 if (sc->msk_intrhand) { 2097 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2098 sc->msk_intrhand = NULL; 2099 } 2100 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2101 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2102 pci_release_msi(dev); 2103 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2104 mtx_destroy(&sc->msk_mtx); 2105 2106 return (0); 2107 } 2108 2109 static bus_dma_tag_t 2110 mskc_get_dma_tag(device_t bus, device_t child __unused) 2111 { 2112 2113 return (bus_get_dma_tag(bus)); 2114 } 2115 2116 struct msk_dmamap_arg { 2117 bus_addr_t msk_busaddr; 2118 }; 2119 2120 static void 2121 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2122 { 2123 struct msk_dmamap_arg *ctx; 2124 2125 if (error != 0) 2126 return; 2127 ctx = arg; 2128 ctx->msk_busaddr = segs[0].ds_addr; 2129 } 2130 2131 /* Create status DMA region. */ 2132 static int 2133 msk_status_dma_alloc(struct msk_softc *sc) 2134 { 2135 struct msk_dmamap_arg ctx; 2136 bus_size_t stat_sz; 2137 int count, error; 2138 2139 /* 2140 * It seems controller requires number of status LE entries 2141 * is power of 2 and the maximum number of status LE entries 2142 * is 4096. For dual-port controllers, the number of status 2143 * LE entries should be large enough to hold both port's 2144 * status updates. 2145 */ 2146 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT; 2147 count = imin(4096, roundup2(count, 1024)); 2148 sc->msk_stat_count = count; 2149 stat_sz = count * sizeof(struct msk_stat_desc); 2150 error = bus_dma_tag_create( 2151 bus_get_dma_tag(sc->msk_dev), /* parent */ 2152 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2153 BUS_SPACE_MAXADDR, /* lowaddr */ 2154 BUS_SPACE_MAXADDR, /* highaddr */ 2155 NULL, NULL, /* filter, filterarg */ 2156 stat_sz, /* maxsize */ 2157 1, /* nsegments */ 2158 stat_sz, /* maxsegsize */ 2159 0, /* flags */ 2160 NULL, NULL, /* lockfunc, lockarg */ 2161 &sc->msk_stat_tag); 2162 if (error != 0) { 2163 device_printf(sc->msk_dev, 2164 "failed to create status DMA tag\n"); 2165 return (error); 2166 } 2167 2168 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2169 error = bus_dmamem_alloc(sc->msk_stat_tag, 2170 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2171 BUS_DMA_ZERO, &sc->msk_stat_map); 2172 if (error != 0) { 2173 device_printf(sc->msk_dev, 2174 "failed to allocate DMA'able memory for status ring\n"); 2175 return (error); 2176 } 2177 2178 ctx.msk_busaddr = 0; 2179 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map, 2180 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2181 if (error != 0) { 2182 device_printf(sc->msk_dev, 2183 "failed to load DMA'able memory for status ring\n"); 2184 return (error); 2185 } 2186 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2187 2188 return (0); 2189 } 2190 2191 static void 2192 msk_status_dma_free(struct msk_softc *sc) 2193 { 2194 2195 /* Destroy status block. */ 2196 if (sc->msk_stat_tag) { 2197 if (sc->msk_stat_ring_paddr) { 2198 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2199 sc->msk_stat_ring_paddr = 0; 2200 } 2201 if (sc->msk_stat_ring) { 2202 bus_dmamem_free(sc->msk_stat_tag, 2203 sc->msk_stat_ring, sc->msk_stat_map); 2204 sc->msk_stat_ring = NULL; 2205 } 2206 bus_dma_tag_destroy(sc->msk_stat_tag); 2207 sc->msk_stat_tag = NULL; 2208 } 2209 } 2210 2211 static int 2212 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2213 { 2214 struct msk_dmamap_arg ctx; 2215 struct msk_txdesc *txd; 2216 struct msk_rxdesc *rxd; 2217 bus_size_t rxalign; 2218 int error, i; 2219 2220 /* Create parent DMA tag. */ 2221 error = bus_dma_tag_create( 2222 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2223 1, 0, /* alignment, boundary */ 2224 BUS_SPACE_MAXADDR, /* lowaddr */ 2225 BUS_SPACE_MAXADDR, /* highaddr */ 2226 NULL, NULL, /* filter, filterarg */ 2227 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2228 0, /* nsegments */ 2229 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2230 0, /* flags */ 2231 NULL, NULL, /* lockfunc, lockarg */ 2232 &sc_if->msk_cdata.msk_parent_tag); 2233 if (error != 0) { 2234 device_printf(sc_if->msk_if_dev, 2235 "failed to create parent DMA tag\n"); 2236 goto fail; 2237 } 2238 /* Create tag for Tx ring. */ 2239 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2240 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2241 BUS_SPACE_MAXADDR, /* lowaddr */ 2242 BUS_SPACE_MAXADDR, /* highaddr */ 2243 NULL, NULL, /* filter, filterarg */ 2244 MSK_TX_RING_SZ, /* maxsize */ 2245 1, /* nsegments */ 2246 MSK_TX_RING_SZ, /* maxsegsize */ 2247 0, /* flags */ 2248 NULL, NULL, /* lockfunc, lockarg */ 2249 &sc_if->msk_cdata.msk_tx_ring_tag); 2250 if (error != 0) { 2251 device_printf(sc_if->msk_if_dev, 2252 "failed to create Tx ring DMA tag\n"); 2253 goto fail; 2254 } 2255 2256 /* Create tag for Rx ring. */ 2257 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2258 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2259 BUS_SPACE_MAXADDR, /* lowaddr */ 2260 BUS_SPACE_MAXADDR, /* highaddr */ 2261 NULL, NULL, /* filter, filterarg */ 2262 MSK_RX_RING_SZ, /* maxsize */ 2263 1, /* nsegments */ 2264 MSK_RX_RING_SZ, /* maxsegsize */ 2265 0, /* flags */ 2266 NULL, NULL, /* lockfunc, lockarg */ 2267 &sc_if->msk_cdata.msk_rx_ring_tag); 2268 if (error != 0) { 2269 device_printf(sc_if->msk_if_dev, 2270 "failed to create Rx ring DMA tag\n"); 2271 goto fail; 2272 } 2273 2274 /* Create tag for Tx buffers. */ 2275 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2276 1, 0, /* alignment, boundary */ 2277 BUS_SPACE_MAXADDR, /* lowaddr */ 2278 BUS_SPACE_MAXADDR, /* highaddr */ 2279 NULL, NULL, /* filter, filterarg */ 2280 MSK_TSO_MAXSIZE, /* maxsize */ 2281 MSK_MAXTXSEGS, /* nsegments */ 2282 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2283 0, /* flags */ 2284 NULL, NULL, /* lockfunc, lockarg */ 2285 &sc_if->msk_cdata.msk_tx_tag); 2286 if (error != 0) { 2287 device_printf(sc_if->msk_if_dev, 2288 "failed to create Tx DMA tag\n"); 2289 goto fail; 2290 } 2291 2292 rxalign = 1; 2293 /* 2294 * Workaround hardware hang which seems to happen when Rx buffer 2295 * is not aligned on multiple of FIFO word(8 bytes). 2296 */ 2297 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2298 rxalign = MSK_RX_BUF_ALIGN; 2299 /* Create tag for Rx buffers. */ 2300 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2301 rxalign, 0, /* alignment, boundary */ 2302 BUS_SPACE_MAXADDR, /* lowaddr */ 2303 BUS_SPACE_MAXADDR, /* highaddr */ 2304 NULL, NULL, /* filter, filterarg */ 2305 MCLBYTES, /* maxsize */ 2306 1, /* nsegments */ 2307 MCLBYTES, /* maxsegsize */ 2308 0, /* flags */ 2309 NULL, NULL, /* lockfunc, lockarg */ 2310 &sc_if->msk_cdata.msk_rx_tag); 2311 if (error != 0) { 2312 device_printf(sc_if->msk_if_dev, 2313 "failed to create Rx DMA tag\n"); 2314 goto fail; 2315 } 2316 2317 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2318 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2319 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2320 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2321 if (error != 0) { 2322 device_printf(sc_if->msk_if_dev, 2323 "failed to allocate DMA'able memory for Tx ring\n"); 2324 goto fail; 2325 } 2326 2327 ctx.msk_busaddr = 0; 2328 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2329 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2330 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2331 if (error != 0) { 2332 device_printf(sc_if->msk_if_dev, 2333 "failed to load DMA'able memory for Tx ring\n"); 2334 goto fail; 2335 } 2336 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2337 2338 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2339 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2340 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2341 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2342 if (error != 0) { 2343 device_printf(sc_if->msk_if_dev, 2344 "failed to allocate DMA'able memory for Rx ring\n"); 2345 goto fail; 2346 } 2347 2348 ctx.msk_busaddr = 0; 2349 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2350 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2351 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2352 if (error != 0) { 2353 device_printf(sc_if->msk_if_dev, 2354 "failed to load DMA'able memory for Rx ring\n"); 2355 goto fail; 2356 } 2357 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2358 2359 /* Create DMA maps for Tx buffers. */ 2360 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2361 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2362 txd->tx_m = NULL; 2363 txd->tx_dmamap = NULL; 2364 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2365 &txd->tx_dmamap); 2366 if (error != 0) { 2367 device_printf(sc_if->msk_if_dev, 2368 "failed to create Tx dmamap\n"); 2369 goto fail; 2370 } 2371 } 2372 /* Create DMA maps for Rx buffers. */ 2373 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2374 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2375 device_printf(sc_if->msk_if_dev, 2376 "failed to create spare Rx dmamap\n"); 2377 goto fail; 2378 } 2379 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2380 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2381 rxd->rx_m = NULL; 2382 rxd->rx_dmamap = NULL; 2383 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2384 &rxd->rx_dmamap); 2385 if (error != 0) { 2386 device_printf(sc_if->msk_if_dev, 2387 "failed to create Rx dmamap\n"); 2388 goto fail; 2389 } 2390 } 2391 2392 fail: 2393 return (error); 2394 } 2395 2396 static int 2397 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2398 { 2399 struct msk_dmamap_arg ctx; 2400 struct msk_rxdesc *jrxd; 2401 bus_size_t rxalign; 2402 int error, i; 2403 2404 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2405 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2406 device_printf(sc_if->msk_if_dev, 2407 "disabling jumbo frame support\n"); 2408 return (0); 2409 } 2410 /* Create tag for jumbo Rx ring. */ 2411 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2412 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2413 BUS_SPACE_MAXADDR, /* lowaddr */ 2414 BUS_SPACE_MAXADDR, /* highaddr */ 2415 NULL, NULL, /* filter, filterarg */ 2416 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2417 1, /* nsegments */ 2418 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2419 0, /* flags */ 2420 NULL, NULL, /* lockfunc, lockarg */ 2421 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2422 if (error != 0) { 2423 device_printf(sc_if->msk_if_dev, 2424 "failed to create jumbo Rx ring DMA tag\n"); 2425 goto jumbo_fail; 2426 } 2427 2428 rxalign = 1; 2429 /* 2430 * Workaround hardware hang which seems to happen when Rx buffer 2431 * is not aligned on multiple of FIFO word(8 bytes). 2432 */ 2433 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2434 rxalign = MSK_RX_BUF_ALIGN; 2435 /* Create tag for jumbo Rx buffers. */ 2436 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2437 rxalign, 0, /* alignment, boundary */ 2438 BUS_SPACE_MAXADDR, /* lowaddr */ 2439 BUS_SPACE_MAXADDR, /* highaddr */ 2440 NULL, NULL, /* filter, filterarg */ 2441 MJUM9BYTES, /* maxsize */ 2442 1, /* nsegments */ 2443 MJUM9BYTES, /* maxsegsize */ 2444 0, /* flags */ 2445 NULL, NULL, /* lockfunc, lockarg */ 2446 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2447 if (error != 0) { 2448 device_printf(sc_if->msk_if_dev, 2449 "failed to create jumbo Rx DMA tag\n"); 2450 goto jumbo_fail; 2451 } 2452 2453 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2454 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2455 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2456 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2457 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2458 if (error != 0) { 2459 device_printf(sc_if->msk_if_dev, 2460 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2461 goto jumbo_fail; 2462 } 2463 2464 ctx.msk_busaddr = 0; 2465 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2466 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2467 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2468 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2469 if (error != 0) { 2470 device_printf(sc_if->msk_if_dev, 2471 "failed to load DMA'able memory for jumbo Rx ring\n"); 2472 goto jumbo_fail; 2473 } 2474 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2475 2476 /* Create DMA maps for jumbo Rx buffers. */ 2477 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2478 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2479 device_printf(sc_if->msk_if_dev, 2480 "failed to create spare jumbo Rx dmamap\n"); 2481 goto jumbo_fail; 2482 } 2483 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2484 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2485 jrxd->rx_m = NULL; 2486 jrxd->rx_dmamap = NULL; 2487 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2488 &jrxd->rx_dmamap); 2489 if (error != 0) { 2490 device_printf(sc_if->msk_if_dev, 2491 "failed to create jumbo Rx dmamap\n"); 2492 goto jumbo_fail; 2493 } 2494 } 2495 2496 return (0); 2497 2498 jumbo_fail: 2499 msk_rx_dma_jfree(sc_if); 2500 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2501 "due to resource shortage\n"); 2502 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2503 return (error); 2504 } 2505 2506 static void 2507 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2508 { 2509 struct msk_txdesc *txd; 2510 struct msk_rxdesc *rxd; 2511 int i; 2512 2513 /* Tx ring. */ 2514 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2515 if (sc_if->msk_rdata.msk_tx_ring_paddr) 2516 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2517 sc_if->msk_cdata.msk_tx_ring_map); 2518 if (sc_if->msk_rdata.msk_tx_ring) 2519 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2520 sc_if->msk_rdata.msk_tx_ring, 2521 sc_if->msk_cdata.msk_tx_ring_map); 2522 sc_if->msk_rdata.msk_tx_ring = NULL; 2523 sc_if->msk_rdata.msk_tx_ring_paddr = 0; 2524 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2525 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2526 } 2527 /* Rx ring. */ 2528 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2529 if (sc_if->msk_rdata.msk_rx_ring_paddr) 2530 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2531 sc_if->msk_cdata.msk_rx_ring_map); 2532 if (sc_if->msk_rdata.msk_rx_ring) 2533 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2534 sc_if->msk_rdata.msk_rx_ring, 2535 sc_if->msk_cdata.msk_rx_ring_map); 2536 sc_if->msk_rdata.msk_rx_ring = NULL; 2537 sc_if->msk_rdata.msk_rx_ring_paddr = 0; 2538 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2539 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2540 } 2541 /* Tx buffers. */ 2542 if (sc_if->msk_cdata.msk_tx_tag) { 2543 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2544 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2545 if (txd->tx_dmamap) { 2546 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2547 txd->tx_dmamap); 2548 txd->tx_dmamap = NULL; 2549 } 2550 } 2551 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2552 sc_if->msk_cdata.msk_tx_tag = NULL; 2553 } 2554 /* Rx buffers. */ 2555 if (sc_if->msk_cdata.msk_rx_tag) { 2556 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2557 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2558 if (rxd->rx_dmamap) { 2559 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2560 rxd->rx_dmamap); 2561 rxd->rx_dmamap = NULL; 2562 } 2563 } 2564 if (sc_if->msk_cdata.msk_rx_sparemap) { 2565 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2566 sc_if->msk_cdata.msk_rx_sparemap); 2567 sc_if->msk_cdata.msk_rx_sparemap = 0; 2568 } 2569 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2570 sc_if->msk_cdata.msk_rx_tag = NULL; 2571 } 2572 if (sc_if->msk_cdata.msk_parent_tag) { 2573 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2574 sc_if->msk_cdata.msk_parent_tag = NULL; 2575 } 2576 } 2577 2578 static void 2579 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2580 { 2581 struct msk_rxdesc *jrxd; 2582 int i; 2583 2584 /* Jumbo Rx ring. */ 2585 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2586 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr) 2587 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2588 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2589 if (sc_if->msk_rdata.msk_jumbo_rx_ring) 2590 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2591 sc_if->msk_rdata.msk_jumbo_rx_ring, 2592 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2593 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2594 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0; 2595 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2596 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2597 } 2598 /* Jumbo Rx buffers. */ 2599 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2600 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2601 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2602 if (jrxd->rx_dmamap) { 2603 bus_dmamap_destroy( 2604 sc_if->msk_cdata.msk_jumbo_rx_tag, 2605 jrxd->rx_dmamap); 2606 jrxd->rx_dmamap = NULL; 2607 } 2608 } 2609 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2610 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2611 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2612 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2613 } 2614 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2615 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2616 } 2617 } 2618 2619 static int 2620 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2621 { 2622 struct msk_txdesc *txd, *txd_last; 2623 struct msk_tx_desc *tx_le; 2624 struct mbuf *m; 2625 bus_dmamap_t map; 2626 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2627 uint32_t control, csum, prod, si; 2628 uint16_t offset, tcp_offset, tso_mtu; 2629 int error, i, nseg, tso; 2630 2631 MSK_IF_LOCK_ASSERT(sc_if); 2632 2633 tcp_offset = offset = 0; 2634 m = *m_head; 2635 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2636 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2637 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2638 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2639 /* 2640 * Since mbuf has no protocol specific structure information 2641 * in it we have to inspect protocol information here to 2642 * setup TSO and checksum offload. I don't know why Marvell 2643 * made a such decision in chip design because other GigE 2644 * hardwares normally takes care of all these chores in 2645 * hardware. However, TSO performance of Yukon II is very 2646 * good such that it's worth to implement it. 2647 */ 2648 struct ether_header *eh; 2649 struct ip *ip; 2650 struct tcphdr *tcp; 2651 2652 if (M_WRITABLE(m) == 0) { 2653 /* Get a writable copy. */ 2654 m = m_dup(*m_head, M_NOWAIT); 2655 m_freem(*m_head); 2656 if (m == NULL) { 2657 *m_head = NULL; 2658 return (ENOBUFS); 2659 } 2660 *m_head = m; 2661 } 2662 2663 offset = sizeof(struct ether_header); 2664 m = m_pullup(m, offset); 2665 if (m == NULL) { 2666 *m_head = NULL; 2667 return (ENOBUFS); 2668 } 2669 eh = mtod(m, struct ether_header *); 2670 /* Check if hardware VLAN insertion is off. */ 2671 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2672 offset = sizeof(struct ether_vlan_header); 2673 m = m_pullup(m, offset); 2674 if (m == NULL) { 2675 *m_head = NULL; 2676 return (ENOBUFS); 2677 } 2678 } 2679 m = m_pullup(m, offset + sizeof(struct ip)); 2680 if (m == NULL) { 2681 *m_head = NULL; 2682 return (ENOBUFS); 2683 } 2684 ip = (struct ip *)(mtod(m, char *) + offset); 2685 offset += (ip->ip_hl << 2); 2686 tcp_offset = offset; 2687 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2688 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2689 if (m == NULL) { 2690 *m_head = NULL; 2691 return (ENOBUFS); 2692 } 2693 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2694 offset += (tcp->th_off << 2); 2695 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2696 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2697 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2698 /* 2699 * It seems that Yukon II has Tx checksum offload bug 2700 * for small TCP packets that's less than 60 bytes in 2701 * size (e.g. TCP window probe packet, pure ACK packet). 2702 * Common work around like padding with zeros to make 2703 * the frame minimum ethernet frame size didn't work at 2704 * all. 2705 * Instead of disabling checksum offload completely we 2706 * resort to S/W checksum routine when we encounter 2707 * short TCP frames. 2708 * Short UDP packets appear to be handled correctly by 2709 * Yukon II. Also I assume this bug does not happen on 2710 * controllers that use newer descriptor format or 2711 * automatic Tx checksum calculation. 2712 */ 2713 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2714 if (m == NULL) { 2715 *m_head = NULL; 2716 return (ENOBUFS); 2717 } 2718 *(uint16_t *)(m->m_data + offset + 2719 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2720 m->m_pkthdr.len, offset); 2721 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2722 } 2723 *m_head = m; 2724 } 2725 2726 prod = sc_if->msk_cdata.msk_tx_prod; 2727 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2728 txd_last = txd; 2729 map = txd->tx_dmamap; 2730 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2731 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2732 if (error == EFBIG) { 2733 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS); 2734 if (m == NULL) { 2735 m_freem(*m_head); 2736 *m_head = NULL; 2737 return (ENOBUFS); 2738 } 2739 *m_head = m; 2740 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2741 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2742 if (error != 0) { 2743 m_freem(*m_head); 2744 *m_head = NULL; 2745 return (error); 2746 } 2747 } else if (error != 0) 2748 return (error); 2749 if (nseg == 0) { 2750 m_freem(*m_head); 2751 *m_head = NULL; 2752 return (EIO); 2753 } 2754 2755 /* Check number of available descriptors. */ 2756 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2757 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2758 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2759 return (ENOBUFS); 2760 } 2761 2762 control = 0; 2763 tso = 0; 2764 tx_le = NULL; 2765 2766 /* Check TSO support. */ 2767 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2768 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2769 tso_mtu = m->m_pkthdr.tso_segsz; 2770 else 2771 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2772 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2773 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2774 tx_le->msk_addr = htole32(tso_mtu); 2775 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2776 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2777 else 2778 tx_le->msk_control = 2779 htole32(OP_LRGLEN | HW_OWNER); 2780 sc_if->msk_cdata.msk_tx_cnt++; 2781 MSK_INC(prod, MSK_TX_RING_CNT); 2782 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2783 } 2784 tso++; 2785 } 2786 /* Check if we have a VLAN tag to insert. */ 2787 if ((m->m_flags & M_VLANTAG) != 0) { 2788 if (tx_le == NULL) { 2789 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2790 tx_le->msk_addr = htole32(0); 2791 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2792 htons(m->m_pkthdr.ether_vtag)); 2793 sc_if->msk_cdata.msk_tx_cnt++; 2794 MSK_INC(prod, MSK_TX_RING_CNT); 2795 } else { 2796 tx_le->msk_control |= htole32(OP_VLAN | 2797 htons(m->m_pkthdr.ether_vtag)); 2798 } 2799 control |= INS_VLAN; 2800 } 2801 /* Check if we have to handle checksum offload. */ 2802 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2803 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2804 control |= CALSUM; 2805 else { 2806 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2807 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2808 control |= UDPTCP; 2809 /* Checksum write position. */ 2810 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2811 /* Checksum start position. */ 2812 csum |= (uint32_t)tcp_offset << 16; 2813 if (csum != sc_if->msk_cdata.msk_last_csum) { 2814 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2815 tx_le->msk_addr = htole32(csum); 2816 tx_le->msk_control = htole32(1 << 16 | 2817 (OP_TCPLISW | HW_OWNER)); 2818 sc_if->msk_cdata.msk_tx_cnt++; 2819 MSK_INC(prod, MSK_TX_RING_CNT); 2820 sc_if->msk_cdata.msk_last_csum = csum; 2821 } 2822 } 2823 } 2824 2825 #ifdef MSK_64BIT_DMA 2826 if (MSK_ADDR_HI(txsegs[0].ds_addr) != 2827 sc_if->msk_cdata.msk_tx_high_addr) { 2828 sc_if->msk_cdata.msk_tx_high_addr = 2829 MSK_ADDR_HI(txsegs[0].ds_addr); 2830 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2831 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr)); 2832 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2833 sc_if->msk_cdata.msk_tx_cnt++; 2834 MSK_INC(prod, MSK_TX_RING_CNT); 2835 } 2836 #endif 2837 si = prod; 2838 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2839 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2840 if (tso == 0) 2841 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2842 OP_PACKET); 2843 else 2844 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2845 OP_LARGESEND); 2846 sc_if->msk_cdata.msk_tx_cnt++; 2847 MSK_INC(prod, MSK_TX_RING_CNT); 2848 2849 for (i = 1; i < nseg; i++) { 2850 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2851 #ifdef MSK_64BIT_DMA 2852 if (MSK_ADDR_HI(txsegs[i].ds_addr) != 2853 sc_if->msk_cdata.msk_tx_high_addr) { 2854 sc_if->msk_cdata.msk_tx_high_addr = 2855 MSK_ADDR_HI(txsegs[i].ds_addr); 2856 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2857 tx_le->msk_addr = 2858 htole32(MSK_ADDR_HI(txsegs[i].ds_addr)); 2859 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2860 sc_if->msk_cdata.msk_tx_cnt++; 2861 MSK_INC(prod, MSK_TX_RING_CNT); 2862 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2863 } 2864 #endif 2865 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2866 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2867 OP_BUFFER | HW_OWNER); 2868 sc_if->msk_cdata.msk_tx_cnt++; 2869 MSK_INC(prod, MSK_TX_RING_CNT); 2870 } 2871 /* Update producer index. */ 2872 sc_if->msk_cdata.msk_tx_prod = prod; 2873 2874 /* Set EOP on the last descriptor. */ 2875 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2876 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2877 tx_le->msk_control |= htole32(EOP); 2878 2879 /* Turn the first descriptor ownership to hardware. */ 2880 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2881 tx_le->msk_control |= htole32(HW_OWNER); 2882 2883 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2884 map = txd_last->tx_dmamap; 2885 txd_last->tx_dmamap = txd->tx_dmamap; 2886 txd->tx_dmamap = map; 2887 txd->tx_m = m; 2888 2889 /* Sync descriptors. */ 2890 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2891 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2892 sc_if->msk_cdata.msk_tx_ring_map, 2893 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2894 2895 return (0); 2896 } 2897 2898 static void 2899 msk_start(struct ifnet *ifp) 2900 { 2901 struct msk_if_softc *sc_if; 2902 2903 sc_if = ifp->if_softc; 2904 MSK_IF_LOCK(sc_if); 2905 msk_start_locked(ifp); 2906 MSK_IF_UNLOCK(sc_if); 2907 } 2908 2909 static void 2910 msk_start_locked(struct ifnet *ifp) 2911 { 2912 struct msk_if_softc *sc_if; 2913 struct mbuf *m_head; 2914 int enq; 2915 2916 sc_if = ifp->if_softc; 2917 MSK_IF_LOCK_ASSERT(sc_if); 2918 2919 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2920 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2921 return; 2922 2923 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2924 sc_if->msk_cdata.msk_tx_cnt < 2925 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2926 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2927 if (m_head == NULL) 2928 break; 2929 /* 2930 * Pack the data into the transmit ring. If we 2931 * don't have room, set the OACTIVE flag and wait 2932 * for the NIC to drain the ring. 2933 */ 2934 if (msk_encap(sc_if, &m_head) != 0) { 2935 if (m_head == NULL) 2936 break; 2937 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2938 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2939 break; 2940 } 2941 2942 enq++; 2943 /* 2944 * If there's a BPF listener, bounce a copy of this frame 2945 * to him. 2946 */ 2947 ETHER_BPF_MTAP(ifp, m_head); 2948 } 2949 2950 if (enq > 0) { 2951 /* Transmit */ 2952 CSR_WRITE_2(sc_if->msk_softc, 2953 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2954 sc_if->msk_cdata.msk_tx_prod); 2955 2956 /* Set a timeout in case the chip goes out to lunch. */ 2957 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2958 } 2959 } 2960 2961 static void 2962 msk_watchdog(struct msk_if_softc *sc_if) 2963 { 2964 struct ifnet *ifp; 2965 2966 MSK_IF_LOCK_ASSERT(sc_if); 2967 2968 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2969 return; 2970 ifp = sc_if->msk_ifp; 2971 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2972 if (bootverbose) 2973 if_printf(sc_if->msk_ifp, "watchdog timeout " 2974 "(missed link)\n"); 2975 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2976 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2977 msk_init_locked(sc_if); 2978 return; 2979 } 2980 2981 if_printf(ifp, "watchdog timeout\n"); 2982 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2983 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2984 msk_init_locked(sc_if); 2985 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2986 msk_start_locked(ifp); 2987 } 2988 2989 static int 2990 mskc_shutdown(device_t dev) 2991 { 2992 struct msk_softc *sc; 2993 int i; 2994 2995 sc = device_get_softc(dev); 2996 MSK_LOCK(sc); 2997 for (i = 0; i < sc->msk_num_port; i++) { 2998 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2999 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 3000 IFF_DRV_RUNNING) != 0)) 3001 msk_stop(sc->msk_if[i]); 3002 } 3003 MSK_UNLOCK(sc); 3004 3005 /* Put hardware reset. */ 3006 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3007 return (0); 3008 } 3009 3010 static int 3011 mskc_suspend(device_t dev) 3012 { 3013 struct msk_softc *sc; 3014 int i; 3015 3016 sc = device_get_softc(dev); 3017 3018 MSK_LOCK(sc); 3019 3020 for (i = 0; i < sc->msk_num_port; i++) { 3021 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3022 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 3023 IFF_DRV_RUNNING) != 0)) 3024 msk_stop(sc->msk_if[i]); 3025 } 3026 3027 /* Disable all interrupts. */ 3028 CSR_WRITE_4(sc, B0_IMSK, 0); 3029 CSR_READ_4(sc, B0_IMSK); 3030 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 3031 CSR_READ_4(sc, B0_HWE_IMSK); 3032 3033 msk_phy_power(sc, MSK_PHY_POWERDOWN); 3034 3035 /* Put hardware reset. */ 3036 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3037 sc->msk_pflags |= MSK_FLAG_SUSPEND; 3038 3039 MSK_UNLOCK(sc); 3040 3041 return (0); 3042 } 3043 3044 static int 3045 mskc_resume(device_t dev) 3046 { 3047 struct msk_softc *sc; 3048 int i; 3049 3050 sc = device_get_softc(dev); 3051 3052 MSK_LOCK(sc); 3053 3054 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 3055 mskc_reset(sc); 3056 for (i = 0; i < sc->msk_num_port; i++) { 3057 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3058 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 3059 sc->msk_if[i]->msk_ifp->if_drv_flags &= 3060 ~IFF_DRV_RUNNING; 3061 msk_init_locked(sc->msk_if[i]); 3062 } 3063 } 3064 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 3065 3066 MSK_UNLOCK(sc); 3067 3068 return (0); 3069 } 3070 3071 #ifndef __NO_STRICT_ALIGNMENT 3072 static __inline void 3073 msk_fixup_rx(struct mbuf *m) 3074 { 3075 int i; 3076 uint16_t *src, *dst; 3077 3078 src = mtod(m, uint16_t *); 3079 dst = src - 3; 3080 3081 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3082 *dst++ = *src++; 3083 3084 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 3085 } 3086 #endif 3087 3088 static __inline void 3089 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3090 { 3091 struct ether_header *eh; 3092 struct ip *ip; 3093 struct udphdr *uh; 3094 int32_t hlen, len, pktlen, temp32; 3095 uint16_t csum, *opts; 3096 3097 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3098 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3099 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3100 if ((control & CSS_IPV4_CSUM_OK) != 0) 3101 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3102 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3103 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3104 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3105 CSUM_PSEUDO_HDR; 3106 m->m_pkthdr.csum_data = 0xffff; 3107 } 3108 } 3109 return; 3110 } 3111 /* 3112 * Marvell Yukon controllers that support OP_RXCHKS has known 3113 * to have various Rx checksum offloading bugs. These 3114 * controllers can be configured to compute simple checksum 3115 * at two different positions. So we can compute IP and TCP/UDP 3116 * checksum at the same time. We intentionally have controller 3117 * compute TCP/UDP checksum twice by specifying the same 3118 * checksum start position and compare the result. If the value 3119 * is different it would indicate the hardware logic was wrong. 3120 */ 3121 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3122 if (bootverbose) 3123 device_printf(sc_if->msk_if_dev, 3124 "Rx checksum value mismatch!\n"); 3125 return; 3126 } 3127 pktlen = m->m_pkthdr.len; 3128 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3129 return; 3130 eh = mtod(m, struct ether_header *); 3131 if (eh->ether_type != htons(ETHERTYPE_IP)) 3132 return; 3133 ip = (struct ip *)(eh + 1); 3134 if (ip->ip_v != IPVERSION) 3135 return; 3136 3137 hlen = ip->ip_hl << 2; 3138 pktlen -= sizeof(struct ether_header); 3139 if (hlen < sizeof(struct ip)) 3140 return; 3141 if (ntohs(ip->ip_len) < hlen) 3142 return; 3143 if (ntohs(ip->ip_len) != pktlen) 3144 return; 3145 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3146 return; /* can't handle fragmented packet. */ 3147 3148 switch (ip->ip_p) { 3149 case IPPROTO_TCP: 3150 if (pktlen < (hlen + sizeof(struct tcphdr))) 3151 return; 3152 break; 3153 case IPPROTO_UDP: 3154 if (pktlen < (hlen + sizeof(struct udphdr))) 3155 return; 3156 uh = (struct udphdr *)((caddr_t)ip + hlen); 3157 if (uh->uh_sum == 0) 3158 return; /* no checksum */ 3159 break; 3160 default: 3161 return; 3162 } 3163 csum = bswap16(sc_if->msk_csum & 0xFFFF); 3164 /* Checksum fixup for IP options. */ 3165 len = hlen - sizeof(struct ip); 3166 if (len > 0) { 3167 opts = (uint16_t *)(ip + 1); 3168 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3169 temp32 = csum - *opts; 3170 temp32 = (temp32 >> 16) + (temp32 & 65535); 3171 csum = temp32 & 65535; 3172 } 3173 } 3174 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3175 m->m_pkthdr.csum_data = csum; 3176 } 3177 3178 static void 3179 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3180 int len) 3181 { 3182 struct mbuf *m; 3183 struct ifnet *ifp; 3184 struct msk_rxdesc *rxd; 3185 int cons, rxlen; 3186 3187 ifp = sc_if->msk_ifp; 3188 3189 MSK_IF_LOCK_ASSERT(sc_if); 3190 3191 cons = sc_if->msk_cdata.msk_rx_cons; 3192 do { 3193 rxlen = status >> 16; 3194 if ((status & GMR_FS_VLAN) != 0 && 3195 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3196 rxlen -= ETHER_VLAN_ENCAP_LEN; 3197 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3198 /* 3199 * For controllers that returns bogus status code 3200 * just do minimal check and let upper stack 3201 * handle this frame. 3202 */ 3203 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3204 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3205 msk_discard_rxbuf(sc_if, cons); 3206 break; 3207 } 3208 } else if (len > sc_if->msk_framesize || 3209 ((status & GMR_FS_ANY_ERR) != 0) || 3210 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3211 /* Don't count flow-control packet as errors. */ 3212 if ((status & GMR_FS_GOOD_FC) == 0) 3213 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3214 msk_discard_rxbuf(sc_if, cons); 3215 break; 3216 } 3217 #ifdef MSK_64BIT_DMA 3218 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) % 3219 MSK_RX_RING_CNT]; 3220 #else 3221 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3222 #endif 3223 m = rxd->rx_m; 3224 if (msk_newbuf(sc_if, cons) != 0) { 3225 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3226 /* Reuse old buffer. */ 3227 msk_discard_rxbuf(sc_if, cons); 3228 break; 3229 } 3230 m->m_pkthdr.rcvif = ifp; 3231 m->m_pkthdr.len = m->m_len = len; 3232 #ifndef __NO_STRICT_ALIGNMENT 3233 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3234 msk_fixup_rx(m); 3235 #endif 3236 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3237 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3238 msk_rxcsum(sc_if, control, m); 3239 /* Check for VLAN tagged packets. */ 3240 if ((status & GMR_FS_VLAN) != 0 && 3241 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3242 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3243 m->m_flags |= M_VLANTAG; 3244 } 3245 MSK_IF_UNLOCK(sc_if); 3246 (*ifp->if_input)(ifp, m); 3247 MSK_IF_LOCK(sc_if); 3248 } while (0); 3249 3250 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3251 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3252 } 3253 3254 static void 3255 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3256 int len) 3257 { 3258 struct mbuf *m; 3259 struct ifnet *ifp; 3260 struct msk_rxdesc *jrxd; 3261 int cons, rxlen; 3262 3263 ifp = sc_if->msk_ifp; 3264 3265 MSK_IF_LOCK_ASSERT(sc_if); 3266 3267 cons = sc_if->msk_cdata.msk_rx_cons; 3268 do { 3269 rxlen = status >> 16; 3270 if ((status & GMR_FS_VLAN) != 0 && 3271 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3272 rxlen -= ETHER_VLAN_ENCAP_LEN; 3273 if (len > sc_if->msk_framesize || 3274 ((status & GMR_FS_ANY_ERR) != 0) || 3275 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3276 /* Don't count flow-control packet as errors. */ 3277 if ((status & GMR_FS_GOOD_FC) == 0) 3278 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3279 msk_discard_jumbo_rxbuf(sc_if, cons); 3280 break; 3281 } 3282 #ifdef MSK_64BIT_DMA 3283 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) % 3284 MSK_JUMBO_RX_RING_CNT]; 3285 #else 3286 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3287 #endif 3288 m = jrxd->rx_m; 3289 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3290 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3291 /* Reuse old buffer. */ 3292 msk_discard_jumbo_rxbuf(sc_if, cons); 3293 break; 3294 } 3295 m->m_pkthdr.rcvif = ifp; 3296 m->m_pkthdr.len = m->m_len = len; 3297 #ifndef __NO_STRICT_ALIGNMENT 3298 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3299 msk_fixup_rx(m); 3300 #endif 3301 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3302 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3303 msk_rxcsum(sc_if, control, m); 3304 /* Check for VLAN tagged packets. */ 3305 if ((status & GMR_FS_VLAN) != 0 && 3306 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3307 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3308 m->m_flags |= M_VLANTAG; 3309 } 3310 MSK_IF_UNLOCK(sc_if); 3311 (*ifp->if_input)(ifp, m); 3312 MSK_IF_LOCK(sc_if); 3313 } while (0); 3314 3315 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3316 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3317 } 3318 3319 static void 3320 msk_txeof(struct msk_if_softc *sc_if, int idx) 3321 { 3322 struct msk_txdesc *txd; 3323 struct msk_tx_desc *cur_tx; 3324 struct ifnet *ifp; 3325 uint32_t control; 3326 int cons, prog; 3327 3328 MSK_IF_LOCK_ASSERT(sc_if); 3329 3330 ifp = sc_if->msk_ifp; 3331 3332 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3333 sc_if->msk_cdata.msk_tx_ring_map, 3334 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3335 /* 3336 * Go through our tx ring and free mbufs for those 3337 * frames that have been sent. 3338 */ 3339 cons = sc_if->msk_cdata.msk_tx_cons; 3340 prog = 0; 3341 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3342 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3343 break; 3344 prog++; 3345 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3346 control = le32toh(cur_tx->msk_control); 3347 sc_if->msk_cdata.msk_tx_cnt--; 3348 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3349 if ((control & EOP) == 0) 3350 continue; 3351 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3352 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3353 BUS_DMASYNC_POSTWRITE); 3354 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3355 3356 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3357 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3358 __func__)); 3359 m_freem(txd->tx_m); 3360 txd->tx_m = NULL; 3361 } 3362 3363 if (prog > 0) { 3364 sc_if->msk_cdata.msk_tx_cons = cons; 3365 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3366 sc_if->msk_watchdog_timer = 0; 3367 /* No need to sync LEs as we didn't update LEs. */ 3368 } 3369 } 3370 3371 static void 3372 msk_tick(void *xsc_if) 3373 { 3374 struct epoch_tracker et; 3375 struct msk_if_softc *sc_if; 3376 struct mii_data *mii; 3377 3378 sc_if = xsc_if; 3379 3380 MSK_IF_LOCK_ASSERT(sc_if); 3381 3382 mii = device_get_softc(sc_if->msk_miibus); 3383 3384 mii_tick(mii); 3385 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3386 msk_miibus_statchg(sc_if->msk_if_dev); 3387 NET_EPOCH_ENTER(et); 3388 msk_handle_events(sc_if->msk_softc); 3389 NET_EPOCH_EXIT(et); 3390 msk_watchdog(sc_if); 3391 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3392 } 3393 3394 static void 3395 msk_intr_phy(struct msk_if_softc *sc_if) 3396 { 3397 uint16_t status; 3398 3399 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3400 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3401 /* Handle FIFO Underrun/Overflow? */ 3402 if ((status & PHY_M_IS_FIFO_ERROR)) 3403 device_printf(sc_if->msk_if_dev, 3404 "PHY FIFO underrun/overflow.\n"); 3405 } 3406 3407 static void 3408 msk_intr_gmac(struct msk_if_softc *sc_if) 3409 { 3410 struct msk_softc *sc; 3411 uint8_t status; 3412 3413 sc = sc_if->msk_softc; 3414 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3415 3416 /* GMAC Rx FIFO overrun. */ 3417 if ((status & GM_IS_RX_FF_OR) != 0) 3418 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3419 GMF_CLI_RX_FO); 3420 /* GMAC Tx FIFO underrun. */ 3421 if ((status & GM_IS_TX_FF_UR) != 0) { 3422 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3423 GMF_CLI_TX_FU); 3424 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3425 /* 3426 * XXX 3427 * In case of Tx underrun, we may need to flush/reset 3428 * Tx MAC but that would also require resynchronization 3429 * with status LEs. Reinitializing status LEs would 3430 * affect other port in dual MAC configuration so it 3431 * should be avoided as possible as we can. 3432 * Due to lack of documentation it's all vague guess but 3433 * it needs more investigation. 3434 */ 3435 } 3436 } 3437 3438 static void 3439 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3440 { 3441 struct msk_softc *sc; 3442 3443 sc = sc_if->msk_softc; 3444 if ((status & Y2_IS_PAR_RD1) != 0) { 3445 device_printf(sc_if->msk_if_dev, 3446 "RAM buffer read parity error\n"); 3447 /* Clear IRQ. */ 3448 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3449 RI_CLR_RD_PERR); 3450 } 3451 if ((status & Y2_IS_PAR_WR1) != 0) { 3452 device_printf(sc_if->msk_if_dev, 3453 "RAM buffer write parity error\n"); 3454 /* Clear IRQ. */ 3455 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3456 RI_CLR_WR_PERR); 3457 } 3458 if ((status & Y2_IS_PAR_MAC1) != 0) { 3459 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3460 /* Clear IRQ. */ 3461 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3462 GMF_CLI_TX_PE); 3463 } 3464 if ((status & Y2_IS_PAR_RX1) != 0) { 3465 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3466 /* Clear IRQ. */ 3467 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3468 } 3469 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3470 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3471 /* Clear IRQ. */ 3472 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3473 } 3474 } 3475 3476 static void 3477 msk_intr_hwerr(struct msk_softc *sc) 3478 { 3479 uint32_t status; 3480 uint32_t tlphead[4]; 3481 3482 status = CSR_READ_4(sc, B0_HWE_ISRC); 3483 /* Time Stamp timer overflow. */ 3484 if ((status & Y2_IS_TIST_OV) != 0) 3485 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3486 if ((status & Y2_IS_PCI_NEXP) != 0) { 3487 /* 3488 * PCI Express Error occurred which is not described in PEX 3489 * spec. 3490 * This error is also mapped either to Master Abort( 3491 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3492 * can only be cleared there. 3493 */ 3494 device_printf(sc->msk_dev, 3495 "PCI Express protocol violation error\n"); 3496 } 3497 3498 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3499 uint16_t v16; 3500 3501 if ((status & Y2_IS_MST_ERR) != 0) 3502 device_printf(sc->msk_dev, 3503 "unexpected IRQ Status error\n"); 3504 else 3505 device_printf(sc->msk_dev, 3506 "unexpected IRQ Master error\n"); 3507 /* Reset all bits in the PCI status register. */ 3508 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3509 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3510 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3511 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3512 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3513 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3514 } 3515 3516 /* Check for PCI Express Uncorrectable Error. */ 3517 if ((status & Y2_IS_PCI_EXP) != 0) { 3518 uint32_t v32; 3519 3520 /* 3521 * On PCI Express bus bridges are called root complexes (RC). 3522 * PCI Express errors are recognized by the root complex too, 3523 * which requests the system to handle the problem. After 3524 * error occurrence it may be that no access to the adapter 3525 * may be performed any longer. 3526 */ 3527 3528 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3529 if ((v32 & PEX_UNSUP_REQ) != 0) { 3530 /* Ignore unsupported request error. */ 3531 device_printf(sc->msk_dev, 3532 "Uncorrectable PCI Express error\n"); 3533 } 3534 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3535 int i; 3536 3537 /* Get TLP header form Log Registers. */ 3538 for (i = 0; i < 4; i++) 3539 tlphead[i] = CSR_PCI_READ_4(sc, 3540 PEX_HEADER_LOG + i * 4); 3541 /* Check for vendor defined broadcast message. */ 3542 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3543 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3544 CSR_WRITE_4(sc, B0_HWE_IMSK, 3545 sc->msk_intrhwemask); 3546 CSR_READ_4(sc, B0_HWE_IMSK); 3547 } 3548 } 3549 /* Clear the interrupt. */ 3550 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3551 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3552 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3553 } 3554 3555 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3556 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3557 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3558 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3559 } 3560 3561 static __inline void 3562 msk_rxput(struct msk_if_softc *sc_if) 3563 { 3564 struct msk_softc *sc; 3565 3566 sc = sc_if->msk_softc; 3567 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3568 bus_dmamap_sync( 3569 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3570 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3571 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3572 else 3573 bus_dmamap_sync( 3574 sc_if->msk_cdata.msk_rx_ring_tag, 3575 sc_if->msk_cdata.msk_rx_ring_map, 3576 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3577 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3578 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3579 } 3580 3581 static int 3582 msk_handle_events(struct msk_softc *sc) 3583 { 3584 struct msk_if_softc *sc_if; 3585 int rxput[2]; 3586 struct msk_stat_desc *sd; 3587 uint32_t control, status; 3588 int cons, len, port, rxprog; 3589 3590 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3591 return (0); 3592 3593 /* Sync status LEs. */ 3594 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3595 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3596 3597 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3598 rxprog = 0; 3599 cons = sc->msk_stat_cons; 3600 for (;;) { 3601 sd = &sc->msk_stat_ring[cons]; 3602 control = le32toh(sd->msk_control); 3603 if ((control & HW_OWNER) == 0) 3604 break; 3605 control &= ~HW_OWNER; 3606 sd->msk_control = htole32(control); 3607 status = le32toh(sd->msk_status); 3608 len = control & STLE_LEN_MASK; 3609 port = (control >> 16) & 0x01; 3610 sc_if = sc->msk_if[port]; 3611 if (sc_if == NULL) { 3612 device_printf(sc->msk_dev, "invalid port opcode " 3613 "0x%08x\n", control & STLE_OP_MASK); 3614 continue; 3615 } 3616 3617 switch (control & STLE_OP_MASK) { 3618 case OP_RXVLAN: 3619 sc_if->msk_vtag = ntohs(len); 3620 break; 3621 case OP_RXCHKSVLAN: 3622 sc_if->msk_vtag = ntohs(len); 3623 /* FALLTHROUGH */ 3624 case OP_RXCHKS: 3625 sc_if->msk_csum = status; 3626 break; 3627 case OP_RXSTAT: 3628 if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING)) 3629 break; 3630 if (sc_if->msk_framesize > 3631 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3632 msk_jumbo_rxeof(sc_if, status, control, len); 3633 else 3634 msk_rxeof(sc_if, status, control, len); 3635 rxprog++; 3636 /* 3637 * Because there is no way to sync single Rx LE 3638 * put the DMA sync operation off until the end of 3639 * event processing. 3640 */ 3641 rxput[port]++; 3642 /* Update prefetch unit if we've passed water mark. */ 3643 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3644 msk_rxput(sc_if); 3645 rxput[port] = 0; 3646 } 3647 break; 3648 case OP_TXINDEXLE: 3649 if (sc->msk_if[MSK_PORT_A] != NULL) 3650 msk_txeof(sc->msk_if[MSK_PORT_A], 3651 status & STLE_TXA1_MSKL); 3652 if (sc->msk_if[MSK_PORT_B] != NULL) 3653 msk_txeof(sc->msk_if[MSK_PORT_B], 3654 ((status & STLE_TXA2_MSKL) >> 3655 STLE_TXA2_SHIFTL) | 3656 ((len & STLE_TXA2_MSKH) << 3657 STLE_TXA2_SHIFTH)); 3658 break; 3659 default: 3660 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3661 control & STLE_OP_MASK); 3662 break; 3663 } 3664 MSK_INC(cons, sc->msk_stat_count); 3665 if (rxprog > sc->msk_process_limit) 3666 break; 3667 } 3668 3669 sc->msk_stat_cons = cons; 3670 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3672 3673 if (rxput[MSK_PORT_A] > 0) 3674 msk_rxput(sc->msk_if[MSK_PORT_A]); 3675 if (rxput[MSK_PORT_B] > 0) 3676 msk_rxput(sc->msk_if[MSK_PORT_B]); 3677 3678 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3679 } 3680 3681 static void 3682 msk_intr(void *xsc) 3683 { 3684 struct msk_softc *sc; 3685 struct msk_if_softc *sc_if0, *sc_if1; 3686 struct ifnet *ifp0, *ifp1; 3687 uint32_t status; 3688 int domore; 3689 3690 sc = xsc; 3691 MSK_LOCK(sc); 3692 3693 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3694 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3695 if (status == 0 || status == 0xffffffff || 3696 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3697 (status & sc->msk_intrmask) == 0) { 3698 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3699 MSK_UNLOCK(sc); 3700 return; 3701 } 3702 3703 sc_if0 = sc->msk_if[MSK_PORT_A]; 3704 sc_if1 = sc->msk_if[MSK_PORT_B]; 3705 ifp0 = ifp1 = NULL; 3706 if (sc_if0 != NULL) 3707 ifp0 = sc_if0->msk_ifp; 3708 if (sc_if1 != NULL) 3709 ifp1 = sc_if1->msk_ifp; 3710 3711 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3712 msk_intr_phy(sc_if0); 3713 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3714 msk_intr_phy(sc_if1); 3715 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3716 msk_intr_gmac(sc_if0); 3717 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3718 msk_intr_gmac(sc_if1); 3719 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3720 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3721 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3722 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3723 CSR_READ_4(sc, B0_IMSK); 3724 } 3725 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3726 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3727 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3728 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3729 CSR_READ_4(sc, B0_IMSK); 3730 } 3731 if ((status & Y2_IS_HW_ERR) != 0) 3732 msk_intr_hwerr(sc); 3733 3734 domore = msk_handle_events(sc); 3735 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3736 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3737 3738 /* Reenable interrupts. */ 3739 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3740 3741 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3742 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3743 msk_start_locked(ifp0); 3744 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3745 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3746 msk_start_locked(ifp1); 3747 3748 MSK_UNLOCK(sc); 3749 } 3750 3751 static void 3752 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3753 { 3754 struct msk_softc *sc; 3755 struct ifnet *ifp; 3756 3757 ifp = sc_if->msk_ifp; 3758 sc = sc_if->msk_softc; 3759 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX && 3760 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) || 3761 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) { 3762 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3763 TX_STFW_ENA); 3764 } else { 3765 if (ifp->if_mtu > ETHERMTU) { 3766 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3767 CSR_WRITE_4(sc, 3768 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3769 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3770 /* Disable Store & Forward mode for Tx. */ 3771 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3772 TX_STFW_DIS); 3773 } else { 3774 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3775 TX_STFW_ENA); 3776 } 3777 } 3778 } 3779 3780 static void 3781 msk_init(void *xsc) 3782 { 3783 struct msk_if_softc *sc_if = xsc; 3784 3785 MSK_IF_LOCK(sc_if); 3786 msk_init_locked(sc_if); 3787 MSK_IF_UNLOCK(sc_if); 3788 } 3789 3790 static void 3791 msk_init_locked(struct msk_if_softc *sc_if) 3792 { 3793 struct msk_softc *sc; 3794 struct ifnet *ifp; 3795 struct mii_data *mii; 3796 uint8_t *eaddr; 3797 uint16_t gmac; 3798 uint32_t reg; 3799 int error; 3800 3801 MSK_IF_LOCK_ASSERT(sc_if); 3802 3803 ifp = sc_if->msk_ifp; 3804 sc = sc_if->msk_softc; 3805 mii = device_get_softc(sc_if->msk_miibus); 3806 3807 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3808 return; 3809 3810 error = 0; 3811 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3812 msk_stop(sc_if); 3813 3814 if (ifp->if_mtu < ETHERMTU) 3815 sc_if->msk_framesize = ETHERMTU; 3816 else 3817 sc_if->msk_framesize = ifp->if_mtu; 3818 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3819 if (ifp->if_mtu > ETHERMTU && 3820 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3821 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3822 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3823 } 3824 3825 /* GMAC Control reset. */ 3826 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3827 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3828 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3829 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3830 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 3831 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3832 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3833 GMC_BYP_RETR_ON); 3834 3835 /* 3836 * Initialize GMAC first such that speed/duplex/flow-control 3837 * parameters are renegotiated when interface is brought up. 3838 */ 3839 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3840 3841 /* Dummy read the Interrupt Source Register. */ 3842 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3843 3844 /* Clear MIB stats. */ 3845 msk_stats_clear(sc_if); 3846 3847 /* Disable FCS. */ 3848 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3849 3850 /* Setup Transmit Control Register. */ 3851 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3852 3853 /* Setup Transmit Flow Control Register. */ 3854 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3855 3856 /* Setup Transmit Parameter Register. */ 3857 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3858 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3859 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3860 3861 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3862 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3863 3864 if (ifp->if_mtu > ETHERMTU) 3865 gmac |= GM_SMOD_JUMBO_ENA; 3866 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3867 3868 /* Set station address. */ 3869 eaddr = IF_LLADDR(ifp); 3870 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3871 eaddr[0] | (eaddr[1] << 8)); 3872 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3873 eaddr[2] | (eaddr[3] << 8)); 3874 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3875 eaddr[4] | (eaddr[5] << 8)); 3876 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3877 eaddr[0] | (eaddr[1] << 8)); 3878 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3879 eaddr[2] | (eaddr[3] << 8)); 3880 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3881 eaddr[4] | (eaddr[5] << 8)); 3882 3883 /* Disable interrupts for counter overflows. */ 3884 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3885 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3886 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3887 3888 /* Configure Rx MAC FIFO. */ 3889 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3890 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3891 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3892 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3893 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3894 reg |= GMF_RX_OVER_ON; 3895 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3896 3897 /* Set receive filter. */ 3898 msk_rxfilter(sc_if); 3899 3900 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3901 /* Clear flush mask - HW bug. */ 3902 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3903 } else { 3904 /* Flush Rx MAC FIFO on any flow control or error. */ 3905 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3906 GMR_FS_ANY_ERR); 3907 } 3908 3909 /* 3910 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3911 * due to hardware hang on receipt of pause frames. 3912 */ 3913 reg = RX_GMF_FL_THR_DEF + 1; 3914 /* Another magic for Yukon FE+ - From Linux. */ 3915 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3916 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3917 reg = 0x178; 3918 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3919 3920 /* Configure Tx MAC FIFO. */ 3921 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3922 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3923 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3924 3925 /* Configure hardware VLAN tag insertion/stripping. */ 3926 msk_setvlan(sc_if, ifp); 3927 3928 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3929 /* Set Rx Pause threshold. */ 3930 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3931 MSK_ECU_LLPP); 3932 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3933 MSK_ECU_ULPP); 3934 /* Configure store-and-forward for Tx. */ 3935 msk_set_tx_stfwd(sc_if); 3936 } 3937 3938 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3939 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3940 /* Disable dynamic watermark - from Linux. */ 3941 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3942 reg &= ~0x03; 3943 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3944 } 3945 3946 /* 3947 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3948 * arbiter as we don't use Sync Tx queue. 3949 */ 3950 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3951 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3952 /* Enable the RAM Interface Arbiter. */ 3953 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3954 3955 /* Setup RAM buffer. */ 3956 msk_set_rambuffer(sc_if); 3957 3958 /* Disable Tx sync Queue. */ 3959 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3960 3961 /* Setup Tx Queue Bus Memory Interface. */ 3962 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3963 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3964 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3965 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3966 switch (sc->msk_hw_id) { 3967 case CHIP_ID_YUKON_EC_U: 3968 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3969 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3970 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3971 MSK_ECU_TXFF_LEV); 3972 } 3973 break; 3974 case CHIP_ID_YUKON_EX: 3975 /* 3976 * Yukon Extreme seems to have silicon bug for 3977 * automatic Tx checksum calculation capability. 3978 */ 3979 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3980 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3981 F_TX_CHK_AUTO_OFF); 3982 break; 3983 } 3984 3985 /* Setup Rx Queue Bus Memory Interface. */ 3986 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3987 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3988 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3989 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3990 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3991 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3992 /* MAC Rx RAM Read is controlled by hardware. */ 3993 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3994 } 3995 3996 msk_set_prefetch(sc, sc_if->msk_txq, 3997 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3998 msk_init_tx_ring(sc_if); 3999 4000 /* Disable Rx checksum offload and RSS hash. */ 4001 reg = BMU_DIS_RX_RSS_HASH; 4002 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 4003 (ifp->if_capenable & IFCAP_RXCSUM) != 0) 4004 reg |= BMU_ENA_RX_CHKSUM; 4005 else 4006 reg |= BMU_DIS_RX_CHKSUM; 4007 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 4008 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 4009 msk_set_prefetch(sc, sc_if->msk_rxq, 4010 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 4011 MSK_JUMBO_RX_RING_CNT - 1); 4012 error = msk_init_jumbo_rx_ring(sc_if); 4013 } else { 4014 msk_set_prefetch(sc, sc_if->msk_rxq, 4015 sc_if->msk_rdata.msk_rx_ring_paddr, 4016 MSK_RX_RING_CNT - 1); 4017 error = msk_init_rx_ring(sc_if); 4018 } 4019 if (error != 0) { 4020 device_printf(sc_if->msk_if_dev, 4021 "initialization failed: no memory for Rx buffers\n"); 4022 msk_stop(sc_if); 4023 return; 4024 } 4025 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 4026 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 4027 /* Disable flushing of non-ASF packets. */ 4028 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 4029 GMF_RX_MACSEC_FLUSH_OFF); 4030 } 4031 4032 /* Configure interrupt handling. */ 4033 if (sc_if->msk_port == MSK_PORT_A) { 4034 sc->msk_intrmask |= Y2_IS_PORT_A; 4035 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 4036 } else { 4037 sc->msk_intrmask |= Y2_IS_PORT_B; 4038 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 4039 } 4040 /* Configure IRQ moderation mask. */ 4041 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 4042 if (sc->msk_int_holdoff > 0) { 4043 /* Configure initial IRQ moderation timer value. */ 4044 CSR_WRITE_4(sc, B2_IRQM_INI, 4045 MSK_USECS(sc, sc->msk_int_holdoff)); 4046 CSR_WRITE_4(sc, B2_IRQM_VAL, 4047 MSK_USECS(sc, sc->msk_int_holdoff)); 4048 /* Start IRQ moderation. */ 4049 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 4050 } 4051 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4052 CSR_READ_4(sc, B0_HWE_IMSK); 4053 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4054 CSR_READ_4(sc, B0_IMSK); 4055 4056 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4057 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4058 4059 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4060 mii_mediachg(mii); 4061 4062 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 4063 } 4064 4065 static void 4066 msk_set_rambuffer(struct msk_if_softc *sc_if) 4067 { 4068 struct msk_softc *sc; 4069 int ltpp, utpp; 4070 4071 sc = sc_if->msk_softc; 4072 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 4073 return; 4074 4075 /* Setup Rx Queue. */ 4076 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 4077 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 4078 sc->msk_rxqstart[sc_if->msk_port] / 8); 4079 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 4080 sc->msk_rxqend[sc_if->msk_port] / 8); 4081 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 4082 sc->msk_rxqstart[sc_if->msk_port] / 8); 4083 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 4084 sc->msk_rxqstart[sc_if->msk_port] / 8); 4085 4086 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4087 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 4088 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4089 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 4090 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 4091 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4092 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4093 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4094 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4095 4096 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4097 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4098 4099 /* Setup Tx Queue. */ 4100 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4101 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4102 sc->msk_txqstart[sc_if->msk_port] / 8); 4103 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4104 sc->msk_txqend[sc_if->msk_port] / 8); 4105 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4106 sc->msk_txqstart[sc_if->msk_port] / 8); 4107 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4108 sc->msk_txqstart[sc_if->msk_port] / 8); 4109 /* Enable Store & Forward for Tx side. */ 4110 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4111 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4112 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4113 } 4114 4115 static void 4116 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4117 uint32_t count) 4118 { 4119 4120 /* Reset the prefetch unit. */ 4121 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4122 PREF_UNIT_RST_SET); 4123 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4124 PREF_UNIT_RST_CLR); 4125 /* Set LE base address. */ 4126 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4127 MSK_ADDR_LO(addr)); 4128 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4129 MSK_ADDR_HI(addr)); 4130 /* Set the list last index. */ 4131 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4132 count); 4133 /* Turn on prefetch unit. */ 4134 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4135 PREF_UNIT_OP_ON); 4136 /* Dummy read to ensure write. */ 4137 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4138 } 4139 4140 static void 4141 msk_stop(struct msk_if_softc *sc_if) 4142 { 4143 struct msk_softc *sc; 4144 struct msk_txdesc *txd; 4145 struct msk_rxdesc *rxd; 4146 struct msk_rxdesc *jrxd; 4147 struct ifnet *ifp; 4148 uint32_t val; 4149 int i; 4150 4151 MSK_IF_LOCK_ASSERT(sc_if); 4152 sc = sc_if->msk_softc; 4153 ifp = sc_if->msk_ifp; 4154 4155 callout_stop(&sc_if->msk_tick_ch); 4156 sc_if->msk_watchdog_timer = 0; 4157 4158 /* Disable interrupts. */ 4159 if (sc_if->msk_port == MSK_PORT_A) { 4160 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4161 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4162 } else { 4163 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4164 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4165 } 4166 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4167 CSR_READ_4(sc, B0_HWE_IMSK); 4168 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4169 CSR_READ_4(sc, B0_IMSK); 4170 4171 /* Disable Tx/Rx MAC. */ 4172 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4173 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4174 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4175 /* Read again to ensure writing. */ 4176 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4177 /* Update stats and clear counters. */ 4178 msk_stats_update(sc_if); 4179 4180 /* Stop Tx BMU. */ 4181 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4182 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4183 for (i = 0; i < MSK_TIMEOUT; i++) { 4184 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4185 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4186 BMU_STOP); 4187 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4188 } else 4189 break; 4190 DELAY(1); 4191 } 4192 if (i == MSK_TIMEOUT) 4193 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4194 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4195 RB_RST_SET | RB_DIS_OP_MD); 4196 4197 /* Disable all GMAC interrupt. */ 4198 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4199 /* Disable PHY interrupt. */ 4200 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4201 4202 /* Disable the RAM Interface Arbiter. */ 4203 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4204 4205 /* Reset the PCI FIFO of the async Tx queue */ 4206 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4207 BMU_RST_SET | BMU_FIFO_RST); 4208 4209 /* Reset the Tx prefetch units. */ 4210 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4211 PREF_UNIT_RST_SET); 4212 4213 /* Reset the RAM Buffer async Tx queue. */ 4214 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4215 4216 /* Reset Tx MAC FIFO. */ 4217 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4218 /* Set Pause Off. */ 4219 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4220 4221 /* 4222 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4223 * reach the end of packet and since we can't make sure that we have 4224 * incoming data, we must reset the BMU while it is not during a DMA 4225 * transfer. Since it is possible that the Rx path is still active, 4226 * the Rx RAM buffer will be stopped first, so any possible incoming 4227 * data will not trigger a DMA. After the RAM buffer is stopped, the 4228 * BMU is polled until any DMA in progress is ended and only then it 4229 * will be reset. 4230 */ 4231 4232 /* Disable the RAM Buffer receive queue. */ 4233 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4234 for (i = 0; i < MSK_TIMEOUT; i++) { 4235 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4236 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4237 break; 4238 DELAY(1); 4239 } 4240 if (i == MSK_TIMEOUT) 4241 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4242 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4243 BMU_RST_SET | BMU_FIFO_RST); 4244 /* Reset the Rx prefetch unit. */ 4245 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4246 PREF_UNIT_RST_SET); 4247 /* Reset the RAM Buffer receive queue. */ 4248 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4249 /* Reset Rx MAC FIFO. */ 4250 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4251 4252 /* Free Rx and Tx mbufs still in the queues. */ 4253 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4254 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4255 if (rxd->rx_m != NULL) { 4256 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4257 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4258 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4259 rxd->rx_dmamap); 4260 m_freem(rxd->rx_m); 4261 rxd->rx_m = NULL; 4262 } 4263 } 4264 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4265 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4266 if (jrxd->rx_m != NULL) { 4267 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4268 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4269 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4270 jrxd->rx_dmamap); 4271 m_freem(jrxd->rx_m); 4272 jrxd->rx_m = NULL; 4273 } 4274 } 4275 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4276 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4277 if (txd->tx_m != NULL) { 4278 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4279 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4280 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4281 txd->tx_dmamap); 4282 m_freem(txd->tx_m); 4283 txd->tx_m = NULL; 4284 } 4285 } 4286 4287 /* 4288 * Mark the interface down. 4289 */ 4290 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4291 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4292 } 4293 4294 /* 4295 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4296 * counter clears high 16 bits of the counter such that accessing 4297 * lower 16 bits should be the last operation. 4298 */ 4299 #define MSK_READ_MIB32(x, y) \ 4300 ((((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4301 (uint32_t)GMAC_READ_2(sc, x, y)) 4302 #define MSK_READ_MIB64(x, y) \ 4303 ((((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4304 (uint64_t)MSK_READ_MIB32(x, y)) 4305 4306 static void 4307 msk_stats_clear(struct msk_if_softc *sc_if) 4308 { 4309 struct msk_softc *sc; 4310 uint16_t gmac; 4311 int i; 4312 4313 MSK_IF_LOCK_ASSERT(sc_if); 4314 4315 sc = sc_if->msk_softc; 4316 /* Set MIB Clear Counter Mode. */ 4317 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4318 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4319 /* Read all MIB Counters with Clear Mode set. */ 4320 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4321 (void)MSK_READ_MIB32(sc_if->msk_port, i); 4322 /* Clear MIB Clear Counter Mode. */ 4323 gmac &= ~GM_PAR_MIB_CLR; 4324 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4325 } 4326 4327 static void 4328 msk_stats_update(struct msk_if_softc *sc_if) 4329 { 4330 struct msk_softc *sc; 4331 struct ifnet *ifp; 4332 struct msk_hw_stats *stats; 4333 uint16_t gmac; 4334 4335 MSK_IF_LOCK_ASSERT(sc_if); 4336 4337 ifp = sc_if->msk_ifp; 4338 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4339 return; 4340 sc = sc_if->msk_softc; 4341 stats = &sc_if->msk_stats; 4342 /* Set MIB Clear Counter Mode. */ 4343 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4344 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4345 4346 /* Rx stats. */ 4347 stats->rx_ucast_frames += 4348 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4349 stats->rx_bcast_frames += 4350 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4351 stats->rx_pause_frames += 4352 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4353 stats->rx_mcast_frames += 4354 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4355 stats->rx_crc_errs += 4356 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4357 stats->rx_good_octets += 4358 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4359 stats->rx_bad_octets += 4360 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4361 stats->rx_runts += 4362 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4363 stats->rx_runt_errs += 4364 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4365 stats->rx_pkts_64 += 4366 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4367 stats->rx_pkts_65_127 += 4368 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4369 stats->rx_pkts_128_255 += 4370 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4371 stats->rx_pkts_256_511 += 4372 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4373 stats->rx_pkts_512_1023 += 4374 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4375 stats->rx_pkts_1024_1518 += 4376 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4377 stats->rx_pkts_1519_max += 4378 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4379 stats->rx_pkts_too_long += 4380 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4381 stats->rx_pkts_jabbers += 4382 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4383 stats->rx_fifo_oflows += 4384 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4385 4386 /* Tx stats. */ 4387 stats->tx_ucast_frames += 4388 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4389 stats->tx_bcast_frames += 4390 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4391 stats->tx_pause_frames += 4392 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4393 stats->tx_mcast_frames += 4394 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4395 stats->tx_octets += 4396 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4397 stats->tx_pkts_64 += 4398 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4399 stats->tx_pkts_65_127 += 4400 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4401 stats->tx_pkts_128_255 += 4402 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4403 stats->tx_pkts_256_511 += 4404 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4405 stats->tx_pkts_512_1023 += 4406 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4407 stats->tx_pkts_1024_1518 += 4408 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4409 stats->tx_pkts_1519_max += 4410 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4411 stats->tx_colls += 4412 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4413 stats->tx_late_colls += 4414 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4415 stats->tx_excess_colls += 4416 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4417 stats->tx_multi_colls += 4418 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4419 stats->tx_single_colls += 4420 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4421 stats->tx_underflows += 4422 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4423 /* Clear MIB Clear Counter Mode. */ 4424 gmac &= ~GM_PAR_MIB_CLR; 4425 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4426 } 4427 4428 static int 4429 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4430 { 4431 struct msk_softc *sc; 4432 struct msk_if_softc *sc_if; 4433 uint32_t result, *stat; 4434 int off; 4435 4436 sc_if = (struct msk_if_softc *)arg1; 4437 sc = sc_if->msk_softc; 4438 off = arg2; 4439 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4440 4441 MSK_IF_LOCK(sc_if); 4442 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4443 result += *stat; 4444 MSK_IF_UNLOCK(sc_if); 4445 4446 return (sysctl_handle_int(oidp, &result, 0, req)); 4447 } 4448 4449 static int 4450 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4451 { 4452 struct msk_softc *sc; 4453 struct msk_if_softc *sc_if; 4454 uint64_t result, *stat; 4455 int off; 4456 4457 sc_if = (struct msk_if_softc *)arg1; 4458 sc = sc_if->msk_softc; 4459 off = arg2; 4460 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4461 4462 MSK_IF_LOCK(sc_if); 4463 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4464 result += *stat; 4465 MSK_IF_UNLOCK(sc_if); 4466 4467 return (sysctl_handle_64(oidp, &result, 0, req)); 4468 } 4469 4470 #undef MSK_READ_MIB32 4471 #undef MSK_READ_MIB64 4472 4473 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4474 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \ 4475 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \ 4476 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4477 "IU", d) 4478 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4479 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \ 4480 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \ 4481 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4482 "QU", d) 4483 4484 static void 4485 msk_sysctl_node(struct msk_if_softc *sc_if) 4486 { 4487 struct sysctl_ctx_list *ctx; 4488 struct sysctl_oid_list *child, *schild; 4489 struct sysctl_oid *tree; 4490 4491 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4492 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4493 4494 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 4495 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK Statistics"); 4496 schild = SYSCTL_CHILDREN(tree); 4497 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", 4498 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK RX Statistics"); 4499 child = SYSCTL_CHILDREN(tree); 4500 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4501 child, rx_ucast_frames, "Good unicast frames"); 4502 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4503 child, rx_bcast_frames, "Good broadcast frames"); 4504 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4505 child, rx_pause_frames, "Pause frames"); 4506 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4507 child, rx_mcast_frames, "Multicast frames"); 4508 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4509 child, rx_crc_errs, "CRC errors"); 4510 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4511 child, rx_good_octets, "Good octets"); 4512 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4513 child, rx_bad_octets, "Bad octets"); 4514 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4515 child, rx_pkts_64, "64 bytes frames"); 4516 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4517 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4518 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4519 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4520 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4521 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4522 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4523 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4524 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4525 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4526 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4527 child, rx_pkts_1519_max, "1519 to max frames"); 4528 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4529 child, rx_pkts_too_long, "frames too long"); 4530 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4531 child, rx_pkts_jabbers, "Jabber errors"); 4532 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4533 child, rx_fifo_oflows, "FIFO overflows"); 4534 4535 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", 4536 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK TX Statistics"); 4537 child = SYSCTL_CHILDREN(tree); 4538 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4539 child, tx_ucast_frames, "Unicast frames"); 4540 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4541 child, tx_bcast_frames, "Broadcast frames"); 4542 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4543 child, tx_pause_frames, "Pause frames"); 4544 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4545 child, tx_mcast_frames, "Multicast frames"); 4546 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4547 child, tx_octets, "Octets"); 4548 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4549 child, tx_pkts_64, "64 bytes frames"); 4550 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4551 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4552 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4553 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4554 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4555 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4556 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4557 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4558 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4559 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4560 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4561 child, tx_pkts_1519_max, "1519 to max frames"); 4562 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4563 child, tx_colls, "Collisions"); 4564 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4565 child, tx_late_colls, "Late collisions"); 4566 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4567 child, tx_excess_colls, "Excessive collisions"); 4568 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4569 child, tx_multi_colls, "Multiple collisions"); 4570 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4571 child, tx_single_colls, "Single collisions"); 4572 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4573 child, tx_underflows, "FIFO underflows"); 4574 } 4575 4576 #undef MSK_SYSCTL_STAT32 4577 #undef MSK_SYSCTL_STAT64 4578 4579 static int 4580 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4581 { 4582 int error, value; 4583 4584 if (!arg1) 4585 return (EINVAL); 4586 value = *(int *)arg1; 4587 error = sysctl_handle_int(oidp, &value, 0, req); 4588 if (error || !req->newptr) 4589 return (error); 4590 if (value < low || value > high) 4591 return (EINVAL); 4592 *(int *)arg1 = value; 4593 4594 return (0); 4595 } 4596 4597 static int 4598 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4599 { 4600 4601 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4602 MSK_PROC_MAX)); 4603 }
Cache object: 5b8e9c4e25401967b16afc3a6621f4d4
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