The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/mvme/memcreg.h

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    1 /*      $NetBSD: memcreg.h,v 1.4 2008/04/28 20:23:54 martin Exp $       */
    2 
    3 /*-
    4  * Copyright (c) 2000, 2002 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Steve C. Woodford.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   29  * POSSIBILITY OF SUCH DAMAGE.
   30  */
   31 
   32 /*
   33  * Register definitions for the MEMECC and MEMC040 devices.
   34  */
   35 #ifndef _MVME_MEMCREG_H
   36 #define _MVME_MEMCREG_H
   37 
   38 /*
   39  * Size, in bytes, of the memory controller's register set
   40  * (Actually, the MEMC040's register set is only 0x20 bytes in size, but
   41  * we go with the larger of the two).
   42  */
   43 #define MEMC_REGSIZE    0x80
   44 
   45 /* Both memory controllers share some registers in common */
   46 #define MEMC_REG_CHIP_ID                0x00
   47 #define  MEMC_CHIP_ID_MEMC040           0x80    /* It's a MEMC040 */
   48 #define  MEMC_CHIP_ID_MEMECC            0x81    /* It's a MEMECC */
   49 
   50 /* Revision of the ASIC */
   51 #define MEMC_REG_CHIP_REVISION          0x04
   52 
   53 /* Configuration of the memory block controlled by this ASIC */
   54 #define MEMC_REG_MEMORY_CONFIG          0x08
   55 #define  MEMC_MEMORY_CONFIG_2_BYTES(x)  (0x400000 << ((x) & 0x07))
   56 #define  MEMC_MEMORY_CONFIG_2_MB(x)     (4 << ((x) & 0x07))
   57 #define  MEMC040_MEMORY_CONFIG_EXTPEN   (1u << 3)  /* External parity enabled */
   58 #define  MEMC040_MEMORY_CONFIG_WPB      (1u << 4)  /* Write Per Bit mode */
   59 #define  MEMC_MEMORY_CONFIG_FSTRD       (1u << 5)  /* Fast RAM Read enabled */
   60 
   61 /* Where, in the CPU's address space, does this memory appear? */
   62 #define MEMC_REG_BASE_ADDRESS_HI        0x14
   63 #define MEMC_REG_BASE_ADDRESS_LO        0x18
   64 #define  MEMC_BASE_ADDRESS(hi,lo)       (((hi) << 24) | (((lo) & 0xc0) << 22))
   65 
   66 /* Tells the memory controller what the board's Bus Clock frequency is */
   67 #define MEMC_REG_BUS_CLOCK              0x1c
   68 
   69 
   70 /* Register offsets and definitions for the Parity Memory Controller */
   71 #define MEMC040_REG_ALT_STATUS          0x0c    /* Not used */
   72 #define MEMC040_REG_ALT_CONTROL         0x10    /* Not used */
   73 
   74 /* Memory Control Register */
   75 #define MEMC040_REG_RAM_CONTROL         0x18
   76 #define  MEMC040_RAM_CONTROL_RAMEN      (1u << 0)
   77 #define  MEMC040_RAM_CONTROL_PAREN      (1u << 1)
   78 #define  MEMC040_RAM_CONTROL_PARINT     (1u << 2)
   79 #define  MEMC040_RAM_CONTROL_WWP        (1u << 3)
   80 #define  MEMC040_RAM_CONTROL_SWAIT      (1u << 4)
   81 #define  MEMC040_RAM_CONTROL_DMCTL      (1u << 5)
   82 
   83 
   84 /* Register offsets and definitions for the ECC Memory Controller */
   85 #define MEMECC_REG_DRAM_CONTROL         0x18
   86 #define  MEMECC_DRAM_CONTROL_RAMEN      (1u << 0)
   87 #define  MEMECC_DRAM_CONTROL_NCEBEN     (1u << 1)
   88 #define  MEMECC_DRAM_CONTROL_NCEIEN     (1u << 2)
   89 #define  MEMECC_DRAM_CONTROL_RWB3       (1u << 3)
   90 #define  MEMECC_DRAM_CONTROL_SWAIT      (1u << 4)
   91 #define  MEMECC_DRAM_CONTROL_RWB5       (1u << 5)
   92 #define  MEMECC_DRAM_CONTROL_BAD22      (1u << 6)
   93 #define  MEMECC_DRAM_CONTROL_BAD23      (1u << 7)
   94 
   95 #define MEMECC_REG_DATA_CONTROL         0x20
   96 #define  MEMECC_DATA_CONTROL_RWCKB      (1u << 3)
   97 #define  MEMECC_DATA_CONTROL_ZFILL      (1u << 4)
   98 #define  MEMECC_DATA_CONTROL_DERC       (1u << 5)
   99 
  100 #define MEMECC_REG_SCRUB_CONTROL        0x24
  101 #define  MEMECC_SCRUB_CONTROL_IDIS      (1u << 0)
  102 #define  MEMECC_SCRUB_CONTROL_SBEIEN    (1u << 1)
  103 #define  MEMECC_SCRUB_CONTROL_SCRBEN    (1u << 3)
  104 #define  MEMECC_SCRUB_CONTROL_SCRB      (1u << 4)
  105 #define  MEMECC_SCRUB_CONTROL_HITDIS    (1u << 5)
  106 #define  MEMECC_SCRUB_CONTROL_RADATA    (1u << 6)
  107 #define  MEMECC_SCRUB_CONTROL_RACODE    (1u << 7)
  108 
  109 #define MEMECC_REG_SCRUB_PERIOD_HI      0x28
  110 #define  MEMECC_SCRUB_PERIOD_HI(secs)   (((secs) / 2) >> 8)
  111 #define MEMECC_REG_SCRUB_PERIOD_LO      0x2c
  112 #define  MEMECC_SCRUB_PERIOD_LO(secs)   (((secs) / 2) & 0xffu)
  113 
  114 #define MEMECC_REG_CHIP_PRESCALE        0x30
  115 
  116 #define MEMECC_REG_SCRUB_TIME_ONOFF     0x34
  117 #define  MEMECC_SCRUB_TIME_ONOFF_MASK   0x07u
  118 #define  MEMECC_SCRUB_TIME_OFF_0        0u
  119 #define  MEMECC_SCRUB_TIME_OFF_16       1u
  120 #define  MEMECC_SCRUB_TIME_OFF_32       2u
  121 #define  MEMECC_SCRUB_TIME_OFF_64       3u
  122 #define  MEMECC_SCRUB_TIME_OFF_128      4u
  123 #define  MEMECC_SCRUB_TIME_OFF_256      5u
  124 #define  MEMECC_SCRUB_TIME_OFF_512      6u
  125 #define  MEMECC_SCRUB_TIME_OFF_NEVER    7u
  126 #define  MEMECC_SCRUB_TIME_ON_1         (0u << 3)
  127 #define  MEMECC_SCRUB_TIME_ON_16        (1u << 3)
  128 #define  MEMECC_SCRUB_TIME_ON_32        (2u << 3)
  129 #define  MEMECC_SCRUB_TIME_ON_64        (3u << 3)
  130 #define  MEMECC_SCRUB_TIME_ON_128       (4u << 3)
  131 #define  MEMECC_SCRUB_TIME_ON_256       (5u << 3)
  132 #define  MEMECC_SCRUB_TIME_ON_512       (6u << 3)
  133 #define  MEMECC_SCRUB_TIME_ON_ALWAYS    (7u << 3)
  134 #define  MEMECC_SCRUB_TIME_SRDIS        (1u << 7)
  135 
  136 #define MEMECC_REG_SCRUB_PRESCALE_HI    0x38
  137 #define MEMECC_REG_SCRUB_PRESCALE_MID   0x3c
  138 #define MEMECC_REG_SCRUB_PRESCALE_LO    0x40
  139 
  140 #define MEMECC_REG_SCRUB_TIMER_HI       0x44
  141 #define MEMECC_REG_SCRUB_TIMER_LO       0x48
  142 
  143 #define MEMECC_REG_SCRUB_ADDR_CNTR_HIHI 0x4c
  144 #define MEMECC_REG_SCRUB_ADDR_CNTR_HI   0x50
  145 #define MEMECC_REG_SCRUB_ADDR_CNTR_MID  0x54
  146 #define MEMECC_REG_SCRUB_ADDR_CNTR_LO   0x58
  147 
  148 #define MEMECC_REG_ERROR_LOGGER         0x5c
  149 #define  MEMECC_ERROR_LOGGER_MASK       0x7fu
  150 #define  MEMECC_ERROR_LOGGER_SBE        (1u << 0)
  151 #define  MEMECC_ERROR_LOGGER_MBE        (1u << 1)
  152 #define  MEMECC_ERROR_LOGGER_EALT       (1u << 3)
  153 #define  MEMECC_ERROR_LOGGER_ERA        (1u << 4)
  154 #define  MEMECC_ERROR_LOGGER_ESCRB      (1u << 5)
  155 #define  MEMECC_ERROR_LOGGER_ERD        (1u << 6)
  156 #define  MEMECC_ERROR_LOGGER_ERRLOG     (1u << 7)
  157 
  158 #define MEMECC_REG_ERROR_ADDRESS_HIHI   0x60
  159 #define MEMECC_REG_ERROR_ADDRESS_HI     0x64
  160 #define MEMECC_REG_ERROR_ADDRESS_MID    0x68
  161 #define MEMECC_REG_ERROR_ADDRESS_LO     0x6c
  162 
  163 #define MEMECC_REG_ERROR_SYNDROME       0x70
  164 
  165 #define MEMECC_REG_DEFAULTS1            0x74
  166 #define MEMECC_REG_DEFAULTS2            0x78
  167 
  168 #define MEMECC_REG_SDRAM_CONFIG         0x7c
  169 
  170 #endif  /* _MVME_MEMCREG_H */

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