Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/mvs/mvs.c
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1 /*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <vm/uma.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include "mvs.h" 47 48 #include <cam/cam.h> 49 #include <cam/cam_ccb.h> 50 #include <cam/cam_sim.h> 51 #include <cam/cam_xpt_sim.h> 52 #include <cam/cam_debug.h> 53 54 /* local prototypes */ 55 static int mvs_ch_init(device_t dev); 56 static int mvs_ch_deinit(device_t dev); 57 static int mvs_ch_suspend(device_t dev); 58 static int mvs_ch_resume(device_t dev); 59 static void mvs_dmainit(device_t dev); 60 static void mvs_dmasetupc_cb(void *xsc, 61 bus_dma_segment_t *segs, int nsegs, int error); 62 static void mvs_dmafini(device_t dev); 63 static void mvs_slotsalloc(device_t dev); 64 static void mvs_slotsfree(device_t dev); 65 static void mvs_setup_edma_queues(device_t dev); 66 static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode); 67 static void mvs_ch_pm(void *arg); 68 static void mvs_ch_intr_locked(void *data); 69 static void mvs_ch_intr(void *data); 70 static void mvs_reset(device_t dev); 71 static void mvs_softreset(device_t dev, union ccb *ccb); 72 73 static int mvs_sata_connect(struct mvs_channel *ch); 74 static int mvs_sata_phy_reset(device_t dev); 75 static int mvs_wait(device_t dev, u_int s, u_int c, int t); 76 static void mvs_tfd_read(device_t dev, union ccb *ccb); 77 static void mvs_tfd_write(device_t dev, union ccb *ccb); 78 static void mvs_legacy_intr(device_t dev, int poll); 79 static void mvs_crbq_intr(device_t dev); 80 static void mvs_begin_transaction(device_t dev, union ccb *ccb); 81 static void mvs_legacy_execute_transaction(struct mvs_slot *slot); 82 static void mvs_timeout(struct mvs_slot *slot); 83 static void mvs_dmasetprd(void *arg, 84 bus_dma_segment_t *segs, int nsegs, int error); 85 static void mvs_requeue_frozen(device_t dev); 86 static void mvs_execute_transaction(struct mvs_slot *slot); 87 static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et); 88 89 static void mvs_issue_recovery(device_t dev); 90 static void mvs_process_read_log(device_t dev, union ccb *ccb); 91 static void mvs_process_request_sense(device_t dev, union ccb *ccb); 92 93 static void mvsaction(struct cam_sim *sim, union ccb *ccb); 94 static void mvspoll(struct cam_sim *sim); 95 96 MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers"); 97 98 #define recovery_type spriv_field0 99 #define RECOVERY_NONE 0 100 #define RECOVERY_READ_LOG 1 101 #define RECOVERY_REQUEST_SENSE 2 102 #define recovery_slot spriv_field1 103 104 static int 105 mvs_ch_probe(device_t dev) 106 { 107 108 device_set_desc_copy(dev, "Marvell SATA channel"); 109 return (0); 110 } 111 112 static int 113 mvs_ch_attach(device_t dev) 114 { 115 struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev)); 116 struct mvs_channel *ch = device_get_softc(dev); 117 struct cam_devq *devq; 118 int rid, error, i, sata_rev = 0; 119 120 ch->dev = dev; 121 ch->unit = (intptr_t)device_get_ivars(dev); 122 ch->quirks = ctlr->quirks; 123 mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF); 124 resource_int_value(device_get_name(dev), 125 device_get_unit(dev), "pm_level", &ch->pm_level); 126 if (ch->pm_level > 3) 127 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 128 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 129 resource_int_value(device_get_name(dev), 130 device_get_unit(dev), "sata_rev", &sata_rev); 131 for (i = 0; i < 16; i++) { 132 ch->user[i].revision = sata_rev; 133 ch->user[i].mode = 0; 134 ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048; 135 ch->user[i].tags = MVS_MAX_SLOTS; 136 ch->curr[i] = ch->user[i]; 137 if (ch->pm_level) { 138 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 139 CTS_SATA_CAPS_H_APST | 140 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 141 } 142 ch->user[i].caps |= CTS_SATA_CAPS_H_AN; 143 } 144 rid = ch->unit; 145 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 146 &rid, RF_ACTIVE))) 147 return (ENXIO); 148 mvs_dmainit(dev); 149 mvs_slotsalloc(dev); 150 mvs_ch_init(dev); 151 mtx_lock(&ch->mtx); 152 rid = ATA_IRQ_RID; 153 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 154 &rid, RF_SHAREABLE | RF_ACTIVE))) { 155 device_printf(dev, "Unable to map interrupt\n"); 156 error = ENXIO; 157 goto err0; 158 } 159 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 160 mvs_ch_intr_locked, dev, &ch->ih))) { 161 device_printf(dev, "Unable to setup interrupt\n"); 162 error = ENXIO; 163 goto err1; 164 } 165 /* Create the device queue for our SIM. */ 166 devq = cam_simq_alloc(MVS_MAX_SLOTS - 1); 167 if (devq == NULL) { 168 device_printf(dev, "Unable to allocate simq\n"); 169 error = ENOMEM; 170 goto err1; 171 } 172 /* Construct SIM entry */ 173 ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch, 174 device_get_unit(dev), &ch->mtx, 175 2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1, 176 devq); 177 if (ch->sim == NULL) { 178 cam_simq_free(devq); 179 device_printf(dev, "unable to allocate sim\n"); 180 error = ENOMEM; 181 goto err1; 182 } 183 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 184 device_printf(dev, "unable to register xpt bus\n"); 185 error = ENXIO; 186 goto err2; 187 } 188 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 189 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 190 device_printf(dev, "unable to create path\n"); 191 error = ENXIO; 192 goto err3; 193 } 194 if (ch->pm_level > 3) { 195 callout_reset(&ch->pm_timer, 196 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 197 mvs_ch_pm, dev); 198 } 199 mtx_unlock(&ch->mtx); 200 return (0); 201 202 err3: 203 xpt_bus_deregister(cam_sim_path(ch->sim)); 204 err2: 205 cam_sim_free(ch->sim, /*free_devq*/TRUE); 206 err1: 207 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 208 err0: 209 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 210 mtx_unlock(&ch->mtx); 211 mtx_destroy(&ch->mtx); 212 return (error); 213 } 214 215 static int 216 mvs_ch_detach(device_t dev) 217 { 218 struct mvs_channel *ch = device_get_softc(dev); 219 220 mtx_lock(&ch->mtx); 221 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 222 /* Forget about reset. */ 223 if (ch->resetting) { 224 ch->resetting = 0; 225 xpt_release_simq(ch->sim, TRUE); 226 } 227 xpt_free_path(ch->path); 228 xpt_bus_deregister(cam_sim_path(ch->sim)); 229 cam_sim_free(ch->sim, /*free_devq*/TRUE); 230 mtx_unlock(&ch->mtx); 231 232 if (ch->pm_level > 3) 233 callout_drain(&ch->pm_timer); 234 callout_drain(&ch->reset_timer); 235 bus_teardown_intr(dev, ch->r_irq, ch->ih); 236 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 237 238 mvs_ch_deinit(dev); 239 mvs_slotsfree(dev); 240 mvs_dmafini(dev); 241 242 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 243 mtx_destroy(&ch->mtx); 244 return (0); 245 } 246 247 static int 248 mvs_ch_init(device_t dev) 249 { 250 struct mvs_channel *ch = device_get_softc(dev); 251 uint32_t reg; 252 253 /* Disable port interrupts */ 254 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 255 /* Stop EDMA */ 256 ch->curr_mode = MVS_EDMA_UNKNOWN; 257 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 258 /* Clear and configure FIS interrupts. */ 259 ATA_OUTL(ch->r_mem, SATA_FISIC, 0); 260 reg = ATA_INL(ch->r_mem, SATA_FISC); 261 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 262 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 263 reg = ATA_INL(ch->r_mem, SATA_FISIM); 264 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 265 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 266 /* Clear SATA error register. */ 267 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 268 /* Clear any outstanding error interrupts. */ 269 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 270 /* Unmask all error interrupts */ 271 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 272 return (0); 273 } 274 275 static int 276 mvs_ch_deinit(device_t dev) 277 { 278 struct mvs_channel *ch = device_get_softc(dev); 279 280 /* Stop EDMA */ 281 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 282 /* Disable port interrupts. */ 283 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 284 return (0); 285 } 286 287 static int 288 mvs_ch_suspend(device_t dev) 289 { 290 struct mvs_channel *ch = device_get_softc(dev); 291 292 mtx_lock(&ch->mtx); 293 xpt_freeze_simq(ch->sim, 1); 294 while (ch->oslots) 295 msleep(ch, &ch->mtx, PRIBIO, "mvssusp", hz/100); 296 /* Forget about reset. */ 297 if (ch->resetting) { 298 ch->resetting = 0; 299 callout_stop(&ch->reset_timer); 300 xpt_release_simq(ch->sim, TRUE); 301 } 302 mvs_ch_deinit(dev); 303 mtx_unlock(&ch->mtx); 304 return (0); 305 } 306 307 static int 308 mvs_ch_resume(device_t dev) 309 { 310 struct mvs_channel *ch = device_get_softc(dev); 311 312 mtx_lock(&ch->mtx); 313 mvs_ch_init(dev); 314 mvs_reset(dev); 315 xpt_release_simq(ch->sim, TRUE); 316 mtx_unlock(&ch->mtx); 317 return (0); 318 } 319 320 struct mvs_dc_cb_args { 321 bus_addr_t maddr; 322 int error; 323 }; 324 325 static void 326 mvs_dmainit(device_t dev) 327 { 328 struct mvs_channel *ch = device_get_softc(dev); 329 struct mvs_dc_cb_args dcba; 330 331 /* EDMA command request area. */ 332 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 333 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 334 NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE, 335 0, NULL, NULL, &ch->dma.workrq_tag)) 336 goto error; 337 if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0, 338 &ch->dma.workrq_map)) 339 goto error; 340 if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map, 341 ch->dma.workrq, MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) || 342 dcba.error) { 343 bus_dmamem_free(ch->dma.workrq_tag, 344 ch->dma.workrq, ch->dma.workrq_map); 345 goto error; 346 } 347 ch->dma.workrq_bus = dcba.maddr; 348 /* EDMA command response area. */ 349 if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0, 350 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 351 NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE, 352 0, NULL, NULL, &ch->dma.workrp_tag)) 353 goto error; 354 if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0, 355 &ch->dma.workrp_map)) 356 goto error; 357 if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map, 358 ch->dma.workrp, MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) || 359 dcba.error) { 360 bus_dmamem_free(ch->dma.workrp_tag, 361 ch->dma.workrp, ch->dma.workrp_map); 362 goto error; 363 } 364 ch->dma.workrp_bus = dcba.maddr; 365 /* Data area. */ 366 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX, 367 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 368 NULL, NULL, 369 MVS_SG_ENTRIES * PAGE_SIZE * MVS_MAX_SLOTS, 370 MVS_SG_ENTRIES, MVS_EPRD_MAX, 371 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 372 goto error; 373 } 374 return; 375 376 error: 377 device_printf(dev, "WARNING - DMA initialization failed\n"); 378 mvs_dmafini(dev); 379 } 380 381 static void 382 mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 383 { 384 struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc; 385 386 if (!(dcba->error = error)) 387 dcba->maddr = segs[0].ds_addr; 388 } 389 390 static void 391 mvs_dmafini(device_t dev) 392 { 393 struct mvs_channel *ch = device_get_softc(dev); 394 395 if (ch->dma.data_tag) { 396 bus_dma_tag_destroy(ch->dma.data_tag); 397 ch->dma.data_tag = NULL; 398 } 399 if (ch->dma.workrp_bus) { 400 bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map); 401 bus_dmamem_free(ch->dma.workrp_tag, 402 ch->dma.workrp, ch->dma.workrp_map); 403 ch->dma.workrp_bus = 0; 404 ch->dma.workrp_map = NULL; 405 ch->dma.workrp = NULL; 406 } 407 if (ch->dma.workrp_tag) { 408 bus_dma_tag_destroy(ch->dma.workrp_tag); 409 ch->dma.workrp_tag = NULL; 410 } 411 if (ch->dma.workrq_bus) { 412 bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map); 413 bus_dmamem_free(ch->dma.workrq_tag, 414 ch->dma.workrq, ch->dma.workrq_map); 415 ch->dma.workrq_bus = 0; 416 ch->dma.workrq_map = NULL; 417 ch->dma.workrq = NULL; 418 } 419 if (ch->dma.workrq_tag) { 420 bus_dma_tag_destroy(ch->dma.workrq_tag); 421 ch->dma.workrq_tag = NULL; 422 } 423 } 424 425 static void 426 mvs_slotsalloc(device_t dev) 427 { 428 struct mvs_channel *ch = device_get_softc(dev); 429 int i; 430 431 /* Alloc and setup command/dma slots */ 432 bzero(ch->slot, sizeof(ch->slot)); 433 for (i = 0; i < MVS_MAX_SLOTS; i++) { 434 struct mvs_slot *slot = &ch->slot[i]; 435 436 slot->dev = dev; 437 slot->slot = i; 438 slot->state = MVS_SLOT_EMPTY; 439 slot->ccb = NULL; 440 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 441 442 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 443 device_printf(ch->dev, "FAILURE - create data_map\n"); 444 } 445 } 446 447 static void 448 mvs_slotsfree(device_t dev) 449 { 450 struct mvs_channel *ch = device_get_softc(dev); 451 int i; 452 453 /* Free all dma slots */ 454 for (i = 0; i < MVS_MAX_SLOTS; i++) { 455 struct mvs_slot *slot = &ch->slot[i]; 456 457 callout_drain(&slot->timeout); 458 if (slot->dma.data_map) { 459 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 460 slot->dma.data_map = NULL; 461 } 462 } 463 } 464 465 static void 466 mvs_setup_edma_queues(device_t dev) 467 { 468 struct mvs_channel *ch = device_get_softc(dev); 469 uint64_t work; 470 471 /* Requests queue. */ 472 work = ch->dma.workrq_bus; 473 ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32); 474 ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff); 475 ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff); 476 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 477 BUS_DMASYNC_PREWRITE); 478 /* Reponses queue. */ 479 memset(ch->dma.workrp, 0xff, MVS_WORKRP_SIZE); 480 work = ch->dma.workrp_bus; 481 ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32); 482 ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff); 483 ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff); 484 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 485 BUS_DMASYNC_PREREAD); 486 ch->out_idx = 0; 487 ch->in_idx = 0; 488 } 489 490 static void 491 mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode) 492 { 493 struct mvs_channel *ch = device_get_softc(dev); 494 int timeout; 495 uint32_t ecfg, fcfg, hc, ltm, unkn; 496 497 if (mode == ch->curr_mode) 498 return; 499 /* If we are running, we should stop first. */ 500 if (ch->curr_mode != MVS_EDMA_OFF) { 501 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA); 502 timeout = 0; 503 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) { 504 DELAY(1000); 505 if (timeout++ > 1000) { 506 device_printf(dev, "stopping EDMA engine failed\n"); 507 break; 508 } 509 }; 510 } 511 ch->curr_mode = mode; 512 ch->fbs_enabled = 0; 513 ch->fake_busy = 0; 514 /* Report mode to controller. Needed for correct CCC operation. */ 515 MVS_EDMA(device_get_parent(dev), dev, mode); 516 /* Configure new mode. */ 517 ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN; 518 if (ch->pm_present) { 519 ecfg |= EDMA_CFG_EMASKRXPM; 520 if (ch->quirks & MVS_Q_GENIIE) { 521 ecfg |= EDMA_CFG_EEDMAFBS; 522 ch->fbs_enabled = 1; 523 } 524 } 525 if (ch->quirks & MVS_Q_GENI) 526 ecfg |= EDMA_CFG_ERDBSZ; 527 else if (ch->quirks & MVS_Q_GENII) 528 ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN; 529 if (ch->quirks & MVS_Q_CT) 530 ecfg |= EDMA_CFG_ECUTTHROUGHEN; 531 if (mode != MVS_EDMA_OFF) 532 ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN; 533 if (mode == MVS_EDMA_QUEUED) 534 ecfg |= EDMA_CFG_EQUE; 535 else if (mode == MVS_EDMA_NCQ) 536 ecfg |= EDMA_CFG_ESATANATVCMDQUE; 537 ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg); 538 mvs_setup_edma_queues(dev); 539 if (ch->quirks & MVS_Q_GENIIE) { 540 /* Configure FBS-related registers */ 541 fcfg = ATA_INL(ch->r_mem, SATA_FISC); 542 ltm = ATA_INL(ch->r_mem, SATA_LTM); 543 hc = ATA_INL(ch->r_mem, EDMA_HC); 544 if (ch->fbs_enabled) { 545 fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP; 546 if (mode == MVS_EDMA_NCQ) { 547 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 548 hc &= ~EDMA_IE_EDEVERR; 549 } else { 550 fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0; 551 hc |= EDMA_IE_EDEVERR; 552 } 553 ltm |= (1 << 8); 554 } else { 555 fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP; 556 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 557 hc |= EDMA_IE_EDEVERR; 558 ltm &= ~(1 << 8); 559 } 560 ATA_OUTL(ch->r_mem, SATA_FISC, fcfg); 561 ATA_OUTL(ch->r_mem, SATA_LTM, ltm); 562 ATA_OUTL(ch->r_mem, EDMA_HC, hc); 563 /* This is some magic, required to handle several DRQs 564 * with basic DMA. */ 565 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD); 566 if (mode == MVS_EDMA_OFF) 567 unkn |= 1; 568 else 569 unkn &= ~1; 570 ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn); 571 } 572 /* Run EDMA. */ 573 if (mode != MVS_EDMA_OFF) 574 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA); 575 } 576 577 devclass_t mvs_devclass; 578 devclass_t mvsch_devclass; 579 static device_method_t mvsch_methods[] = { 580 DEVMETHOD(device_probe, mvs_ch_probe), 581 DEVMETHOD(device_attach, mvs_ch_attach), 582 DEVMETHOD(device_detach, mvs_ch_detach), 583 DEVMETHOD(device_suspend, mvs_ch_suspend), 584 DEVMETHOD(device_resume, mvs_ch_resume), 585 { 0, 0 } 586 }; 587 static driver_t mvsch_driver = { 588 "mvsch", 589 mvsch_methods, 590 sizeof(struct mvs_channel) 591 }; 592 DRIVER_MODULE(mvsch, mvs, mvsch_driver, mvsch_devclass, 0, 0); 593 DRIVER_MODULE(mvsch, sata, mvsch_driver, mvsch_devclass, 0, 0); 594 595 static void 596 mvs_phy_check_events(device_t dev, u_int32_t serr) 597 { 598 struct mvs_channel *ch = device_get_softc(dev); 599 600 if (ch->pm_level == 0) { 601 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS); 602 union ccb *ccb; 603 604 if (bootverbose) { 605 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 606 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 607 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) { 608 device_printf(dev, "CONNECT requested\n"); 609 } else 610 device_printf(dev, "DISCONNECT requested\n"); 611 } 612 mvs_reset(dev); 613 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 614 return; 615 if (xpt_create_path(&ccb->ccb_h.path, NULL, 616 cam_sim_path(ch->sim), 617 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 618 xpt_free_ccb(ccb); 619 return; 620 } 621 xpt_rescan(ccb); 622 } 623 } 624 625 static void 626 mvs_notify_events(device_t dev) 627 { 628 struct mvs_channel *ch = device_get_softc(dev); 629 struct cam_path *dpath; 630 uint32_t fis; 631 int d; 632 633 /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */ 634 fis = ATA_INL(ch->r_mem, SATA_FISDW0); 635 if ((fis & 0x80ff) == 0x80a1) 636 d = (fis & 0x0f00) >> 8; 637 else 638 d = ch->pm_present ? 15 : 0; 639 if (bootverbose) 640 device_printf(dev, "SNTF %d\n", d); 641 if (xpt_create_path(&dpath, NULL, 642 xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) { 643 xpt_async(AC_SCSI_AEN, dpath, NULL); 644 xpt_free_path(dpath); 645 } 646 } 647 648 static void 649 mvs_ch_intr_locked(void *data) 650 { 651 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 652 device_t dev = (device_t)arg->arg; 653 struct mvs_channel *ch = device_get_softc(dev); 654 655 mtx_lock(&ch->mtx); 656 xpt_batch_start(ch->sim); 657 mvs_ch_intr(data); 658 xpt_batch_done(ch->sim); 659 mtx_unlock(&ch->mtx); 660 } 661 662 static void 663 mvs_ch_pm(void *arg) 664 { 665 device_t dev = (device_t)arg; 666 struct mvs_channel *ch = device_get_softc(dev); 667 uint32_t work; 668 669 if (ch->numrslots != 0) 670 return; 671 /* If we are idle - request power state transition. */ 672 work = ATA_INL(ch->r_mem, SATA_SC); 673 work &= ~SATA_SC_SPM_MASK; 674 if (ch->pm_level == 4) 675 work |= SATA_SC_SPM_PARTIAL; 676 else 677 work |= SATA_SC_SPM_SLUMBER; 678 ATA_OUTL(ch->r_mem, SATA_SC, work); 679 } 680 681 static void 682 mvs_ch_pm_wake(device_t dev) 683 { 684 struct mvs_channel *ch = device_get_softc(dev); 685 uint32_t work; 686 int timeout = 0; 687 688 work = ATA_INL(ch->r_mem, SATA_SS); 689 if (work & SATA_SS_IPM_ACTIVE) 690 return; 691 /* If we are not in active state - request power state transition. */ 692 work = ATA_INL(ch->r_mem, SATA_SC); 693 work &= ~SATA_SC_SPM_MASK; 694 work |= SATA_SC_SPM_ACTIVE; 695 ATA_OUTL(ch->r_mem, SATA_SC, work); 696 /* Wait for transition to happen. */ 697 while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 && 698 timeout++ < 100) { 699 DELAY(100); 700 } 701 } 702 703 static void 704 mvs_ch_intr(void *data) 705 { 706 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 707 device_t dev = (device_t)arg->arg; 708 struct mvs_channel *ch = device_get_softc(dev); 709 uint32_t iec, serr = 0, fisic = 0; 710 enum mvs_err_type et; 711 int i, ccs, port = -1, selfdis = 0; 712 int edma = (ch->numtslots != 0 || ch->numdslots != 0); 713 714 /* New item in response queue. */ 715 if ((arg->cause & 2) && edma) 716 mvs_crbq_intr(dev); 717 /* Some error or special event. */ 718 if (arg->cause & 1) { 719 iec = ATA_INL(ch->r_mem, EDMA_IEC); 720 if (iec & EDMA_IE_SERRINT) { 721 serr = ATA_INL(ch->r_mem, SATA_SE); 722 ATA_OUTL(ch->r_mem, SATA_SE, serr); 723 } 724 /* EDMA self-disabled due to error. */ 725 if (iec & EDMA_IE_ESELFDIS) 726 selfdis = 1; 727 /* Transport interrupt. */ 728 if (iec & EDMA_IE_ETRANSINT) { 729 /* For Gen-I this bit means self-disable. */ 730 if (ch->quirks & MVS_Q_GENI) 731 selfdis = 1; 732 /* For Gen-II this bit means SDB-N. */ 733 else if (ch->quirks & MVS_Q_GENII) 734 fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1; 735 else /* For Gen-IIe - read FIS interrupt cause. */ 736 fisic = ATA_INL(ch->r_mem, SATA_FISIC); 737 } 738 if (selfdis) 739 ch->curr_mode = MVS_EDMA_UNKNOWN; 740 ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec); 741 /* Interface errors or Device error. */ 742 if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) { 743 port = -1; 744 if (ch->numpslots != 0) { 745 ccs = 0; 746 } else { 747 if (ch->quirks & MVS_Q_GENIIE) 748 ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S)); 749 else 750 ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S)); 751 /* Check if error is one-PMP-port-specific, */ 752 if (ch->fbs_enabled) { 753 /* Which ports were active. */ 754 for (i = 0; i < 16; i++) { 755 if (ch->numrslotspd[i] == 0) 756 continue; 757 if (port == -1) 758 port = i; 759 else if (port != i) { 760 port = -2; 761 break; 762 } 763 } 764 /* If several ports were active and EDMA still enabled - 765 * other ports are probably unaffected and may continue. 766 */ 767 if (port == -2 && !selfdis) { 768 uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16; 769 port = ffs(p) - 1; 770 if (port != (fls(p) - 1)) 771 port = -2; 772 } 773 } 774 } 775 mvs_requeue_frozen(dev); 776 for (i = 0; i < MVS_MAX_SLOTS; i++) { 777 /* XXX: reqests in loading state. */ 778 if (((ch->rslots >> i) & 1) == 0) 779 continue; 780 if (port >= 0 && 781 ch->slot[i].ccb->ccb_h.target_id != port) 782 continue; 783 if (iec & EDMA_IE_EDEVERR) { /* Device error. */ 784 if (port != -2) { 785 if (ch->numtslots == 0) { 786 /* Untagged operation. */ 787 if (i == ccs) 788 et = MVS_ERR_TFE; 789 else 790 et = MVS_ERR_INNOCENT; 791 } else { 792 /* Tagged operation. */ 793 et = MVS_ERR_NCQ; 794 } 795 } else { 796 et = MVS_ERR_TFE; 797 ch->fatalerr = 1; 798 } 799 } else if (iec & 0xfc1e9000) { 800 if (ch->numtslots == 0 && 801 i != ccs && port != -2) 802 et = MVS_ERR_INNOCENT; 803 else 804 et = MVS_ERR_SATA; 805 } else 806 et = MVS_ERR_INVALID; 807 mvs_end_transaction(&ch->slot[i], et); 808 } 809 } 810 /* Process SDB-N. */ 811 if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1) 812 mvs_notify_events(dev); 813 if (fisic) 814 ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic); 815 /* Process hot-plug. */ 816 if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) || 817 (serr & SATA_SE_PHY_CHANGED)) 818 mvs_phy_check_events(dev, serr); 819 } 820 /* Legacy mode device interrupt. */ 821 if ((arg->cause & 2) && !edma) 822 mvs_legacy_intr(dev, arg->cause & 4); 823 } 824 825 static uint8_t 826 mvs_getstatus(device_t dev, int clear) 827 { 828 struct mvs_channel *ch = device_get_softc(dev); 829 uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT); 830 831 if (ch->fake_busy) { 832 if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR)) 833 ch->fake_busy = 0; 834 else 835 status |= ATA_S_BUSY; 836 } 837 return (status); 838 } 839 840 static void 841 mvs_legacy_intr(device_t dev, int poll) 842 { 843 struct mvs_channel *ch = device_get_softc(dev); 844 struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */ 845 union ccb *ccb = slot->ccb; 846 enum mvs_err_type et = MVS_ERR_NONE; 847 int port; 848 u_int length, resid, size; 849 uint8_t buf[2]; 850 uint8_t status, ireason; 851 852 /* Clear interrupt and get status. */ 853 status = mvs_getstatus(dev, 1); 854 if (slot->state < MVS_SLOT_RUNNING) 855 return; 856 port = ccb->ccb_h.target_id & 0x0f; 857 /* Wait a bit for late !BUSY status update. */ 858 if (status & ATA_S_BUSY) { 859 if (poll) 860 return; 861 DELAY(100); 862 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) { 863 DELAY(1000); 864 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) 865 return; 866 } 867 } 868 /* If we got an error, we are done. */ 869 if (status & ATA_S_ERROR) { 870 et = MVS_ERR_TFE; 871 goto end_finished; 872 } 873 if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */ 874 ccb->ataio.res.status = status; 875 /* Are we moving data? */ 876 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 877 /* If data read command - get them. */ 878 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 879 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 880 device_printf(dev, "timeout waiting for read DRQ\n"); 881 et = MVS_ERR_TIMEOUT; 882 xpt_freeze_simq(ch->sim, 1); 883 ch->toslots |= (1 << slot->slot); 884 goto end_finished; 885 } 886 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 887 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 888 ch->transfersize / 2); 889 } 890 /* Update how far we've gotten. */ 891 ch->donecount += ch->transfersize; 892 /* Do we need more? */ 893 if (ccb->ataio.dxfer_len > ch->donecount) { 894 /* Set this transfer size according to HW capabilities */ 895 ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount, 896 ch->transfersize); 897 /* If data write command - put them */ 898 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 899 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 900 device_printf(dev, 901 "timeout waiting for write DRQ\n"); 902 et = MVS_ERR_TIMEOUT; 903 xpt_freeze_simq(ch->sim, 1); 904 ch->toslots |= (1 << slot->slot); 905 goto end_finished; 906 } 907 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 908 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 909 ch->transfersize / 2); 910 return; 911 } 912 /* If data read command, return & wait for interrupt */ 913 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 914 return; 915 } 916 } 917 } else if (ch->basic_dma) { /* ATAPI DMA */ 918 if (status & ATA_S_DWF) 919 et = MVS_ERR_TFE; 920 else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR) 921 et = MVS_ERR_TFE; 922 /* Stop basic DMA. */ 923 ATA_OUTL(ch->r_mem, DMA_C, 0); 924 goto end_finished; 925 } else { /* ATAPI PIO */ 926 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) | 927 (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8); 928 size = min(ch->transfersize, length); 929 ireason = ATA_INB(ch->r_mem,ATA_IREASON); 930 switch ((ireason & (ATA_I_CMD | ATA_I_IN)) | 931 (status & ATA_S_DRQ)) { 932 933 case ATAPI_P_CMDOUT: 934 device_printf(dev, "ATAPI CMDOUT\n"); 935 /* Return wait for interrupt */ 936 return; 937 938 case ATAPI_P_WRITE: 939 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 940 device_printf(dev, "trying to write on read buffer\n"); 941 et = MVS_ERR_TFE; 942 goto end_finished; 943 break; 944 } 945 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 946 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 947 (size + 1) / 2); 948 for (resid = ch->transfersize + (size & 1); 949 resid < length; resid += sizeof(int16_t)) 950 ATA_OUTW(ch->r_mem, ATA_DATA, 0); 951 ch->donecount += length; 952 /* Set next transfer size according to HW capabilities */ 953 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 954 ch->curr[ccb->ccb_h.target_id].bytecount); 955 /* Return wait for interrupt */ 956 return; 957 958 case ATAPI_P_READ: 959 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 960 device_printf(dev, "trying to read on write buffer\n"); 961 et = MVS_ERR_TFE; 962 goto end_finished; 963 } 964 if (size >= 2) { 965 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 966 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 967 size / 2); 968 } 969 if (size & 1) { 970 ATA_INSW_STRM(ch->r_mem, ATA_DATA, (void*)buf, 1); 971 ((uint8_t *)ccb->csio.data_ptr + ch->donecount + 972 (size & ~1))[0] = buf[0]; 973 } 974 for (resid = ch->transfersize + (size & 1); 975 resid < length; resid += sizeof(int16_t)) 976 ATA_INW(ch->r_mem, ATA_DATA); 977 ch->donecount += length; 978 /* Set next transfer size according to HW capabilities */ 979 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 980 ch->curr[ccb->ccb_h.target_id].bytecount); 981 /* Return wait for interrupt */ 982 return; 983 984 case ATAPI_P_DONEDRQ: 985 device_printf(dev, 986 "WARNING - DONEDRQ non conformant device\n"); 987 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 988 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 989 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 990 length / 2); 991 ch->donecount += length; 992 } 993 else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 994 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 995 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 996 length / 2); 997 ch->donecount += length; 998 } 999 else 1000 et = MVS_ERR_TFE; 1001 /* FALLTHROUGH */ 1002 1003 case ATAPI_P_ABORT: 1004 case ATAPI_P_DONE: 1005 if (status & (ATA_S_ERROR | ATA_S_DWF)) 1006 et = MVS_ERR_TFE; 1007 goto end_finished; 1008 1009 default: 1010 device_printf(dev, "unknown transfer phase" 1011 " (status %02x, ireason %02x)\n", 1012 status, ireason); 1013 et = MVS_ERR_TFE; 1014 } 1015 } 1016 1017 end_finished: 1018 mvs_end_transaction(slot, et); 1019 } 1020 1021 static void 1022 mvs_crbq_intr(device_t dev) 1023 { 1024 struct mvs_channel *ch = device_get_softc(dev); 1025 struct mvs_crpb *crpb; 1026 union ccb *ccb; 1027 int in_idx, fin_idx, cin_idx, slot; 1028 uint32_t val; 1029 uint16_t flags; 1030 1031 val = ATA_INL(ch->r_mem, EDMA_RESQIP); 1032 if (val == 0) 1033 val = ATA_INL(ch->r_mem, EDMA_RESQIP); 1034 in_idx = (val & EDMA_RESQP_ERPQP_MASK) >> 1035 EDMA_RESQP_ERPQP_SHIFT; 1036 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1037 BUS_DMASYNC_POSTREAD); 1038 fin_idx = cin_idx = ch->in_idx; 1039 ch->in_idx = in_idx; 1040 while (in_idx != cin_idx) { 1041 crpb = (struct mvs_crpb *) 1042 (ch->dma.workrp + MVS_CRPB_OFFSET + 1043 (MVS_CRPB_SIZE * cin_idx)); 1044 slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK; 1045 flags = le16toh(crpb->rspflg); 1046 /* 1047 * Handle only successfull completions here. 1048 * Errors will be handled by main intr handler. 1049 */ 1050 #if defined(__i386__) || defined(__amd64__) 1051 if (crpb->id == 0xffff && crpb->rspflg == 0xffff) { 1052 device_printf(dev, "Unfilled CRPB " 1053 "%d (%d->%d) tag %d flags %04x rs %08x\n", 1054 cin_idx, fin_idx, in_idx, slot, flags, ch->rslots); 1055 } else 1056 #endif 1057 if (ch->numtslots != 0 || 1058 (flags & EDMA_IE_EDEVERR) == 0) { 1059 #if defined(__i386__) || defined(__amd64__) 1060 crpb->id = 0xffff; 1061 crpb->rspflg = 0xffff; 1062 #endif 1063 if (ch->slot[slot].state >= MVS_SLOT_RUNNING) { 1064 ccb = ch->slot[slot].ccb; 1065 ccb->ataio.res.status = 1066 (flags & MVS_CRPB_ATASTS_MASK) >> 1067 MVS_CRPB_ATASTS_SHIFT; 1068 mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE); 1069 } else { 1070 device_printf(dev, "Unused tag in CRPB " 1071 "%d (%d->%d) tag %d flags %04x rs %08x\n", 1072 cin_idx, fin_idx, in_idx, slot, flags, 1073 ch->rslots); 1074 } 1075 } else { 1076 device_printf(dev, 1077 "CRPB with error %d tag %d flags %04x\n", 1078 cin_idx, slot, flags); 1079 } 1080 cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1); 1081 } 1082 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1083 BUS_DMASYNC_PREREAD); 1084 if (cin_idx == ch->in_idx) { 1085 ATA_OUTL(ch->r_mem, EDMA_RESQOP, 1086 ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT)); 1087 } 1088 } 1089 1090 /* Must be called with channel locked. */ 1091 static int 1092 mvs_check_collision(device_t dev, union ccb *ccb) 1093 { 1094 struct mvs_channel *ch = device_get_softc(dev); 1095 1096 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1097 /* NCQ DMA */ 1098 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1099 /* Can't mix NCQ and non-NCQ DMA commands. */ 1100 if (ch->numdslots != 0) 1101 return (1); 1102 /* Can't mix NCQ and PIO commands. */ 1103 if (ch->numpslots != 0) 1104 return (1); 1105 /* If we have no FBS */ 1106 if (!ch->fbs_enabled) { 1107 /* Tagged command while tagged to other target is active. */ 1108 if (ch->numtslots != 0 && 1109 ch->taggedtarget != ccb->ccb_h.target_id) 1110 return (1); 1111 } 1112 /* Non-NCQ DMA */ 1113 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1114 /* Can't mix non-NCQ DMA and NCQ commands. */ 1115 if (ch->numtslots != 0) 1116 return (1); 1117 /* Can't mix non-NCQ DMA and PIO commands. */ 1118 if (ch->numpslots != 0) 1119 return (1); 1120 /* PIO */ 1121 } else { 1122 /* Can't mix PIO with anything. */ 1123 if (ch->numrslots != 0) 1124 return (1); 1125 } 1126 if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1127 /* Atomic command while anything active. */ 1128 if (ch->numrslots != 0) 1129 return (1); 1130 } 1131 } else { /* ATAPI */ 1132 /* ATAPI goes without EDMA, so can't mix it with anything. */ 1133 if (ch->numrslots != 0) 1134 return (1); 1135 } 1136 /* We have some atomic command running. */ 1137 if (ch->aslots != 0) 1138 return (1); 1139 return (0); 1140 } 1141 1142 static void 1143 mvs_tfd_read(device_t dev, union ccb *ccb) 1144 { 1145 struct mvs_channel *ch = device_get_softc(dev); 1146 struct ata_res *res = &ccb->ataio.res; 1147 1148 res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT); 1149 res->error = ATA_INB(ch->r_mem, ATA_ERROR); 1150 res->device = ATA_INB(ch->r_mem, ATA_DRIVE); 1151 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB); 1152 res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT); 1153 res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR); 1154 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1155 res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1156 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 1157 res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT); 1158 res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR); 1159 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1160 res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1161 } 1162 1163 static void 1164 mvs_tfd_write(device_t dev, union ccb *ccb) 1165 { 1166 struct mvs_channel *ch = device_get_softc(dev); 1167 struct ata_cmd *cmd = &ccb->ataio.cmd; 1168 1169 ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device); 1170 ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control); 1171 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp); 1172 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features); 1173 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp); 1174 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count); 1175 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp); 1176 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low); 1177 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp); 1178 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid); 1179 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp); 1180 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high); 1181 ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command); 1182 } 1183 1184 1185 /* Must be called with channel locked. */ 1186 static void 1187 mvs_begin_transaction(device_t dev, union ccb *ccb) 1188 { 1189 struct mvs_channel *ch = device_get_softc(dev); 1190 struct mvs_slot *slot; 1191 int slotn, tag; 1192 1193 if (ch->pm_level > 0) 1194 mvs_ch_pm_wake(dev); 1195 /* Softreset is a special case. */ 1196 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1197 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1198 mvs_softreset(dev, ccb); 1199 return; 1200 } 1201 /* Choose empty slot. */ 1202 slotn = ffs(~ch->oslots) - 1; 1203 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1204 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1205 if (ch->quirks & MVS_Q_GENIIE) 1206 tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1; 1207 else 1208 tag = slotn; 1209 } else 1210 tag = 0; 1211 /* Occupy chosen slot. */ 1212 slot = &ch->slot[slotn]; 1213 slot->ccb = ccb; 1214 slot->tag = tag; 1215 /* Stop PM timer. */ 1216 if (ch->numrslots == 0 && ch->pm_level > 3) 1217 callout_stop(&ch->pm_timer); 1218 /* Update channel stats. */ 1219 ch->oslots |= (1 << slot->slot); 1220 ch->numrslots++; 1221 ch->numrslotspd[ccb->ccb_h.target_id]++; 1222 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1223 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1224 ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag); 1225 ch->numtslots++; 1226 ch->numtslotspd[ccb->ccb_h.target_id]++; 1227 ch->taggedtarget = ccb->ccb_h.target_id; 1228 mvs_set_edma_mode(dev, MVS_EDMA_NCQ); 1229 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1230 ch->numdslots++; 1231 mvs_set_edma_mode(dev, MVS_EDMA_ON); 1232 } else { 1233 ch->numpslots++; 1234 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1235 } 1236 if (ccb->ataio.cmd.flags & 1237 (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1238 ch->aslots |= (1 << slot->slot); 1239 } 1240 } else { 1241 uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1242 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes; 1243 ch->numpslots++; 1244 /* Use ATAPI DMA only for commands without under-/overruns. */ 1245 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1246 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA && 1247 (ch->quirks & MVS_Q_SOC) == 0 && 1248 (cdb[0] == 0x08 || 1249 cdb[0] == 0x0a || 1250 cdb[0] == 0x28 || 1251 cdb[0] == 0x2a || 1252 cdb[0] == 0x88 || 1253 cdb[0] == 0x8a || 1254 cdb[0] == 0xa8 || 1255 cdb[0] == 0xaa || 1256 cdb[0] == 0xbe)) { 1257 ch->basic_dma = 1; 1258 } 1259 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1260 } 1261 if (ch->numpslots == 0 || ch->basic_dma) { 1262 void *buf; 1263 bus_size_t size; 1264 1265 slot->state = MVS_SLOT_LOADING; 1266 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1267 buf = ccb->ataio.data_ptr; 1268 size = ccb->ataio.dxfer_len; 1269 } else { 1270 buf = ccb->csio.data_ptr; 1271 size = ccb->csio.dxfer_len; 1272 } 1273 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1274 buf, size, mvs_dmasetprd, slot, 0); 1275 } else 1276 mvs_legacy_execute_transaction(slot); 1277 } 1278 1279 /* Locked by busdma engine. */ 1280 static void 1281 mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1282 { 1283 struct mvs_slot *slot = arg; 1284 struct mvs_channel *ch = device_get_softc(slot->dev); 1285 struct mvs_eprd *eprd; 1286 int i; 1287 1288 if (error) { 1289 device_printf(slot->dev, "DMA load error\n"); 1290 mvs_end_transaction(slot, MVS_ERR_INVALID); 1291 return; 1292 } 1293 KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n")); 1294 /* If there is only one segment - no need to use S/G table on Gen-IIe. */ 1295 if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) { 1296 slot->dma.addr = segs[0].ds_addr; 1297 slot->dma.len = segs[0].ds_len; 1298 } else { 1299 slot->dma.addr = 0; 1300 /* Get a piece of the workspace for this EPRD */ 1301 eprd = (struct mvs_eprd *) 1302 (ch->dma.workrq + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot)); 1303 /* Fill S/G table */ 1304 for (i = 0; i < nsegs; i++) { 1305 eprd[i].prdbal = htole32(segs[i].ds_addr); 1306 eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK); 1307 eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16); 1308 } 1309 eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF); 1310 } 1311 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1312 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1313 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1314 if (ch->basic_dma) 1315 mvs_legacy_execute_transaction(slot); 1316 else 1317 mvs_execute_transaction(slot); 1318 } 1319 1320 static void 1321 mvs_legacy_execute_transaction(struct mvs_slot *slot) 1322 { 1323 device_t dev = slot->dev; 1324 struct mvs_channel *ch = device_get_softc(dev); 1325 bus_addr_t eprd; 1326 union ccb *ccb = slot->ccb; 1327 int port = ccb->ccb_h.target_id & 0x0f; 1328 int timeout; 1329 1330 slot->state = MVS_SLOT_RUNNING; 1331 ch->rslots |= (1 << slot->slot); 1332 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 1333 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1334 mvs_tfd_write(dev, ccb); 1335 /* Device reset doesn't interrupt. */ 1336 if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) { 1337 int timeout = 1000000; 1338 do { 1339 DELAY(10); 1340 ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS); 1341 } while (ccb->ataio.res.status & ATA_S_BUSY && timeout--); 1342 mvs_legacy_intr(dev, 1); 1343 return; 1344 } 1345 ch->donecount = 0; 1346 if (ccb->ataio.cmd.command == ATA_READ_MUL || 1347 ccb->ataio.cmd.command == ATA_READ_MUL48 || 1348 ccb->ataio.cmd.command == ATA_WRITE_MUL || 1349 ccb->ataio.cmd.command == ATA_WRITE_MUL48) { 1350 ch->transfersize = min(ccb->ataio.dxfer_len, 1351 ch->curr[port].bytecount); 1352 } else 1353 ch->transfersize = min(ccb->ataio.dxfer_len, 512); 1354 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1355 ch->fake_busy = 1; 1356 /* If data write command - output the data */ 1357 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1358 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 1359 device_printf(dev, 1360 "timeout waiting for write DRQ\n"); 1361 xpt_freeze_simq(ch->sim, 1); 1362 ch->toslots |= (1 << slot->slot); 1363 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1364 return; 1365 } 1366 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1367 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 1368 ch->transfersize / 2); 1369 } 1370 } else { 1371 ch->donecount = 0; 1372 ch->transfersize = min(ccb->csio.dxfer_len, 1373 ch->curr[port].bytecount); 1374 /* Write ATA PACKET command. */ 1375 if (ch->basic_dma) { 1376 ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA); 1377 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0); 1378 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0); 1379 } else { 1380 ATA_OUTB(ch->r_mem, ATA_FEATURE, 0); 1381 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize); 1382 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8); 1383 } 1384 ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD); 1385 ch->fake_busy = 1; 1386 /* Wait for ready to write ATAPI command block */ 1387 if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) { 1388 device_printf(dev, "timeout waiting for ATAPI !BUSY\n"); 1389 xpt_freeze_simq(ch->sim, 1); 1390 ch->toslots |= (1 << slot->slot); 1391 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1392 return; 1393 } 1394 timeout = 5000; 1395 while (timeout--) { 1396 int reason = ATA_INB(ch->r_mem, ATA_IREASON); 1397 int status = ATA_INB(ch->r_mem, ATA_STATUS); 1398 1399 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 1400 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 1401 break; 1402 DELAY(20); 1403 } 1404 if (timeout <= 0) { 1405 device_printf(dev, 1406 "timeout waiting for ATAPI command ready\n"); 1407 xpt_freeze_simq(ch->sim, 1); 1408 ch->toslots |= (1 << slot->slot); 1409 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1410 return; 1411 } 1412 /* Write ATAPI command. */ 1413 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1414 (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1415 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes), 1416 ch->curr[port].atapi / 2); 1417 DELAY(10); 1418 if (ch->basic_dma) { 1419 /* Start basic DMA. */ 1420 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + 1421 (MVS_EPRD_SIZE * slot->slot); 1422 ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd); 1423 ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16); 1424 ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START | 1425 (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ? 1426 DMA_C_READ : 0)); 1427 } 1428 } 1429 /* Start command execution timeout */ 1430 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1431 (timeout_t*)mvs_timeout, slot); 1432 } 1433 1434 /* Must be called with channel locked. */ 1435 static void 1436 mvs_execute_transaction(struct mvs_slot *slot) 1437 { 1438 device_t dev = slot->dev; 1439 struct mvs_channel *ch = device_get_softc(dev); 1440 bus_addr_t eprd; 1441 struct mvs_crqb *crqb; 1442 struct mvs_crqb_gen2e *crqb2e; 1443 union ccb *ccb = slot->ccb; 1444 int port = ccb->ccb_h.target_id & 0x0f; 1445 int i; 1446 1447 /* Get address of the prepared EPRD */ 1448 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot); 1449 /* Prepare CRQB. Gen IIe uses different CRQB format. */ 1450 if (ch->quirks & MVS_Q_GENIIE) { 1451 crqb2e = (struct mvs_crqb_gen2e *) 1452 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1453 crqb2e->ctrlflg = htole32( 1454 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) | 1455 (slot->tag << MVS_CRQB2E_DTAG_SHIFT) | 1456 (port << MVS_CRQB2E_PMP_SHIFT) | 1457 (slot->slot << MVS_CRQB2E_HTAG_SHIFT)); 1458 /* If there is only one segment - no need to use S/G table. */ 1459 if (slot->dma.addr != 0) { 1460 eprd = slot->dma.addr; 1461 crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD); 1462 crqb2e->drbc = slot->dma.len; 1463 } 1464 crqb2e->cprdbl = htole32(eprd); 1465 crqb2e->cprdbh = htole32((eprd >> 16) >> 16); 1466 crqb2e->cmd[0] = 0; 1467 crqb2e->cmd[1] = 0; 1468 crqb2e->cmd[2] = ccb->ataio.cmd.command; 1469 crqb2e->cmd[3] = ccb->ataio.cmd.features; 1470 crqb2e->cmd[4] = ccb->ataio.cmd.lba_low; 1471 crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid; 1472 crqb2e->cmd[6] = ccb->ataio.cmd.lba_high; 1473 crqb2e->cmd[7] = ccb->ataio.cmd.device; 1474 crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp; 1475 crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp; 1476 crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp; 1477 crqb2e->cmd[11] = ccb->ataio.cmd.features_exp; 1478 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1479 crqb2e->cmd[12] = slot->tag << 3; 1480 crqb2e->cmd[13] = 0; 1481 } else { 1482 crqb2e->cmd[12] = ccb->ataio.cmd.sector_count; 1483 crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp; 1484 } 1485 crqb2e->cmd[14] = 0; 1486 crqb2e->cmd[15] = 0; 1487 } else { 1488 crqb = (struct mvs_crqb *) 1489 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1490 crqb->cprdbl = htole32(eprd); 1491 crqb->cprdbh = htole32((eprd >> 16) >> 16); 1492 crqb->ctrlflg = htole16( 1493 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) | 1494 (slot->slot << MVS_CRQB_TAG_SHIFT) | 1495 (port << MVS_CRQB_PMP_SHIFT)); 1496 i = 0; 1497 /* 1498 * Controller can handle only 11 of 12 ATA registers, 1499 * so we have to choose which one to skip. 1500 */ 1501 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1502 crqb->cmd[i++] = ccb->ataio.cmd.features_exp; 1503 crqb->cmd[i++] = 0x11; 1504 } 1505 crqb->cmd[i++] = ccb->ataio.cmd.features; 1506 crqb->cmd[i++] = 0x11; 1507 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1508 crqb->cmd[i++] = slot->tag << 3; 1509 crqb->cmd[i++] = 0x12; 1510 } else { 1511 crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp; 1512 crqb->cmd[i++] = 0x12; 1513 crqb->cmd[i++] = ccb->ataio.cmd.sector_count; 1514 crqb->cmd[i++] = 0x12; 1515 } 1516 crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp; 1517 crqb->cmd[i++] = 0x13; 1518 crqb->cmd[i++] = ccb->ataio.cmd.lba_low; 1519 crqb->cmd[i++] = 0x13; 1520 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp; 1521 crqb->cmd[i++] = 0x14; 1522 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid; 1523 crqb->cmd[i++] = 0x14; 1524 crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp; 1525 crqb->cmd[i++] = 0x15; 1526 crqb->cmd[i++] = ccb->ataio.cmd.lba_high; 1527 crqb->cmd[i++] = 0x15; 1528 crqb->cmd[i++] = ccb->ataio.cmd.device; 1529 crqb->cmd[i++] = 0x16; 1530 crqb->cmd[i++] = ccb->ataio.cmd.command; 1531 crqb->cmd[i++] = 0x97; 1532 } 1533 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1534 BUS_DMASYNC_PREWRITE); 1535 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1536 BUS_DMASYNC_PREREAD); 1537 slot->state = MVS_SLOT_RUNNING; 1538 ch->rslots |= (1 << slot->slot); 1539 /* Issue command to the controller. */ 1540 ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1); 1541 ATA_OUTL(ch->r_mem, EDMA_REQQIP, 1542 ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1543 /* Start command execution timeout */ 1544 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1545 (timeout_t*)mvs_timeout, slot); 1546 return; 1547 } 1548 1549 /* Must be called with channel locked. */ 1550 static void 1551 mvs_process_timeout(device_t dev) 1552 { 1553 struct mvs_channel *ch = device_get_softc(dev); 1554 int i; 1555 1556 mtx_assert(&ch->mtx, MA_OWNED); 1557 /* Handle the rest of commands. */ 1558 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1559 /* Do we have a running request on slot? */ 1560 if (ch->slot[i].state < MVS_SLOT_RUNNING) 1561 continue; 1562 mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT); 1563 } 1564 } 1565 1566 /* Must be called with channel locked. */ 1567 static void 1568 mvs_rearm_timeout(device_t dev) 1569 { 1570 struct mvs_channel *ch = device_get_softc(dev); 1571 int i; 1572 1573 mtx_assert(&ch->mtx, MA_OWNED); 1574 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1575 struct mvs_slot *slot = &ch->slot[i]; 1576 1577 /* Do we have a running request on slot? */ 1578 if (slot->state < MVS_SLOT_RUNNING) 1579 continue; 1580 if ((ch->toslots & (1 << i)) == 0) 1581 continue; 1582 callout_reset(&slot->timeout, 1583 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1584 (timeout_t*)mvs_timeout, slot); 1585 } 1586 } 1587 1588 /* Locked by callout mechanism. */ 1589 static void 1590 mvs_timeout(struct mvs_slot *slot) 1591 { 1592 device_t dev = slot->dev; 1593 struct mvs_channel *ch = device_get_softc(dev); 1594 1595 /* Check for stale timeout. */ 1596 if (slot->state < MVS_SLOT_RUNNING) 1597 return; 1598 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1599 device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x " 1600 "dma_c %08x dma_s %08x rs %08x status %02x\n", 1601 ATA_INL(ch->r_mem, EDMA_IEC), 1602 ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE), 1603 ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C), 1604 ATA_INL(ch->r_mem, DMA_S), ch->rslots, 1605 ATA_INB(ch->r_mem, ATA_ALTSTAT)); 1606 /* Handle frozen command. */ 1607 mvs_requeue_frozen(dev); 1608 /* We wait for other commands timeout and pray. */ 1609 if (ch->toslots == 0) 1610 xpt_freeze_simq(ch->sim, 1); 1611 ch->toslots |= (1 << slot->slot); 1612 if ((ch->rslots & ~ch->toslots) == 0) 1613 mvs_process_timeout(dev); 1614 else 1615 device_printf(dev, " ... waiting for slots %08x\n", 1616 ch->rslots & ~ch->toslots); 1617 } 1618 1619 /* Must be called with channel locked. */ 1620 static void 1621 mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et) 1622 { 1623 device_t dev = slot->dev; 1624 struct mvs_channel *ch = device_get_softc(dev); 1625 union ccb *ccb = slot->ccb; 1626 int lastto; 1627 1628 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1629 BUS_DMASYNC_POSTWRITE); 1630 /* Read result registers to the result struct 1631 * May be incorrect if several commands finished same time, 1632 * so read only when sure or have to. 1633 */ 1634 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1635 struct ata_res *res = &ccb->ataio.res; 1636 1637 if ((et == MVS_ERR_TFE) || 1638 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1639 mvs_tfd_read(dev, ccb); 1640 } else 1641 bzero(res, sizeof(*res)); 1642 } else { 1643 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1644 ch->basic_dma == 0) 1645 ccb->csio.resid = ccb->csio.dxfer_len - ch->donecount; 1646 } 1647 if (ch->numpslots == 0 || ch->basic_dma) { 1648 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1649 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1650 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1651 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1652 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1653 } 1654 } 1655 if (et != MVS_ERR_NONE) 1656 ch->eslots |= (1 << slot->slot); 1657 /* In case of error, freeze device for proper recovery. */ 1658 if ((et != MVS_ERR_NONE) && (!ch->recoverycmd) && 1659 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1660 xpt_freeze_devq(ccb->ccb_h.path, 1); 1661 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1662 } 1663 /* Set proper result status. */ 1664 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1665 switch (et) { 1666 case MVS_ERR_NONE: 1667 ccb->ccb_h.status |= CAM_REQ_CMP; 1668 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1669 ccb->csio.scsi_status = SCSI_STATUS_OK; 1670 break; 1671 case MVS_ERR_INVALID: 1672 ch->fatalerr = 1; 1673 ccb->ccb_h.status |= CAM_REQ_INVALID; 1674 break; 1675 case MVS_ERR_INNOCENT: 1676 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1677 break; 1678 case MVS_ERR_TFE: 1679 case MVS_ERR_NCQ: 1680 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1681 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1682 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1683 } else { 1684 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1685 } 1686 break; 1687 case MVS_ERR_SATA: 1688 ch->fatalerr = 1; 1689 if (!ch->recoverycmd) { 1690 xpt_freeze_simq(ch->sim, 1); 1691 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1692 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1693 } 1694 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1695 break; 1696 case MVS_ERR_TIMEOUT: 1697 if (!ch->recoverycmd) { 1698 xpt_freeze_simq(ch->sim, 1); 1699 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1700 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1701 } 1702 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1703 break; 1704 default: 1705 ch->fatalerr = 1; 1706 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1707 } 1708 /* Free slot. */ 1709 ch->oslots &= ~(1 << slot->slot); 1710 ch->rslots &= ~(1 << slot->slot); 1711 ch->aslots &= ~(1 << slot->slot); 1712 slot->state = MVS_SLOT_EMPTY; 1713 slot->ccb = NULL; 1714 /* Update channel stats. */ 1715 ch->numrslots--; 1716 ch->numrslotspd[ccb->ccb_h.target_id]--; 1717 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1718 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1719 ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag); 1720 ch->numtslots--; 1721 ch->numtslotspd[ccb->ccb_h.target_id]--; 1722 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1723 ch->numdslots--; 1724 } else { 1725 ch->numpslots--; 1726 } 1727 } else { 1728 ch->numpslots--; 1729 ch->basic_dma = 0; 1730 } 1731 /* Cancel timeout state if request completed normally. */ 1732 if (et != MVS_ERR_TIMEOUT) { 1733 lastto = (ch->toslots == (1 << slot->slot)); 1734 ch->toslots &= ~(1 << slot->slot); 1735 if (lastto) 1736 xpt_release_simq(ch->sim, TRUE); 1737 } 1738 /* If it was our READ LOG command - process it. */ 1739 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 1740 mvs_process_read_log(dev, ccb); 1741 /* If it was our REQUEST SENSE command - process it. */ 1742 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 1743 mvs_process_request_sense(dev, ccb); 1744 /* If it was NCQ or ATAPI command error, put result on hold. */ 1745 } else if (et == MVS_ERR_NCQ || 1746 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 1747 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 1748 ch->hold[slot->slot] = ccb; 1749 ch->holdtag[slot->slot] = slot->tag; 1750 ch->numhslots++; 1751 } else 1752 xpt_done(ccb); 1753 /* If we have no other active commands, ... */ 1754 if (ch->rslots == 0) { 1755 /* if there was fatal error - reset port. */ 1756 if (ch->toslots != 0 || ch->fatalerr) { 1757 mvs_reset(dev); 1758 } else { 1759 /* if we have slots in error, we can reinit port. */ 1760 if (ch->eslots != 0) { 1761 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1762 ch->eslots = 0; 1763 } 1764 /* if there commands on hold, we can do READ LOG. */ 1765 if (!ch->recoverycmd && ch->numhslots) 1766 mvs_issue_recovery(dev); 1767 } 1768 /* If all the rest of commands are in timeout - give them chance. */ 1769 } else if ((ch->rslots & ~ch->toslots) == 0 && 1770 et != MVS_ERR_TIMEOUT) 1771 mvs_rearm_timeout(dev); 1772 /* Unfreeze frozen command. */ 1773 if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) { 1774 union ccb *fccb = ch->frozen; 1775 ch->frozen = NULL; 1776 mvs_begin_transaction(dev, fccb); 1777 xpt_release_simq(ch->sim, TRUE); 1778 } 1779 /* Start PM timer. */ 1780 if (ch->numrslots == 0 && ch->pm_level > 3 && 1781 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1782 callout_schedule(&ch->pm_timer, 1783 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1784 } 1785 } 1786 1787 static void 1788 mvs_issue_recovery(device_t dev) 1789 { 1790 struct mvs_channel *ch = device_get_softc(dev); 1791 union ccb *ccb; 1792 struct ccb_ataio *ataio; 1793 struct ccb_scsiio *csio; 1794 int i; 1795 1796 /* Find some held command. */ 1797 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1798 if (ch->hold[i]) 1799 break; 1800 } 1801 ccb = xpt_alloc_ccb_nowait(); 1802 if (ccb == NULL) { 1803 device_printf(dev, "Unable to allocate recovery command\n"); 1804 completeall: 1805 /* We can't do anything -- complete held commands. */ 1806 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1807 if (ch->hold[i] == NULL) 1808 continue; 1809 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1810 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 1811 xpt_done(ch->hold[i]); 1812 ch->hold[i] = NULL; 1813 ch->numhslots--; 1814 } 1815 mvs_reset(dev); 1816 return; 1817 } 1818 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1819 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1820 /* READ LOG */ 1821 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 1822 ccb->ccb_h.func_code = XPT_ATA_IO; 1823 ccb->ccb_h.flags = CAM_DIR_IN; 1824 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1825 ataio = &ccb->ataio; 1826 ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT); 1827 if (ataio->data_ptr == NULL) { 1828 xpt_free_ccb(ccb); 1829 device_printf(dev, 1830 "Unable to allocate memory for READ LOG command\n"); 1831 goto completeall; 1832 } 1833 ataio->dxfer_len = 512; 1834 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1835 ataio->cmd.flags = CAM_ATAIO_48BIT; 1836 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1837 ataio->cmd.sector_count = 1; 1838 ataio->cmd.sector_count_exp = 0; 1839 ataio->cmd.lba_low = 0x10; 1840 ataio->cmd.lba_mid = 0; 1841 ataio->cmd.lba_mid_exp = 0; 1842 } else { 1843 /* REQUEST SENSE */ 1844 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 1845 ccb->ccb_h.recovery_slot = i; 1846 ccb->ccb_h.func_code = XPT_SCSI_IO; 1847 ccb->ccb_h.flags = CAM_DIR_IN; 1848 ccb->ccb_h.status = 0; 1849 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1850 csio = &ccb->csio; 1851 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 1852 csio->dxfer_len = ch->hold[i]->csio.sense_len; 1853 csio->cdb_len = 6; 1854 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 1855 csio->cdb_io.cdb_bytes[0] = 0x03; 1856 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 1857 } 1858 /* Freeze SIM while doing recovery. */ 1859 ch->recoverycmd = 1; 1860 xpt_freeze_simq(ch->sim, 1); 1861 mvs_begin_transaction(dev, ccb); 1862 } 1863 1864 static void 1865 mvs_process_read_log(device_t dev, union ccb *ccb) 1866 { 1867 struct mvs_channel *ch = device_get_softc(dev); 1868 uint8_t *data; 1869 struct ata_res *res; 1870 int i; 1871 1872 ch->recoverycmd = 0; 1873 1874 data = ccb->ataio.data_ptr; 1875 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1876 (data[0] & 0x80) == 0) { 1877 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1878 if (!ch->hold[i]) 1879 continue; 1880 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1881 continue; 1882 if ((data[0] & 0x1F) == ch->holdtag[i]) { 1883 res = &ch->hold[i]->ataio.res; 1884 res->status = data[2]; 1885 res->error = data[3]; 1886 res->lba_low = data[4]; 1887 res->lba_mid = data[5]; 1888 res->lba_high = data[6]; 1889 res->device = data[7]; 1890 res->lba_low_exp = data[8]; 1891 res->lba_mid_exp = data[9]; 1892 res->lba_high_exp = data[10]; 1893 res->sector_count = data[12]; 1894 res->sector_count_exp = data[13]; 1895 } else { 1896 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1897 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1898 } 1899 xpt_done(ch->hold[i]); 1900 ch->hold[i] = NULL; 1901 ch->numhslots--; 1902 } 1903 } else { 1904 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1905 device_printf(dev, "Error while READ LOG EXT\n"); 1906 else if ((data[0] & 0x80) == 0) { 1907 device_printf(dev, 1908 "Non-queued command error in READ LOG EXT\n"); 1909 } 1910 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1911 if (!ch->hold[i]) 1912 continue; 1913 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1914 continue; 1915 xpt_done(ch->hold[i]); 1916 ch->hold[i] = NULL; 1917 ch->numhslots--; 1918 } 1919 } 1920 free(ccb->ataio.data_ptr, M_MVS); 1921 xpt_free_ccb(ccb); 1922 xpt_release_simq(ch->sim, TRUE); 1923 } 1924 1925 static void 1926 mvs_process_request_sense(device_t dev, union ccb *ccb) 1927 { 1928 struct mvs_channel *ch = device_get_softc(dev); 1929 int i; 1930 1931 ch->recoverycmd = 0; 1932 1933 i = ccb->ccb_h.recovery_slot; 1934 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 1935 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 1936 } else { 1937 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1938 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 1939 } 1940 xpt_done(ch->hold[i]); 1941 ch->hold[i] = NULL; 1942 ch->numhslots--; 1943 xpt_free_ccb(ccb); 1944 xpt_release_simq(ch->sim, TRUE); 1945 } 1946 1947 static int 1948 mvs_wait(device_t dev, u_int s, u_int c, int t) 1949 { 1950 int timeout = 0; 1951 uint8_t st; 1952 1953 while (((st = mvs_getstatus(dev, 0)) & (s | c)) != s) { 1954 if (timeout >= t) { 1955 if (t != 0) 1956 device_printf(dev, "Wait status %02x\n", st); 1957 return (-1); 1958 } 1959 DELAY(1000); 1960 timeout++; 1961 } 1962 return (timeout); 1963 } 1964 1965 static void 1966 mvs_requeue_frozen(device_t dev) 1967 { 1968 struct mvs_channel *ch = device_get_softc(dev); 1969 union ccb *fccb = ch->frozen; 1970 1971 if (fccb) { 1972 ch->frozen = NULL; 1973 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1974 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1975 xpt_freeze_devq(fccb->ccb_h.path, 1); 1976 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1977 } 1978 xpt_done(fccb); 1979 } 1980 } 1981 1982 static void 1983 mvs_reset_to(void *arg) 1984 { 1985 device_t dev = arg; 1986 struct mvs_channel *ch = device_get_softc(dev); 1987 int t; 1988 1989 if (ch->resetting == 0) 1990 return; 1991 ch->resetting--; 1992 if ((t = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 0)) >= 0) { 1993 if (bootverbose) { 1994 device_printf(dev, 1995 "MVS reset: device ready after %dms\n", 1996 (310 - ch->resetting) * 100); 1997 } 1998 ch->resetting = 0; 1999 xpt_release_simq(ch->sim, TRUE); 2000 return; 2001 } 2002 if (ch->resetting == 0) { 2003 device_printf(dev, 2004 "MVS reset: device not ready after 31000ms\n"); 2005 xpt_release_simq(ch->sim, TRUE); 2006 return; 2007 } 2008 callout_schedule(&ch->reset_timer, hz / 10); 2009 } 2010 2011 static void 2012 mvs_errata(device_t dev) 2013 { 2014 struct mvs_channel *ch = device_get_softc(dev); 2015 uint32_t val; 2016 2017 if (ch->quirks & MVS_Q_SOC65) { 2018 val = ATA_INL(ch->r_mem, SATA_PHYM3); 2019 val &= ~(0x3 << 27); /* SELMUPF = 1 */ 2020 val |= (0x1 << 27); 2021 val &= ~(0x3 << 29); /* SELMUPI = 1 */ 2022 val |= (0x1 << 29); 2023 ATA_OUTL(ch->r_mem, SATA_PHYM3, val); 2024 2025 val = ATA_INL(ch->r_mem, SATA_PHYM4); 2026 val &= ~0x1; /* SATU_OD8 = 0 */ 2027 val |= (0x1 << 16); /* reserved bit 16 = 1 */ 2028 ATA_OUTL(ch->r_mem, SATA_PHYM4, val); 2029 2030 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN2); 2031 val &= ~0xf; /* TXAMP[3:0] = 8 */ 2032 val |= 0x8; 2033 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */ 2034 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN2, val); 2035 2036 val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN1); 2037 val &= ~0xf; /* TXAMP[3:0] = 8 */ 2038 val |= 0x8; 2039 val &= ~(0x1 << 14); /* TXAMP[4] = 0 */ 2040 ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN1, val); 2041 } 2042 } 2043 2044 static void 2045 mvs_reset(device_t dev) 2046 { 2047 struct mvs_channel *ch = device_get_softc(dev); 2048 int i; 2049 2050 xpt_freeze_simq(ch->sim, 1); 2051 if (bootverbose) 2052 device_printf(dev, "MVS reset...\n"); 2053 /* Forget about previous reset. */ 2054 if (ch->resetting) { 2055 ch->resetting = 0; 2056 callout_stop(&ch->reset_timer); 2057 xpt_release_simq(ch->sim, TRUE); 2058 } 2059 /* Requeue freezed command. */ 2060 mvs_requeue_frozen(dev); 2061 /* Kill the engine and requeue all running commands. */ 2062 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 2063 ATA_OUTL(ch->r_mem, DMA_C, 0); 2064 for (i = 0; i < MVS_MAX_SLOTS; i++) { 2065 /* Do we have a running request on slot? */ 2066 if (ch->slot[i].state < MVS_SLOT_RUNNING) 2067 continue; 2068 /* XXX; Commands in loading state. */ 2069 mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT); 2070 } 2071 for (i = 0; i < MVS_MAX_SLOTS; i++) { 2072 if (!ch->hold[i]) 2073 continue; 2074 xpt_done(ch->hold[i]); 2075 ch->hold[i] = NULL; 2076 ch->numhslots--; 2077 } 2078 if (ch->toslots != 0) 2079 xpt_release_simq(ch->sim, TRUE); 2080 ch->eslots = 0; 2081 ch->toslots = 0; 2082 ch->fatalerr = 0; 2083 ch->fake_busy = 0; 2084 /* Tell the XPT about the event */ 2085 xpt_async(AC_BUS_RESET, ch->path, NULL); 2086 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 2087 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST); 2088 DELAY(25); 2089 ATA_OUTL(ch->r_mem, EDMA_CMD, 0); 2090 mvs_errata(dev); 2091 /* Reset and reconnect PHY, */ 2092 if (!mvs_sata_phy_reset(dev)) { 2093 if (bootverbose) 2094 device_printf(dev, "MVS reset: device not found\n"); 2095 ch->devices = 0; 2096 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 2097 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 2098 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 2099 xpt_release_simq(ch->sim, TRUE); 2100 return; 2101 } 2102 if (bootverbose) 2103 device_printf(dev, "MVS reset: device found\n"); 2104 /* Wait for clearing busy status. */ 2105 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 2106 dumping ? 31000 : 0)) < 0) { 2107 if (dumping) { 2108 device_printf(dev, 2109 "MVS reset: device not ready after 31000ms\n"); 2110 } else 2111 ch->resetting = 310; 2112 } else if (bootverbose) 2113 device_printf(dev, "MVS reset: device ready after %dms\n", i); 2114 ch->devices = 1; 2115 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 2116 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 2117 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 2118 if (ch->resetting) 2119 callout_reset(&ch->reset_timer, hz / 10, mvs_reset_to, dev); 2120 else 2121 xpt_release_simq(ch->sim, TRUE); 2122 } 2123 2124 static void 2125 mvs_softreset(device_t dev, union ccb *ccb) 2126 { 2127 struct mvs_channel *ch = device_get_softc(dev); 2128 int port = ccb->ccb_h.target_id & 0x0f; 2129 int i, stuck; 2130 uint8_t status; 2131 2132 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 2133 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 2134 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET); 2135 DELAY(10000); 2136 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 2137 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2138 /* Wait for clearing busy status. */ 2139 if ((i = mvs_wait(dev, 0, ATA_S_BUSY, ccb->ccb_h.timeout)) < 0) { 2140 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2141 stuck = 1; 2142 } else { 2143 status = mvs_getstatus(dev, 0); 2144 if (status & ATA_S_ERROR) 2145 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2146 else 2147 ccb->ccb_h.status |= CAM_REQ_CMP; 2148 if (status & ATA_S_DRQ) 2149 stuck = 1; 2150 else 2151 stuck = 0; 2152 } 2153 mvs_tfd_read(dev, ccb); 2154 2155 /* 2156 * XXX: If some device on PMP failed to soft-reset, 2157 * try to recover by sending dummy soft-reset to PMP. 2158 */ 2159 if (stuck && ch->pm_present && port != 15) { 2160 ATA_OUTB(ch->r_mem, SATA_SATAICTL, 2161 15 << SATA_SATAICTL_PMPTX_SHIFT); 2162 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET); 2163 DELAY(10000); 2164 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 2165 mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout); 2166 } 2167 2168 xpt_done(ccb); 2169 } 2170 2171 static int 2172 mvs_sata_connect(struct mvs_channel *ch) 2173 { 2174 u_int32_t status; 2175 int timeout, found = 0; 2176 2177 /* Wait up to 100ms for "connect well" */ 2178 for (timeout = 0; timeout < 1000 ; timeout++) { 2179 status = ATA_INL(ch->r_mem, SATA_SS); 2180 if ((status & SATA_SS_DET_MASK) != SATA_SS_DET_NO_DEVICE) 2181 found = 1; 2182 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 2183 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 2184 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) 2185 break; 2186 if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) { 2187 if (bootverbose) { 2188 device_printf(ch->dev, "SATA offline status=%08x\n", 2189 status); 2190 } 2191 return (0); 2192 } 2193 if (found == 0 && timeout >= 100) 2194 break; 2195 DELAY(100); 2196 } 2197 if (timeout >= 1000 || !found) { 2198 if (bootverbose) { 2199 device_printf(ch->dev, 2200 "SATA connect timeout time=%dus status=%08x\n", 2201 timeout * 100, status); 2202 } 2203 return (0); 2204 } 2205 if (bootverbose) { 2206 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2207 timeout * 100, status); 2208 } 2209 /* Clear SATA error register */ 2210 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 2211 return (1); 2212 } 2213 2214 static int 2215 mvs_sata_phy_reset(device_t dev) 2216 { 2217 struct mvs_channel *ch = device_get_softc(dev); 2218 int sata_rev; 2219 uint32_t val; 2220 2221 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2222 if (sata_rev == 1) 2223 val = SATA_SC_SPD_SPEED_GEN1; 2224 else if (sata_rev == 2) 2225 val = SATA_SC_SPD_SPEED_GEN2; 2226 else if (sata_rev == 3) 2227 val = SATA_SC_SPD_SPEED_GEN3; 2228 else 2229 val = 0; 2230 ATA_OUTL(ch->r_mem, SATA_SC, 2231 SATA_SC_DET_RESET | val | 2232 SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER); 2233 DELAY(1000); 2234 ATA_OUTL(ch->r_mem, SATA_SC, 2235 SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2236 (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER))); 2237 if (!mvs_sata_connect(ch)) { 2238 if (ch->pm_level > 0) 2239 ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE); 2240 return (0); 2241 } 2242 return (1); 2243 } 2244 2245 static int 2246 mvs_check_ids(device_t dev, union ccb *ccb) 2247 { 2248 struct mvs_channel *ch = device_get_softc(dev); 2249 2250 if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) { 2251 ccb->ccb_h.status = CAM_TID_INVALID; 2252 xpt_done(ccb); 2253 return (-1); 2254 } 2255 if (ccb->ccb_h.target_lun != 0) { 2256 ccb->ccb_h.status = CAM_LUN_INVALID; 2257 xpt_done(ccb); 2258 return (-1); 2259 } 2260 return (0); 2261 } 2262 2263 static void 2264 mvsaction(struct cam_sim *sim, union ccb *ccb) 2265 { 2266 device_t dev; 2267 struct mvs_channel *ch; 2268 2269 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n", 2270 ccb->ccb_h.func_code)); 2271 2272 ch = (struct mvs_channel *)cam_sim_softc(sim); 2273 dev = ch->dev; 2274 switch (ccb->ccb_h.func_code) { 2275 /* Common cases first */ 2276 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2277 case XPT_SCSI_IO: 2278 if (mvs_check_ids(dev, ccb)) 2279 return; 2280 if (ch->devices == 0 || 2281 (ch->pm_present == 0 && 2282 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2283 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2284 break; 2285 } 2286 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2287 /* Check for command collision. */ 2288 if (mvs_check_collision(dev, ccb)) { 2289 /* Freeze command. */ 2290 ch->frozen = ccb; 2291 /* We have only one frozen slot, so freeze simq also. */ 2292 xpt_freeze_simq(ch->sim, 1); 2293 return; 2294 } 2295 mvs_begin_transaction(dev, ccb); 2296 return; 2297 case XPT_EN_LUN: /* Enable LUN as a target */ 2298 case XPT_TARGET_IO: /* Execute target I/O request */ 2299 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2300 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2301 case XPT_ABORT: /* Abort the specified CCB */ 2302 /* XXX Implement */ 2303 ccb->ccb_h.status = CAM_REQ_INVALID; 2304 break; 2305 case XPT_SET_TRAN_SETTINGS: 2306 { 2307 struct ccb_trans_settings *cts = &ccb->cts; 2308 struct mvs_device *d; 2309 2310 if (mvs_check_ids(dev, ccb)) 2311 return; 2312 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2313 d = &ch->curr[ccb->ccb_h.target_id]; 2314 else 2315 d = &ch->user[ccb->ccb_h.target_id]; 2316 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2317 d->revision = cts->xport_specific.sata.revision; 2318 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2319 d->mode = cts->xport_specific.sata.mode; 2320 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) { 2321 d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048, 2322 cts->xport_specific.sata.bytecount); 2323 } 2324 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2325 d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags); 2326 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2327 ch->pm_present = cts->xport_specific.sata.pm_present; 2328 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2329 d->atapi = cts->xport_specific.sata.atapi; 2330 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2331 d->caps = cts->xport_specific.sata.caps; 2332 ccb->ccb_h.status = CAM_REQ_CMP; 2333 break; 2334 } 2335 case XPT_GET_TRAN_SETTINGS: 2336 /* Get default/user set transfer settings for the target */ 2337 { 2338 struct ccb_trans_settings *cts = &ccb->cts; 2339 struct mvs_device *d; 2340 uint32_t status; 2341 2342 if (mvs_check_ids(dev, ccb)) 2343 return; 2344 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2345 d = &ch->curr[ccb->ccb_h.target_id]; 2346 else 2347 d = &ch->user[ccb->ccb_h.target_id]; 2348 cts->protocol = PROTO_UNSPECIFIED; 2349 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2350 cts->transport = XPORT_SATA; 2351 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2352 cts->proto_specific.valid = 0; 2353 cts->xport_specific.sata.valid = 0; 2354 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2355 (ccb->ccb_h.target_id == 15 || 2356 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2357 status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK; 2358 if (status & 0x0f0) { 2359 cts->xport_specific.sata.revision = 2360 (status & 0x0f0) >> 4; 2361 cts->xport_specific.sata.valid |= 2362 CTS_SATA_VALID_REVISION; 2363 } 2364 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2365 // if (ch->pm_level) 2366 // cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2367 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2368 cts->xport_specific.sata.caps &= 2369 ch->user[ccb->ccb_h.target_id].caps; 2370 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2371 } else { 2372 cts->xport_specific.sata.revision = d->revision; 2373 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2374 cts->xport_specific.sata.caps = d->caps; 2375 if (cts->type == CTS_TYPE_CURRENT_SETTINGS/* && 2376 (ch->quirks & MVS_Q_GENIIE) == 0*/) 2377 cts->xport_specific.sata.caps &= ~CTS_SATA_CAPS_H_AN; 2378 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2379 } 2380 cts->xport_specific.sata.mode = d->mode; 2381 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2382 cts->xport_specific.sata.bytecount = d->bytecount; 2383 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2384 cts->xport_specific.sata.pm_present = ch->pm_present; 2385 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2386 cts->xport_specific.sata.tags = d->tags; 2387 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2388 cts->xport_specific.sata.atapi = d->atapi; 2389 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2390 ccb->ccb_h.status = CAM_REQ_CMP; 2391 break; 2392 } 2393 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2394 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2395 mvs_reset(dev); 2396 ccb->ccb_h.status = CAM_REQ_CMP; 2397 break; 2398 case XPT_TERM_IO: /* Terminate the I/O process */ 2399 /* XXX Implement */ 2400 ccb->ccb_h.status = CAM_REQ_INVALID; 2401 break; 2402 case XPT_PATH_INQ: /* Path routing inquiry */ 2403 { 2404 struct ccb_pathinq *cpi = &ccb->cpi; 2405 2406 cpi->version_num = 1; /* XXX??? */ 2407 cpi->hba_inquiry = PI_SDTR_ABLE; 2408 if (!(ch->quirks & MVS_Q_GENI)) { 2409 cpi->hba_inquiry |= PI_SATAPM; 2410 /* Gen-II is extremely slow with NCQ on PMP. */ 2411 if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0) 2412 cpi->hba_inquiry |= PI_TAG_ABLE; 2413 } 2414 cpi->target_sprt = 0; 2415 cpi->hba_misc = PIM_SEQSCAN; 2416 cpi->hba_eng_cnt = 0; 2417 if (!(ch->quirks & MVS_Q_GENI)) 2418 cpi->max_target = 15; 2419 else 2420 cpi->max_target = 0; 2421 cpi->max_lun = 0; 2422 cpi->initiator_id = 0; 2423 cpi->bus_id = cam_sim_bus(sim); 2424 cpi->base_transfer_speed = 150000; 2425 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2426 strncpy(cpi->hba_vid, "Marvell", HBA_IDLEN); 2427 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2428 cpi->unit_number = cam_sim_unit(sim); 2429 cpi->transport = XPORT_SATA; 2430 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2431 cpi->protocol = PROTO_ATA; 2432 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2433 cpi->maxio = MAXPHYS; 2434 cpi->ccb_h.status = CAM_REQ_CMP; 2435 break; 2436 } 2437 default: 2438 ccb->ccb_h.status = CAM_REQ_INVALID; 2439 break; 2440 } 2441 xpt_done(ccb); 2442 } 2443 2444 static void 2445 mvspoll(struct cam_sim *sim) 2446 { 2447 struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim); 2448 struct mvs_intr_arg arg; 2449 2450 arg.arg = ch->dev; 2451 arg.cause = 2 | 4; /* XXX */ 2452 mvs_ch_intr(&arg); 2453 if (ch->resetting != 0 && 2454 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2455 ch->resetpolldiv = 1000; 2456 mvs_reset_to(ch->dev); 2457 } 2458 } 2459
Cache object: d5284edcd054da22e6115044269368e8
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