Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/mvs/mvs_soc.c
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1 /*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD: releng/8.4/sys/dev/mvs/mvs_soc.c 237379 2012-06-21 10:41:27Z mav $"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <vm/uma.h> 40 #include <machine/stdarg.h> 41 #include <machine/resource.h> 42 #include <machine/bus.h> 43 #include <sys/rman.h> 44 #include <arm/mv/mvreg.h> 45 #include <arm/mv/mvvar.h> 46 #include "mvs.h" 47 48 /* local prototypes */ 49 static int mvs_setup_interrupt(device_t dev); 50 static void mvs_intr(void *data); 51 static int mvs_suspend(device_t dev); 52 static int mvs_resume(device_t dev); 53 static int mvs_ctlr_setup(device_t dev); 54 55 static struct { 56 uint32_t id; 57 uint8_t rev; 58 const char *name; 59 int ports; 60 int quirks; 61 } mvs_ids[] = { 62 {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 63 {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 64 {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 65 {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC}, 66 {0, 0x00, NULL, 0, 0} 67 }; 68 69 static int 70 mvs_probe(device_t dev) 71 { 72 char buf[64]; 73 int i; 74 uint32_t devid, revid; 75 76 soc_id(&devid, &revid); 77 for (i = 0; mvs_ids[i].id != 0; i++) { 78 if (mvs_ids[i].id == devid && 79 mvs_ids[i].rev <= revid) { 80 snprintf(buf, sizeof(buf), "%s SATA controller", 81 mvs_ids[i].name); 82 device_set_desc_copy(dev, buf); 83 return (BUS_PROBE_VENDOR); 84 } 85 } 86 return (ENXIO); 87 } 88 89 static int 90 mvs_attach(device_t dev) 91 { 92 struct mvs_controller *ctlr = device_get_softc(dev); 93 device_t child; 94 int error, unit, i; 95 uint32_t devid, revid; 96 97 soc_id(&devid, &revid); 98 ctlr->dev = dev; 99 i = 0; 100 while (mvs_ids[i].id != 0 && 101 (mvs_ids[i].id != devid || 102 mvs_ids[i].rev > revid)) 103 i++; 104 ctlr->channels = mvs_ids[i].ports; 105 ctlr->quirks = mvs_ids[i].quirks; 106 resource_int_value(device_get_name(dev), 107 device_get_unit(dev), "ccc", &ctlr->ccc); 108 ctlr->cccc = 8; 109 resource_int_value(device_get_name(dev), 110 device_get_unit(dev), "cccc", &ctlr->cccc); 111 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 112 ctlr->ccc = 0; 113 ctlr->cccc = 0; 114 } 115 if (ctlr->ccc > 100000) 116 ctlr->ccc = 100000; 117 device_printf(dev, 118 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 119 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 120 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 121 ctlr->channels, 122 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 123 ((ctlr->quirks & MVS_Q_GENI) ? 124 "not supported" : "supported"), 125 ((ctlr->quirks & MVS_Q_GENIIE) ? 126 " with FBS" : "")); 127 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 128 /* We should have a memory BAR(0). */ 129 ctlr->r_rid = 0; 130 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 131 &ctlr->r_rid, RF_ACTIVE))) 132 return ENXIO; 133 if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0) 134 ctlr->quirks |= MVS_Q_SOC65; 135 /* Setup our own memory management for channels. */ 136 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 137 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 138 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 139 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 140 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 141 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 142 return (error); 143 } 144 if ((error = rman_manage_region(&ctlr->sc_iomem, 145 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 146 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 147 rman_fini(&ctlr->sc_iomem); 148 return (error); 149 } 150 mvs_ctlr_setup(dev); 151 /* Setup interrupts. */ 152 if (mvs_setup_interrupt(dev)) { 153 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 154 rman_fini(&ctlr->sc_iomem); 155 return ENXIO; 156 } 157 /* Attach all channels on this controller */ 158 for (unit = 0; unit < ctlr->channels; unit++) { 159 child = device_add_child(dev, "mvsch", -1); 160 if (child == NULL) 161 device_printf(dev, "failed to add channel device\n"); 162 else 163 device_set_ivars(child, (void *)(intptr_t)unit); 164 } 165 bus_generic_attach(dev); 166 return 0; 167 } 168 169 static int 170 mvs_detach(device_t dev) 171 { 172 struct mvs_controller *ctlr = device_get_softc(dev); 173 device_t *children; 174 int nchildren, i; 175 176 /* Detach & delete all children */ 177 if (!device_get_children(dev, &children, &nchildren)) { 178 for (i = 0; i < nchildren; i++) 179 device_delete_child(dev, children[i]); 180 free(children, M_TEMP); 181 } 182 /* Free interrupt. */ 183 if (ctlr->irq.r_irq) { 184 bus_teardown_intr(dev, ctlr->irq.r_irq, 185 ctlr->irq.handle); 186 bus_release_resource(dev, SYS_RES_IRQ, 187 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 188 } 189 /* Free memory. */ 190 rman_fini(&ctlr->sc_iomem); 191 if (ctlr->r_mem) 192 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 193 mtx_destroy(&ctlr->mtx); 194 return (0); 195 } 196 197 static int 198 mvs_ctlr_setup(device_t dev) 199 { 200 struct mvs_controller *ctlr = device_get_softc(dev); 201 int ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0; 202 203 /* Mask chip interrupts */ 204 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 205 /* Clear HC interrupts */ 206 ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000); 207 /* Clear chip interrupts */ 208 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0); 209 /* Configure per-HC CCC */ 210 if (ccc && bootverbose) { 211 device_printf(dev, 212 "CCC with %dus/%dcmd enabled\n", 213 ctlr->ccc, ctlr->cccc); 214 } 215 ccc *= 150; 216 ATA_OUTL(ctlr->r_mem, HC_ICT, cccc); 217 ATA_OUTL(ctlr->r_mem, HC_ITT, ccc); 218 if (ccc) 219 ccim |= IC_HC0_COAL_DONE; 220 /* Enable chip interrupts */ 221 ctlr->gmim = (ccc ? IC_HC0_COAL_DONE : IC_DONE_HC0) | IC_ERR_HC0; 222 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 223 return (0); 224 } 225 226 static void 227 mvs_edma(device_t dev, device_t child, int mode) 228 { 229 struct mvs_controller *ctlr = device_get_softc(dev); 230 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 231 int bit = IC_DONE_IRQ << (unit * 2); 232 233 if (ctlr->ccc == 0) 234 return; 235 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 236 mtx_lock(&ctlr->mtx); 237 if (mode == MVS_EDMA_OFF) 238 ctlr->pmim |= bit; 239 else 240 ctlr->pmim &= ~bit; 241 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim); 242 mtx_unlock(&ctlr->mtx); 243 } 244 245 static int 246 mvs_suspend(device_t dev) 247 { 248 struct mvs_controller *ctlr = device_get_softc(dev); 249 250 bus_generic_suspend(dev); 251 /* Mask chip interrupts */ 252 ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000); 253 return 0; 254 } 255 256 static int 257 mvs_resume(device_t dev) 258 { 259 260 mvs_ctlr_setup(dev); 261 return (bus_generic_resume(dev)); 262 } 263 264 static int 265 mvs_setup_interrupt(device_t dev) 266 { 267 struct mvs_controller *ctlr = device_get_softc(dev); 268 269 /* Allocate all IRQs. */ 270 ctlr->irq.r_irq_rid = 0; 271 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 272 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 273 device_printf(dev, "unable to map interrupt\n"); 274 return (ENXIO); 275 } 276 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 277 mvs_intr, ctlr, &ctlr->irq.handle))) { 278 device_printf(dev, "unable to setup interrupt\n"); 279 bus_release_resource(dev, SYS_RES_IRQ, 280 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 281 ctlr->irq.r_irq = 0; 282 return (ENXIO); 283 } 284 return (0); 285 } 286 287 /* 288 * Common case interrupt handler. 289 */ 290 static void 291 mvs_intr(void *data) 292 { 293 struct mvs_controller *ctlr = data; 294 struct mvs_intr_arg arg; 295 void (*function)(void *); 296 int p; 297 u_int32_t ic, aic; 298 299 ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC); 300 if ((ic & IC_HC0) == 0) 301 return; 302 /* Acknowledge interrupts of this HC. */ 303 aic = 0; 304 if (ic & (IC_DONE_IRQ << 0)) 305 aic |= HC_IC_DONE(0) | HC_IC_DEV(0); 306 if (ic & (IC_DONE_IRQ << 2)) 307 aic |= HC_IC_DONE(1) | HC_IC_DEV(1); 308 if (ic & (IC_DONE_IRQ << 4)) 309 aic |= HC_IC_DONE(2) | HC_IC_DEV(2); 310 if (ic & (IC_DONE_IRQ << 6)) 311 aic |= HC_IC_DONE(3) | HC_IC_DEV(3); 312 if (ic & IC_HC0_COAL_DONE) 313 aic |= HC_IC_COAL; 314 ATA_OUTL(ctlr->r_mem, HC_IC, ~aic); 315 /* Call per-port interrupt handler. */ 316 for (p = 0; p < ctlr->channels; p++) { 317 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 318 if ((arg.cause != 0) && 319 (function = ctlr->interrupt[p].function)) { 320 arg.arg = ctlr->interrupt[p].argument; 321 function(&arg); 322 } 323 ic >>= 2; 324 } 325 } 326 327 static struct resource * 328 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 329 u_long start, u_long end, u_long count, u_int flags) 330 { 331 struct mvs_controller *ctlr = device_get_softc(dev); 332 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 333 struct resource *res = NULL; 334 int offset = PORT_BASE(unit & 0x03); 335 long st; 336 337 switch (type) { 338 case SYS_RES_MEMORY: 339 st = rman_get_start(ctlr->r_mem); 340 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 341 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 342 if (res) { 343 bus_space_handle_t bsh; 344 bus_space_tag_t bst; 345 bsh = rman_get_bushandle(ctlr->r_mem); 346 bst = rman_get_bustag(ctlr->r_mem); 347 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 348 rman_set_bushandle(res, bsh); 349 rman_set_bustag(res, bst); 350 } 351 break; 352 case SYS_RES_IRQ: 353 if (*rid == ATA_IRQ_RID) 354 res = ctlr->irq.r_irq; 355 break; 356 } 357 return (res); 358 } 359 360 static int 361 mvs_release_resource(device_t dev, device_t child, int type, int rid, 362 struct resource *r) 363 { 364 365 switch (type) { 366 case SYS_RES_MEMORY: 367 rman_release_resource(r); 368 return (0); 369 case SYS_RES_IRQ: 370 if (rid != ATA_IRQ_RID) 371 return ENOENT; 372 return (0); 373 } 374 return (EINVAL); 375 } 376 377 static int 378 mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 379 int flags, driver_filter_t *filter, driver_intr_t *function, 380 void *argument, void **cookiep) 381 { 382 struct mvs_controller *ctlr = device_get_softc(dev); 383 int unit = (intptr_t)device_get_ivars(child); 384 385 if (filter != NULL) { 386 printf("mvs.c: we cannot use a filter here\n"); 387 return (EINVAL); 388 } 389 ctlr->interrupt[unit].function = function; 390 ctlr->interrupt[unit].argument = argument; 391 return (0); 392 } 393 394 static int 395 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 396 void *cookie) 397 { 398 struct mvs_controller *ctlr = device_get_softc(dev); 399 int unit = (intptr_t)device_get_ivars(child); 400 401 ctlr->interrupt[unit].function = NULL; 402 ctlr->interrupt[unit].argument = NULL; 403 return (0); 404 } 405 406 static int 407 mvs_print_child(device_t dev, device_t child) 408 { 409 int retval; 410 411 retval = bus_print_child_header(dev, child); 412 retval += printf(" at channel %d", 413 (int)(intptr_t)device_get_ivars(child)); 414 retval += bus_print_child_footer(dev, child); 415 416 return (retval); 417 } 418 419 static int 420 mvs_child_location_str(device_t dev, device_t child, char *buf, 421 size_t buflen) 422 { 423 424 snprintf(buf, buflen, "channel=%d", 425 (int)(intptr_t)device_get_ivars(child)); 426 return (0); 427 } 428 429 static device_method_t mvs_methods[] = { 430 DEVMETHOD(device_probe, mvs_probe), 431 DEVMETHOD(device_attach, mvs_attach), 432 DEVMETHOD(device_detach, mvs_detach), 433 DEVMETHOD(device_suspend, mvs_suspend), 434 DEVMETHOD(device_resume, mvs_resume), 435 DEVMETHOD(bus_print_child, mvs_print_child), 436 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 437 DEVMETHOD(bus_release_resource, mvs_release_resource), 438 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 439 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 440 DEVMETHOD(mvs_edma, mvs_edma), 441 DEVMETHOD(bus_child_location_str, mvs_child_location_str), 442 { 0, 0 } 443 }; 444 static driver_t mvs_driver = { 445 "sata", 446 mvs_methods, 447 sizeof(struct mvs_controller) 448 }; 449 DRIVER_MODULE(sata, mbus, mvs_driver, mvs_devclass, 0, 0); 450 MODULE_VERSION(sata, 1); 451
Cache object: 03d57caf83b2ccf541a8fbc73a543702
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