FreeBSD/Linux Kernel Cross Reference
sys/dev/my/if_my.c
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Written by: yen_cw@myson.com.tw
5 * Copyright (c) 2002 Myson Technology Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification, immediately at the beginning of the file.
14 * 2. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD: releng/12.0/sys/dev/my/if_my.c 338949 2018-09-26 17:12:30Z imp $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
38 #include <sys/mbuf.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
43 #include <sys/types.h>
44 #include <sys/module.h>
45 #include <sys/lock.h>
46 #include <sys/mutex.h>
47
48 #define NBPFILTER 1
49
50 #include <net/if.h>
51 #include <net/if_var.h>
52 #include <net/if_arp.h>
53 #include <net/ethernet.h>
54 #include <net/if_media.h>
55 #include <net/if_types.h>
56 #include <net/if_dl.h>
57 #include <net/bpf.h>
58
59 #include <vm/vm.h> /* for vtophys */
60 #include <vm/pmap.h> /* for vtophys */
61 #include <machine/bus.h>
62 #include <machine/resource.h>
63 #include <sys/bus.h>
64 #include <sys/rman.h>
65
66 #include <dev/pci/pcireg.h>
67 #include <dev/pci/pcivar.h>
68
69 /*
70 * #define MY_USEIOSPACE
71 */
72
73 static int MY_USEIOSPACE = 1;
74
75 #ifdef MY_USEIOSPACE
76 #define MY_RES SYS_RES_IOPORT
77 #define MY_RID MY_PCI_LOIO
78 #else
79 #define MY_RES SYS_RES_MEMORY
80 #define MY_RID MY_PCI_LOMEM
81 #endif
82
83
84 #include <dev/my/if_myreg.h>
85
86 /*
87 * Various supported device vendors/types and their names.
88 */
89 struct my_type *my_info_tmp;
90 static struct my_type my_devs[] = {
91 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
92 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
93 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
94 {0, 0, NULL}
95 };
96
97 /*
98 * Various supported PHY vendors/types and their names. Note that this driver
99 * will work with pretty much any MII-compliant PHY, so failure to positively
100 * identify the chip is not a fatal error.
101 */
102 static struct my_type my_phys[] = {
103 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
104 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
105 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
106 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
107 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
108 {0, 0, "<MII-compliant physical interface>"}
109 };
110
111 static int my_probe(device_t);
112 static int my_attach(device_t);
113 static int my_detach(device_t);
114 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
115 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
116 static void my_rxeof(struct my_softc *);
117 static void my_txeof(struct my_softc *);
118 static void my_txeoc(struct my_softc *);
119 static void my_intr(void *);
120 static void my_start(struct ifnet *);
121 static void my_start_locked(struct ifnet *);
122 static int my_ioctl(struct ifnet *, u_long, caddr_t);
123 static void my_init(void *);
124 static void my_init_locked(struct my_softc *);
125 static void my_stop(struct my_softc *);
126 static void my_autoneg_timeout(void *);
127 static void my_watchdog(void *);
128 static int my_shutdown(device_t);
129 static int my_ifmedia_upd(struct ifnet *);
130 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
131 static u_int16_t my_phy_readreg(struct my_softc *, int);
132 static void my_phy_writereg(struct my_softc *, int, int);
133 static void my_autoneg_xmit(struct my_softc *);
134 static void my_autoneg_mii(struct my_softc *, int, int);
135 static void my_setmode_mii(struct my_softc *, int);
136 static void my_getmode_mii(struct my_softc *);
137 static void my_setcfg(struct my_softc *, int);
138 static void my_setmulti(struct my_softc *);
139 static void my_reset(struct my_softc *);
140 static int my_list_rx_init(struct my_softc *);
141 static int my_list_tx_init(struct my_softc *);
142 static long my_send_cmd_to_phy(struct my_softc *, int, int);
143
144 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
145 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
146
147 static device_method_t my_methods[] = {
148 /* Device interface */
149 DEVMETHOD(device_probe, my_probe),
150 DEVMETHOD(device_attach, my_attach),
151 DEVMETHOD(device_detach, my_detach),
152 DEVMETHOD(device_shutdown, my_shutdown),
153
154 DEVMETHOD_END
155 };
156
157 static driver_t my_driver = {
158 "my",
159 my_methods,
160 sizeof(struct my_softc)
161 };
162
163 static devclass_t my_devclass;
164
165 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0);
166 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, my, my_devs,
167 nitems(my_devs) - 1);
168 MODULE_DEPEND(my, pci, 1, 1, 1);
169 MODULE_DEPEND(my, ether, 1, 1, 1);
170
171 static long
172 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
173 {
174 long miir;
175 int i;
176 int mask, data;
177
178 MY_LOCK_ASSERT(sc);
179
180 /* enable MII output */
181 miir = CSR_READ_4(sc, MY_MANAGEMENT);
182 miir &= 0xfffffff0;
183
184 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
185
186 /* send 32 1's preamble */
187 for (i = 0; i < 32; i++) {
188 /* low MDC; MDO is already high (miir) */
189 miir &= ~MY_MASK_MIIR_MII_MDC;
190 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
191
192 /* high MDC */
193 miir |= MY_MASK_MIIR_MII_MDC;
194 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
195 }
196
197 /* calculate ST+OP+PHYAD+REGAD+TA */
198 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
199
200 /* sent out */
201 mask = 0x8000;
202 while (mask) {
203 /* low MDC, prepare MDO */
204 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
205 if (mask & data)
206 miir |= MY_MASK_MIIR_MII_MDO;
207
208 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
209 /* high MDC */
210 miir |= MY_MASK_MIIR_MII_MDC;
211 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
212 DELAY(30);
213
214 /* next */
215 mask >>= 1;
216 if (mask == 0x2 && opcode == MY_OP_READ)
217 miir &= ~MY_MASK_MIIR_MII_WRITE;
218 }
219
220 return miir;
221 }
222
223
224 static u_int16_t
225 my_phy_readreg(struct my_softc * sc, int reg)
226 {
227 long miir;
228 int mask, data;
229
230 MY_LOCK_ASSERT(sc);
231
232 if (sc->my_info->my_did == MTD803ID)
233 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
234 else {
235 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
236
237 /* read data */
238 mask = 0x8000;
239 data = 0;
240 while (mask) {
241 /* low MDC */
242 miir &= ~MY_MASK_MIIR_MII_MDC;
243 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
244
245 /* read MDI */
246 miir = CSR_READ_4(sc, MY_MANAGEMENT);
247 if (miir & MY_MASK_MIIR_MII_MDI)
248 data |= mask;
249
250 /* high MDC, and wait */
251 miir |= MY_MASK_MIIR_MII_MDC;
252 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
253 DELAY(30);
254
255 /* next */
256 mask >>= 1;
257 }
258
259 /* low MDC */
260 miir &= ~MY_MASK_MIIR_MII_MDC;
261 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
262 }
263
264 return (u_int16_t) data;
265 }
266
267
268 static void
269 my_phy_writereg(struct my_softc * sc, int reg, int data)
270 {
271 long miir;
272 int mask;
273
274 MY_LOCK_ASSERT(sc);
275
276 if (sc->my_info->my_did == MTD803ID)
277 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
278 else {
279 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
280
281 /* write data */
282 mask = 0x8000;
283 while (mask) {
284 /* low MDC, prepare MDO */
285 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
286 if (mask & data)
287 miir |= MY_MASK_MIIR_MII_MDO;
288 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
289 DELAY(1);
290
291 /* high MDC */
292 miir |= MY_MASK_MIIR_MII_MDC;
293 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
294 DELAY(1);
295
296 /* next */
297 mask >>= 1;
298 }
299
300 /* low MDC */
301 miir &= ~MY_MASK_MIIR_MII_MDC;
302 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
303 }
304 return;
305 }
306
307
308 /*
309 * Program the 64-bit multicast hash filter.
310 */
311 static void
312 my_setmulti(struct my_softc * sc)
313 {
314 struct ifnet *ifp;
315 int h = 0;
316 u_int32_t hashes[2] = {0, 0};
317 struct ifmultiaddr *ifma;
318 u_int32_t rxfilt;
319 int mcnt = 0;
320
321 MY_LOCK_ASSERT(sc);
322
323 ifp = sc->my_ifp;
324
325 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
326
327 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
328 rxfilt |= MY_AM;
329 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
330 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
331 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
332
333 return;
334 }
335 /* first, zot all the existing hash bits */
336 CSR_WRITE_4(sc, MY_MAR0, 0);
337 CSR_WRITE_4(sc, MY_MAR1, 0);
338
339 /* now program new ones */
340 if_maddr_rlock(ifp);
341 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
342 if (ifma->ifma_addr->sa_family != AF_LINK)
343 continue;
344 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
345 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
346 if (h < 32)
347 hashes[0] |= (1 << h);
348 else
349 hashes[1] |= (1 << (h - 32));
350 mcnt++;
351 }
352 if_maddr_runlock(ifp);
353
354 if (mcnt)
355 rxfilt |= MY_AM;
356 else
357 rxfilt &= ~MY_AM;
358 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
359 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
360 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
361 return;
362 }
363
364 /*
365 * Initiate an autonegotiation session.
366 */
367 static void
368 my_autoneg_xmit(struct my_softc * sc)
369 {
370 u_int16_t phy_sts = 0;
371
372 MY_LOCK_ASSERT(sc);
373
374 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
375 DELAY(500);
376 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
377
378 phy_sts = my_phy_readreg(sc, PHY_BMCR);
379 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
380 my_phy_writereg(sc, PHY_BMCR, phy_sts);
381
382 return;
383 }
384
385 static void
386 my_autoneg_timeout(void *arg)
387 {
388 struct my_softc *sc;
389
390 sc = arg;
391 MY_LOCK_ASSERT(sc);
392 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
393 }
394
395 /*
396 * Invoke autonegotiation on a PHY.
397 */
398 static void
399 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
400 {
401 u_int16_t phy_sts = 0, media, advert, ability;
402 u_int16_t ability2 = 0;
403 struct ifnet *ifp;
404 struct ifmedia *ifm;
405
406 MY_LOCK_ASSERT(sc);
407
408 ifm = &sc->ifmedia;
409 ifp = sc->my_ifp;
410
411 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
412
413 #ifndef FORCE_AUTONEG_TFOUR
414 /*
415 * First, see if autoneg is supported. If not, there's no point in
416 * continuing.
417 */
418 phy_sts = my_phy_readreg(sc, PHY_BMSR);
419 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
420 if (verbose)
421 device_printf(sc->my_dev,
422 "autonegotiation not supported\n");
423 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
424 return;
425 }
426 #endif
427 switch (flag) {
428 case MY_FLAG_FORCEDELAY:
429 /*
430 * XXX Never use this option anywhere but in the probe
431 * routine: making the kernel stop dead in its tracks for
432 * three whole seconds after we've gone multi-user is really
433 * bad manners.
434 */
435 my_autoneg_xmit(sc);
436 DELAY(5000000);
437 break;
438 case MY_FLAG_SCHEDDELAY:
439 /*
440 * Wait for the transmitter to go idle before starting an
441 * autoneg session, otherwise my_start() may clobber our
442 * timeout, and we don't want to allow transmission during an
443 * autoneg session since that can screw it up.
444 */
445 if (sc->my_cdata.my_tx_head != NULL) {
446 sc->my_want_auto = 1;
447 MY_UNLOCK(sc);
448 return;
449 }
450 my_autoneg_xmit(sc);
451 callout_reset(&sc->my_autoneg_timer, hz * 5, my_autoneg_timeout,
452 sc);
453 sc->my_autoneg = 1;
454 sc->my_want_auto = 0;
455 return;
456 case MY_FLAG_DELAYTIMEO:
457 callout_stop(&sc->my_autoneg_timer);
458 sc->my_autoneg = 0;
459 break;
460 default:
461 device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag);
462 return;
463 }
464
465 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
466 if (verbose)
467 device_printf(sc->my_dev, "autoneg complete, ");
468 phy_sts = my_phy_readreg(sc, PHY_BMSR);
469 } else {
470 if (verbose)
471 device_printf(sc->my_dev, "autoneg not complete, ");
472 }
473
474 media = my_phy_readreg(sc, PHY_BMCR);
475
476 /* Link is good. Report modes and set duplex mode. */
477 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
478 if (verbose)
479 device_printf(sc->my_dev, "link status good. ");
480 advert = my_phy_readreg(sc, PHY_ANAR);
481 ability = my_phy_readreg(sc, PHY_LPAR);
482 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
483 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
484 ability2 = my_phy_readreg(sc, PHY_1000SR);
485 if (ability2 & PHY_1000SR_1000BTXFULL) {
486 advert = 0;
487 ability = 0;
488 /*
489 * this version did not support 1000M,
490 * ifm->ifm_media =
491 * IFM_ETHER|IFM_1000_T|IFM_FDX;
492 */
493 ifm->ifm_media =
494 IFM_ETHER | IFM_100_TX | IFM_FDX;
495 media &= ~PHY_BMCR_SPEEDSEL;
496 media |= PHY_BMCR_1000;
497 media |= PHY_BMCR_DUPLEX;
498 printf("(full-duplex, 1000Mbps)\n");
499 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
500 advert = 0;
501 ability = 0;
502 /*
503 * this version did not support 1000M,
504 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
505 */
506 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
507 media &= ~PHY_BMCR_SPEEDSEL;
508 media &= ~PHY_BMCR_DUPLEX;
509 media |= PHY_BMCR_1000;
510 printf("(half-duplex, 1000Mbps)\n");
511 }
512 }
513 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
514 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
515 media |= PHY_BMCR_SPEEDSEL;
516 media &= ~PHY_BMCR_DUPLEX;
517 printf("(100baseT4)\n");
518 } else if (advert & PHY_ANAR_100BTXFULL &&
519 ability & PHY_ANAR_100BTXFULL) {
520 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
521 media |= PHY_BMCR_SPEEDSEL;
522 media |= PHY_BMCR_DUPLEX;
523 printf("(full-duplex, 100Mbps)\n");
524 } else if (advert & PHY_ANAR_100BTXHALF &&
525 ability & PHY_ANAR_100BTXHALF) {
526 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
527 media |= PHY_BMCR_SPEEDSEL;
528 media &= ~PHY_BMCR_DUPLEX;
529 printf("(half-duplex, 100Mbps)\n");
530 } else if (advert & PHY_ANAR_10BTFULL &&
531 ability & PHY_ANAR_10BTFULL) {
532 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
533 media &= ~PHY_BMCR_SPEEDSEL;
534 media |= PHY_BMCR_DUPLEX;
535 printf("(full-duplex, 10Mbps)\n");
536 } else if (advert) {
537 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
538 media &= ~PHY_BMCR_SPEEDSEL;
539 media &= ~PHY_BMCR_DUPLEX;
540 printf("(half-duplex, 10Mbps)\n");
541 }
542 media &= ~PHY_BMCR_AUTONEGENBL;
543
544 /* Set ASIC's duplex mode to match the PHY. */
545 my_phy_writereg(sc, PHY_BMCR, media);
546 my_setcfg(sc, media);
547 } else {
548 if (verbose)
549 device_printf(sc->my_dev, "no carrier\n");
550 }
551
552 my_init_locked(sc);
553 if (sc->my_tx_pend) {
554 sc->my_autoneg = 0;
555 sc->my_tx_pend = 0;
556 my_start_locked(ifp);
557 }
558 return;
559 }
560
561 /*
562 * To get PHY ability.
563 */
564 static void
565 my_getmode_mii(struct my_softc * sc)
566 {
567 u_int16_t bmsr;
568 struct ifnet *ifp;
569
570 MY_LOCK_ASSERT(sc);
571 ifp = sc->my_ifp;
572 bmsr = my_phy_readreg(sc, PHY_BMSR);
573 if (bootverbose)
574 device_printf(sc->my_dev, "PHY status word: %x\n", bmsr);
575
576 /* fallback */
577 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
578
579 if (bmsr & PHY_BMSR_10BTHALF) {
580 if (bootverbose)
581 device_printf(sc->my_dev,
582 "10Mbps half-duplex mode supported\n");
583 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
584 0, NULL);
585 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
586 }
587 if (bmsr & PHY_BMSR_10BTFULL) {
588 if (bootverbose)
589 device_printf(sc->my_dev,
590 "10Mbps full-duplex mode supported\n");
591
592 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
593 0, NULL);
594 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
595 }
596 if (bmsr & PHY_BMSR_100BTXHALF) {
597 if (bootverbose)
598 device_printf(sc->my_dev,
599 "100Mbps half-duplex mode supported\n");
600 ifp->if_baudrate = 100000000;
601 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
602 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
603 0, NULL);
604 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
605 }
606 if (bmsr & PHY_BMSR_100BTXFULL) {
607 if (bootverbose)
608 device_printf(sc->my_dev,
609 "100Mbps full-duplex mode supported\n");
610 ifp->if_baudrate = 100000000;
611 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
612 0, NULL);
613 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
614 }
615 /* Some also support 100BaseT4. */
616 if (bmsr & PHY_BMSR_100BT4) {
617 if (bootverbose)
618 device_printf(sc->my_dev, "100baseT4 mode supported\n");
619 ifp->if_baudrate = 100000000;
620 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
621 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
622 #ifdef FORCE_AUTONEG_TFOUR
623 if (bootverbose)
624 device_printf(sc->my_dev,
625 "forcing on autoneg support for BT4\n");
626 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
627 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
628 #endif
629 }
630 #if 0 /* this version did not support 1000M, */
631 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
632 if (bootverbose)
633 device_printf(sc->my_dev,
634 "1000Mbps half-duplex mode supported\n");
635
636 ifp->if_baudrate = 1000000000;
637 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
638 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
639 0, NULL);
640 if (bootverbose)
641 device_printf(sc->my_dev,
642 "1000Mbps full-duplex mode supported\n");
643 ifp->if_baudrate = 1000000000;
644 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
645 0, NULL);
646 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
647 }
648 #endif
649 if (bmsr & PHY_BMSR_CANAUTONEG) {
650 if (bootverbose)
651 device_printf(sc->my_dev, "autoneg supported\n");
652 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
653 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
654 }
655 return;
656 }
657
658 /*
659 * Set speed and duplex mode.
660 */
661 static void
662 my_setmode_mii(struct my_softc * sc, int media)
663 {
664 u_int16_t bmcr;
665
666 MY_LOCK_ASSERT(sc);
667 /*
668 * If an autoneg session is in progress, stop it.
669 */
670 if (sc->my_autoneg) {
671 device_printf(sc->my_dev, "canceling autoneg session\n");
672 callout_stop(&sc->my_autoneg_timer);
673 sc->my_autoneg = sc->my_want_auto = 0;
674 bmcr = my_phy_readreg(sc, PHY_BMCR);
675 bmcr &= ~PHY_BMCR_AUTONEGENBL;
676 my_phy_writereg(sc, PHY_BMCR, bmcr);
677 }
678 device_printf(sc->my_dev, "selecting MII, ");
679 bmcr = my_phy_readreg(sc, PHY_BMCR);
680 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
681 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
682
683 #if 0 /* this version did not support 1000M, */
684 if (IFM_SUBTYPE(media) == IFM_1000_T) {
685 printf("1000Mbps/T4, half-duplex\n");
686 bmcr &= ~PHY_BMCR_SPEEDSEL;
687 bmcr &= ~PHY_BMCR_DUPLEX;
688 bmcr |= PHY_BMCR_1000;
689 }
690 #endif
691 if (IFM_SUBTYPE(media) == IFM_100_T4) {
692 printf("100Mbps/T4, half-duplex\n");
693 bmcr |= PHY_BMCR_SPEEDSEL;
694 bmcr &= ~PHY_BMCR_DUPLEX;
695 }
696 if (IFM_SUBTYPE(media) == IFM_100_TX) {
697 printf("100Mbps, ");
698 bmcr |= PHY_BMCR_SPEEDSEL;
699 }
700 if (IFM_SUBTYPE(media) == IFM_10_T) {
701 printf("10Mbps, ");
702 bmcr &= ~PHY_BMCR_SPEEDSEL;
703 }
704 if ((media & IFM_GMASK) == IFM_FDX) {
705 printf("full duplex\n");
706 bmcr |= PHY_BMCR_DUPLEX;
707 } else {
708 printf("half duplex\n");
709 bmcr &= ~PHY_BMCR_DUPLEX;
710 }
711 my_phy_writereg(sc, PHY_BMCR, bmcr);
712 my_setcfg(sc, bmcr);
713 return;
714 }
715
716 /*
717 * The Myson manual states that in order to fiddle with the 'full-duplex' and
718 * '100Mbps' bits in the netconfig register, we first have to put the
719 * transmit and/or receive logic in the idle state.
720 */
721 static void
722 my_setcfg(struct my_softc * sc, int bmcr)
723 {
724 int i, restart = 0;
725
726 MY_LOCK_ASSERT(sc);
727 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
728 restart = 1;
729 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
730 for (i = 0; i < MY_TIMEOUT; i++) {
731 DELAY(10);
732 if (!(CSR_READ_4(sc, MY_TCRRCR) &
733 (MY_TXRUN | MY_RXRUN)))
734 break;
735 }
736 if (i == MY_TIMEOUT)
737 device_printf(sc->my_dev,
738 "failed to force tx and rx to idle \n");
739 }
740 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
741 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
742 if (bmcr & PHY_BMCR_1000)
743 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
744 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
745 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
746 if (bmcr & PHY_BMCR_DUPLEX)
747 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
748 else
749 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
750 if (restart)
751 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
752 return;
753 }
754
755 static void
756 my_reset(struct my_softc * sc)
757 {
758 int i;
759
760 MY_LOCK_ASSERT(sc);
761 MY_SETBIT(sc, MY_BCR, MY_SWR);
762 for (i = 0; i < MY_TIMEOUT; i++) {
763 DELAY(10);
764 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
765 break;
766 }
767 if (i == MY_TIMEOUT)
768 device_printf(sc->my_dev, "reset never completed!\n");
769
770 /* Wait a little while for the chip to get its brains in order. */
771 DELAY(1000);
772 return;
773 }
774
775 /*
776 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
777 * list and return a device name if we find a match.
778 */
779 static int
780 my_probe(device_t dev)
781 {
782 struct my_type *t;
783
784 t = my_devs;
785 while (t->my_name != NULL) {
786 if ((pci_get_vendor(dev) == t->my_vid) &&
787 (pci_get_device(dev) == t->my_did)) {
788 device_set_desc(dev, t->my_name);
789 my_info_tmp = t;
790 return (BUS_PROBE_DEFAULT);
791 }
792 t++;
793 }
794 return (ENXIO);
795 }
796
797 /*
798 * Attach the interface. Allocate softc structures, do ifmedia setup and
799 * ethernet/BPF attach.
800 */
801 static int
802 my_attach(device_t dev)
803 {
804 int i;
805 u_char eaddr[ETHER_ADDR_LEN];
806 u_int32_t iobase;
807 struct my_softc *sc;
808 struct ifnet *ifp;
809 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
810 unsigned int round;
811 caddr_t roundptr;
812 struct my_type *p;
813 u_int16_t phy_vid, phy_did, phy_sts = 0;
814 int rid, error = 0;
815
816 sc = device_get_softc(dev);
817 sc->my_dev = dev;
818 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
819 MTX_DEF);
820 callout_init_mtx(&sc->my_autoneg_timer, &sc->my_mtx, 0);
821 callout_init_mtx(&sc->my_watchdog, &sc->my_mtx, 0);
822
823 /*
824 * Map control/status registers.
825 */
826 pci_enable_busmaster(dev);
827
828 if (my_info_tmp->my_did == MTD800ID) {
829 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
830 if (iobase & 0x300)
831 MY_USEIOSPACE = 0;
832 }
833
834 rid = MY_RID;
835 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
836
837 if (sc->my_res == NULL) {
838 device_printf(dev, "couldn't map ports/memory\n");
839 error = ENXIO;
840 goto destroy_mutex;
841 }
842 sc->my_btag = rman_get_bustag(sc->my_res);
843 sc->my_bhandle = rman_get_bushandle(sc->my_res);
844
845 rid = 0;
846 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
847 RF_SHAREABLE | RF_ACTIVE);
848
849 if (sc->my_irq == NULL) {
850 device_printf(dev, "couldn't map interrupt\n");
851 error = ENXIO;
852 goto release_io;
853 }
854
855 sc->my_info = my_info_tmp;
856
857 /* Reset the adapter. */
858 MY_LOCK(sc);
859 my_reset(sc);
860 MY_UNLOCK(sc);
861
862 /*
863 * Get station address
864 */
865 for (i = 0; i < ETHER_ADDR_LEN; ++i)
866 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
867
868 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
869 M_DEVBUF, M_NOWAIT);
870 if (sc->my_ldata_ptr == NULL) {
871 device_printf(dev, "no memory for list buffers!\n");
872 error = ENXIO;
873 goto release_irq;
874 }
875 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
876 round = (uintptr_t)sc->my_ldata_ptr & 0xF;
877 roundptr = sc->my_ldata_ptr;
878 for (i = 0; i < 8; i++) {
879 if (round % 8) {
880 round++;
881 roundptr++;
882 } else
883 break;
884 }
885 sc->my_ldata = (struct my_list_data *) roundptr;
886 bzero(sc->my_ldata, sizeof(struct my_list_data));
887
888 ifp = sc->my_ifp = if_alloc(IFT_ETHER);
889 if (ifp == NULL) {
890 device_printf(dev, "can not if_alloc()\n");
891 error = ENOSPC;
892 goto free_ldata;
893 }
894 ifp->if_softc = sc;
895 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
896 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
897 ifp->if_ioctl = my_ioctl;
898 ifp->if_start = my_start;
899 ifp->if_init = my_init;
900 ifp->if_baudrate = 10000000;
901 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
902 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
903 IFQ_SET_READY(&ifp->if_snd);
904
905 if (sc->my_info->my_did == MTD803ID)
906 sc->my_pinfo = my_phys;
907 else {
908 if (bootverbose)
909 device_printf(dev, "probing for a PHY\n");
910 MY_LOCK(sc);
911 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
912 if (bootverbose)
913 device_printf(dev, "checking address: %d\n", i);
914 sc->my_phy_addr = i;
915 phy_sts = my_phy_readreg(sc, PHY_BMSR);
916 if ((phy_sts != 0) && (phy_sts != 0xffff))
917 break;
918 else
919 phy_sts = 0;
920 }
921 if (phy_sts) {
922 phy_vid = my_phy_readreg(sc, PHY_VENID);
923 phy_did = my_phy_readreg(sc, PHY_DEVID);
924 if (bootverbose) {
925 device_printf(dev, "found PHY at address %d, ",
926 sc->my_phy_addr);
927 printf("vendor id: %x device id: %x\n",
928 phy_vid, phy_did);
929 }
930 p = my_phys;
931 while (p->my_vid) {
932 if (phy_vid == p->my_vid) {
933 sc->my_pinfo = p;
934 break;
935 }
936 p++;
937 }
938 if (sc->my_pinfo == NULL)
939 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
940 if (bootverbose)
941 device_printf(dev, "PHY type: %s\n",
942 sc->my_pinfo->my_name);
943 } else {
944 MY_UNLOCK(sc);
945 device_printf(dev, "MII without any phy!\n");
946 error = ENXIO;
947 goto free_if;
948 }
949 MY_UNLOCK(sc);
950 }
951
952 /* Do ifmedia setup. */
953 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
954 MY_LOCK(sc);
955 my_getmode_mii(sc);
956 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
957 media = sc->ifmedia.ifm_media;
958 my_stop(sc);
959 MY_UNLOCK(sc);
960 ifmedia_set(&sc->ifmedia, media);
961
962 ether_ifattach(ifp, eaddr);
963
964 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE,
965 NULL, my_intr, sc, &sc->my_intrhand);
966
967 if (error) {
968 device_printf(dev, "couldn't set up irq\n");
969 goto detach_if;
970 }
971
972 return (0);
973
974 detach_if:
975 ether_ifdetach(ifp);
976 free_if:
977 if_free(ifp);
978 free_ldata:
979 free(sc->my_ldata_ptr, M_DEVBUF);
980 release_irq:
981 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
982 release_io:
983 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
984 destroy_mutex:
985 mtx_destroy(&sc->my_mtx);
986 return (error);
987 }
988
989 static int
990 my_detach(device_t dev)
991 {
992 struct my_softc *sc;
993 struct ifnet *ifp;
994
995 sc = device_get_softc(dev);
996 ifp = sc->my_ifp;
997 ether_ifdetach(ifp);
998 MY_LOCK(sc);
999 my_stop(sc);
1000 MY_UNLOCK(sc);
1001 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1002 callout_drain(&sc->my_watchdog);
1003 callout_drain(&sc->my_autoneg_timer);
1004
1005 if_free(ifp);
1006 free(sc->my_ldata_ptr, M_DEVBUF);
1007
1008 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1009 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1010 mtx_destroy(&sc->my_mtx);
1011 return (0);
1012 }
1013
1014
1015 /*
1016 * Initialize the transmit descriptors.
1017 */
1018 static int
1019 my_list_tx_init(struct my_softc * sc)
1020 {
1021 struct my_chain_data *cd;
1022 struct my_list_data *ld;
1023 int i;
1024
1025 MY_LOCK_ASSERT(sc);
1026 cd = &sc->my_cdata;
1027 ld = sc->my_ldata;
1028 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1029 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1030 if (i == (MY_TX_LIST_CNT - 1))
1031 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1032 else
1033 cd->my_tx_chain[i].my_nextdesc =
1034 &cd->my_tx_chain[i + 1];
1035 }
1036 cd->my_tx_free = &cd->my_tx_chain[0];
1037 cd->my_tx_tail = cd->my_tx_head = NULL;
1038 return (0);
1039 }
1040
1041 /*
1042 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1043 * arrange the descriptors in a closed ring, so that the last descriptor
1044 * points back to the first.
1045 */
1046 static int
1047 my_list_rx_init(struct my_softc * sc)
1048 {
1049 struct my_chain_data *cd;
1050 struct my_list_data *ld;
1051 int i;
1052
1053 MY_LOCK_ASSERT(sc);
1054 cd = &sc->my_cdata;
1055 ld = sc->my_ldata;
1056 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1057 cd->my_rx_chain[i].my_ptr =
1058 (struct my_desc *) & ld->my_rx_list[i];
1059 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1060 MY_UNLOCK(sc);
1061 return (ENOBUFS);
1062 }
1063 if (i == (MY_RX_LIST_CNT - 1)) {
1064 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1065 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1066 } else {
1067 cd->my_rx_chain[i].my_nextdesc =
1068 &cd->my_rx_chain[i + 1];
1069 ld->my_rx_list[i].my_next =
1070 vtophys(&ld->my_rx_list[i + 1]);
1071 }
1072 }
1073 cd->my_rx_head = &cd->my_rx_chain[0];
1074 return (0);
1075 }
1076
1077 /*
1078 * Initialize an RX descriptor and attach an MBUF cluster.
1079 */
1080 static int
1081 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1082 {
1083 struct mbuf *m_new = NULL;
1084
1085 MY_LOCK_ASSERT(sc);
1086 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1087 if (m_new == NULL) {
1088 device_printf(sc->my_dev,
1089 "no memory for rx list -- packet dropped!\n");
1090 return (ENOBUFS);
1091 }
1092 if (!(MCLGET(m_new, M_NOWAIT))) {
1093 device_printf(sc->my_dev,
1094 "no memory for rx list -- packet dropped!\n");
1095 m_freem(m_new);
1096 return (ENOBUFS);
1097 }
1098 c->my_mbuf = m_new;
1099 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1100 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1101 c->my_ptr->my_status = MY_OWNByNIC;
1102 return (0);
1103 }
1104
1105 /*
1106 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1107 * level protocols.
1108 */
1109 static void
1110 my_rxeof(struct my_softc * sc)
1111 {
1112 struct ether_header *eh;
1113 struct mbuf *m;
1114 struct ifnet *ifp;
1115 struct my_chain_onefrag *cur_rx;
1116 int total_len = 0;
1117 u_int32_t rxstat;
1118
1119 MY_LOCK_ASSERT(sc);
1120 ifp = sc->my_ifp;
1121 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1122 & MY_OWNByNIC)) {
1123 cur_rx = sc->my_cdata.my_rx_head;
1124 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1125
1126 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1127 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1128 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1129 continue;
1130 }
1131 /* No errors; receive the packet. */
1132 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1133 total_len -= ETHER_CRC_LEN;
1134
1135 if (total_len < MINCLSIZE) {
1136 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1137 total_len, 0, ifp, NULL);
1138 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1139 if (m == NULL) {
1140 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1141 continue;
1142 }
1143 } else {
1144 m = cur_rx->my_mbuf;
1145 /*
1146 * Try to conjure up a new mbuf cluster. If that
1147 * fails, it means we have an out of memory condition
1148 * and should leave the buffer in place and continue.
1149 * This will result in a lost packet, but there's
1150 * little else we can do in this situation.
1151 */
1152 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1153 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1154 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1155 continue;
1156 }
1157 m->m_pkthdr.rcvif = ifp;
1158 m->m_pkthdr.len = m->m_len = total_len;
1159 }
1160 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1161 eh = mtod(m, struct ether_header *);
1162 #if NBPFILTER > 0
1163 /*
1164 * Handle BPF listeners. Let the BPF user see the packet, but
1165 * don't pass it up to the ether_input() layer unless it's a
1166 * broadcast packet, multicast packet, matches our ethernet
1167 * address or the interface is in promiscuous mode.
1168 */
1169 if (bpf_peers_present(ifp->if_bpf)) {
1170 bpf_mtap(ifp->if_bpf, m);
1171 if (ifp->if_flags & IFF_PROMISC &&
1172 (bcmp(eh->ether_dhost, IF_LLADDR(sc->my_ifp),
1173 ETHER_ADDR_LEN) &&
1174 (eh->ether_dhost[0] & 1) == 0)) {
1175 m_freem(m);
1176 continue;
1177 }
1178 }
1179 #endif
1180 MY_UNLOCK(sc);
1181 (*ifp->if_input)(ifp, m);
1182 MY_LOCK(sc);
1183 }
1184 return;
1185 }
1186
1187
1188 /*
1189 * A frame was downloaded to the chip. It's safe for us to clean up the list
1190 * buffers.
1191 */
1192 static void
1193 my_txeof(struct my_softc * sc)
1194 {
1195 struct my_chain *cur_tx;
1196 struct ifnet *ifp;
1197
1198 MY_LOCK_ASSERT(sc);
1199 ifp = sc->my_ifp;
1200 /* Clear the timeout timer. */
1201 sc->my_timer = 0;
1202 if (sc->my_cdata.my_tx_head == NULL) {
1203 return;
1204 }
1205 /*
1206 * Go through our tx list and free mbufs for those frames that have
1207 * been transmitted.
1208 */
1209 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1210 u_int32_t txstat;
1211
1212 cur_tx = sc->my_cdata.my_tx_head;
1213 txstat = MY_TXSTATUS(cur_tx);
1214 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1215 break;
1216 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1217 if (txstat & MY_TXERR) {
1218 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1219 if (txstat & MY_EC) /* excessive collision */
1220 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1221 if (txstat & MY_LC) /* late collision */
1222 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1);
1223 }
1224 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
1225 (txstat & MY_NCRMASK) >> MY_NCRShift);
1226 }
1227 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1228 m_freem(cur_tx->my_mbuf);
1229 cur_tx->my_mbuf = NULL;
1230 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1231 sc->my_cdata.my_tx_head = NULL;
1232 sc->my_cdata.my_tx_tail = NULL;
1233 break;
1234 }
1235 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1236 }
1237 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1238 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (CSR_READ_4(sc, MY_TSR) & MY_NCRMask));
1239 }
1240 return;
1241 }
1242
1243 /*
1244 * TX 'end of channel' interrupt handler.
1245 */
1246 static void
1247 my_txeoc(struct my_softc * sc)
1248 {
1249 struct ifnet *ifp;
1250
1251 MY_LOCK_ASSERT(sc);
1252 ifp = sc->my_ifp;
1253 sc->my_timer = 0;
1254 if (sc->my_cdata.my_tx_head == NULL) {
1255 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1256 sc->my_cdata.my_tx_tail = NULL;
1257 if (sc->my_want_auto)
1258 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1259 } else {
1260 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1261 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1262 sc->my_timer = 5;
1263 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1264 }
1265 }
1266 return;
1267 }
1268
1269 static void
1270 my_intr(void *arg)
1271 {
1272 struct my_softc *sc;
1273 struct ifnet *ifp;
1274 u_int32_t status;
1275
1276 sc = arg;
1277 MY_LOCK(sc);
1278 ifp = sc->my_ifp;
1279 if (!(ifp->if_flags & IFF_UP)) {
1280 MY_UNLOCK(sc);
1281 return;
1282 }
1283 /* Disable interrupts. */
1284 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1285
1286 for (;;) {
1287 status = CSR_READ_4(sc, MY_ISR);
1288 status &= MY_INTRS;
1289 if (status)
1290 CSR_WRITE_4(sc, MY_ISR, status);
1291 else
1292 break;
1293
1294 if (status & MY_RI) /* receive interrupt */
1295 my_rxeof(sc);
1296
1297 if ((status & MY_RBU) || (status & MY_RxErr)) {
1298 /* rx buffer unavailable or rx error */
1299 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1300 #ifdef foo
1301 my_stop(sc);
1302 my_reset(sc);
1303 my_init_locked(sc);
1304 #endif
1305 }
1306 if (status & MY_TI) /* tx interrupt */
1307 my_txeof(sc);
1308 if (status & MY_ETI) /* tx early interrupt */
1309 my_txeof(sc);
1310 if (status & MY_TBU) /* tx buffer unavailable */
1311 my_txeoc(sc);
1312
1313 #if 0 /* 90/1/18 delete */
1314 if (status & MY_FBE) {
1315 my_reset(sc);
1316 my_init_locked(sc);
1317 }
1318 #endif
1319
1320 }
1321
1322 /* Re-enable interrupts. */
1323 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1324 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1325 my_start_locked(ifp);
1326 MY_UNLOCK(sc);
1327 return;
1328 }
1329
1330 /*
1331 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1332 * pointers to the fragment pointers.
1333 */
1334 static int
1335 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1336 {
1337 struct my_desc *f = NULL;
1338 int total_len;
1339 struct mbuf *m, *m_new = NULL;
1340
1341 MY_LOCK_ASSERT(sc);
1342 /* calculate the total tx pkt length */
1343 total_len = 0;
1344 for (m = m_head; m != NULL; m = m->m_next)
1345 total_len += m->m_len;
1346 /*
1347 * Start packing the mbufs in this chain into the fragment pointers.
1348 * Stop when we run out of fragments or hit the end of the mbuf
1349 * chain.
1350 */
1351 m = m_head;
1352 MGETHDR(m_new, M_NOWAIT, MT_DATA);
1353 if (m_new == NULL) {
1354 device_printf(sc->my_dev, "no memory for tx list");
1355 return (1);
1356 }
1357 if (m_head->m_pkthdr.len > MHLEN) {
1358 if (!(MCLGET(m_new, M_NOWAIT))) {
1359 m_freem(m_new);
1360 device_printf(sc->my_dev, "no memory for tx list");
1361 return (1);
1362 }
1363 }
1364 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1365 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1366 m_freem(m_head);
1367 m_head = m_new;
1368 f = &c->my_ptr->my_frag[0];
1369 f->my_status = 0;
1370 f->my_data = vtophys(mtod(m_new, caddr_t));
1371 total_len = m_new->m_len;
1372 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1373 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1374 f->my_ctl |= total_len; /* buffer size */
1375 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1376 if (sc->my_info->my_did == MTD891ID)
1377 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1378 c->my_mbuf = m_head;
1379 c->my_lastdesc = 0;
1380 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1381 return (0);
1382 }
1383
1384 /*
1385 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1386 * to the mbuf data regions directly in the transmit lists. We also save a
1387 * copy of the pointers since the transmit list fragment pointers are
1388 * physical addresses.
1389 */
1390 static void
1391 my_start(struct ifnet * ifp)
1392 {
1393 struct my_softc *sc;
1394
1395 sc = ifp->if_softc;
1396 MY_LOCK(sc);
1397 my_start_locked(ifp);
1398 MY_UNLOCK(sc);
1399 }
1400
1401 static void
1402 my_start_locked(struct ifnet * ifp)
1403 {
1404 struct my_softc *sc;
1405 struct mbuf *m_head = NULL;
1406 struct my_chain *cur_tx = NULL, *start_tx;
1407
1408 sc = ifp->if_softc;
1409 MY_LOCK_ASSERT(sc);
1410 if (sc->my_autoneg) {
1411 sc->my_tx_pend = 1;
1412 return;
1413 }
1414 /*
1415 * Check for an available queue slot. If there are none, punt.
1416 */
1417 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1418 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1419 return;
1420 }
1421 start_tx = sc->my_cdata.my_tx_free;
1422 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1423 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1424 if (m_head == NULL)
1425 break;
1426
1427 /* Pick a descriptor off the free list. */
1428 cur_tx = sc->my_cdata.my_tx_free;
1429 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1430
1431 /* Pack the data into the descriptor. */
1432 my_encap(sc, cur_tx, m_head);
1433
1434 if (cur_tx != start_tx)
1435 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1436 #if NBPFILTER > 0
1437 /*
1438 * If there's a BPF listener, bounce a copy of this frame to
1439 * him.
1440 */
1441 BPF_MTAP(ifp, cur_tx->my_mbuf);
1442 #endif
1443 }
1444 /*
1445 * If there are no packets queued, bail.
1446 */
1447 if (cur_tx == NULL) {
1448 return;
1449 }
1450 /*
1451 * Place the request for the upload interrupt in the last descriptor
1452 * in the chain. This way, if we're chaining several packets at once,
1453 * we'll only get an interrupt once for the whole chain rather than
1454 * once for each packet.
1455 */
1456 MY_TXCTL(cur_tx) |= MY_TXIC;
1457 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1458 sc->my_cdata.my_tx_tail = cur_tx;
1459 if (sc->my_cdata.my_tx_head == NULL)
1460 sc->my_cdata.my_tx_head = start_tx;
1461 MY_TXOWN(start_tx) = MY_OWNByNIC;
1462 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1463
1464 /*
1465 * Set a timeout in case the chip goes out to lunch.
1466 */
1467 sc->my_timer = 5;
1468 return;
1469 }
1470
1471 static void
1472 my_init(void *xsc)
1473 {
1474 struct my_softc *sc = xsc;
1475
1476 MY_LOCK(sc);
1477 my_init_locked(sc);
1478 MY_UNLOCK(sc);
1479 }
1480
1481 static void
1482 my_init_locked(struct my_softc *sc)
1483 {
1484 struct ifnet *ifp = sc->my_ifp;
1485 u_int16_t phy_bmcr = 0;
1486
1487 MY_LOCK_ASSERT(sc);
1488 if (sc->my_autoneg) {
1489 return;
1490 }
1491 if (sc->my_pinfo != NULL)
1492 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1493 /*
1494 * Cancel pending I/O and free all RX/TX buffers.
1495 */
1496 my_stop(sc);
1497 my_reset(sc);
1498
1499 /*
1500 * Set cache alignment and burst length.
1501 */
1502 #if 0 /* 89/9/1 modify, */
1503 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1504 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1505 #endif
1506 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1507 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1508 /*
1509 * 89/12/29 add, for mtd891,
1510 */
1511 if (sc->my_info->my_did == MTD891ID) {
1512 MY_SETBIT(sc, MY_BCR, MY_PROG);
1513 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1514 }
1515 my_setcfg(sc, phy_bmcr);
1516 /* Init circular RX list. */
1517 if (my_list_rx_init(sc) == ENOBUFS) {
1518 device_printf(sc->my_dev, "init failed: no memory for rx buffers\n");
1519 my_stop(sc);
1520 return;
1521 }
1522 /* Init TX descriptors. */
1523 my_list_tx_init(sc);
1524
1525 /* If we want promiscuous mode, set the allframes bit. */
1526 if (ifp->if_flags & IFF_PROMISC)
1527 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1528 else
1529 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1530
1531 /*
1532 * Set capture broadcast bit to capture broadcast frames.
1533 */
1534 if (ifp->if_flags & IFF_BROADCAST)
1535 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1536 else
1537 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1538
1539 /*
1540 * Program the multicast filter, if necessary.
1541 */
1542 my_setmulti(sc);
1543
1544 /*
1545 * Load the address of the RX list.
1546 */
1547 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1548 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1549
1550 /*
1551 * Enable interrupts.
1552 */
1553 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1554 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1555
1556 /* Enable receiver and transmitter. */
1557 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1558 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1559 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1560 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1561
1562 /* Restore state of BMCR */
1563 if (sc->my_pinfo != NULL)
1564 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1565 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1566 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1567
1568 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1569 return;
1570 }
1571
1572 /*
1573 * Set media options.
1574 */
1575
1576 static int
1577 my_ifmedia_upd(struct ifnet * ifp)
1578 {
1579 struct my_softc *sc;
1580 struct ifmedia *ifm;
1581
1582 sc = ifp->if_softc;
1583 MY_LOCK(sc);
1584 ifm = &sc->ifmedia;
1585 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1586 MY_UNLOCK(sc);
1587 return (EINVAL);
1588 }
1589 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1590 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1591 else
1592 my_setmode_mii(sc, ifm->ifm_media);
1593 MY_UNLOCK(sc);
1594 return (0);
1595 }
1596
1597 /*
1598 * Report current media status.
1599 */
1600
1601 static void
1602 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1603 {
1604 struct my_softc *sc;
1605 u_int16_t advert = 0, ability = 0;
1606
1607 sc = ifp->if_softc;
1608 MY_LOCK(sc);
1609 ifmr->ifm_active = IFM_ETHER;
1610 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1611 #if 0 /* this version did not support 1000M, */
1612 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1613 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1614 #endif
1615 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1616 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1617 else
1618 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1619 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1620 ifmr->ifm_active |= IFM_FDX;
1621 else
1622 ifmr->ifm_active |= IFM_HDX;
1623
1624 MY_UNLOCK(sc);
1625 return;
1626 }
1627 ability = my_phy_readreg(sc, PHY_LPAR);
1628 advert = my_phy_readreg(sc, PHY_ANAR);
1629
1630 #if 0 /* this version did not support 1000M, */
1631 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1632 ability2 = my_phy_readreg(sc, PHY_1000SR);
1633 if (ability2 & PHY_1000SR_1000BTXFULL) {
1634 advert = 0;
1635 ability = 0;
1636 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1637 } else if (ability & PHY_1000SR_1000BTXHALF) {
1638 advert = 0;
1639 ability = 0;
1640 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1641 }
1642 }
1643 #endif
1644 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1645 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1646 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1647 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1648 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1649 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1650 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1651 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1652 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1653 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1654 MY_UNLOCK(sc);
1655 return;
1656 }
1657
1658 static int
1659 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1660 {
1661 struct my_softc *sc = ifp->if_softc;
1662 struct ifreq *ifr = (struct ifreq *) data;
1663 int error;
1664
1665 switch (command) {
1666 case SIOCSIFFLAGS:
1667 MY_LOCK(sc);
1668 if (ifp->if_flags & IFF_UP)
1669 my_init_locked(sc);
1670 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1671 my_stop(sc);
1672 MY_UNLOCK(sc);
1673 error = 0;
1674 break;
1675 case SIOCADDMULTI:
1676 case SIOCDELMULTI:
1677 MY_LOCK(sc);
1678 my_setmulti(sc);
1679 MY_UNLOCK(sc);
1680 error = 0;
1681 break;
1682 case SIOCGIFMEDIA:
1683 case SIOCSIFMEDIA:
1684 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1685 break;
1686 default:
1687 error = ether_ioctl(ifp, command, data);
1688 break;
1689 }
1690 return (error);
1691 }
1692
1693 static void
1694 my_watchdog(void *arg)
1695 {
1696 struct my_softc *sc;
1697 struct ifnet *ifp;
1698
1699 sc = arg;
1700 MY_LOCK_ASSERT(sc);
1701 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1702 if (sc->my_timer == 0 || --sc->my_timer > 0)
1703 return;
1704
1705 ifp = sc->my_ifp;
1706 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1707 if_printf(ifp, "watchdog timeout\n");
1708 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1709 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1710 my_stop(sc);
1711 my_reset(sc);
1712 my_init_locked(sc);
1713 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1714 my_start_locked(ifp);
1715 }
1716
1717
1718 /*
1719 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1720 */
1721 static void
1722 my_stop(struct my_softc * sc)
1723 {
1724 int i;
1725 struct ifnet *ifp;
1726
1727 MY_LOCK_ASSERT(sc);
1728 ifp = sc->my_ifp;
1729
1730 callout_stop(&sc->my_autoneg_timer);
1731 callout_stop(&sc->my_watchdog);
1732
1733 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1734 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1735 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1736 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1737
1738 /*
1739 * Free data in the RX lists.
1740 */
1741 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1742 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1743 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1744 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1745 }
1746 }
1747 bzero((char *)&sc->my_ldata->my_rx_list,
1748 sizeof(sc->my_ldata->my_rx_list));
1749 /*
1750 * Free the TX list buffers.
1751 */
1752 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1753 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1754 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1755 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1756 }
1757 }
1758 bzero((char *)&sc->my_ldata->my_tx_list,
1759 sizeof(sc->my_ldata->my_tx_list));
1760 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1761 return;
1762 }
1763
1764 /*
1765 * Stop all chip I/O so that the kernel's probe routines don't get confused
1766 * by errant DMAs when rebooting.
1767 */
1768 static int
1769 my_shutdown(device_t dev)
1770 {
1771 struct my_softc *sc;
1772
1773 sc = device_get_softc(dev);
1774 MY_LOCK(sc);
1775 my_stop(sc);
1776 MY_UNLOCK(sc);
1777 return 0;
1778 }
Cache object: e93c816b554043f3e0827f974410f307
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