FreeBSD/Linux Kernel Cross Reference
sys/dev/my/if_my.c
1 /*
2 * Copyright (c) 2002 Myson Technology Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
27 *
28 * $FreeBSD$
29 *
30 * Myson fast ethernet PCI NIC driver
31 */
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/sockio.h>
35 #include <sys/mbuf.h>
36 #include <sys/malloc.h>
37 #include <sys/kernel.h>
38 #include <sys/socket.h>
39 #include <sys/queue.h>
40 #include <sys/types.h>
41 #include <sys/bus.h>
42 #include <sys/module.h>
43
44 #define NBPFILTER 1
45
46 #include <net/if.h>
47 #include <net/if_arp.h>
48 #include <net/ethernet.h>
49 #include <net/if_media.h>
50 #include <net/if_dl.h>
51 #include <net/bpf.h>
52
53 #include <vm/vm.h> /* for vtophys */
54 #include <vm/pmap.h> /* for vtophys */
55 #include <machine/clock.h> /* for DELAY */
56 #include <machine/bus_memio.h>
57 #include <machine/bus_pio.h>
58 #include <machine/bus.h>
59 #include <machine/resource.h>
60 #include <sys/bus.h>
61 #include <sys/rman.h>
62
63 #include <pci/pcireg.h>
64 #include <pci/pcivar.h>
65
66 #include <dev/mii/mii.h>
67 #include <dev/mii/miivar.h>
68
69 #include "miibus_if.h"
70
71 /*
72 * #define MY_USEIOSPACE
73 */
74
75 static int MY_USEIOSPACE = 1;
76
77 #if (MY_USEIOSPACE)
78 #define MY_RES SYS_RES_IOPORT
79 #define MY_RID MY_PCI_LOIO
80 #else
81 #define MY_RES SYS_RES_MEMORY
82 #define MY_RID MY_PCI_LOMEM
83 #endif
84
85
86 #include <dev/my/if_myreg.h>
87
88 #ifndef lint
89 static const char rcsid[] =
90 "$Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $";
91 #endif
92
93 /*
94 * Various supported device vendors/types and their names.
95 */
96 struct my_type *my_info_tmp;
97 static struct my_type my_devs[] = {
98 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
99 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
100 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
101 {0, 0, NULL}
102 };
103
104 /*
105 * Various supported PHY vendors/types and their names. Note that this driver
106 * will work with pretty much any MII-compliant PHY, so failure to positively
107 * identify the chip is not a fatal error.
108 */
109 static struct my_type my_phys[] = {
110 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
111 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
112 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
113 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
114 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
115 {0, 0, "<MII-compliant physical interface>"}
116 };
117
118 static int my_probe(device_t);
119 static int my_attach(device_t);
120 static int my_detach(device_t);
121 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
122 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
123 static void my_rxeof(struct my_softc *);
124 static void my_txeof(struct my_softc *);
125 static void my_txeoc(struct my_softc *);
126 static void my_intr(void *);
127 static void my_start(struct ifnet *);
128 static int my_ioctl(struct ifnet *, u_long, caddr_t);
129 static void my_init(void *);
130 static void my_stop(struct my_softc *);
131 static void my_watchdog(struct ifnet *);
132 static void my_shutdown(device_t);
133 static int my_ifmedia_upd(struct ifnet *);
134 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
135 static u_int16_t my_phy_readreg(struct my_softc *, int);
136 static void my_phy_writereg(struct my_softc *, int, int);
137 static void my_autoneg_xmit(struct my_softc *);
138 static void my_autoneg_mii(struct my_softc *, int, int);
139 static void my_setmode_mii(struct my_softc *, int);
140 static void my_getmode_mii(struct my_softc *);
141 static void my_setcfg(struct my_softc *, int);
142 static u_int8_t my_calchash(caddr_t);
143 static void my_setmulti(struct my_softc *);
144 static void my_reset(struct my_softc *);
145 static int my_list_rx_init(struct my_softc *);
146 static int my_list_tx_init(struct my_softc *);
147 static long my_send_cmd_to_phy(struct my_softc *, int, int);
148
149 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
150 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
151
152 static device_method_t my_methods[] = {
153 /* Device interface */
154 DEVMETHOD(device_probe, my_probe),
155 DEVMETHOD(device_attach, my_attach),
156 DEVMETHOD(device_detach, my_detach),
157 DEVMETHOD(device_shutdown, my_shutdown),
158
159 {0, 0}
160 };
161
162 static driver_t my_driver = {
163 "my",
164 my_methods,
165 sizeof(struct my_softc)
166 };
167
168 static devclass_t my_devclass;
169
170 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0);
171
172 static long
173 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
174 {
175 long miir;
176 int i;
177 int mask, data;
178
179 MY_LOCK(sc);
180
181 /* enable MII output */
182 miir = CSR_READ_4(sc, MY_MANAGEMENT);
183 miir &= 0xfffffff0;
184
185 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
186
187 /* send 32 1's preamble */
188 for (i = 0; i < 32; i++) {
189 /* low MDC; MDO is already high (miir) */
190 miir &= ~MY_MASK_MIIR_MII_MDC;
191 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
192
193 /* high MDC */
194 miir |= MY_MASK_MIIR_MII_MDC;
195 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
196 }
197
198 /* calculate ST+OP+PHYAD+REGAD+TA */
199 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
200
201 /* sent out */
202 mask = 0x8000;
203 while (mask) {
204 /* low MDC, prepare MDO */
205 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
206 if (mask & data)
207 miir |= MY_MASK_MIIR_MII_MDO;
208
209 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
210 /* high MDC */
211 miir |= MY_MASK_MIIR_MII_MDC;
212 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
213 DELAY(30);
214
215 /* next */
216 mask >>= 1;
217 if (mask == 0x2 && opcode == MY_OP_READ)
218 miir &= ~MY_MASK_MIIR_MII_WRITE;
219 }
220
221 MY_UNLOCK(sc);
222 return miir;
223 }
224
225
226 static u_int16_t
227 my_phy_readreg(struct my_softc * sc, int reg)
228 {
229 long miir;
230 int mask, data;
231
232 MY_LOCK(sc);
233
234 if (sc->my_info->my_did == MTD803ID)
235 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
236 else {
237 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
238
239 /* read data */
240 mask = 0x8000;
241 data = 0;
242 while (mask) {
243 /* low MDC */
244 miir &= ~MY_MASK_MIIR_MII_MDC;
245 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
246
247 /* read MDI */
248 miir = CSR_READ_4(sc, MY_MANAGEMENT);
249 if (miir & MY_MASK_MIIR_MII_MDI)
250 data |= mask;
251
252 /* high MDC, and wait */
253 miir |= MY_MASK_MIIR_MII_MDC;
254 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
255 DELAY(30);
256
257 /* next */
258 mask >>= 1;
259 }
260
261 /* low MDC */
262 miir &= ~MY_MASK_MIIR_MII_MDC;
263 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
264 }
265
266 MY_UNLOCK(sc);
267 return (u_int16_t) data;
268 }
269
270
271 static void
272 my_phy_writereg(struct my_softc * sc, int reg, int data)
273 {
274 long miir;
275 int mask;
276
277 MY_LOCK(sc);
278
279 if (sc->my_info->my_did == MTD803ID)
280 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
281 else {
282 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
283
284 /* write data */
285 mask = 0x8000;
286 while (mask) {
287 /* low MDC, prepare MDO */
288 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
289 if (mask & data)
290 miir |= MY_MASK_MIIR_MII_MDO;
291 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
292 DELAY(1);
293
294 /* high MDC */
295 miir |= MY_MASK_MIIR_MII_MDC;
296 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
297 DELAY(1);
298
299 /* next */
300 mask >>= 1;
301 }
302
303 /* low MDC */
304 miir &= ~MY_MASK_MIIR_MII_MDC;
305 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
306 }
307 MY_UNLOCK(sc);
308 return;
309 }
310
311 static u_int8_t
312 my_calchash(caddr_t addr)
313 {
314 u_int32_t crc, carry;
315 int i, j;
316 u_int8_t c;
317
318 /* Compute CRC for the address value. */
319 crc = 0xFFFFFFFF; /* initial value */
320
321 for (i = 0; i < 6; i++) {
322 c = *(addr + i);
323 for (j = 0; j < 8; j++) {
324 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
325 crc <<= 1;
326 c >>= 1;
327 if (carry)
328 crc = (crc ^ 0x04c11db6) | carry;
329 }
330 }
331
332 /*
333 * return the filter bit position Note: I arrived at the following
334 * nonsense through experimentation. It's not the usual way to
335 * generate the bit position but it's the only thing I could come up
336 * with that works.
337 */
338 return (~(crc >> 26) & 0x0000003F);
339 }
340
341
342 /*
343 * Program the 64-bit multicast hash filter.
344 */
345 static void
346 my_setmulti(struct my_softc * sc)
347 {
348 struct ifnet *ifp;
349 int h = 0;
350 u_int32_t hashes[2] = {0, 0};
351 struct ifmultiaddr *ifma;
352 u_int32_t rxfilt;
353 int mcnt = 0;
354
355 MY_LOCK(sc);
356
357 ifp = &sc->arpcom.ac_if;
358
359 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
360
361 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
362 rxfilt |= MY_AM;
363 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
364 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
365 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
366
367 MY_UNLOCK(sc);
368
369 return;
370 }
371 /* first, zot all the existing hash bits */
372 CSR_WRITE_4(sc, MY_MAR0, 0);
373 CSR_WRITE_4(sc, MY_MAR1, 0);
374
375 /* now program new ones */
376 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
377 if (ifma->ifma_addr->sa_family != AF_LINK)
378 continue;
379 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr));
380 if (h < 32)
381 hashes[0] |= (1 << h);
382 else
383 hashes[1] |= (1 << (h - 32));
384 mcnt++;
385 }
386
387 if (mcnt)
388 rxfilt |= MY_AM;
389 else
390 rxfilt &= ~MY_AM;
391 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
392 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
393 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
394 MY_UNLOCK(sc);
395 return;
396 }
397
398 /*
399 * Initiate an autonegotiation session.
400 */
401 static void
402 my_autoneg_xmit(struct my_softc * sc)
403 {
404 u_int16_t phy_sts = 0;
405
406 MY_LOCK(sc);
407
408 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
409 DELAY(500);
410 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
411
412 phy_sts = my_phy_readreg(sc, PHY_BMCR);
413 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
414 my_phy_writereg(sc, PHY_BMCR, phy_sts);
415
416 MY_UNLOCK(sc);
417 return;
418 }
419
420
421 /*
422 * Invoke autonegotiation on a PHY.
423 */
424 static void
425 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
426 {
427 u_int16_t phy_sts = 0, media, advert, ability;
428 u_int16_t ability2 = 0;
429 struct ifnet *ifp;
430 struct ifmedia *ifm;
431
432 MY_LOCK(sc);
433
434 ifm = &sc->ifmedia;
435 ifp = &sc->arpcom.ac_if;
436
437 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
438
439 #ifndef FORCE_AUTONEG_TFOUR
440 /*
441 * First, see if autoneg is supported. If not, there's no point in
442 * continuing.
443 */
444 phy_sts = my_phy_readreg(sc, PHY_BMSR);
445 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
446 if (verbose)
447 printf("my%d: autonegotiation not supported\n",
448 sc->my_unit);
449 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
450 MY_UNLOCK(sc);
451 return;
452 }
453 #endif
454 switch (flag) {
455 case MY_FLAG_FORCEDELAY:
456 /*
457 * XXX Never use this option anywhere but in the probe
458 * routine: making the kernel stop dead in its tracks for
459 * three whole seconds after we've gone multi-user is really
460 * bad manners.
461 */
462 my_autoneg_xmit(sc);
463 DELAY(5000000);
464 break;
465 case MY_FLAG_SCHEDDELAY:
466 /*
467 * Wait for the transmitter to go idle before starting an
468 * autoneg session, otherwise my_start() may clobber our
469 * timeout, and we don't want to allow transmission during an
470 * autoneg session since that can screw it up.
471 */
472 if (sc->my_cdata.my_tx_head != NULL) {
473 sc->my_want_auto = 1;
474 MY_UNLOCK(sc);
475 return;
476 }
477 my_autoneg_xmit(sc);
478 ifp->if_timer = 5;
479 sc->my_autoneg = 1;
480 sc->my_want_auto = 0;
481 MY_UNLOCK(sc);
482 return;
483 case MY_FLAG_DELAYTIMEO:
484 ifp->if_timer = 0;
485 sc->my_autoneg = 0;
486 break;
487 default:
488 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag);
489 MY_UNLOCK(sc);
490 return;
491 }
492
493 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
494 if (verbose)
495 printf("my%d: autoneg complete, ", sc->my_unit);
496 phy_sts = my_phy_readreg(sc, PHY_BMSR);
497 } else {
498 if (verbose)
499 printf("my%d: autoneg not complete, ", sc->my_unit);
500 }
501
502 media = my_phy_readreg(sc, PHY_BMCR);
503
504 /* Link is good. Report modes and set duplex mode. */
505 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
506 if (verbose)
507 printf("my%d: link status good. ", sc->my_unit);
508 advert = my_phy_readreg(sc, PHY_ANAR);
509 ability = my_phy_readreg(sc, PHY_LPAR);
510 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
511 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
512 ability2 = my_phy_readreg(sc, PHY_1000SR);
513 if (ability2 & PHY_1000SR_1000BTXFULL) {
514 advert = 0;
515 ability = 0;
516 /*
517 * this version did not support 1000M,
518 * ifm->ifm_media =
519 * IFM_ETHER|IFM_1000_TX|IFM_FDX;
520 */
521 ifm->ifm_media =
522 IFM_ETHER | IFM_100_TX | IFM_FDX;
523 media &= ~PHY_BMCR_SPEEDSEL;
524 media |= PHY_BMCR_1000;
525 media |= PHY_BMCR_DUPLEX;
526 printf("(full-duplex, 1000Mbps)\n");
527 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
528 advert = 0;
529 ability = 0;
530 /*
531 * this version did not support 1000M,
532 * ifm->ifm_media = IFM_ETHER|IFM_1000_TX;
533 */
534 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
535 media &= ~PHY_BMCR_SPEEDSEL;
536 media &= ~PHY_BMCR_DUPLEX;
537 media |= PHY_BMCR_1000;
538 printf("(half-duplex, 1000Mbps)\n");
539 }
540 }
541 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
542 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
543 media |= PHY_BMCR_SPEEDSEL;
544 media &= ~PHY_BMCR_DUPLEX;
545 printf("(100baseT4)\n");
546 } else if (advert & PHY_ANAR_100BTXFULL &&
547 ability & PHY_ANAR_100BTXFULL) {
548 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
549 media |= PHY_BMCR_SPEEDSEL;
550 media |= PHY_BMCR_DUPLEX;
551 printf("(full-duplex, 100Mbps)\n");
552 } else if (advert & PHY_ANAR_100BTXHALF &&
553 ability & PHY_ANAR_100BTXHALF) {
554 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
555 media |= PHY_BMCR_SPEEDSEL;
556 media &= ~PHY_BMCR_DUPLEX;
557 printf("(half-duplex, 100Mbps)\n");
558 } else if (advert & PHY_ANAR_10BTFULL &&
559 ability & PHY_ANAR_10BTFULL) {
560 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
561 media &= ~PHY_BMCR_SPEEDSEL;
562 media |= PHY_BMCR_DUPLEX;
563 printf("(full-duplex, 10Mbps)\n");
564 } else if (advert) {
565 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
566 media &= ~PHY_BMCR_SPEEDSEL;
567 media &= ~PHY_BMCR_DUPLEX;
568 printf("(half-duplex, 10Mbps)\n");
569 }
570 media &= ~PHY_BMCR_AUTONEGENBL;
571
572 /* Set ASIC's duplex mode to match the PHY. */
573 my_phy_writereg(sc, PHY_BMCR, media);
574 my_setcfg(sc, media);
575 } else {
576 if (verbose)
577 printf("my%d: no carrier\n", sc->my_unit);
578 }
579
580 my_init(sc);
581 if (sc->my_tx_pend) {
582 sc->my_autoneg = 0;
583 sc->my_tx_pend = 0;
584 my_start(ifp);
585 }
586 MY_UNLOCK(sc);
587 return;
588 }
589
590 /*
591 * To get PHY ability.
592 */
593 static void
594 my_getmode_mii(struct my_softc * sc)
595 {
596 u_int16_t bmsr;
597 struct ifnet *ifp;
598
599 MY_LOCK(sc);
600 ifp = &sc->arpcom.ac_if;
601 bmsr = my_phy_readreg(sc, PHY_BMSR);
602 if (bootverbose)
603 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr);
604
605 /* fallback */
606 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
607
608 if (bmsr & PHY_BMSR_10BTHALF) {
609 if (bootverbose)
610 printf("my%d: 10Mbps half-duplex mode supported\n",
611 sc->my_unit);
612 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
613 0, NULL);
614 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
615 }
616 if (bmsr & PHY_BMSR_10BTFULL) {
617 if (bootverbose)
618 printf("my%d: 10Mbps full-duplex mode supported\n",
619 sc->my_unit);
620
621 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
622 0, NULL);
623 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
624 }
625 if (bmsr & PHY_BMSR_100BTXHALF) {
626 if (bootverbose)
627 printf("my%d: 100Mbps half-duplex mode supported\n",
628 sc->my_unit);
629 ifp->if_baudrate = 100000000;
630 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
631 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
632 0, NULL);
633 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
634 }
635 if (bmsr & PHY_BMSR_100BTXFULL) {
636 if (bootverbose)
637 printf("my%d: 100Mbps full-duplex mode supported\n",
638 sc->my_unit);
639 ifp->if_baudrate = 100000000;
640 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
641 0, NULL);
642 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
643 }
644 /* Some also support 100BaseT4. */
645 if (bmsr & PHY_BMSR_100BT4) {
646 if (bootverbose)
647 printf("my%d: 100baseT4 mode supported\n", sc->my_unit);
648 ifp->if_baudrate = 100000000;
649 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
650 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
651 #ifdef FORCE_AUTONEG_TFOUR
652 if (bootverbose)
653 printf("my%d: forcing on autoneg support for BT4\n",
654 sc->my_unit);
655 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
656 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
657 #endif
658 }
659 #if 0 /* this version did not support 1000M, */
660 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
661 if (bootverbose)
662 printf("my%d: 1000Mbps half-duplex mode supported\n",
663 sc->my_unit);
664
665 ifp->if_baudrate = 1000000000;
666 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX, 0, NULL);
667 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_HDX,
668 0, NULL);
669 if (bootverbose)
670 printf("my%d: 1000Mbps full-duplex mode supported\n",
671 sc->my_unit);
672 ifp->if_baudrate = 1000000000;
673 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_TX | IFM_FDX,
674 0, NULL);
675 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_TX | IFM_FDX;
676 }
677 #endif
678 if (bmsr & PHY_BMSR_CANAUTONEG) {
679 if (bootverbose)
680 printf("my%d: autoneg supported\n", sc->my_unit);
681 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
682 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
683 }
684 MY_UNLOCK(sc);
685 return;
686 }
687
688 /*
689 * Set speed and duplex mode.
690 */
691 static void
692 my_setmode_mii(struct my_softc * sc, int media)
693 {
694 u_int16_t bmcr;
695 struct ifnet *ifp;
696
697 MY_LOCK(sc);
698 ifp = &sc->arpcom.ac_if;
699 /*
700 * If an autoneg session is in progress, stop it.
701 */
702 if (sc->my_autoneg) {
703 printf("my%d: canceling autoneg session\n", sc->my_unit);
704 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
705 bmcr = my_phy_readreg(sc, PHY_BMCR);
706 bmcr &= ~PHY_BMCR_AUTONEGENBL;
707 my_phy_writereg(sc, PHY_BMCR, bmcr);
708 }
709 printf("my%d: selecting MII, ", sc->my_unit);
710 bmcr = my_phy_readreg(sc, PHY_BMCR);
711 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
712 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
713
714 #if 0 /* this version did not support 1000M, */
715 if (IFM_SUBTYPE(media) == IFM_1000_TX) {
716 printf("1000Mbps/T4, half-duplex\n");
717 bmcr &= ~PHY_BMCR_SPEEDSEL;
718 bmcr &= ~PHY_BMCR_DUPLEX;
719 bmcr |= PHY_BMCR_1000;
720 }
721 #endif
722 if (IFM_SUBTYPE(media) == IFM_100_T4) {
723 printf("100Mbps/T4, half-duplex\n");
724 bmcr |= PHY_BMCR_SPEEDSEL;
725 bmcr &= ~PHY_BMCR_DUPLEX;
726 }
727 if (IFM_SUBTYPE(media) == IFM_100_TX) {
728 printf("100Mbps, ");
729 bmcr |= PHY_BMCR_SPEEDSEL;
730 }
731 if (IFM_SUBTYPE(media) == IFM_10_T) {
732 printf("10Mbps, ");
733 bmcr &= ~PHY_BMCR_SPEEDSEL;
734 }
735 if ((media & IFM_GMASK) == IFM_FDX) {
736 printf("full duplex\n");
737 bmcr |= PHY_BMCR_DUPLEX;
738 } else {
739 printf("half duplex\n");
740 bmcr &= ~PHY_BMCR_DUPLEX;
741 }
742 my_phy_writereg(sc, PHY_BMCR, bmcr);
743 my_setcfg(sc, bmcr);
744 MY_UNLOCK(sc);
745 return;
746 }
747
748 /*
749 * The Myson manual states that in order to fiddle with the 'full-duplex' and
750 * '100Mbps' bits in the netconfig register, we first have to put the
751 * transmit and/or receive logic in the idle state.
752 */
753 static void
754 my_setcfg(struct my_softc * sc, int bmcr)
755 {
756 int i, restart = 0;
757
758 MY_LOCK(sc);
759 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
760 restart = 1;
761 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
762 for (i = 0; i < MY_TIMEOUT; i++) {
763 DELAY(10);
764 if (!(CSR_READ_4(sc, MY_TCRRCR) &
765 (MY_TXRUN | MY_RXRUN)))
766 break;
767 }
768 if (i == MY_TIMEOUT)
769 printf("my%d: failed to force tx and rx to idle \n",
770 sc->my_unit);
771 }
772 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
773 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
774 if (bmcr & PHY_BMCR_1000)
775 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
776 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
777 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
778 if (bmcr & PHY_BMCR_DUPLEX)
779 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
780 else
781 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
782 if (restart)
783 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
784 MY_UNLOCK(sc);
785 return;
786 }
787
788 static void
789 my_reset(struct my_softc * sc)
790 {
791 register int i;
792
793 MY_LOCK(sc);
794 MY_SETBIT(sc, MY_BCR, MY_SWR);
795 for (i = 0; i < MY_TIMEOUT; i++) {
796 DELAY(10);
797 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
798 break;
799 }
800 if (i == MY_TIMEOUT)
801 printf("m0x%d: reset never completed!\n", sc->my_unit);
802
803 /* Wait a little while for the chip to get its brains in order. */
804 DELAY(1000);
805 MY_UNLOCK(sc);
806 return;
807 }
808
809 /*
810 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
811 * list and return a device name if we find a match.
812 */
813 static int
814 my_probe(device_t dev)
815 {
816 struct my_type *t;
817
818 t = my_devs;
819 while (t->my_name != NULL) {
820 if ((pci_get_vendor(dev) == t->my_vid) &&
821 (pci_get_device(dev) == t->my_did)) {
822 device_set_desc(dev, t->my_name);
823 my_info_tmp = t;
824 return (0);
825 }
826 t++;
827 }
828 return (ENXIO);
829 }
830
831 /*
832 * Attach the interface. Allocate softc structures, do ifmedia setup and
833 * ethernet/BPF attach.
834 */
835 static int
836 my_attach(device_t dev)
837 {
838 int s, i;
839 u_char eaddr[ETHER_ADDR_LEN];
840 u_int32_t command, iobase;
841 struct my_softc *sc;
842 struct ifnet *ifp;
843 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
844 unsigned int round;
845 caddr_t roundptr;
846 struct my_type *p;
847 u_int16_t phy_vid, phy_did, phy_sts = 0;
848 int rid, unit, error = 0;
849
850 s = splimp();
851 sc = device_get_softc(dev);
852 unit = device_get_unit(dev);
853 if (sc == NULL) {
854 printf("my%d: no memory for softc struct!\n", unit);
855 error = ENXIO;
856 goto fail;
857
858 }
859 bzero(sc, sizeof(struct my_softc));
860 /*mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_DEF | MTX_RECURSE);*/
861 MY_LOCK(sc);
862
863 /*
864 * Map control/status registers.
865 */
866 #if 0
867 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
868 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
869 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4);
870 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4);
871 #endif
872 command = pci_read_config(dev, PCIR_COMMAND, 4);
873 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
874 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
875 command = pci_read_config(dev, PCIR_COMMAND, 4);
876
877 if (my_info_tmp->my_did == MTD800ID) {
878 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
879 if (iobase & 0x300)
880 MY_USEIOSPACE = 0;
881 }
882 if (MY_USEIOSPACE) {
883 if (!(command & PCIM_CMD_PORTEN)) {
884 printf("my%d: failed to enable I/O ports!\n", unit);
885 free(sc, M_DEVBUF);
886 error = ENXIO;
887 goto fail;
888 }
889 #if 0
890 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) {
891 printf("my%d: couldn't map ports\n", unit);
892 error = ENXIO;
893 goto fail;
894 }
895
896 sc->my_btag = I386_BUS_SPACE_IO;
897 #endif
898 } else {
899 if (!(command & PCIM_CMD_MEMEN)) {
900 printf("my%d: failed to enable memory mapping!\n",
901 unit);
902 error = ENXIO;
903 goto fail;
904 }
905 #if 0
906 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) {
907 printf ("my%d: couldn't map memory\n", unit);
908 error = ENXIO;
909 goto fail;
910 }
911 sc->my_btag = I386_BUS_SPACE_MEM;
912 sc->my_bhandle = vbase;
913 #endif
914 }
915
916 rid = MY_RID;
917 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid,
918 0, ~0, 1, RF_ACTIVE);
919
920 if (sc->my_res == NULL) {
921 printf("my%d: couldn't map ports/memory\n", unit);
922 error = ENXIO;
923 goto fail;
924 }
925 sc->my_btag = rman_get_bustag(sc->my_res);
926 sc->my_bhandle = rman_get_bushandle(sc->my_res);
927
928 rid = 0;
929 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
930 RF_SHAREABLE | RF_ACTIVE);
931
932 if (sc->my_irq == NULL) {
933 printf("my%d: couldn't map interrupt\n", unit);
934 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
935 error = ENXIO;
936 goto fail;
937 }
938 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET,
939 my_intr, sc, &sc->my_intrhand);
940
941 if (error) {
942 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
943 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
944 printf("my%d: couldn't set up irq\n", unit);
945 goto fail;
946 }
947 callout_handle_init(&sc->my_stat_ch);
948
949 sc->my_info = my_info_tmp;
950
951 /* Reset the adapter. */
952 my_reset(sc);
953
954 /*
955 * Get station address
956 */
957 for (i = 0; i < ETHER_ADDR_LEN; ++i)
958 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
959
960 /*
961 * A Myson chip was detected. Inform the world.
962 */
963 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":");
964
965 sc->my_unit = unit;
966 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN);
967
968 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
969 M_DEVBUF, M_NOWAIT);
970 if (sc->my_ldata_ptr == NULL) {
971 free(sc, M_DEVBUF);
972 printf("my%d: no memory for list buffers!\n", unit);
973 error = ENXIO;
974 goto fail;
975 }
976 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
977 round = (unsigned int)sc->my_ldata_ptr & 0xF;
978 roundptr = sc->my_ldata_ptr;
979 for (i = 0; i < 8; i++) {
980 if (round % 8) {
981 round++;
982 roundptr++;
983 } else
984 break;
985 }
986 sc->my_ldata = (struct my_list_data *) roundptr;
987 bzero(sc->my_ldata, sizeof(struct my_list_data));
988
989 ifp = &sc->arpcom.ac_if;
990 ifp->if_softc = sc;
991 ifp->if_unit = unit;
992 ifp->if_name = "my";
993 ifp->if_mtu = ETHERMTU;
994 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
995 ifp->if_ioctl = my_ioctl;
996 ifp->if_output = ether_output;
997 ifp->if_start = my_start;
998 ifp->if_watchdog = my_watchdog;
999 ifp->if_init = my_init;
1000 ifp->if_baudrate = 10000000;
1001 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
1002
1003 if (sc->my_info->my_did == MTD803ID)
1004 sc->my_pinfo = my_phys;
1005 else {
1006 if (bootverbose)
1007 printf("my%d: probing for a PHY\n", sc->my_unit);
1008 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
1009 if (bootverbose)
1010 printf("my%d: checking address: %d\n",
1011 sc->my_unit, i);
1012 sc->my_phy_addr = i;
1013 phy_sts = my_phy_readreg(sc, PHY_BMSR);
1014 if ((phy_sts != 0) && (phy_sts != 0xffff))
1015 break;
1016 else
1017 phy_sts = 0;
1018 }
1019 if (phy_sts) {
1020 phy_vid = my_phy_readreg(sc, PHY_VENID);
1021 phy_did = my_phy_readreg(sc, PHY_DEVID);
1022 if (bootverbose) {
1023 printf("my%d: found PHY at address %d, ",
1024 sc->my_unit, sc->my_phy_addr);
1025 printf("vendor id: %x device id: %x\n",
1026 phy_vid, phy_did);
1027 }
1028 p = my_phys;
1029 while (p->my_vid) {
1030 if (phy_vid == p->my_vid) {
1031 sc->my_pinfo = p;
1032 break;
1033 }
1034 p++;
1035 }
1036 if (sc->my_pinfo == NULL)
1037 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
1038 if (bootverbose)
1039 printf("my%d: PHY type: %s\n",
1040 sc->my_unit, sc->my_pinfo->my_name);
1041 } else {
1042 printf("my%d: MII without any phy!\n", sc->my_unit);
1043 error = ENXIO;
1044 goto fail;
1045 }
1046 }
1047
1048 /* Do ifmedia setup. */
1049 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
1050 my_getmode_mii(sc);
1051 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
1052 media = sc->ifmedia.ifm_media;
1053 my_stop(sc);
1054 ifmedia_set(&sc->ifmedia, media);
1055
1056 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
1057
1058 #if 0
1059 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC);
1060 shutdownhook_establish(my_shutdown, sc);
1061 #endif
1062
1063 MY_UNLOCK(sc);
1064 return (0);
1065
1066 fail:
1067 MY_UNLOCK(sc);
1068 /*mtx_destroy(&sc->my_mtx);*/
1069 splx(s);
1070 return (error);
1071 }
1072
1073 static int
1074 my_detach(device_t dev)
1075 {
1076 struct my_softc *sc;
1077 struct ifnet *ifp;
1078 int s;
1079
1080 s = splimp();
1081 sc = device_get_softc(dev);
1082 MY_LOCK(sc);
1083 ifp = &sc->arpcom.ac_if;
1084 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
1085 my_stop(sc);
1086
1087 #if 0
1088 bus_generic_detach(dev);
1089 device_delete_child(dev, sc->rl_miibus);
1090 #endif
1091
1092 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1093 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1094 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1095 #if 0
1096 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF);
1097 #endif
1098 free(sc, M_DEVBUF);
1099 MY_UNLOCK(sc);
1100 splx(s);
1101 /*mtx_destroy(&sc->my_mtx);*/
1102 return (0);
1103 }
1104
1105
1106 /*
1107 * Initialize the transmit descriptors.
1108 */
1109 static int
1110 my_list_tx_init(struct my_softc * sc)
1111 {
1112 struct my_chain_data *cd;
1113 struct my_list_data *ld;
1114 int i;
1115
1116 MY_LOCK(sc);
1117 cd = &sc->my_cdata;
1118 ld = sc->my_ldata;
1119 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1120 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1121 if (i == (MY_TX_LIST_CNT - 1))
1122 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1123 else
1124 cd->my_tx_chain[i].my_nextdesc =
1125 &cd->my_tx_chain[i + 1];
1126 }
1127 cd->my_tx_free = &cd->my_tx_chain[0];
1128 cd->my_tx_tail = cd->my_tx_head = NULL;
1129 MY_UNLOCK(sc);
1130 return (0);
1131 }
1132
1133 /*
1134 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1135 * arrange the descriptors in a closed ring, so that the last descriptor
1136 * points back to the first.
1137 */
1138 static int
1139 my_list_rx_init(struct my_softc * sc)
1140 {
1141 struct my_chain_data *cd;
1142 struct my_list_data *ld;
1143 int i;
1144
1145 MY_LOCK(sc);
1146 cd = &sc->my_cdata;
1147 ld = sc->my_ldata;
1148 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1149 cd->my_rx_chain[i].my_ptr =
1150 (struct my_desc *) & ld->my_rx_list[i];
1151 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS)
1152 return (ENOBUFS);
1153 if (i == (MY_RX_LIST_CNT - 1)) {
1154 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1155 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1156 } else {
1157 cd->my_rx_chain[i].my_nextdesc =
1158 &cd->my_rx_chain[i + 1];
1159 ld->my_rx_list[i].my_next =
1160 vtophys(&ld->my_rx_list[i + 1]);
1161 }
1162 }
1163 cd->my_rx_head = &cd->my_rx_chain[0];
1164 MY_UNLOCK(sc);
1165 return (0);
1166 }
1167
1168 /*
1169 * Initialize an RX descriptor and attach an MBUF cluster.
1170 */
1171 static int
1172 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1173 {
1174 struct mbuf *m_new = NULL;
1175
1176 MY_LOCK(sc);
1177 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1178 if (m_new == NULL) {
1179 printf("my%d: no memory for rx list -- packet dropped!\n",
1180 sc->my_unit);
1181 return (ENOBUFS);
1182 }
1183 MCLGET(m_new, M_DONTWAIT);
1184 if (!(m_new->m_flags & M_EXT)) {
1185 printf("my%d: no memory for rx list -- packet dropped!\n",
1186 sc->my_unit);
1187 m_freem(m_new);
1188 return (ENOBUFS);
1189 }
1190 c->my_mbuf = m_new;
1191 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1192 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1193 c->my_ptr->my_status = MY_OWNByNIC;
1194 MY_UNLOCK(sc);
1195 return (0);
1196 }
1197
1198 /*
1199 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1200 * level protocols.
1201 */
1202 static void
1203 my_rxeof(struct my_softc * sc)
1204 {
1205 struct ether_header *eh;
1206 struct mbuf *m;
1207 struct ifnet *ifp;
1208 struct my_chain_onefrag *cur_rx;
1209 int total_len = 0;
1210 u_int32_t rxstat;
1211
1212 MY_LOCK(sc);
1213 ifp = &sc->arpcom.ac_if;
1214 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1215 & MY_OWNByNIC)) {
1216 cur_rx = sc->my_cdata.my_rx_head;
1217 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1218
1219 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1220 ifp->if_ierrors++;
1221 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1222 continue;
1223 }
1224 /* No errors; receive the packet. */
1225 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1226 total_len -= ETHER_CRC_LEN;
1227
1228 if (total_len < MINCLSIZE) {
1229 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1230 total_len, 0, ifp, NULL);
1231 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1232 if (m == NULL) {
1233 ifp->if_ierrors++;
1234 continue;
1235 }
1236 } else {
1237 m = cur_rx->my_mbuf;
1238 /*
1239 * Try to conjure up a new mbuf cluster. If that
1240 * fails, it means we have an out of memory condition
1241 * and should leave the buffer in place and continue.
1242 * This will result in a lost packet, but there's
1243 * little else we can do in this situation.
1244 */
1245 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1246 ifp->if_ierrors++;
1247 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1248 continue;
1249 }
1250 m->m_pkthdr.rcvif = ifp;
1251 m->m_pkthdr.len = m->m_len = total_len;
1252 }
1253 ifp->if_ipackets++;
1254 eh = mtod(m, struct ether_header *);
1255 #if NBPFILTER > 0
1256 /*
1257 * Handle BPF listeners. Let the BPF user see the packet, but
1258 * don't pass it up to the ether_input() layer unless it's a
1259 * broadcast packet, multicast packet, matches our ethernet
1260 * address or the interface is in promiscuous mode.
1261 */
1262 if (ifp->if_bpf) {
1263 bpf_mtap(ifp, m);
1264 if (ifp->if_flags & IFF_PROMISC &&
1265 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
1266 ETHER_ADDR_LEN) &&
1267 (eh->ether_dhost[0] & 1) == 0)) {
1268 m_freem(m);
1269 continue;
1270 }
1271 }
1272 #endif
1273 /* Remove header from mbuf and pass it on. */
1274 m_adj(m, sizeof(struct ether_header));
1275 ether_input(ifp, eh, m);
1276 }
1277 MY_UNLOCK(sc);
1278 return;
1279 }
1280
1281
1282 /*
1283 * A frame was downloaded to the chip. It's safe for us to clean up the list
1284 * buffers.
1285 */
1286 static void
1287 my_txeof(struct my_softc * sc)
1288 {
1289 struct my_chain *cur_tx;
1290 struct ifnet *ifp;
1291
1292 MY_LOCK(sc);
1293 ifp = &sc->arpcom.ac_if;
1294 /* Clear the timeout timer. */
1295 ifp->if_timer = 0;
1296 if (sc->my_cdata.my_tx_head == NULL)
1297 return;
1298 /*
1299 * Go through our tx list and free mbufs for those frames that have
1300 * been transmitted.
1301 */
1302 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1303 u_int32_t txstat;
1304
1305 cur_tx = sc->my_cdata.my_tx_head;
1306 txstat = MY_TXSTATUS(cur_tx);
1307 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1308 break;
1309 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1310 if (txstat & MY_TXERR) {
1311 ifp->if_oerrors++;
1312 if (txstat & MY_EC) /* excessive collision */
1313 ifp->if_collisions++;
1314 if (txstat & MY_LC) /* late collision */
1315 ifp->if_collisions++;
1316 }
1317 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1318 MY_NCRShift;
1319 }
1320 ifp->if_opackets++;
1321 m_freem(cur_tx->my_mbuf);
1322 cur_tx->my_mbuf = NULL;
1323 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1324 sc->my_cdata.my_tx_head = NULL;
1325 sc->my_cdata.my_tx_tail = NULL;
1326 break;
1327 }
1328 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1329 }
1330 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1331 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1332 }
1333 MY_UNLOCK(sc);
1334 return;
1335 }
1336
1337 /*
1338 * TX 'end of channel' interrupt handler.
1339 */
1340 static void
1341 my_txeoc(struct my_softc * sc)
1342 {
1343 struct ifnet *ifp;
1344
1345 MY_LOCK(sc);
1346 ifp = &sc->arpcom.ac_if;
1347 ifp->if_timer = 0;
1348 if (sc->my_cdata.my_tx_head == NULL) {
1349 ifp->if_flags &= ~IFF_OACTIVE;
1350 sc->my_cdata.my_tx_tail = NULL;
1351 if (sc->my_want_auto)
1352 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1353 } else {
1354 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1355 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1356 ifp->if_timer = 5;
1357 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1358 }
1359 }
1360 MY_UNLOCK(sc);
1361 return;
1362 }
1363
1364 static void
1365 my_intr(void *arg)
1366 {
1367 struct my_softc *sc;
1368 struct ifnet *ifp;
1369 u_int32_t status;
1370
1371 sc = arg;
1372 MY_LOCK(sc);
1373 ifp = &sc->arpcom.ac_if;
1374 if (!(ifp->if_flags & IFF_UP)) {
1375 MY_UNLOCK(sc);
1376 return;
1377 }
1378 /* Disable interrupts. */
1379 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1380
1381 for (;;) {
1382 status = CSR_READ_4(sc, MY_ISR);
1383 status &= MY_INTRS;
1384 if (status)
1385 CSR_WRITE_4(sc, MY_ISR, status);
1386 else
1387 break;
1388
1389 if (status & MY_RI) /* receive interrupt */
1390 my_rxeof(sc);
1391
1392 if ((status & MY_RBU) || (status & MY_RxErr)) {
1393 /* rx buffer unavailable or rx error */
1394 ifp->if_ierrors++;
1395 #ifdef foo
1396 my_stop(sc);
1397 my_reset(sc);
1398 my_init(sc);
1399 #endif
1400 }
1401 if (status & MY_TI) /* tx interrupt */
1402 my_txeof(sc);
1403 if (status & MY_ETI) /* tx early interrupt */
1404 my_txeof(sc);
1405 if (status & MY_TBU) /* tx buffer unavailable */
1406 my_txeoc(sc);
1407
1408 #if 0 /* 90/1/18 delete */
1409 if (status & MY_FBE) {
1410 my_reset(sc);
1411 my_init(sc);
1412 }
1413 #endif
1414
1415 }
1416
1417 /* Re-enable interrupts. */
1418 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1419 if (ifp->if_snd.ifq_head != NULL)
1420 my_start(ifp);
1421 MY_UNLOCK(sc);
1422 return;
1423 }
1424
1425 /*
1426 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1427 * pointers to the fragment pointers.
1428 */
1429 static int
1430 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1431 {
1432 struct my_desc *f = NULL;
1433 int total_len;
1434 struct mbuf *m, *m_new = NULL;
1435
1436 MY_LOCK(sc);
1437 /* calculate the total tx pkt length */
1438 total_len = 0;
1439 for (m = m_head; m != NULL; m = m->m_next)
1440 total_len += m->m_len;
1441 /*
1442 * Start packing the mbufs in this chain into the fragment pointers.
1443 * Stop when we run out of fragments or hit the end of the mbuf
1444 * chain.
1445 */
1446 m = m_head;
1447 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1448 if (m_new == NULL) {
1449 printf("my%d: no memory for tx list", sc->my_unit);
1450 return (1);
1451 }
1452 if (m_head->m_pkthdr.len > MHLEN) {
1453 MCLGET(m_new, M_DONTWAIT);
1454 if (!(m_new->m_flags & M_EXT)) {
1455 m_freem(m_new);
1456 printf("my%d: no memory for tx list", sc->my_unit);
1457 return (1);
1458 }
1459 }
1460 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1461 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1462 m_freem(m_head);
1463 m_head = m_new;
1464 f = &c->my_ptr->my_frag[0];
1465 f->my_status = 0;
1466 f->my_data = vtophys(mtod(m_new, caddr_t));
1467 total_len = m_new->m_len;
1468 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1469 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1470 f->my_ctl |= total_len; /* buffer size */
1471 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1472 if (sc->my_info->my_did == MTD891ID)
1473 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1474 c->my_mbuf = m_head;
1475 c->my_lastdesc = 0;
1476 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1477 MY_UNLOCK(sc);
1478 return (0);
1479 }
1480
1481 /*
1482 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1483 * to the mbuf data regions directly in the transmit lists. We also save a
1484 * copy of the pointers since the transmit list fragment pointers are
1485 * physical addresses.
1486 */
1487 static void
1488 my_start(struct ifnet * ifp)
1489 {
1490 struct my_softc *sc;
1491 struct mbuf *m_head = NULL;
1492 struct my_chain *cur_tx = NULL, *start_tx;
1493
1494 sc = ifp->if_softc;
1495 MY_LOCK(sc);
1496 if (sc->my_autoneg) {
1497 sc->my_tx_pend = 1;
1498 MY_UNLOCK(sc);
1499 return;
1500 }
1501 /*
1502 * Check for an available queue slot. If there are none, punt.
1503 */
1504 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1505 ifp->if_flags |= IFF_OACTIVE;
1506 MY_UNLOCK(sc);
1507 return;
1508 }
1509 start_tx = sc->my_cdata.my_tx_free;
1510 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1511 IF_DEQUEUE(&ifp->if_snd, m_head);
1512 if (m_head == NULL)
1513 break;
1514
1515 /* Pick a descriptor off the free list. */
1516 cur_tx = sc->my_cdata.my_tx_free;
1517 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1518
1519 /* Pack the data into the descriptor. */
1520 my_encap(sc, cur_tx, m_head);
1521
1522 if (cur_tx != start_tx)
1523 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1524 #if NBPFILTER > 0
1525 /*
1526 * If there's a BPF listener, bounce a copy of this frame to
1527 * him.
1528 */
1529 if (ifp->if_bpf)
1530 bpf_mtap(ifp, cur_tx->my_mbuf);
1531 #endif
1532 }
1533 /*
1534 * If there are no packets queued, bail.
1535 */
1536 if (cur_tx == NULL) {
1537 MY_UNLOCK(sc);
1538 return;
1539 }
1540 /*
1541 * Place the request for the upload interrupt in the last descriptor
1542 * in the chain. This way, if we're chaining several packets at once,
1543 * we'll only get an interupt once for the whole chain rather than
1544 * once for each packet.
1545 */
1546 MY_TXCTL(cur_tx) |= MY_TXIC;
1547 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1548 sc->my_cdata.my_tx_tail = cur_tx;
1549 if (sc->my_cdata.my_tx_head == NULL)
1550 sc->my_cdata.my_tx_head = start_tx;
1551 MY_TXOWN(start_tx) = MY_OWNByNIC;
1552 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1553
1554 /*
1555 * Set a timeout in case the chip goes out to lunch.
1556 */
1557 ifp->if_timer = 5;
1558 MY_UNLOCK(sc);
1559 return;
1560 }
1561
1562 static void
1563 my_init(void *xsc)
1564 {
1565 struct my_softc *sc = xsc;
1566 struct ifnet *ifp = &sc->arpcom.ac_if;
1567 int s;
1568 u_int16_t phy_bmcr = 0;
1569
1570 MY_LOCK(sc);
1571 if (sc->my_autoneg) {
1572 MY_UNLOCK(sc);
1573 return;
1574 }
1575 s = splimp();
1576 if (sc->my_pinfo != NULL)
1577 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1578 /*
1579 * Cancel pending I/O and free all RX/TX buffers.
1580 */
1581 my_stop(sc);
1582 my_reset(sc);
1583
1584 /*
1585 * Set cache alignment and burst length.
1586 */
1587 #if 0 /* 89/9/1 modify, */
1588 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1589 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1590 #endif
1591 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1592 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1593 /*
1594 * 89/12/29 add, for mtd891,
1595 */
1596 if (sc->my_info->my_did == MTD891ID) {
1597 MY_SETBIT(sc, MY_BCR, MY_PROG);
1598 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1599 }
1600 my_setcfg(sc, phy_bmcr);
1601 /* Init circular RX list. */
1602 if (my_list_rx_init(sc) == ENOBUFS) {
1603 printf("my%d: init failed: no memory for rx buffers\n",
1604 sc->my_unit);
1605 my_stop(sc);
1606 (void)splx(s);
1607 MY_UNLOCK(sc);
1608 return;
1609 }
1610 /* Init TX descriptors. */
1611 my_list_tx_init(sc);
1612
1613 /* If we want promiscuous mode, set the allframes bit. */
1614 if (ifp->if_flags & IFF_PROMISC)
1615 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1616 else
1617 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1618
1619 /*
1620 * Set capture broadcast bit to capture broadcast frames.
1621 */
1622 if (ifp->if_flags & IFF_BROADCAST)
1623 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1624 else
1625 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1626
1627 /*
1628 * Program the multicast filter, if necessary.
1629 */
1630 my_setmulti(sc);
1631
1632 /*
1633 * Load the address of the RX list.
1634 */
1635 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1636 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1637
1638 /*
1639 * Enable interrupts.
1640 */
1641 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1642 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1643
1644 /* Enable receiver and transmitter. */
1645 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1646 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1647 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1648 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1649
1650 /* Restore state of BMCR */
1651 if (sc->my_pinfo != NULL)
1652 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1653 ifp->if_flags |= IFF_RUNNING;
1654 ifp->if_flags &= ~IFF_OACTIVE;
1655 (void)splx(s);
1656 MY_UNLOCK(sc);
1657 return;
1658 }
1659
1660 /*
1661 * Set media options.
1662 */
1663
1664 static int
1665 my_ifmedia_upd(struct ifnet * ifp)
1666 {
1667 struct my_softc *sc;
1668 struct ifmedia *ifm;
1669
1670 sc = ifp->if_softc;
1671 MY_LOCK(sc);
1672 ifm = &sc->ifmedia;
1673 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1674 MY_UNLOCK(sc);
1675 return (EINVAL);
1676 }
1677 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1678 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1679 else
1680 my_setmode_mii(sc, ifm->ifm_media);
1681 MY_UNLOCK(sc);
1682 return (0);
1683 }
1684
1685 /*
1686 * Report current media status.
1687 */
1688
1689 static void
1690 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1691 {
1692 struct my_softc *sc;
1693 u_int16_t advert = 0, ability = 0;
1694
1695 sc = ifp->if_softc;
1696 MY_LOCK(sc);
1697 ifmr->ifm_active = IFM_ETHER;
1698 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1699 #if 0 /* this version did not support 1000M, */
1700 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1701 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1702 #endif
1703 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1704 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1705 else
1706 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1707 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1708 ifmr->ifm_active |= IFM_FDX;
1709 else
1710 ifmr->ifm_active |= IFM_HDX;
1711
1712 MY_UNLOCK(sc);
1713 return;
1714 }
1715 ability = my_phy_readreg(sc, PHY_LPAR);
1716 advert = my_phy_readreg(sc, PHY_ANAR);
1717
1718 #if 0 /* this version did not support 1000M, */
1719 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1720 ability2 = my_phy_readreg(sc, PHY_1000SR);
1721 if (ability2 & PHY_1000SR_1000BTXFULL) {
1722 advert = 0;
1723 ability = 0;
1724 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_FDX;
1725 } else if (ability & PHY_1000SR_1000BTXHALF) {
1726 advert = 0;
1727 ability = 0;
1728 ifmr->ifm_active = IFM_ETHER|IFM_1000_TX|IFM_HDX;
1729 }
1730 }
1731 #endif
1732 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1733 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1734 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1735 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1736 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1737 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1738 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1739 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1740 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1741 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1742 MY_UNLOCK(sc);
1743 return;
1744 }
1745
1746 static int
1747 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1748 {
1749 struct my_softc *sc = ifp->if_softc;
1750 struct ifreq *ifr = (struct ifreq *) data;
1751 int s, error = 0;
1752
1753 s = splimp();
1754 MY_LOCK(sc);
1755 switch (command) {
1756 case SIOCSIFADDR:
1757 case SIOCGIFADDR:
1758 case SIOCSIFMTU:
1759 error = ether_ioctl(ifp, command, data);
1760 break;
1761 case SIOCSIFFLAGS:
1762 if (ifp->if_flags & IFF_UP)
1763 my_init(sc);
1764 else if (ifp->if_flags & IFF_RUNNING)
1765 my_stop(sc);
1766 error = 0;
1767 break;
1768 case SIOCADDMULTI:
1769 case SIOCDELMULTI:
1770 my_setmulti(sc);
1771 error = 0;
1772 break;
1773 case SIOCGIFMEDIA:
1774 case SIOCSIFMEDIA:
1775 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1776 break;
1777 default:
1778 error = EINVAL;
1779 break;
1780 }
1781 MY_UNLOCK(sc);
1782 (void)splx(s);
1783 return (error);
1784 }
1785
1786 static void
1787 my_watchdog(struct ifnet * ifp)
1788 {
1789 struct my_softc *sc;
1790
1791 sc = ifp->if_softc;
1792 MY_LOCK(sc);
1793 if (sc->my_autoneg) {
1794 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
1795 MY_UNLOCK(sc);
1796 return;
1797 }
1798 ifp->if_oerrors++;
1799 printf("my%d: watchdog timeout\n", sc->my_unit);
1800 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1801 printf("my%d: no carrier - transceiver cable problem?\n",
1802 sc->my_unit);
1803 my_stop(sc);
1804 my_reset(sc);
1805 my_init(sc);
1806 if (ifp->if_snd.ifq_head != NULL)
1807 my_start(ifp);
1808 MY_LOCK(sc);
1809 return;
1810 }
1811
1812
1813 /*
1814 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1815 */
1816 static void
1817 my_stop(struct my_softc * sc)
1818 {
1819 register int i;
1820 struct ifnet *ifp;
1821
1822 MY_LOCK(sc);
1823 ifp = &sc->arpcom.ac_if;
1824 ifp->if_timer = 0;
1825
1826 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1827 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1828 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1829 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1830
1831 /*
1832 * Free data in the RX lists.
1833 */
1834 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1835 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1836 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1837 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1838 }
1839 }
1840 bzero((char *)&sc->my_ldata->my_rx_list,
1841 sizeof(sc->my_ldata->my_rx_list));
1842 /*
1843 * Free the TX list buffers.
1844 */
1845 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1846 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1847 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1848 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1849 }
1850 }
1851 bzero((char *)&sc->my_ldata->my_tx_list,
1852 sizeof(sc->my_ldata->my_tx_list));
1853 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1854 MY_UNLOCK(sc);
1855 return;
1856 }
1857
1858 /*
1859 * Stop all chip I/O so that the kernel's probe routines don't get confused
1860 * by errant DMAs when rebooting.
1861 */
1862 static void
1863 my_shutdown(device_t dev)
1864 {
1865 struct my_softc *sc;
1866
1867 sc = device_get_softc(dev);
1868 my_stop(sc);
1869 return;
1870 }
Cache object: 65cbede1e4eb420293b836bac9ef7c9d
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