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sys/dev/my/if_my.c
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1 /* 2 * Copyright (c) 2002 Myson Technology Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 27 * 28 * Myson fast ethernet PCI NIC driver 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD: releng/5.1/sys/dev/my/if_my.c 113506 2003-04-15 06:37:30Z mdodd $"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/sockio.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/queue.h> 42 #include <sys/types.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/lock.h> 46 #include <sys/mutex.h> 47 48 #define NBPFILTER 1 49 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_media.h> 54 #include <net/if_dl.h> 55 #include <net/bpf.h> 56 57 #include <vm/vm.h> /* for vtophys */ 58 #include <vm/pmap.h> /* for vtophys */ 59 #include <machine/clock.h> /* for DELAY */ 60 #include <machine/bus_memio.h> 61 #include <machine/bus_pio.h> 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/bus.h> 65 #include <sys/rman.h> 66 67 #include <pci/pcireg.h> 68 #include <pci/pcivar.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 73 #include "miibus_if.h" 74 75 /* 76 * #define MY_USEIOSPACE 77 */ 78 79 static int MY_USEIOSPACE = 1; 80 81 #if (MY_USEIOSPACE) 82 #define MY_RES SYS_RES_IOPORT 83 #define MY_RID MY_PCI_LOIO 84 #else 85 #define MY_RES SYS_RES_MEMORY 86 #define MY_RID MY_PCI_LOMEM 87 #endif 88 89 90 #include <dev/my/if_myreg.h> 91 92 #ifndef lint 93 static const char rcsid[] = 94 "$Id: if_my.c,v 1.50 2001/12/03 04:15:33 <yen_cw@myson.com.tw> wpaul Exp $"; 95 #endif 96 97 /* 98 * Various supported device vendors/types and their names. 99 */ 100 struct my_type *my_info_tmp; 101 static struct my_type my_devs[] = { 102 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 103 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 104 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 105 {0, 0, NULL} 106 }; 107 108 /* 109 * Various supported PHY vendors/types and their names. Note that this driver 110 * will work with pretty much any MII-compliant PHY, so failure to positively 111 * identify the chip is not a fatal error. 112 */ 113 static struct my_type my_phys[] = { 114 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 115 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 116 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 117 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 118 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 119 {0, 0, "<MII-compliant physical interface>"} 120 }; 121 122 static int my_probe(device_t); 123 static int my_attach(device_t); 124 static int my_detach(device_t); 125 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 126 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 127 static void my_rxeof(struct my_softc *); 128 static void my_txeof(struct my_softc *); 129 static void my_txeoc(struct my_softc *); 130 static void my_intr(void *); 131 static void my_start(struct ifnet *); 132 static int my_ioctl(struct ifnet *, u_long, caddr_t); 133 static void my_init(void *); 134 static void my_stop(struct my_softc *); 135 static void my_watchdog(struct ifnet *); 136 static void my_shutdown(device_t); 137 static int my_ifmedia_upd(struct ifnet *); 138 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 139 static u_int16_t my_phy_readreg(struct my_softc *, int); 140 static void my_phy_writereg(struct my_softc *, int, int); 141 static void my_autoneg_xmit(struct my_softc *); 142 static void my_autoneg_mii(struct my_softc *, int, int); 143 static void my_setmode_mii(struct my_softc *, int); 144 static void my_getmode_mii(struct my_softc *); 145 static void my_setcfg(struct my_softc *, int); 146 static u_int8_t my_calchash(caddr_t); 147 static void my_setmulti(struct my_softc *); 148 static void my_reset(struct my_softc *); 149 static int my_list_rx_init(struct my_softc *); 150 static int my_list_tx_init(struct my_softc *); 151 static long my_send_cmd_to_phy(struct my_softc *, int, int); 152 153 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 154 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 155 156 static device_method_t my_methods[] = { 157 /* Device interface */ 158 DEVMETHOD(device_probe, my_probe), 159 DEVMETHOD(device_attach, my_attach), 160 DEVMETHOD(device_detach, my_detach), 161 DEVMETHOD(device_shutdown, my_shutdown), 162 163 {0, 0} 164 }; 165 166 static driver_t my_driver = { 167 "my", 168 my_methods, 169 sizeof(struct my_softc) 170 }; 171 172 static devclass_t my_devclass; 173 174 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0); 175 MODULE_DEPEND(my, pci, 1, 1, 1); 176 MODULE_DEPEND(my, ether, 1, 1, 1); 177 178 static long 179 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 180 { 181 long miir; 182 int i; 183 int mask, data; 184 185 MY_LOCK(sc); 186 187 /* enable MII output */ 188 miir = CSR_READ_4(sc, MY_MANAGEMENT); 189 miir &= 0xfffffff0; 190 191 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 192 193 /* send 32 1's preamble */ 194 for (i = 0; i < 32; i++) { 195 /* low MDC; MDO is already high (miir) */ 196 miir &= ~MY_MASK_MIIR_MII_MDC; 197 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 198 199 /* high MDC */ 200 miir |= MY_MASK_MIIR_MII_MDC; 201 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 202 } 203 204 /* calculate ST+OP+PHYAD+REGAD+TA */ 205 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 206 207 /* sent out */ 208 mask = 0x8000; 209 while (mask) { 210 /* low MDC, prepare MDO */ 211 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 212 if (mask & data) 213 miir |= MY_MASK_MIIR_MII_MDO; 214 215 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 216 /* high MDC */ 217 miir |= MY_MASK_MIIR_MII_MDC; 218 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 219 DELAY(30); 220 221 /* next */ 222 mask >>= 1; 223 if (mask == 0x2 && opcode == MY_OP_READ) 224 miir &= ~MY_MASK_MIIR_MII_WRITE; 225 } 226 227 MY_UNLOCK(sc); 228 return miir; 229 } 230 231 232 static u_int16_t 233 my_phy_readreg(struct my_softc * sc, int reg) 234 { 235 long miir; 236 int mask, data; 237 238 MY_LOCK(sc); 239 240 if (sc->my_info->my_did == MTD803ID) 241 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 242 else { 243 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 244 245 /* read data */ 246 mask = 0x8000; 247 data = 0; 248 while (mask) { 249 /* low MDC */ 250 miir &= ~MY_MASK_MIIR_MII_MDC; 251 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 252 253 /* read MDI */ 254 miir = CSR_READ_4(sc, MY_MANAGEMENT); 255 if (miir & MY_MASK_MIIR_MII_MDI) 256 data |= mask; 257 258 /* high MDC, and wait */ 259 miir |= MY_MASK_MIIR_MII_MDC; 260 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 261 DELAY(30); 262 263 /* next */ 264 mask >>= 1; 265 } 266 267 /* low MDC */ 268 miir &= ~MY_MASK_MIIR_MII_MDC; 269 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 270 } 271 272 MY_UNLOCK(sc); 273 return (u_int16_t) data; 274 } 275 276 277 static void 278 my_phy_writereg(struct my_softc * sc, int reg, int data) 279 { 280 long miir; 281 int mask; 282 283 MY_LOCK(sc); 284 285 if (sc->my_info->my_did == MTD803ID) 286 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 287 else { 288 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 289 290 /* write data */ 291 mask = 0x8000; 292 while (mask) { 293 /* low MDC, prepare MDO */ 294 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 295 if (mask & data) 296 miir |= MY_MASK_MIIR_MII_MDO; 297 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 298 DELAY(1); 299 300 /* high MDC */ 301 miir |= MY_MASK_MIIR_MII_MDC; 302 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 303 DELAY(1); 304 305 /* next */ 306 mask >>= 1; 307 } 308 309 /* low MDC */ 310 miir &= ~MY_MASK_MIIR_MII_MDC; 311 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 312 } 313 MY_UNLOCK(sc); 314 return; 315 } 316 317 static u_int8_t 318 my_calchash(caddr_t addr) 319 { 320 u_int32_t crc, carry; 321 int i, j; 322 u_int8_t c; 323 324 /* Compute CRC for the address value. */ 325 crc = 0xFFFFFFFF; /* initial value */ 326 327 for (i = 0; i < 6; i++) { 328 c = *(addr + i); 329 for (j = 0; j < 8; j++) { 330 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 331 crc <<= 1; 332 c >>= 1; 333 if (carry) 334 crc = (crc ^ 0x04c11db6) | carry; 335 } 336 } 337 338 /* 339 * return the filter bit position Note: I arrived at the following 340 * nonsense through experimentation. It's not the usual way to 341 * generate the bit position but it's the only thing I could come up 342 * with that works. 343 */ 344 return (~(crc >> 26) & 0x0000003F); 345 } 346 347 348 /* 349 * Program the 64-bit multicast hash filter. 350 */ 351 static void 352 my_setmulti(struct my_softc * sc) 353 { 354 struct ifnet *ifp; 355 int h = 0; 356 u_int32_t hashes[2] = {0, 0}; 357 struct ifmultiaddr *ifma; 358 u_int32_t rxfilt; 359 int mcnt = 0; 360 361 MY_LOCK(sc); 362 363 ifp = &sc->arpcom.ac_if; 364 365 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 366 367 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 368 rxfilt |= MY_AM; 369 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 370 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 371 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 372 373 MY_UNLOCK(sc); 374 375 return; 376 } 377 /* first, zot all the existing hash bits */ 378 CSR_WRITE_4(sc, MY_MAR0, 0); 379 CSR_WRITE_4(sc, MY_MAR1, 0); 380 381 /* now program new ones */ 382 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 383 if (ifma->ifma_addr->sa_family != AF_LINK) 384 continue; 385 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 386 if (h < 32) 387 hashes[0] |= (1 << h); 388 else 389 hashes[1] |= (1 << (h - 32)); 390 mcnt++; 391 } 392 393 if (mcnt) 394 rxfilt |= MY_AM; 395 else 396 rxfilt &= ~MY_AM; 397 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 398 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 399 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 400 MY_UNLOCK(sc); 401 return; 402 } 403 404 /* 405 * Initiate an autonegotiation session. 406 */ 407 static void 408 my_autoneg_xmit(struct my_softc * sc) 409 { 410 u_int16_t phy_sts = 0; 411 412 MY_LOCK(sc); 413 414 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 415 DELAY(500); 416 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 417 418 phy_sts = my_phy_readreg(sc, PHY_BMCR); 419 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 420 my_phy_writereg(sc, PHY_BMCR, phy_sts); 421 422 MY_UNLOCK(sc); 423 return; 424 } 425 426 427 /* 428 * Invoke autonegotiation on a PHY. 429 */ 430 static void 431 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 432 { 433 u_int16_t phy_sts = 0, media, advert, ability; 434 u_int16_t ability2 = 0; 435 struct ifnet *ifp; 436 struct ifmedia *ifm; 437 438 MY_LOCK(sc); 439 440 ifm = &sc->ifmedia; 441 ifp = &sc->arpcom.ac_if; 442 443 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 444 445 #ifndef FORCE_AUTONEG_TFOUR 446 /* 447 * First, see if autoneg is supported. If not, there's no point in 448 * continuing. 449 */ 450 phy_sts = my_phy_readreg(sc, PHY_BMSR); 451 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 452 if (verbose) 453 printf("my%d: autonegotiation not supported\n", 454 sc->my_unit); 455 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 456 MY_UNLOCK(sc); 457 return; 458 } 459 #endif 460 switch (flag) { 461 case MY_FLAG_FORCEDELAY: 462 /* 463 * XXX Never use this option anywhere but in the probe 464 * routine: making the kernel stop dead in its tracks for 465 * three whole seconds after we've gone multi-user is really 466 * bad manners. 467 */ 468 my_autoneg_xmit(sc); 469 DELAY(5000000); 470 break; 471 case MY_FLAG_SCHEDDELAY: 472 /* 473 * Wait for the transmitter to go idle before starting an 474 * autoneg session, otherwise my_start() may clobber our 475 * timeout, and we don't want to allow transmission during an 476 * autoneg session since that can screw it up. 477 */ 478 if (sc->my_cdata.my_tx_head != NULL) { 479 sc->my_want_auto = 1; 480 MY_UNLOCK(sc); 481 return; 482 } 483 my_autoneg_xmit(sc); 484 ifp->if_timer = 5; 485 sc->my_autoneg = 1; 486 sc->my_want_auto = 0; 487 MY_UNLOCK(sc); 488 return; 489 case MY_FLAG_DELAYTIMEO: 490 ifp->if_timer = 0; 491 sc->my_autoneg = 0; 492 break; 493 default: 494 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 495 MY_UNLOCK(sc); 496 return; 497 } 498 499 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 500 if (verbose) 501 printf("my%d: autoneg complete, ", sc->my_unit); 502 phy_sts = my_phy_readreg(sc, PHY_BMSR); 503 } else { 504 if (verbose) 505 printf("my%d: autoneg not complete, ", sc->my_unit); 506 } 507 508 media = my_phy_readreg(sc, PHY_BMCR); 509 510 /* Link is good. Report modes and set duplex mode. */ 511 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 512 if (verbose) 513 printf("my%d: link status good. ", sc->my_unit); 514 advert = my_phy_readreg(sc, PHY_ANAR); 515 ability = my_phy_readreg(sc, PHY_LPAR); 516 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 517 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 518 ability2 = my_phy_readreg(sc, PHY_1000SR); 519 if (ability2 & PHY_1000SR_1000BTXFULL) { 520 advert = 0; 521 ability = 0; 522 /* 523 * this version did not support 1000M, 524 * ifm->ifm_media = 525 * IFM_ETHER|IFM_1000_T|IFM_FDX; 526 */ 527 ifm->ifm_media = 528 IFM_ETHER | IFM_100_TX | IFM_FDX; 529 media &= ~PHY_BMCR_SPEEDSEL; 530 media |= PHY_BMCR_1000; 531 media |= PHY_BMCR_DUPLEX; 532 printf("(full-duplex, 1000Mbps)\n"); 533 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 534 advert = 0; 535 ability = 0; 536 /* 537 * this version did not support 1000M, 538 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 539 */ 540 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 541 media &= ~PHY_BMCR_SPEEDSEL; 542 media &= ~PHY_BMCR_DUPLEX; 543 media |= PHY_BMCR_1000; 544 printf("(half-duplex, 1000Mbps)\n"); 545 } 546 } 547 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 548 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 549 media |= PHY_BMCR_SPEEDSEL; 550 media &= ~PHY_BMCR_DUPLEX; 551 printf("(100baseT4)\n"); 552 } else if (advert & PHY_ANAR_100BTXFULL && 553 ability & PHY_ANAR_100BTXFULL) { 554 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 555 media |= PHY_BMCR_SPEEDSEL; 556 media |= PHY_BMCR_DUPLEX; 557 printf("(full-duplex, 100Mbps)\n"); 558 } else if (advert & PHY_ANAR_100BTXHALF && 559 ability & PHY_ANAR_100BTXHALF) { 560 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 561 media |= PHY_BMCR_SPEEDSEL; 562 media &= ~PHY_BMCR_DUPLEX; 563 printf("(half-duplex, 100Mbps)\n"); 564 } else if (advert & PHY_ANAR_10BTFULL && 565 ability & PHY_ANAR_10BTFULL) { 566 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 567 media &= ~PHY_BMCR_SPEEDSEL; 568 media |= PHY_BMCR_DUPLEX; 569 printf("(full-duplex, 10Mbps)\n"); 570 } else if (advert) { 571 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 572 media &= ~PHY_BMCR_SPEEDSEL; 573 media &= ~PHY_BMCR_DUPLEX; 574 printf("(half-duplex, 10Mbps)\n"); 575 } 576 media &= ~PHY_BMCR_AUTONEGENBL; 577 578 /* Set ASIC's duplex mode to match the PHY. */ 579 my_phy_writereg(sc, PHY_BMCR, media); 580 my_setcfg(sc, media); 581 } else { 582 if (verbose) 583 printf("my%d: no carrier\n", sc->my_unit); 584 } 585 586 my_init(sc); 587 if (sc->my_tx_pend) { 588 sc->my_autoneg = 0; 589 sc->my_tx_pend = 0; 590 my_start(ifp); 591 } 592 MY_UNLOCK(sc); 593 return; 594 } 595 596 /* 597 * To get PHY ability. 598 */ 599 static void 600 my_getmode_mii(struct my_softc * sc) 601 { 602 u_int16_t bmsr; 603 struct ifnet *ifp; 604 605 MY_LOCK(sc); 606 ifp = &sc->arpcom.ac_if; 607 bmsr = my_phy_readreg(sc, PHY_BMSR); 608 if (bootverbose) 609 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 610 611 /* fallback */ 612 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 613 614 if (bmsr & PHY_BMSR_10BTHALF) { 615 if (bootverbose) 616 printf("my%d: 10Mbps half-duplex mode supported\n", 617 sc->my_unit); 618 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 619 0, NULL); 620 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 621 } 622 if (bmsr & PHY_BMSR_10BTFULL) { 623 if (bootverbose) 624 printf("my%d: 10Mbps full-duplex mode supported\n", 625 sc->my_unit); 626 627 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 628 0, NULL); 629 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 630 } 631 if (bmsr & PHY_BMSR_100BTXHALF) { 632 if (bootverbose) 633 printf("my%d: 100Mbps half-duplex mode supported\n", 634 sc->my_unit); 635 ifp->if_baudrate = 100000000; 636 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 637 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 638 0, NULL); 639 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 640 } 641 if (bmsr & PHY_BMSR_100BTXFULL) { 642 if (bootverbose) 643 printf("my%d: 100Mbps full-duplex mode supported\n", 644 sc->my_unit); 645 ifp->if_baudrate = 100000000; 646 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 647 0, NULL); 648 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 649 } 650 /* Some also support 100BaseT4. */ 651 if (bmsr & PHY_BMSR_100BT4) { 652 if (bootverbose) 653 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 654 ifp->if_baudrate = 100000000; 655 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 656 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 657 #ifdef FORCE_AUTONEG_TFOUR 658 if (bootverbose) 659 printf("my%d: forcing on autoneg support for BT4\n", 660 sc->my_unit); 661 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 662 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 663 #endif 664 } 665 #if 0 /* this version did not support 1000M, */ 666 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 667 if (bootverbose) 668 printf("my%d: 1000Mbps half-duplex mode supported\n", 669 sc->my_unit); 670 671 ifp->if_baudrate = 1000000000; 672 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 673 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 674 0, NULL); 675 if (bootverbose) 676 printf("my%d: 1000Mbps full-duplex mode supported\n", 677 sc->my_unit); 678 ifp->if_baudrate = 1000000000; 679 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 680 0, NULL); 681 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 682 } 683 #endif 684 if (bmsr & PHY_BMSR_CANAUTONEG) { 685 if (bootverbose) 686 printf("my%d: autoneg supported\n", sc->my_unit); 687 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 688 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 689 } 690 MY_UNLOCK(sc); 691 return; 692 } 693 694 /* 695 * Set speed and duplex mode. 696 */ 697 static void 698 my_setmode_mii(struct my_softc * sc, int media) 699 { 700 u_int16_t bmcr; 701 struct ifnet *ifp; 702 703 MY_LOCK(sc); 704 ifp = &sc->arpcom.ac_if; 705 /* 706 * If an autoneg session is in progress, stop it. 707 */ 708 if (sc->my_autoneg) { 709 printf("my%d: canceling autoneg session\n", sc->my_unit); 710 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 711 bmcr = my_phy_readreg(sc, PHY_BMCR); 712 bmcr &= ~PHY_BMCR_AUTONEGENBL; 713 my_phy_writereg(sc, PHY_BMCR, bmcr); 714 } 715 printf("my%d: selecting MII, ", sc->my_unit); 716 bmcr = my_phy_readreg(sc, PHY_BMCR); 717 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 718 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 719 720 #if 0 /* this version did not support 1000M, */ 721 if (IFM_SUBTYPE(media) == IFM_1000_T) { 722 printf("1000Mbps/T4, half-duplex\n"); 723 bmcr &= ~PHY_BMCR_SPEEDSEL; 724 bmcr &= ~PHY_BMCR_DUPLEX; 725 bmcr |= PHY_BMCR_1000; 726 } 727 #endif 728 if (IFM_SUBTYPE(media) == IFM_100_T4) { 729 printf("100Mbps/T4, half-duplex\n"); 730 bmcr |= PHY_BMCR_SPEEDSEL; 731 bmcr &= ~PHY_BMCR_DUPLEX; 732 } 733 if (IFM_SUBTYPE(media) == IFM_100_TX) { 734 printf("100Mbps, "); 735 bmcr |= PHY_BMCR_SPEEDSEL; 736 } 737 if (IFM_SUBTYPE(media) == IFM_10_T) { 738 printf("10Mbps, "); 739 bmcr &= ~PHY_BMCR_SPEEDSEL; 740 } 741 if ((media & IFM_GMASK) == IFM_FDX) { 742 printf("full duplex\n"); 743 bmcr |= PHY_BMCR_DUPLEX; 744 } else { 745 printf("half duplex\n"); 746 bmcr &= ~PHY_BMCR_DUPLEX; 747 } 748 my_phy_writereg(sc, PHY_BMCR, bmcr); 749 my_setcfg(sc, bmcr); 750 MY_UNLOCK(sc); 751 return; 752 } 753 754 /* 755 * The Myson manual states that in order to fiddle with the 'full-duplex' and 756 * '100Mbps' bits in the netconfig register, we first have to put the 757 * transmit and/or receive logic in the idle state. 758 */ 759 static void 760 my_setcfg(struct my_softc * sc, int bmcr) 761 { 762 int i, restart = 0; 763 764 MY_LOCK(sc); 765 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 766 restart = 1; 767 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 768 for (i = 0; i < MY_TIMEOUT; i++) { 769 DELAY(10); 770 if (!(CSR_READ_4(sc, MY_TCRRCR) & 771 (MY_TXRUN | MY_RXRUN))) 772 break; 773 } 774 if (i == MY_TIMEOUT) 775 printf("my%d: failed to force tx and rx to idle \n", 776 sc->my_unit); 777 } 778 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 779 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 780 if (bmcr & PHY_BMCR_1000) 781 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 782 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 783 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 784 if (bmcr & PHY_BMCR_DUPLEX) 785 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 786 else 787 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 788 if (restart) 789 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 790 MY_UNLOCK(sc); 791 return; 792 } 793 794 static void 795 my_reset(struct my_softc * sc) 796 { 797 register int i; 798 799 MY_LOCK(sc); 800 MY_SETBIT(sc, MY_BCR, MY_SWR); 801 for (i = 0; i < MY_TIMEOUT; i++) { 802 DELAY(10); 803 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 804 break; 805 } 806 if (i == MY_TIMEOUT) 807 printf("m0x%d: reset never completed!\n", sc->my_unit); 808 809 /* Wait a little while for the chip to get its brains in order. */ 810 DELAY(1000); 811 MY_UNLOCK(sc); 812 return; 813 } 814 815 /* 816 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 817 * list and return a device name if we find a match. 818 */ 819 static int 820 my_probe(device_t dev) 821 { 822 struct my_type *t; 823 824 t = my_devs; 825 while (t->my_name != NULL) { 826 if ((pci_get_vendor(dev) == t->my_vid) && 827 (pci_get_device(dev) == t->my_did)) { 828 device_set_desc(dev, t->my_name); 829 my_info_tmp = t; 830 return (0); 831 } 832 t++; 833 } 834 return (ENXIO); 835 } 836 837 /* 838 * Attach the interface. Allocate softc structures, do ifmedia setup and 839 * ethernet/BPF attach. 840 */ 841 static int 842 my_attach(device_t dev) 843 { 844 int s, i; 845 u_char eaddr[ETHER_ADDR_LEN]; 846 u_int32_t command, iobase; 847 struct my_softc *sc; 848 struct ifnet *ifp; 849 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 850 unsigned int round; 851 caddr_t roundptr; 852 struct my_type *p; 853 u_int16_t phy_vid, phy_did, phy_sts = 0; 854 int rid, unit, error = 0; 855 856 s = splimp(); 857 sc = device_get_softc(dev); 858 unit = device_get_unit(dev); 859 if (sc == NULL) { 860 printf("my%d: no memory for softc struct!\n", unit); 861 error = ENXIO; 862 goto fail; 863 864 } 865 bzero(sc, sizeof(struct my_softc)); 866 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 867 MTX_DEF | MTX_RECURSE); 868 MY_LOCK(sc); 869 870 /* 871 * Map control/status registers. 872 */ 873 #if 0 874 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 875 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 876 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 877 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 878 #endif 879 command = pci_read_config(dev, PCIR_COMMAND, 4); 880 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 881 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 882 command = pci_read_config(dev, PCIR_COMMAND, 4); 883 884 if (my_info_tmp->my_did == MTD800ID) { 885 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 886 if (iobase & 0x300) 887 MY_USEIOSPACE = 0; 888 } 889 if (MY_USEIOSPACE) { 890 if (!(command & PCIM_CMD_PORTEN)) { 891 printf("my%d: failed to enable I/O ports!\n", unit); 892 free(sc, M_DEVBUF); 893 error = ENXIO; 894 goto fail; 895 } 896 #if 0 897 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 898 printf("my%d: couldn't map ports\n", unit); 899 error = ENXIO; 900 goto fail; 901 } 902 903 sc->my_btag = I386_BUS_SPACE_IO; 904 #endif 905 } else { 906 if (!(command & PCIM_CMD_MEMEN)) { 907 printf("my%d: failed to enable memory mapping!\n", 908 unit); 909 error = ENXIO; 910 goto fail; 911 } 912 #if 0 913 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 914 printf ("my%d: couldn't map memory\n", unit); 915 error = ENXIO; 916 goto fail; 917 } 918 sc->my_btag = I386_BUS_SPACE_MEM; 919 sc->my_bhandle = vbase; 920 #endif 921 } 922 923 rid = MY_RID; 924 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid, 925 0, ~0, 1, RF_ACTIVE); 926 927 if (sc->my_res == NULL) { 928 printf("my%d: couldn't map ports/memory\n", unit); 929 error = ENXIO; 930 goto fail; 931 } 932 sc->my_btag = rman_get_bustag(sc->my_res); 933 sc->my_bhandle = rman_get_bushandle(sc->my_res); 934 935 rid = 0; 936 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 937 RF_SHAREABLE | RF_ACTIVE); 938 939 if (sc->my_irq == NULL) { 940 printf("my%d: couldn't map interrupt\n", unit); 941 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 942 error = ENXIO; 943 goto fail; 944 } 945 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 946 my_intr, sc, &sc->my_intrhand); 947 948 if (error) { 949 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 950 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 951 printf("my%d: couldn't set up irq\n", unit); 952 goto fail; 953 } 954 callout_handle_init(&sc->my_stat_ch); 955 956 sc->my_info = my_info_tmp; 957 958 /* Reset the adapter. */ 959 my_reset(sc); 960 961 /* 962 * Get station address 963 */ 964 for (i = 0; i < ETHER_ADDR_LEN; ++i) 965 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 966 967 /* 968 * A Myson chip was detected. Inform the world. 969 */ 970 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":"); 971 972 sc->my_unit = unit; 973 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 974 975 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 976 M_DEVBUF, M_NOWAIT); 977 if (sc->my_ldata_ptr == NULL) { 978 free(sc, M_DEVBUF); 979 printf("my%d: no memory for list buffers!\n", unit); 980 error = ENXIO; 981 goto fail; 982 } 983 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 984 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 985 roundptr = sc->my_ldata_ptr; 986 for (i = 0; i < 8; i++) { 987 if (round % 8) { 988 round++; 989 roundptr++; 990 } else 991 break; 992 } 993 sc->my_ldata = (struct my_list_data *) roundptr; 994 bzero(sc->my_ldata, sizeof(struct my_list_data)); 995 996 ifp = &sc->arpcom.ac_if; 997 ifp->if_softc = sc; 998 ifp->if_unit = unit; 999 ifp->if_name = "my"; 1000 ifp->if_mtu = ETHERMTU; 1001 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1002 ifp->if_ioctl = my_ioctl; 1003 ifp->if_output = ether_output; 1004 ifp->if_start = my_start; 1005 ifp->if_watchdog = my_watchdog; 1006 ifp->if_init = my_init; 1007 ifp->if_baudrate = 10000000; 1008 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1009 1010 if (sc->my_info->my_did == MTD803ID) 1011 sc->my_pinfo = my_phys; 1012 else { 1013 if (bootverbose) 1014 printf("my%d: probing for a PHY\n", sc->my_unit); 1015 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 1016 if (bootverbose) 1017 printf("my%d: checking address: %d\n", 1018 sc->my_unit, i); 1019 sc->my_phy_addr = i; 1020 phy_sts = my_phy_readreg(sc, PHY_BMSR); 1021 if ((phy_sts != 0) && (phy_sts != 0xffff)) 1022 break; 1023 else 1024 phy_sts = 0; 1025 } 1026 if (phy_sts) { 1027 phy_vid = my_phy_readreg(sc, PHY_VENID); 1028 phy_did = my_phy_readreg(sc, PHY_DEVID); 1029 if (bootverbose) { 1030 printf("my%d: found PHY at address %d, ", 1031 sc->my_unit, sc->my_phy_addr); 1032 printf("vendor id: %x device id: %x\n", 1033 phy_vid, phy_did); 1034 } 1035 p = my_phys; 1036 while (p->my_vid) { 1037 if (phy_vid == p->my_vid) { 1038 sc->my_pinfo = p; 1039 break; 1040 } 1041 p++; 1042 } 1043 if (sc->my_pinfo == NULL) 1044 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1045 if (bootverbose) 1046 printf("my%d: PHY type: %s\n", 1047 sc->my_unit, sc->my_pinfo->my_name); 1048 } else { 1049 printf("my%d: MII without any phy!\n", sc->my_unit); 1050 error = ENXIO; 1051 goto fail; 1052 } 1053 } 1054 1055 /* Do ifmedia setup. */ 1056 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1057 my_getmode_mii(sc); 1058 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1059 media = sc->ifmedia.ifm_media; 1060 my_stop(sc); 1061 ifmedia_set(&sc->ifmedia, media); 1062 1063 ether_ifattach(ifp, eaddr); 1064 1065 #if 0 1066 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1067 shutdownhook_establish(my_shutdown, sc); 1068 #endif 1069 1070 MY_UNLOCK(sc); 1071 return (0); 1072 1073 fail: 1074 MY_UNLOCK(sc); 1075 mtx_destroy(&sc->my_mtx); 1076 splx(s); 1077 return (error); 1078 } 1079 1080 static int 1081 my_detach(device_t dev) 1082 { 1083 struct my_softc *sc; 1084 struct ifnet *ifp; 1085 int s; 1086 1087 s = splimp(); 1088 sc = device_get_softc(dev); 1089 MY_LOCK(sc); 1090 ifp = &sc->arpcom.ac_if; 1091 ether_ifdetach(ifp); 1092 my_stop(sc); 1093 1094 #if 0 1095 bus_generic_detach(dev); 1096 device_delete_child(dev, sc->rl_miibus); 1097 #endif 1098 1099 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1100 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1101 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1102 #if 0 1103 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1104 #endif 1105 free(sc, M_DEVBUF); 1106 MY_UNLOCK(sc); 1107 splx(s); 1108 mtx_destroy(&sc->my_mtx); 1109 return (0); 1110 } 1111 1112 1113 /* 1114 * Initialize the transmit descriptors. 1115 */ 1116 static int 1117 my_list_tx_init(struct my_softc * sc) 1118 { 1119 struct my_chain_data *cd; 1120 struct my_list_data *ld; 1121 int i; 1122 1123 MY_LOCK(sc); 1124 cd = &sc->my_cdata; 1125 ld = sc->my_ldata; 1126 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1127 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1128 if (i == (MY_TX_LIST_CNT - 1)) 1129 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1130 else 1131 cd->my_tx_chain[i].my_nextdesc = 1132 &cd->my_tx_chain[i + 1]; 1133 } 1134 cd->my_tx_free = &cd->my_tx_chain[0]; 1135 cd->my_tx_tail = cd->my_tx_head = NULL; 1136 MY_UNLOCK(sc); 1137 return (0); 1138 } 1139 1140 /* 1141 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1142 * arrange the descriptors in a closed ring, so that the last descriptor 1143 * points back to the first. 1144 */ 1145 static int 1146 my_list_rx_init(struct my_softc * sc) 1147 { 1148 struct my_chain_data *cd; 1149 struct my_list_data *ld; 1150 int i; 1151 1152 MY_LOCK(sc); 1153 cd = &sc->my_cdata; 1154 ld = sc->my_ldata; 1155 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1156 cd->my_rx_chain[i].my_ptr = 1157 (struct my_desc *) & ld->my_rx_list[i]; 1158 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1159 MY_UNLOCK(sc); 1160 return (ENOBUFS); 1161 } 1162 if (i == (MY_RX_LIST_CNT - 1)) { 1163 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1164 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1165 } else { 1166 cd->my_rx_chain[i].my_nextdesc = 1167 &cd->my_rx_chain[i + 1]; 1168 ld->my_rx_list[i].my_next = 1169 vtophys(&ld->my_rx_list[i + 1]); 1170 } 1171 } 1172 cd->my_rx_head = &cd->my_rx_chain[0]; 1173 MY_UNLOCK(sc); 1174 return (0); 1175 } 1176 1177 /* 1178 * Initialize an RX descriptor and attach an MBUF cluster. 1179 */ 1180 static int 1181 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1182 { 1183 struct mbuf *m_new = NULL; 1184 1185 MY_LOCK(sc); 1186 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1187 if (m_new == NULL) { 1188 printf("my%d: no memory for rx list -- packet dropped!\n", 1189 sc->my_unit); 1190 MY_UNLOCK(sc); 1191 return (ENOBUFS); 1192 } 1193 MCLGET(m_new, M_DONTWAIT); 1194 if (!(m_new->m_flags & M_EXT)) { 1195 printf("my%d: no memory for rx list -- packet dropped!\n", 1196 sc->my_unit); 1197 m_freem(m_new); 1198 MY_UNLOCK(sc); 1199 return (ENOBUFS); 1200 } 1201 c->my_mbuf = m_new; 1202 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1203 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1204 c->my_ptr->my_status = MY_OWNByNIC; 1205 MY_UNLOCK(sc); 1206 return (0); 1207 } 1208 1209 /* 1210 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1211 * level protocols. 1212 */ 1213 static void 1214 my_rxeof(struct my_softc * sc) 1215 { 1216 struct ether_header *eh; 1217 struct mbuf *m; 1218 struct ifnet *ifp; 1219 struct my_chain_onefrag *cur_rx; 1220 int total_len = 0; 1221 u_int32_t rxstat; 1222 1223 MY_LOCK(sc); 1224 ifp = &sc->arpcom.ac_if; 1225 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1226 & MY_OWNByNIC)) { 1227 cur_rx = sc->my_cdata.my_rx_head; 1228 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1229 1230 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1231 ifp->if_ierrors++; 1232 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1233 continue; 1234 } 1235 /* No errors; receive the packet. */ 1236 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1237 total_len -= ETHER_CRC_LEN; 1238 1239 if (total_len < MINCLSIZE) { 1240 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1241 total_len, 0, ifp, NULL); 1242 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1243 if (m == NULL) { 1244 ifp->if_ierrors++; 1245 continue; 1246 } 1247 } else { 1248 m = cur_rx->my_mbuf; 1249 /* 1250 * Try to conjure up a new mbuf cluster. If that 1251 * fails, it means we have an out of memory condition 1252 * and should leave the buffer in place and continue. 1253 * This will result in a lost packet, but there's 1254 * little else we can do in this situation. 1255 */ 1256 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1257 ifp->if_ierrors++; 1258 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1259 continue; 1260 } 1261 m->m_pkthdr.rcvif = ifp; 1262 m->m_pkthdr.len = m->m_len = total_len; 1263 } 1264 ifp->if_ipackets++; 1265 eh = mtod(m, struct ether_header *); 1266 #if NBPFILTER > 0 1267 /* 1268 * Handle BPF listeners. Let the BPF user see the packet, but 1269 * don't pass it up to the ether_input() layer unless it's a 1270 * broadcast packet, multicast packet, matches our ethernet 1271 * address or the interface is in promiscuous mode. 1272 */ 1273 if (ifp->if_bpf) { 1274 BPF_MTAP(ifp, m); 1275 if (ifp->if_flags & IFF_PROMISC && 1276 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1277 ETHER_ADDR_LEN) && 1278 (eh->ether_dhost[0] & 1) == 0)) { 1279 m_freem(m); 1280 continue; 1281 } 1282 } 1283 #endif 1284 (*ifp->if_input)(ifp, m); 1285 } 1286 MY_UNLOCK(sc); 1287 return; 1288 } 1289 1290 1291 /* 1292 * A frame was downloaded to the chip. It's safe for us to clean up the list 1293 * buffers. 1294 */ 1295 static void 1296 my_txeof(struct my_softc * sc) 1297 { 1298 struct my_chain *cur_tx; 1299 struct ifnet *ifp; 1300 1301 MY_LOCK(sc); 1302 ifp = &sc->arpcom.ac_if; 1303 /* Clear the timeout timer. */ 1304 ifp->if_timer = 0; 1305 if (sc->my_cdata.my_tx_head == NULL) { 1306 MY_UNLOCK(sc); 1307 return; 1308 } 1309 /* 1310 * Go through our tx list and free mbufs for those frames that have 1311 * been transmitted. 1312 */ 1313 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1314 u_int32_t txstat; 1315 1316 cur_tx = sc->my_cdata.my_tx_head; 1317 txstat = MY_TXSTATUS(cur_tx); 1318 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1319 break; 1320 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1321 if (txstat & MY_TXERR) { 1322 ifp->if_oerrors++; 1323 if (txstat & MY_EC) /* excessive collision */ 1324 ifp->if_collisions++; 1325 if (txstat & MY_LC) /* late collision */ 1326 ifp->if_collisions++; 1327 } 1328 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1329 MY_NCRShift; 1330 } 1331 ifp->if_opackets++; 1332 m_freem(cur_tx->my_mbuf); 1333 cur_tx->my_mbuf = NULL; 1334 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1335 sc->my_cdata.my_tx_head = NULL; 1336 sc->my_cdata.my_tx_tail = NULL; 1337 break; 1338 } 1339 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1340 } 1341 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1342 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1343 } 1344 MY_UNLOCK(sc); 1345 return; 1346 } 1347 1348 /* 1349 * TX 'end of channel' interrupt handler. 1350 */ 1351 static void 1352 my_txeoc(struct my_softc * sc) 1353 { 1354 struct ifnet *ifp; 1355 1356 MY_LOCK(sc); 1357 ifp = &sc->arpcom.ac_if; 1358 ifp->if_timer = 0; 1359 if (sc->my_cdata.my_tx_head == NULL) { 1360 ifp->if_flags &= ~IFF_OACTIVE; 1361 sc->my_cdata.my_tx_tail = NULL; 1362 if (sc->my_want_auto) 1363 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1364 } else { 1365 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1366 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1367 ifp->if_timer = 5; 1368 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1369 } 1370 } 1371 MY_UNLOCK(sc); 1372 return; 1373 } 1374 1375 static void 1376 my_intr(void *arg) 1377 { 1378 struct my_softc *sc; 1379 struct ifnet *ifp; 1380 u_int32_t status; 1381 1382 sc = arg; 1383 MY_LOCK(sc); 1384 ifp = &sc->arpcom.ac_if; 1385 if (!(ifp->if_flags & IFF_UP)) { 1386 MY_UNLOCK(sc); 1387 return; 1388 } 1389 /* Disable interrupts. */ 1390 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1391 1392 for (;;) { 1393 status = CSR_READ_4(sc, MY_ISR); 1394 status &= MY_INTRS; 1395 if (status) 1396 CSR_WRITE_4(sc, MY_ISR, status); 1397 else 1398 break; 1399 1400 if (status & MY_RI) /* receive interrupt */ 1401 my_rxeof(sc); 1402 1403 if ((status & MY_RBU) || (status & MY_RxErr)) { 1404 /* rx buffer unavailable or rx error */ 1405 ifp->if_ierrors++; 1406 #ifdef foo 1407 my_stop(sc); 1408 my_reset(sc); 1409 my_init(sc); 1410 #endif 1411 } 1412 if (status & MY_TI) /* tx interrupt */ 1413 my_txeof(sc); 1414 if (status & MY_ETI) /* tx early interrupt */ 1415 my_txeof(sc); 1416 if (status & MY_TBU) /* tx buffer unavailable */ 1417 my_txeoc(sc); 1418 1419 #if 0 /* 90/1/18 delete */ 1420 if (status & MY_FBE) { 1421 my_reset(sc); 1422 my_init(sc); 1423 } 1424 #endif 1425 1426 } 1427 1428 /* Re-enable interrupts. */ 1429 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1430 if (ifp->if_snd.ifq_head != NULL) 1431 my_start(ifp); 1432 MY_UNLOCK(sc); 1433 return; 1434 } 1435 1436 /* 1437 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1438 * pointers to the fragment pointers. 1439 */ 1440 static int 1441 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1442 { 1443 struct my_desc *f = NULL; 1444 int total_len; 1445 struct mbuf *m, *m_new = NULL; 1446 1447 MY_LOCK(sc); 1448 /* calculate the total tx pkt length */ 1449 total_len = 0; 1450 for (m = m_head; m != NULL; m = m->m_next) 1451 total_len += m->m_len; 1452 /* 1453 * Start packing the mbufs in this chain into the fragment pointers. 1454 * Stop when we run out of fragments or hit the end of the mbuf 1455 * chain. 1456 */ 1457 m = m_head; 1458 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1459 if (m_new == NULL) { 1460 printf("my%d: no memory for tx list", sc->my_unit); 1461 MY_UNLOCK(sc); 1462 return (1); 1463 } 1464 if (m_head->m_pkthdr.len > MHLEN) { 1465 MCLGET(m_new, M_DONTWAIT); 1466 if (!(m_new->m_flags & M_EXT)) { 1467 m_freem(m_new); 1468 printf("my%d: no memory for tx list", sc->my_unit); 1469 MY_UNLOCK(sc); 1470 return (1); 1471 } 1472 } 1473 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1474 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1475 m_freem(m_head); 1476 m_head = m_new; 1477 f = &c->my_ptr->my_frag[0]; 1478 f->my_status = 0; 1479 f->my_data = vtophys(mtod(m_new, caddr_t)); 1480 total_len = m_new->m_len; 1481 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1482 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1483 f->my_ctl |= total_len; /* buffer size */ 1484 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1485 if (sc->my_info->my_did == MTD891ID) 1486 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1487 c->my_mbuf = m_head; 1488 c->my_lastdesc = 0; 1489 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1490 MY_UNLOCK(sc); 1491 return (0); 1492 } 1493 1494 /* 1495 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1496 * to the mbuf data regions directly in the transmit lists. We also save a 1497 * copy of the pointers since the transmit list fragment pointers are 1498 * physical addresses. 1499 */ 1500 static void 1501 my_start(struct ifnet * ifp) 1502 { 1503 struct my_softc *sc; 1504 struct mbuf *m_head = NULL; 1505 struct my_chain *cur_tx = NULL, *start_tx; 1506 1507 sc = ifp->if_softc; 1508 MY_LOCK(sc); 1509 if (sc->my_autoneg) { 1510 sc->my_tx_pend = 1; 1511 MY_UNLOCK(sc); 1512 return; 1513 } 1514 /* 1515 * Check for an available queue slot. If there are none, punt. 1516 */ 1517 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1518 ifp->if_flags |= IFF_OACTIVE; 1519 MY_UNLOCK(sc); 1520 return; 1521 } 1522 start_tx = sc->my_cdata.my_tx_free; 1523 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1524 IF_DEQUEUE(&ifp->if_snd, m_head); 1525 if (m_head == NULL) 1526 break; 1527 1528 /* Pick a descriptor off the free list. */ 1529 cur_tx = sc->my_cdata.my_tx_free; 1530 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1531 1532 /* Pack the data into the descriptor. */ 1533 my_encap(sc, cur_tx, m_head); 1534 1535 if (cur_tx != start_tx) 1536 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1537 #if NBPFILTER > 0 1538 /* 1539 * If there's a BPF listener, bounce a copy of this frame to 1540 * him. 1541 */ 1542 BPF_MTAP(ifp, cur_tx->my_mbuf); 1543 #endif 1544 } 1545 /* 1546 * If there are no packets queued, bail. 1547 */ 1548 if (cur_tx == NULL) { 1549 MY_UNLOCK(sc); 1550 return; 1551 } 1552 /* 1553 * Place the request for the upload interrupt in the last descriptor 1554 * in the chain. This way, if we're chaining several packets at once, 1555 * we'll only get an interupt once for the whole chain rather than 1556 * once for each packet. 1557 */ 1558 MY_TXCTL(cur_tx) |= MY_TXIC; 1559 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1560 sc->my_cdata.my_tx_tail = cur_tx; 1561 if (sc->my_cdata.my_tx_head == NULL) 1562 sc->my_cdata.my_tx_head = start_tx; 1563 MY_TXOWN(start_tx) = MY_OWNByNIC; 1564 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1565 1566 /* 1567 * Set a timeout in case the chip goes out to lunch. 1568 */ 1569 ifp->if_timer = 5; 1570 MY_UNLOCK(sc); 1571 return; 1572 } 1573 1574 static void 1575 my_init(void *xsc) 1576 { 1577 struct my_softc *sc = xsc; 1578 struct ifnet *ifp = &sc->arpcom.ac_if; 1579 int s; 1580 u_int16_t phy_bmcr = 0; 1581 1582 MY_LOCK(sc); 1583 if (sc->my_autoneg) { 1584 MY_UNLOCK(sc); 1585 return; 1586 } 1587 s = splimp(); 1588 if (sc->my_pinfo != NULL) 1589 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1590 /* 1591 * Cancel pending I/O and free all RX/TX buffers. 1592 */ 1593 my_stop(sc); 1594 my_reset(sc); 1595 1596 /* 1597 * Set cache alignment and burst length. 1598 */ 1599 #if 0 /* 89/9/1 modify, */ 1600 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1601 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1602 #endif 1603 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1604 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1605 /* 1606 * 89/12/29 add, for mtd891, 1607 */ 1608 if (sc->my_info->my_did == MTD891ID) { 1609 MY_SETBIT(sc, MY_BCR, MY_PROG); 1610 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1611 } 1612 my_setcfg(sc, phy_bmcr); 1613 /* Init circular RX list. */ 1614 if (my_list_rx_init(sc) == ENOBUFS) { 1615 printf("my%d: init failed: no memory for rx buffers\n", 1616 sc->my_unit); 1617 my_stop(sc); 1618 (void)splx(s); 1619 MY_UNLOCK(sc); 1620 return; 1621 } 1622 /* Init TX descriptors. */ 1623 my_list_tx_init(sc); 1624 1625 /* If we want promiscuous mode, set the allframes bit. */ 1626 if (ifp->if_flags & IFF_PROMISC) 1627 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1628 else 1629 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1630 1631 /* 1632 * Set capture broadcast bit to capture broadcast frames. 1633 */ 1634 if (ifp->if_flags & IFF_BROADCAST) 1635 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1636 else 1637 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1638 1639 /* 1640 * Program the multicast filter, if necessary. 1641 */ 1642 my_setmulti(sc); 1643 1644 /* 1645 * Load the address of the RX list. 1646 */ 1647 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1648 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1649 1650 /* 1651 * Enable interrupts. 1652 */ 1653 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1654 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1655 1656 /* Enable receiver and transmitter. */ 1657 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1658 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1659 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1660 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1661 1662 /* Restore state of BMCR */ 1663 if (sc->my_pinfo != NULL) 1664 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1665 ifp->if_flags |= IFF_RUNNING; 1666 ifp->if_flags &= ~IFF_OACTIVE; 1667 (void)splx(s); 1668 MY_UNLOCK(sc); 1669 return; 1670 } 1671 1672 /* 1673 * Set media options. 1674 */ 1675 1676 static int 1677 my_ifmedia_upd(struct ifnet * ifp) 1678 { 1679 struct my_softc *sc; 1680 struct ifmedia *ifm; 1681 1682 sc = ifp->if_softc; 1683 MY_LOCK(sc); 1684 ifm = &sc->ifmedia; 1685 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1686 MY_UNLOCK(sc); 1687 return (EINVAL); 1688 } 1689 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1690 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1691 else 1692 my_setmode_mii(sc, ifm->ifm_media); 1693 MY_UNLOCK(sc); 1694 return (0); 1695 } 1696 1697 /* 1698 * Report current media status. 1699 */ 1700 1701 static void 1702 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1703 { 1704 struct my_softc *sc; 1705 u_int16_t advert = 0, ability = 0; 1706 1707 sc = ifp->if_softc; 1708 MY_LOCK(sc); 1709 ifmr->ifm_active = IFM_ETHER; 1710 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1711 #if 0 /* this version did not support 1000M, */ 1712 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1713 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1714 #endif 1715 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1716 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1717 else 1718 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1719 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1720 ifmr->ifm_active |= IFM_FDX; 1721 else 1722 ifmr->ifm_active |= IFM_HDX; 1723 1724 MY_UNLOCK(sc); 1725 return; 1726 } 1727 ability = my_phy_readreg(sc, PHY_LPAR); 1728 advert = my_phy_readreg(sc, PHY_ANAR); 1729 1730 #if 0 /* this version did not support 1000M, */ 1731 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1732 ability2 = my_phy_readreg(sc, PHY_1000SR); 1733 if (ability2 & PHY_1000SR_1000BTXFULL) { 1734 advert = 0; 1735 ability = 0; 1736 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1737 } else if (ability & PHY_1000SR_1000BTXHALF) { 1738 advert = 0; 1739 ability = 0; 1740 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1741 } 1742 } 1743 #endif 1744 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1745 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1746 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1747 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1748 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1749 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1750 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1751 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1752 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1753 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1754 MY_UNLOCK(sc); 1755 return; 1756 } 1757 1758 static int 1759 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1760 { 1761 struct my_softc *sc = ifp->if_softc; 1762 struct ifreq *ifr = (struct ifreq *) data; 1763 int s, error = 0; 1764 1765 s = splimp(); 1766 MY_LOCK(sc); 1767 switch (command) { 1768 case SIOCSIFFLAGS: 1769 if (ifp->if_flags & IFF_UP) 1770 my_init(sc); 1771 else if (ifp->if_flags & IFF_RUNNING) 1772 my_stop(sc); 1773 error = 0; 1774 break; 1775 case SIOCADDMULTI: 1776 case SIOCDELMULTI: 1777 my_setmulti(sc); 1778 error = 0; 1779 break; 1780 case SIOCGIFMEDIA: 1781 case SIOCSIFMEDIA: 1782 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1783 break; 1784 default: 1785 error = ether_ioctl(ifp, command, data); 1786 break; 1787 } 1788 MY_UNLOCK(sc); 1789 (void)splx(s); 1790 return (error); 1791 } 1792 1793 static void 1794 my_watchdog(struct ifnet * ifp) 1795 { 1796 struct my_softc *sc; 1797 1798 sc = ifp->if_softc; 1799 MY_LOCK(sc); 1800 if (sc->my_autoneg) { 1801 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1802 MY_UNLOCK(sc); 1803 return; 1804 } 1805 ifp->if_oerrors++; 1806 printf("my%d: watchdog timeout\n", sc->my_unit); 1807 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1808 printf("my%d: no carrier - transceiver cable problem?\n", 1809 sc->my_unit); 1810 my_stop(sc); 1811 my_reset(sc); 1812 my_init(sc); 1813 if (ifp->if_snd.ifq_head != NULL) 1814 my_start(ifp); 1815 MY_LOCK(sc); 1816 return; 1817 } 1818 1819 1820 /* 1821 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1822 */ 1823 static void 1824 my_stop(struct my_softc * sc) 1825 { 1826 register int i; 1827 struct ifnet *ifp; 1828 1829 MY_LOCK(sc); 1830 ifp = &sc->arpcom.ac_if; 1831 ifp->if_timer = 0; 1832 1833 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1834 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1835 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1836 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1837 1838 /* 1839 * Free data in the RX lists. 1840 */ 1841 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1842 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1843 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1844 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1845 } 1846 } 1847 bzero((char *)&sc->my_ldata->my_rx_list, 1848 sizeof(sc->my_ldata->my_rx_list)); 1849 /* 1850 * Free the TX list buffers. 1851 */ 1852 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1853 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1854 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1855 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1856 } 1857 } 1858 bzero((char *)&sc->my_ldata->my_tx_list, 1859 sizeof(sc->my_ldata->my_tx_list)); 1860 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1861 MY_UNLOCK(sc); 1862 return; 1863 } 1864 1865 /* 1866 * Stop all chip I/O so that the kernel's probe routines don't get confused 1867 * by errant DMAs when rebooting. 1868 */ 1869 static void 1870 my_shutdown(device_t dev) 1871 { 1872 struct my_softc *sc; 1873 1874 sc = device_get_softc(dev); 1875 my_stop(sc); 1876 return; 1877 } 1878 1879
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