FreeBSD/Linux Kernel Cross Reference
sys/dev/my/if_my.c
1 /*-
2 * Written by: yen_cw@myson.com.tw
3 * Copyright (c) 2002 Myson Technology Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: releng/6.2/sys/dev/my/if_my.c 159777 2006-06-19 19:40:59Z brueffer $");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
36 #include <sys/mbuf.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
41 #include <sys/types.h>
42 #include <sys/bus.h>
43 #include <sys/module.h>
44 #include <sys/lock.h>
45 #include <sys/mutex.h>
46
47 #define NBPFILTER 1
48
49 #include <net/if.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_dl.h>
55 #include <net/bpf.h>
56
57 #include <vm/vm.h> /* for vtophys */
58 #include <vm/pmap.h> /* for vtophys */
59 #include <machine/clock.h> /* for DELAY */
60 #include <machine/bus.h>
61 #include <machine/resource.h>
62 #include <sys/bus.h>
63 #include <sys/rman.h>
64
65 #include <dev/pci/pcireg.h>
66 #include <dev/pci/pcivar.h>
67
68 #include <dev/mii/mii.h>
69 #include <dev/mii/miivar.h>
70
71 #include "miibus_if.h"
72
73 /*
74 * #define MY_USEIOSPACE
75 */
76
77 static int MY_USEIOSPACE = 1;
78
79 #if (MY_USEIOSPACE)
80 #define MY_RES SYS_RES_IOPORT
81 #define MY_RID MY_PCI_LOIO
82 #else
83 #define MY_RES SYS_RES_MEMORY
84 #define MY_RID MY_PCI_LOMEM
85 #endif
86
87
88 #include <dev/my/if_myreg.h>
89
90 #ifndef lint
91 static const char rcsid[] =
92 "$Id: if_my.c,v 1.16 2003/04/15 06:37:25 mdodd Exp $";
93 #endif
94
95 /*
96 * Various supported device vendors/types and their names.
97 */
98 struct my_type *my_info_tmp;
99 static struct my_type my_devs[] = {
100 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
101 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
102 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
103 {0, 0, NULL}
104 };
105
106 /*
107 * Various supported PHY vendors/types and their names. Note that this driver
108 * will work with pretty much any MII-compliant PHY, so failure to positively
109 * identify the chip is not a fatal error.
110 */
111 static struct my_type my_phys[] = {
112 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
113 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
114 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
115 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
116 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
117 {0, 0, "<MII-compliant physical interface>"}
118 };
119
120 static int my_probe(device_t);
121 static int my_attach(device_t);
122 static int my_detach(device_t);
123 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
124 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
125 static void my_rxeof(struct my_softc *);
126 static void my_txeof(struct my_softc *);
127 static void my_txeoc(struct my_softc *);
128 static void my_intr(void *);
129 static void my_start(struct ifnet *);
130 static void my_start_locked(struct ifnet *);
131 static int my_ioctl(struct ifnet *, u_long, caddr_t);
132 static void my_init(void *);
133 static void my_init_locked(struct my_softc *);
134 static void my_stop(struct my_softc *);
135 static void my_watchdog(struct ifnet *);
136 static void my_shutdown(device_t);
137 static int my_ifmedia_upd(struct ifnet *);
138 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
139 static u_int16_t my_phy_readreg(struct my_softc *, int);
140 static void my_phy_writereg(struct my_softc *, int, int);
141 static void my_autoneg_xmit(struct my_softc *);
142 static void my_autoneg_mii(struct my_softc *, int, int);
143 static void my_setmode_mii(struct my_softc *, int);
144 static void my_getmode_mii(struct my_softc *);
145 static void my_setcfg(struct my_softc *, int);
146 static void my_setmulti(struct my_softc *);
147 static void my_reset(struct my_softc *);
148 static int my_list_rx_init(struct my_softc *);
149 static int my_list_tx_init(struct my_softc *);
150 static long my_send_cmd_to_phy(struct my_softc *, int, int);
151
152 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
153 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
154
155 static device_method_t my_methods[] = {
156 /* Device interface */
157 DEVMETHOD(device_probe, my_probe),
158 DEVMETHOD(device_attach, my_attach),
159 DEVMETHOD(device_detach, my_detach),
160 DEVMETHOD(device_shutdown, my_shutdown),
161
162 {0, 0}
163 };
164
165 static driver_t my_driver = {
166 "my",
167 my_methods,
168 sizeof(struct my_softc)
169 };
170
171 static devclass_t my_devclass;
172
173 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0);
174 MODULE_DEPEND(my, pci, 1, 1, 1);
175 MODULE_DEPEND(my, ether, 1, 1, 1);
176
177 static long
178 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
179 {
180 long miir;
181 int i;
182 int mask, data;
183
184 MY_LOCK_ASSERT(sc);
185
186 /* enable MII output */
187 miir = CSR_READ_4(sc, MY_MANAGEMENT);
188 miir &= 0xfffffff0;
189
190 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
191
192 /* send 32 1's preamble */
193 for (i = 0; i < 32; i++) {
194 /* low MDC; MDO is already high (miir) */
195 miir &= ~MY_MASK_MIIR_MII_MDC;
196 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
197
198 /* high MDC */
199 miir |= MY_MASK_MIIR_MII_MDC;
200 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
201 }
202
203 /* calculate ST+OP+PHYAD+REGAD+TA */
204 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
205
206 /* sent out */
207 mask = 0x8000;
208 while (mask) {
209 /* low MDC, prepare MDO */
210 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
211 if (mask & data)
212 miir |= MY_MASK_MIIR_MII_MDO;
213
214 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
215 /* high MDC */
216 miir |= MY_MASK_MIIR_MII_MDC;
217 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
218 DELAY(30);
219
220 /* next */
221 mask >>= 1;
222 if (mask == 0x2 && opcode == MY_OP_READ)
223 miir &= ~MY_MASK_MIIR_MII_WRITE;
224 }
225
226 return miir;
227 }
228
229
230 static u_int16_t
231 my_phy_readreg(struct my_softc * sc, int reg)
232 {
233 long miir;
234 int mask, data;
235
236 MY_LOCK_ASSERT(sc);
237
238 if (sc->my_info->my_did == MTD803ID)
239 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
240 else {
241 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
242
243 /* read data */
244 mask = 0x8000;
245 data = 0;
246 while (mask) {
247 /* low MDC */
248 miir &= ~MY_MASK_MIIR_MII_MDC;
249 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
250
251 /* read MDI */
252 miir = CSR_READ_4(sc, MY_MANAGEMENT);
253 if (miir & MY_MASK_MIIR_MII_MDI)
254 data |= mask;
255
256 /* high MDC, and wait */
257 miir |= MY_MASK_MIIR_MII_MDC;
258 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
259 DELAY(30);
260
261 /* next */
262 mask >>= 1;
263 }
264
265 /* low MDC */
266 miir &= ~MY_MASK_MIIR_MII_MDC;
267 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
268 }
269
270 return (u_int16_t) data;
271 }
272
273
274 static void
275 my_phy_writereg(struct my_softc * sc, int reg, int data)
276 {
277 long miir;
278 int mask;
279
280 MY_LOCK_ASSERT(sc);
281
282 if (sc->my_info->my_did == MTD803ID)
283 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
284 else {
285 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
286
287 /* write data */
288 mask = 0x8000;
289 while (mask) {
290 /* low MDC, prepare MDO */
291 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
292 if (mask & data)
293 miir |= MY_MASK_MIIR_MII_MDO;
294 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
295 DELAY(1);
296
297 /* high MDC */
298 miir |= MY_MASK_MIIR_MII_MDC;
299 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
300 DELAY(1);
301
302 /* next */
303 mask >>= 1;
304 }
305
306 /* low MDC */
307 miir &= ~MY_MASK_MIIR_MII_MDC;
308 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
309 }
310 return;
311 }
312
313
314 /*
315 * Program the 64-bit multicast hash filter.
316 */
317 static void
318 my_setmulti(struct my_softc * sc)
319 {
320 struct ifnet *ifp;
321 int h = 0;
322 u_int32_t hashes[2] = {0, 0};
323 struct ifmultiaddr *ifma;
324 u_int32_t rxfilt;
325 int mcnt = 0;
326
327 MY_LOCK_ASSERT(sc);
328
329 ifp = sc->my_ifp;
330
331 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
332
333 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
334 rxfilt |= MY_AM;
335 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
336 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
337 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
338
339 return;
340 }
341 /* first, zot all the existing hash bits */
342 CSR_WRITE_4(sc, MY_MAR0, 0);
343 CSR_WRITE_4(sc, MY_MAR1, 0);
344
345 /* now program new ones */
346 IF_ADDR_LOCK(ifp);
347 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
348 if (ifma->ifma_addr->sa_family != AF_LINK)
349 continue;
350 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
351 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
352 if (h < 32)
353 hashes[0] |= (1 << h);
354 else
355 hashes[1] |= (1 << (h - 32));
356 mcnt++;
357 }
358 IF_ADDR_UNLOCK(ifp);
359
360 if (mcnt)
361 rxfilt |= MY_AM;
362 else
363 rxfilt &= ~MY_AM;
364 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
365 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
366 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
367 return;
368 }
369
370 /*
371 * Initiate an autonegotiation session.
372 */
373 static void
374 my_autoneg_xmit(struct my_softc * sc)
375 {
376 u_int16_t phy_sts = 0;
377
378 MY_LOCK_ASSERT(sc);
379
380 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
381 DELAY(500);
382 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
383
384 phy_sts = my_phy_readreg(sc, PHY_BMCR);
385 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
386 my_phy_writereg(sc, PHY_BMCR, phy_sts);
387
388 return;
389 }
390
391
392 /*
393 * Invoke autonegotiation on a PHY.
394 */
395 static void
396 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
397 {
398 u_int16_t phy_sts = 0, media, advert, ability;
399 u_int16_t ability2 = 0;
400 struct ifnet *ifp;
401 struct ifmedia *ifm;
402
403 MY_LOCK_ASSERT(sc);
404
405 ifm = &sc->ifmedia;
406 ifp = sc->my_ifp;
407
408 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
409
410 #ifndef FORCE_AUTONEG_TFOUR
411 /*
412 * First, see if autoneg is supported. If not, there's no point in
413 * continuing.
414 */
415 phy_sts = my_phy_readreg(sc, PHY_BMSR);
416 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
417 if (verbose)
418 if_printf(ifp, "autonegotiation not supported\n");
419 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
420 return;
421 }
422 #endif
423 switch (flag) {
424 case MY_FLAG_FORCEDELAY:
425 /*
426 * XXX Never use this option anywhere but in the probe
427 * routine: making the kernel stop dead in its tracks for
428 * three whole seconds after we've gone multi-user is really
429 * bad manners.
430 */
431 my_autoneg_xmit(sc);
432 DELAY(5000000);
433 break;
434 case MY_FLAG_SCHEDDELAY:
435 /*
436 * Wait for the transmitter to go idle before starting an
437 * autoneg session, otherwise my_start() may clobber our
438 * timeout, and we don't want to allow transmission during an
439 * autoneg session since that can screw it up.
440 */
441 if (sc->my_cdata.my_tx_head != NULL) {
442 sc->my_want_auto = 1;
443 MY_UNLOCK(sc);
444 return;
445 }
446 my_autoneg_xmit(sc);
447 ifp->if_timer = 5;
448 sc->my_autoneg = 1;
449 sc->my_want_auto = 0;
450 return;
451 case MY_FLAG_DELAYTIMEO:
452 ifp->if_timer = 0;
453 sc->my_autoneg = 0;
454 break;
455 default:
456 if_printf(ifp, "invalid autoneg flag: %d\n", flag);
457 return;
458 }
459
460 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
461 if (verbose)
462 if_printf(ifp, "autoneg complete, ");
463 phy_sts = my_phy_readreg(sc, PHY_BMSR);
464 } else {
465 if (verbose)
466 if_printf(ifp, "autoneg not complete, ");
467 }
468
469 media = my_phy_readreg(sc, PHY_BMCR);
470
471 /* Link is good. Report modes and set duplex mode. */
472 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
473 if (verbose)
474 if_printf(ifp, "link status good. ");
475 advert = my_phy_readreg(sc, PHY_ANAR);
476 ability = my_phy_readreg(sc, PHY_LPAR);
477 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
478 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
479 ability2 = my_phy_readreg(sc, PHY_1000SR);
480 if (ability2 & PHY_1000SR_1000BTXFULL) {
481 advert = 0;
482 ability = 0;
483 /*
484 * this version did not support 1000M,
485 * ifm->ifm_media =
486 * IFM_ETHER|IFM_1000_T|IFM_FDX;
487 */
488 ifm->ifm_media =
489 IFM_ETHER | IFM_100_TX | IFM_FDX;
490 media &= ~PHY_BMCR_SPEEDSEL;
491 media |= PHY_BMCR_1000;
492 media |= PHY_BMCR_DUPLEX;
493 printf("(full-duplex, 1000Mbps)\n");
494 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
495 advert = 0;
496 ability = 0;
497 /*
498 * this version did not support 1000M,
499 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
500 */
501 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
502 media &= ~PHY_BMCR_SPEEDSEL;
503 media &= ~PHY_BMCR_DUPLEX;
504 media |= PHY_BMCR_1000;
505 printf("(half-duplex, 1000Mbps)\n");
506 }
507 }
508 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
509 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
510 media |= PHY_BMCR_SPEEDSEL;
511 media &= ~PHY_BMCR_DUPLEX;
512 printf("(100baseT4)\n");
513 } else if (advert & PHY_ANAR_100BTXFULL &&
514 ability & PHY_ANAR_100BTXFULL) {
515 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
516 media |= PHY_BMCR_SPEEDSEL;
517 media |= PHY_BMCR_DUPLEX;
518 printf("(full-duplex, 100Mbps)\n");
519 } else if (advert & PHY_ANAR_100BTXHALF &&
520 ability & PHY_ANAR_100BTXHALF) {
521 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
522 media |= PHY_BMCR_SPEEDSEL;
523 media &= ~PHY_BMCR_DUPLEX;
524 printf("(half-duplex, 100Mbps)\n");
525 } else if (advert & PHY_ANAR_10BTFULL &&
526 ability & PHY_ANAR_10BTFULL) {
527 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
528 media &= ~PHY_BMCR_SPEEDSEL;
529 media |= PHY_BMCR_DUPLEX;
530 printf("(full-duplex, 10Mbps)\n");
531 } else if (advert) {
532 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
533 media &= ~PHY_BMCR_SPEEDSEL;
534 media &= ~PHY_BMCR_DUPLEX;
535 printf("(half-duplex, 10Mbps)\n");
536 }
537 media &= ~PHY_BMCR_AUTONEGENBL;
538
539 /* Set ASIC's duplex mode to match the PHY. */
540 my_phy_writereg(sc, PHY_BMCR, media);
541 my_setcfg(sc, media);
542 } else {
543 if (verbose)
544 if_printf(ifp, "no carrier\n");
545 }
546
547 my_init_locked(sc);
548 if (sc->my_tx_pend) {
549 sc->my_autoneg = 0;
550 sc->my_tx_pend = 0;
551 my_start_locked(ifp);
552 }
553 return;
554 }
555
556 /*
557 * To get PHY ability.
558 */
559 static void
560 my_getmode_mii(struct my_softc * sc)
561 {
562 u_int16_t bmsr;
563 struct ifnet *ifp;
564
565 MY_LOCK_ASSERT(sc);
566 ifp = sc->my_ifp;
567 bmsr = my_phy_readreg(sc, PHY_BMSR);
568 if (bootverbose)
569 if_printf(ifp, "PHY status word: %x\n", bmsr);
570
571 /* fallback */
572 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
573
574 if (bmsr & PHY_BMSR_10BTHALF) {
575 if (bootverbose)
576 if_printf(ifp, "10Mbps half-duplex mode supported\n");
577 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
578 0, NULL);
579 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
580 }
581 if (bmsr & PHY_BMSR_10BTFULL) {
582 if (bootverbose)
583 if_printf(ifp, "10Mbps full-duplex mode supported\n");
584
585 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
586 0, NULL);
587 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
588 }
589 if (bmsr & PHY_BMSR_100BTXHALF) {
590 if (bootverbose)
591 if_printf(ifp, "100Mbps half-duplex mode supported\n");
592 ifp->if_baudrate = 100000000;
593 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
594 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
595 0, NULL);
596 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
597 }
598 if (bmsr & PHY_BMSR_100BTXFULL) {
599 if (bootverbose)
600 if_printf(ifp, "100Mbps full-duplex mode supported\n");
601 ifp->if_baudrate = 100000000;
602 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
603 0, NULL);
604 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
605 }
606 /* Some also support 100BaseT4. */
607 if (bmsr & PHY_BMSR_100BT4) {
608 if (bootverbose)
609 if_printf(ifp, "100baseT4 mode supported\n");
610 ifp->if_baudrate = 100000000;
611 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
612 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
613 #ifdef FORCE_AUTONEG_TFOUR
614 if (bootverbose)
615 if_printf(ifp, "forcing on autoneg support for BT4\n");
616 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
617 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
618 #endif
619 }
620 #if 0 /* this version did not support 1000M, */
621 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
622 if (bootverbose)
623 if_printf(ifp, "1000Mbps half-duplex mode supported\n");
624
625 ifp->if_baudrate = 1000000000;
626 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
627 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
628 0, NULL);
629 if (bootverbose)
630 if_printf(ifp, "1000Mbps full-duplex mode supported\n");
631 ifp->if_baudrate = 1000000000;
632 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
633 0, NULL);
634 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
635 }
636 #endif
637 if (bmsr & PHY_BMSR_CANAUTONEG) {
638 if (bootverbose)
639 if_printf(ifp, "autoneg supported\n");
640 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
641 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
642 }
643 return;
644 }
645
646 /*
647 * Set speed and duplex mode.
648 */
649 static void
650 my_setmode_mii(struct my_softc * sc, int media)
651 {
652 u_int16_t bmcr;
653 struct ifnet *ifp;
654
655 MY_LOCK_ASSERT(sc);
656 ifp = sc->my_ifp;
657 /*
658 * If an autoneg session is in progress, stop it.
659 */
660 if (sc->my_autoneg) {
661 if_printf(ifp, "canceling autoneg session\n");
662 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
663 bmcr = my_phy_readreg(sc, PHY_BMCR);
664 bmcr &= ~PHY_BMCR_AUTONEGENBL;
665 my_phy_writereg(sc, PHY_BMCR, bmcr);
666 }
667 if_printf(ifp, "selecting MII, ");
668 bmcr = my_phy_readreg(sc, PHY_BMCR);
669 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
670 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
671
672 #if 0 /* this version did not support 1000M, */
673 if (IFM_SUBTYPE(media) == IFM_1000_T) {
674 printf("1000Mbps/T4, half-duplex\n");
675 bmcr &= ~PHY_BMCR_SPEEDSEL;
676 bmcr &= ~PHY_BMCR_DUPLEX;
677 bmcr |= PHY_BMCR_1000;
678 }
679 #endif
680 if (IFM_SUBTYPE(media) == IFM_100_T4) {
681 printf("100Mbps/T4, half-duplex\n");
682 bmcr |= PHY_BMCR_SPEEDSEL;
683 bmcr &= ~PHY_BMCR_DUPLEX;
684 }
685 if (IFM_SUBTYPE(media) == IFM_100_TX) {
686 printf("100Mbps, ");
687 bmcr |= PHY_BMCR_SPEEDSEL;
688 }
689 if (IFM_SUBTYPE(media) == IFM_10_T) {
690 printf("10Mbps, ");
691 bmcr &= ~PHY_BMCR_SPEEDSEL;
692 }
693 if ((media & IFM_GMASK) == IFM_FDX) {
694 printf("full duplex\n");
695 bmcr |= PHY_BMCR_DUPLEX;
696 } else {
697 printf("half duplex\n");
698 bmcr &= ~PHY_BMCR_DUPLEX;
699 }
700 my_phy_writereg(sc, PHY_BMCR, bmcr);
701 my_setcfg(sc, bmcr);
702 return;
703 }
704
705 /*
706 * The Myson manual states that in order to fiddle with the 'full-duplex' and
707 * '100Mbps' bits in the netconfig register, we first have to put the
708 * transmit and/or receive logic in the idle state.
709 */
710 static void
711 my_setcfg(struct my_softc * sc, int bmcr)
712 {
713 int i, restart = 0;
714
715 MY_LOCK_ASSERT(sc);
716 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
717 restart = 1;
718 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
719 for (i = 0; i < MY_TIMEOUT; i++) {
720 DELAY(10);
721 if (!(CSR_READ_4(sc, MY_TCRRCR) &
722 (MY_TXRUN | MY_RXRUN)))
723 break;
724 }
725 if (i == MY_TIMEOUT)
726 if_printf(sc->my_ifp,
727 "failed to force tx and rx to idle \n");
728 }
729 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
730 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
731 if (bmcr & PHY_BMCR_1000)
732 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
733 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
734 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
735 if (bmcr & PHY_BMCR_DUPLEX)
736 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
737 else
738 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
739 if (restart)
740 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
741 return;
742 }
743
744 static void
745 my_reset(struct my_softc * sc)
746 {
747 register int i;
748
749 MY_LOCK_ASSERT(sc);
750 MY_SETBIT(sc, MY_BCR, MY_SWR);
751 for (i = 0; i < MY_TIMEOUT; i++) {
752 DELAY(10);
753 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
754 break;
755 }
756 if (i == MY_TIMEOUT)
757 if_printf(sc->my_ifp, "reset never completed!\n");
758
759 /* Wait a little while for the chip to get its brains in order. */
760 DELAY(1000);
761 return;
762 }
763
764 /*
765 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
766 * list and return a device name if we find a match.
767 */
768 static int
769 my_probe(device_t dev)
770 {
771 struct my_type *t;
772
773 t = my_devs;
774 while (t->my_name != NULL) {
775 if ((pci_get_vendor(dev) == t->my_vid) &&
776 (pci_get_device(dev) == t->my_did)) {
777 device_set_desc(dev, t->my_name);
778 my_info_tmp = t;
779 return (BUS_PROBE_DEFAULT);
780 }
781 t++;
782 }
783 return (ENXIO);
784 }
785
786 /*
787 * Attach the interface. Allocate softc structures, do ifmedia setup and
788 * ethernet/BPF attach.
789 */
790 static int
791 my_attach(device_t dev)
792 {
793 int i;
794 u_char eaddr[ETHER_ADDR_LEN];
795 u_int32_t iobase;
796 struct my_softc *sc;
797 struct ifnet *ifp;
798 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
799 unsigned int round;
800 caddr_t roundptr;
801 struct my_type *p;
802 u_int16_t phy_vid, phy_did, phy_sts = 0;
803 int rid, error = 0;
804
805 sc = device_get_softc(dev);
806 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
807 MTX_DEF);
808
809 /*
810 * Map control/status registers.
811 */
812 pci_enable_busmaster(dev);
813
814 if (my_info_tmp->my_did == MTD800ID) {
815 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
816 if (iobase & 0x300)
817 MY_USEIOSPACE = 0;
818 }
819
820 rid = MY_RID;
821 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
822
823 if (sc->my_res == NULL) {
824 device_printf(dev, "couldn't map ports/memory\n");
825 error = ENXIO;
826 goto destroy_mutex;
827 }
828 sc->my_btag = rman_get_bustag(sc->my_res);
829 sc->my_bhandle = rman_get_bushandle(sc->my_res);
830
831 rid = 0;
832 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
833 RF_SHAREABLE | RF_ACTIVE);
834
835 if (sc->my_irq == NULL) {
836 device_printf(dev, "couldn't map interrupt\n");
837 error = ENXIO;
838 goto release_io;
839 }
840
841 sc->my_info = my_info_tmp;
842
843 /* Reset the adapter. */
844 MY_LOCK(sc);
845 my_reset(sc);
846 MY_UNLOCK(sc);
847
848 /*
849 * Get station address
850 */
851 for (i = 0; i < ETHER_ADDR_LEN; ++i)
852 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
853
854 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
855 M_DEVBUF, M_NOWAIT);
856 if (sc->my_ldata_ptr == NULL) {
857 device_printf(dev, "no memory for list buffers!\n");
858 error = ENXIO;
859 goto release_irq;
860 }
861 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
862 round = (uintptr_t)sc->my_ldata_ptr & 0xF;
863 roundptr = sc->my_ldata_ptr;
864 for (i = 0; i < 8; i++) {
865 if (round % 8) {
866 round++;
867 roundptr++;
868 } else
869 break;
870 }
871 sc->my_ldata = (struct my_list_data *) roundptr;
872 bzero(sc->my_ldata, sizeof(struct my_list_data));
873
874 ifp = sc->my_ifp = if_alloc(IFT_ETHER);
875 if (ifp == NULL) {
876 device_printf(dev, "can not if_alloc()\n");
877 error = ENOSPC;
878 goto free_ldata;
879 }
880 ifp->if_softc = sc;
881 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
882 ifp->if_mtu = ETHERMTU;
883 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
884 ifp->if_ioctl = my_ioctl;
885 ifp->if_start = my_start;
886 ifp->if_watchdog = my_watchdog;
887 ifp->if_init = my_init;
888 ifp->if_baudrate = 10000000;
889 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
890 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
891 IFQ_SET_READY(&ifp->if_snd);
892
893 if (sc->my_info->my_did == MTD803ID)
894 sc->my_pinfo = my_phys;
895 else {
896 if (bootverbose)
897 device_printf(dev, "probing for a PHY\n");
898 MY_LOCK(sc);
899 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
900 if (bootverbose)
901 device_printf(dev, "checking address: %d\n", i);
902 sc->my_phy_addr = i;
903 phy_sts = my_phy_readreg(sc, PHY_BMSR);
904 if ((phy_sts != 0) && (phy_sts != 0xffff))
905 break;
906 else
907 phy_sts = 0;
908 }
909 if (phy_sts) {
910 phy_vid = my_phy_readreg(sc, PHY_VENID);
911 phy_did = my_phy_readreg(sc, PHY_DEVID);
912 if (bootverbose) {
913 device_printf(dev, "found PHY at address %d, ",
914 sc->my_phy_addr);
915 printf("vendor id: %x device id: %x\n",
916 phy_vid, phy_did);
917 }
918 p = my_phys;
919 while (p->my_vid) {
920 if (phy_vid == p->my_vid) {
921 sc->my_pinfo = p;
922 break;
923 }
924 p++;
925 }
926 if (sc->my_pinfo == NULL)
927 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
928 if (bootverbose)
929 device_printf(dev, "PHY type: %s\n",
930 sc->my_pinfo->my_name);
931 } else {
932 MY_UNLOCK(sc);
933 device_printf(dev, "MII without any phy!\n");
934 error = ENXIO;
935 goto free_if;
936 }
937 MY_UNLOCK(sc);
938 }
939
940 /* Do ifmedia setup. */
941 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
942 MY_LOCK(sc);
943 my_getmode_mii(sc);
944 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
945 media = sc->ifmedia.ifm_media;
946 my_stop(sc);
947 MY_UNLOCK(sc);
948 ifmedia_set(&sc->ifmedia, media);
949
950 ether_ifattach(ifp, eaddr);
951
952 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE,
953 my_intr, sc, &sc->my_intrhand);
954
955 if (error) {
956 device_printf(dev, "couldn't set up irq\n");
957 goto detach_if;
958 }
959
960 return (0);
961
962 detach_if:
963 ether_ifdetach(ifp);
964 free_if:
965 if_free(ifp);
966 free_ldata:
967 free(sc->my_ldata_ptr, M_DEVBUF);
968 release_irq:
969 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
970 release_io:
971 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
972 destroy_mutex:
973 mtx_destroy(&sc->my_mtx);
974 return (error);
975 }
976
977 static int
978 my_detach(device_t dev)
979 {
980 struct my_softc *sc;
981 struct ifnet *ifp;
982
983 sc = device_get_softc(dev);
984 MY_LOCK(sc);
985 my_stop(sc);
986 MY_UNLOCK(sc);
987 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
988
989 ifp = sc->my_ifp;
990 ether_ifdetach(ifp);
991 if_free(ifp);
992 free(sc->my_ldata_ptr, M_DEVBUF);
993
994 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
995 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
996 mtx_destroy(&sc->my_mtx);
997 return (0);
998 }
999
1000
1001 /*
1002 * Initialize the transmit descriptors.
1003 */
1004 static int
1005 my_list_tx_init(struct my_softc * sc)
1006 {
1007 struct my_chain_data *cd;
1008 struct my_list_data *ld;
1009 int i;
1010
1011 MY_LOCK_ASSERT(sc);
1012 cd = &sc->my_cdata;
1013 ld = sc->my_ldata;
1014 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1015 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1016 if (i == (MY_TX_LIST_CNT - 1))
1017 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1018 else
1019 cd->my_tx_chain[i].my_nextdesc =
1020 &cd->my_tx_chain[i + 1];
1021 }
1022 cd->my_tx_free = &cd->my_tx_chain[0];
1023 cd->my_tx_tail = cd->my_tx_head = NULL;
1024 return (0);
1025 }
1026
1027 /*
1028 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1029 * arrange the descriptors in a closed ring, so that the last descriptor
1030 * points back to the first.
1031 */
1032 static int
1033 my_list_rx_init(struct my_softc * sc)
1034 {
1035 struct my_chain_data *cd;
1036 struct my_list_data *ld;
1037 int i;
1038
1039 MY_LOCK_ASSERT(sc);
1040 cd = &sc->my_cdata;
1041 ld = sc->my_ldata;
1042 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1043 cd->my_rx_chain[i].my_ptr =
1044 (struct my_desc *) & ld->my_rx_list[i];
1045 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1046 MY_UNLOCK(sc);
1047 return (ENOBUFS);
1048 }
1049 if (i == (MY_RX_LIST_CNT - 1)) {
1050 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1051 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1052 } else {
1053 cd->my_rx_chain[i].my_nextdesc =
1054 &cd->my_rx_chain[i + 1];
1055 ld->my_rx_list[i].my_next =
1056 vtophys(&ld->my_rx_list[i + 1]);
1057 }
1058 }
1059 cd->my_rx_head = &cd->my_rx_chain[0];
1060 return (0);
1061 }
1062
1063 /*
1064 * Initialize an RX descriptor and attach an MBUF cluster.
1065 */
1066 static int
1067 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1068 {
1069 struct mbuf *m_new = NULL;
1070
1071 MY_LOCK_ASSERT(sc);
1072 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1073 if (m_new == NULL) {
1074 if_printf(sc->my_ifp,
1075 "no memory for rx list -- packet dropped!\n");
1076 return (ENOBUFS);
1077 }
1078 MCLGET(m_new, M_DONTWAIT);
1079 if (!(m_new->m_flags & M_EXT)) {
1080 if_printf(sc->my_ifp,
1081 "no memory for rx list -- packet dropped!\n");
1082 m_freem(m_new);
1083 return (ENOBUFS);
1084 }
1085 c->my_mbuf = m_new;
1086 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1087 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1088 c->my_ptr->my_status = MY_OWNByNIC;
1089 return (0);
1090 }
1091
1092 /*
1093 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1094 * level protocols.
1095 */
1096 static void
1097 my_rxeof(struct my_softc * sc)
1098 {
1099 struct ether_header *eh;
1100 struct mbuf *m;
1101 struct ifnet *ifp;
1102 struct my_chain_onefrag *cur_rx;
1103 int total_len = 0;
1104 u_int32_t rxstat;
1105
1106 MY_LOCK_ASSERT(sc);
1107 ifp = sc->my_ifp;
1108 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1109 & MY_OWNByNIC)) {
1110 cur_rx = sc->my_cdata.my_rx_head;
1111 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1112
1113 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1114 ifp->if_ierrors++;
1115 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1116 continue;
1117 }
1118 /* No errors; receive the packet. */
1119 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1120 total_len -= ETHER_CRC_LEN;
1121
1122 if (total_len < MINCLSIZE) {
1123 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1124 total_len, 0, ifp, NULL);
1125 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1126 if (m == NULL) {
1127 ifp->if_ierrors++;
1128 continue;
1129 }
1130 } else {
1131 m = cur_rx->my_mbuf;
1132 /*
1133 * Try to conjure up a new mbuf cluster. If that
1134 * fails, it means we have an out of memory condition
1135 * and should leave the buffer in place and continue.
1136 * This will result in a lost packet, but there's
1137 * little else we can do in this situation.
1138 */
1139 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1140 ifp->if_ierrors++;
1141 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1142 continue;
1143 }
1144 m->m_pkthdr.rcvif = ifp;
1145 m->m_pkthdr.len = m->m_len = total_len;
1146 }
1147 ifp->if_ipackets++;
1148 eh = mtod(m, struct ether_header *);
1149 #if NBPFILTER > 0
1150 /*
1151 * Handle BPF listeners. Let the BPF user see the packet, but
1152 * don't pass it up to the ether_input() layer unless it's a
1153 * broadcast packet, multicast packet, matches our ethernet
1154 * address or the interface is in promiscuous mode.
1155 */
1156 if (ifp->if_bpf) {
1157 BPF_MTAP(ifp, m);
1158 if (ifp->if_flags & IFF_PROMISC &&
1159 (bcmp(eh->ether_dhost, IFP2ENADDR(sc->my_ifp),
1160 ETHER_ADDR_LEN) &&
1161 (eh->ether_dhost[0] & 1) == 0)) {
1162 m_freem(m);
1163 continue;
1164 }
1165 }
1166 #endif
1167 MY_UNLOCK(sc);
1168 (*ifp->if_input)(ifp, m);
1169 MY_LOCK(sc);
1170 }
1171 return;
1172 }
1173
1174
1175 /*
1176 * A frame was downloaded to the chip. It's safe for us to clean up the list
1177 * buffers.
1178 */
1179 static void
1180 my_txeof(struct my_softc * sc)
1181 {
1182 struct my_chain *cur_tx;
1183 struct ifnet *ifp;
1184
1185 MY_LOCK_ASSERT(sc);
1186 ifp = sc->my_ifp;
1187 /* Clear the timeout timer. */
1188 ifp->if_timer = 0;
1189 if (sc->my_cdata.my_tx_head == NULL) {
1190 return;
1191 }
1192 /*
1193 * Go through our tx list and free mbufs for those frames that have
1194 * been transmitted.
1195 */
1196 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1197 u_int32_t txstat;
1198
1199 cur_tx = sc->my_cdata.my_tx_head;
1200 txstat = MY_TXSTATUS(cur_tx);
1201 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1202 break;
1203 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1204 if (txstat & MY_TXERR) {
1205 ifp->if_oerrors++;
1206 if (txstat & MY_EC) /* excessive collision */
1207 ifp->if_collisions++;
1208 if (txstat & MY_LC) /* late collision */
1209 ifp->if_collisions++;
1210 }
1211 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1212 MY_NCRShift;
1213 }
1214 ifp->if_opackets++;
1215 m_freem(cur_tx->my_mbuf);
1216 cur_tx->my_mbuf = NULL;
1217 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1218 sc->my_cdata.my_tx_head = NULL;
1219 sc->my_cdata.my_tx_tail = NULL;
1220 break;
1221 }
1222 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1223 }
1224 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1225 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1226 }
1227 return;
1228 }
1229
1230 /*
1231 * TX 'end of channel' interrupt handler.
1232 */
1233 static void
1234 my_txeoc(struct my_softc * sc)
1235 {
1236 struct ifnet *ifp;
1237
1238 MY_LOCK_ASSERT(sc);
1239 ifp = sc->my_ifp;
1240 ifp->if_timer = 0;
1241 if (sc->my_cdata.my_tx_head == NULL) {
1242 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1243 sc->my_cdata.my_tx_tail = NULL;
1244 if (sc->my_want_auto)
1245 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1246 } else {
1247 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1248 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1249 ifp->if_timer = 5;
1250 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1251 }
1252 }
1253 return;
1254 }
1255
1256 static void
1257 my_intr(void *arg)
1258 {
1259 struct my_softc *sc;
1260 struct ifnet *ifp;
1261 u_int32_t status;
1262
1263 sc = arg;
1264 MY_LOCK(sc);
1265 ifp = sc->my_ifp;
1266 if (!(ifp->if_flags & IFF_UP)) {
1267 MY_UNLOCK(sc);
1268 return;
1269 }
1270 /* Disable interrupts. */
1271 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1272
1273 for (;;) {
1274 status = CSR_READ_4(sc, MY_ISR);
1275 status &= MY_INTRS;
1276 if (status)
1277 CSR_WRITE_4(sc, MY_ISR, status);
1278 else
1279 break;
1280
1281 if (status & MY_RI) /* receive interrupt */
1282 my_rxeof(sc);
1283
1284 if ((status & MY_RBU) || (status & MY_RxErr)) {
1285 /* rx buffer unavailable or rx error */
1286 ifp->if_ierrors++;
1287 #ifdef foo
1288 my_stop(sc);
1289 my_reset(sc);
1290 my_init_locked(sc);
1291 #endif
1292 }
1293 if (status & MY_TI) /* tx interrupt */
1294 my_txeof(sc);
1295 if (status & MY_ETI) /* tx early interrupt */
1296 my_txeof(sc);
1297 if (status & MY_TBU) /* tx buffer unavailable */
1298 my_txeoc(sc);
1299
1300 #if 0 /* 90/1/18 delete */
1301 if (status & MY_FBE) {
1302 my_reset(sc);
1303 my_init_locked(sc);
1304 }
1305 #endif
1306
1307 }
1308
1309 /* Re-enable interrupts. */
1310 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1311 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1312 my_start_locked(ifp);
1313 MY_UNLOCK(sc);
1314 return;
1315 }
1316
1317 /*
1318 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1319 * pointers to the fragment pointers.
1320 */
1321 static int
1322 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1323 {
1324 struct my_desc *f = NULL;
1325 int total_len;
1326 struct mbuf *m, *m_new = NULL;
1327
1328 MY_LOCK_ASSERT(sc);
1329 /* calculate the total tx pkt length */
1330 total_len = 0;
1331 for (m = m_head; m != NULL; m = m->m_next)
1332 total_len += m->m_len;
1333 /*
1334 * Start packing the mbufs in this chain into the fragment pointers.
1335 * Stop when we run out of fragments or hit the end of the mbuf
1336 * chain.
1337 */
1338 m = m_head;
1339 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1340 if (m_new == NULL) {
1341 if_printf(sc->my_ifp, "no memory for tx list");
1342 return (1);
1343 }
1344 if (m_head->m_pkthdr.len > MHLEN) {
1345 MCLGET(m_new, M_DONTWAIT);
1346 if (!(m_new->m_flags & M_EXT)) {
1347 m_freem(m_new);
1348 if_printf(sc->my_ifp, "no memory for tx list");
1349 return (1);
1350 }
1351 }
1352 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1353 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1354 m_freem(m_head);
1355 m_head = m_new;
1356 f = &c->my_ptr->my_frag[0];
1357 f->my_status = 0;
1358 f->my_data = vtophys(mtod(m_new, caddr_t));
1359 total_len = m_new->m_len;
1360 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1361 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1362 f->my_ctl |= total_len; /* buffer size */
1363 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1364 if (sc->my_info->my_did == MTD891ID)
1365 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1366 c->my_mbuf = m_head;
1367 c->my_lastdesc = 0;
1368 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1369 return (0);
1370 }
1371
1372 /*
1373 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1374 * to the mbuf data regions directly in the transmit lists. We also save a
1375 * copy of the pointers since the transmit list fragment pointers are
1376 * physical addresses.
1377 */
1378 static void
1379 my_start(struct ifnet * ifp)
1380 {
1381 struct my_softc *sc;
1382
1383 sc = ifp->if_softc;
1384 MY_LOCK(sc);
1385 my_start_locked(ifp);
1386 MY_UNLOCK(sc);
1387 }
1388
1389 static void
1390 my_start_locked(struct ifnet * ifp)
1391 {
1392 struct my_softc *sc;
1393 struct mbuf *m_head = NULL;
1394 struct my_chain *cur_tx = NULL, *start_tx;
1395
1396 sc = ifp->if_softc;
1397 MY_LOCK_ASSERT(sc);
1398 if (sc->my_autoneg) {
1399 sc->my_tx_pend = 1;
1400 return;
1401 }
1402 /*
1403 * Check for an available queue slot. If there are none, punt.
1404 */
1405 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1406 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1407 return;
1408 }
1409 start_tx = sc->my_cdata.my_tx_free;
1410 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1411 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1412 if (m_head == NULL)
1413 break;
1414
1415 /* Pick a descriptor off the free list. */
1416 cur_tx = sc->my_cdata.my_tx_free;
1417 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1418
1419 /* Pack the data into the descriptor. */
1420 my_encap(sc, cur_tx, m_head);
1421
1422 if (cur_tx != start_tx)
1423 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1424 #if NBPFILTER > 0
1425 /*
1426 * If there's a BPF listener, bounce a copy of this frame to
1427 * him.
1428 */
1429 BPF_MTAP(ifp, cur_tx->my_mbuf);
1430 #endif
1431 }
1432 /*
1433 * If there are no packets queued, bail.
1434 */
1435 if (cur_tx == NULL) {
1436 return;
1437 }
1438 /*
1439 * Place the request for the upload interrupt in the last descriptor
1440 * in the chain. This way, if we're chaining several packets at once,
1441 * we'll only get an interupt once for the whole chain rather than
1442 * once for each packet.
1443 */
1444 MY_TXCTL(cur_tx) |= MY_TXIC;
1445 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1446 sc->my_cdata.my_tx_tail = cur_tx;
1447 if (sc->my_cdata.my_tx_head == NULL)
1448 sc->my_cdata.my_tx_head = start_tx;
1449 MY_TXOWN(start_tx) = MY_OWNByNIC;
1450 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1451
1452 /*
1453 * Set a timeout in case the chip goes out to lunch.
1454 */
1455 ifp->if_timer = 5;
1456 return;
1457 }
1458
1459 static void
1460 my_init(void *xsc)
1461 {
1462 struct my_softc *sc = xsc;
1463
1464 MY_LOCK(sc);
1465 my_init_locked(sc);
1466 MY_UNLOCK(sc);
1467 }
1468
1469 static void
1470 my_init_locked(struct my_softc *sc)
1471 {
1472 struct ifnet *ifp = sc->my_ifp;
1473 u_int16_t phy_bmcr = 0;
1474
1475 MY_LOCK_ASSERT(sc);
1476 if (sc->my_autoneg) {
1477 return;
1478 }
1479 if (sc->my_pinfo != NULL)
1480 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1481 /*
1482 * Cancel pending I/O and free all RX/TX buffers.
1483 */
1484 my_stop(sc);
1485 my_reset(sc);
1486
1487 /*
1488 * Set cache alignment and burst length.
1489 */
1490 #if 0 /* 89/9/1 modify, */
1491 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1492 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1493 #endif
1494 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1495 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1496 /*
1497 * 89/12/29 add, for mtd891,
1498 */
1499 if (sc->my_info->my_did == MTD891ID) {
1500 MY_SETBIT(sc, MY_BCR, MY_PROG);
1501 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1502 }
1503 my_setcfg(sc, phy_bmcr);
1504 /* Init circular RX list. */
1505 if (my_list_rx_init(sc) == ENOBUFS) {
1506 if_printf(ifp, "init failed: no memory for rx buffers\n");
1507 my_stop(sc);
1508 return;
1509 }
1510 /* Init TX descriptors. */
1511 my_list_tx_init(sc);
1512
1513 /* If we want promiscuous mode, set the allframes bit. */
1514 if (ifp->if_flags & IFF_PROMISC)
1515 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1516 else
1517 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1518
1519 /*
1520 * Set capture broadcast bit to capture broadcast frames.
1521 */
1522 if (ifp->if_flags & IFF_BROADCAST)
1523 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1524 else
1525 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1526
1527 /*
1528 * Program the multicast filter, if necessary.
1529 */
1530 my_setmulti(sc);
1531
1532 /*
1533 * Load the address of the RX list.
1534 */
1535 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1536 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1537
1538 /*
1539 * Enable interrupts.
1540 */
1541 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1542 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1543
1544 /* Enable receiver and transmitter. */
1545 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1546 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1547 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1548 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1549
1550 /* Restore state of BMCR */
1551 if (sc->my_pinfo != NULL)
1552 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1553 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1554 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1555 return;
1556 }
1557
1558 /*
1559 * Set media options.
1560 */
1561
1562 static int
1563 my_ifmedia_upd(struct ifnet * ifp)
1564 {
1565 struct my_softc *sc;
1566 struct ifmedia *ifm;
1567
1568 sc = ifp->if_softc;
1569 MY_LOCK(sc);
1570 ifm = &sc->ifmedia;
1571 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1572 MY_UNLOCK(sc);
1573 return (EINVAL);
1574 }
1575 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1576 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1577 else
1578 my_setmode_mii(sc, ifm->ifm_media);
1579 MY_UNLOCK(sc);
1580 return (0);
1581 }
1582
1583 /*
1584 * Report current media status.
1585 */
1586
1587 static void
1588 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1589 {
1590 struct my_softc *sc;
1591 u_int16_t advert = 0, ability = 0;
1592
1593 sc = ifp->if_softc;
1594 MY_LOCK(sc);
1595 ifmr->ifm_active = IFM_ETHER;
1596 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1597 #if 0 /* this version did not support 1000M, */
1598 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1599 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1600 #endif
1601 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1602 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1603 else
1604 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1605 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1606 ifmr->ifm_active |= IFM_FDX;
1607 else
1608 ifmr->ifm_active |= IFM_HDX;
1609
1610 MY_UNLOCK(sc);
1611 return;
1612 }
1613 ability = my_phy_readreg(sc, PHY_LPAR);
1614 advert = my_phy_readreg(sc, PHY_ANAR);
1615
1616 #if 0 /* this version did not support 1000M, */
1617 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1618 ability2 = my_phy_readreg(sc, PHY_1000SR);
1619 if (ability2 & PHY_1000SR_1000BTXFULL) {
1620 advert = 0;
1621 ability = 0;
1622 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1623 } else if (ability & PHY_1000SR_1000BTXHALF) {
1624 advert = 0;
1625 ability = 0;
1626 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1627 }
1628 }
1629 #endif
1630 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1631 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1632 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1633 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1634 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1635 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1636 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1637 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1638 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1639 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1640 MY_UNLOCK(sc);
1641 return;
1642 }
1643
1644 static int
1645 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1646 {
1647 struct my_softc *sc = ifp->if_softc;
1648 struct ifreq *ifr = (struct ifreq *) data;
1649 int error;
1650
1651 switch (command) {
1652 case SIOCSIFFLAGS:
1653 MY_LOCK(sc);
1654 if (ifp->if_flags & IFF_UP)
1655 my_init_locked(sc);
1656 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1657 my_stop(sc);
1658 MY_UNLOCK(sc);
1659 error = 0;
1660 break;
1661 case SIOCADDMULTI:
1662 case SIOCDELMULTI:
1663 MY_LOCK(sc);
1664 my_setmulti(sc);
1665 MY_UNLOCK(sc);
1666 error = 0;
1667 break;
1668 case SIOCGIFMEDIA:
1669 case SIOCSIFMEDIA:
1670 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1671 break;
1672 default:
1673 error = ether_ioctl(ifp, command, data);
1674 break;
1675 }
1676 return (error);
1677 }
1678
1679 static void
1680 my_watchdog(struct ifnet * ifp)
1681 {
1682 struct my_softc *sc;
1683
1684 sc = ifp->if_softc;
1685 MY_LOCK(sc);
1686 if (sc->my_autoneg) {
1687 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
1688 MY_UNLOCK(sc);
1689 return;
1690 }
1691 ifp->if_oerrors++;
1692 if_printf(ifp, "watchdog timeout\n");
1693 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1694 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1695 my_stop(sc);
1696 my_reset(sc);
1697 my_init_locked(sc);
1698 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1699 my_start_locked(ifp);
1700 MY_LOCK(sc);
1701 return;
1702 }
1703
1704
1705 /*
1706 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1707 */
1708 static void
1709 my_stop(struct my_softc * sc)
1710 {
1711 register int i;
1712 struct ifnet *ifp;
1713
1714 MY_LOCK_ASSERT(sc);
1715 ifp = sc->my_ifp;
1716 ifp->if_timer = 0;
1717
1718 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1719 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1720 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1721 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1722
1723 /*
1724 * Free data in the RX lists.
1725 */
1726 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1727 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1728 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1729 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1730 }
1731 }
1732 bzero((char *)&sc->my_ldata->my_rx_list,
1733 sizeof(sc->my_ldata->my_rx_list));
1734 /*
1735 * Free the TX list buffers.
1736 */
1737 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1738 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1739 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1740 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1741 }
1742 }
1743 bzero((char *)&sc->my_ldata->my_tx_list,
1744 sizeof(sc->my_ldata->my_tx_list));
1745 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1746 return;
1747 }
1748
1749 /*
1750 * Stop all chip I/O so that the kernel's probe routines don't get confused
1751 * by errant DMAs when rebooting.
1752 */
1753 static void
1754 my_shutdown(device_t dev)
1755 {
1756 struct my_softc *sc;
1757
1758 sc = device_get_softc(dev);
1759 MY_LOCK(sc);
1760 my_stop(sc);
1761 MY_UNLOCK(sc);
1762 return;
1763 }
Cache object: af9793940c713460894b73513b98e731
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