FreeBSD/Linux Kernel Cross Reference
sys/dev/my/if_my.c
1 /*-
2 * Written by: yen_cw@myson.com.tw
3 * Copyright (c) 2002 Myson Technology Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification, immediately at the beginning of the file.
12 * 2. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD: releng/9.0/sys/dev/my/if_my.c 223624 2011-06-28 08:36:48Z kevlo $");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
36 #include <sys/mbuf.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
41 #include <sys/types.h>
42 #include <sys/module.h>
43 #include <sys/lock.h>
44 #include <sys/mutex.h>
45
46 #define NBPFILTER 1
47
48 #include <net/if.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_media.h>
52 #include <net/if_types.h>
53 #include <net/if_dl.h>
54 #include <net/bpf.h>
55
56 #include <vm/vm.h> /* for vtophys */
57 #include <vm/pmap.h> /* for vtophys */
58 #include <machine/bus.h>
59 #include <machine/resource.h>
60 #include <sys/bus.h>
61 #include <sys/rman.h>
62
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65
66 /*
67 * #define MY_USEIOSPACE
68 */
69
70 static int MY_USEIOSPACE = 1;
71
72 #ifdef MY_USEIOSPACE
73 #define MY_RES SYS_RES_IOPORT
74 #define MY_RID MY_PCI_LOIO
75 #else
76 #define MY_RES SYS_RES_MEMORY
77 #define MY_RID MY_PCI_LOMEM
78 #endif
79
80
81 #include <dev/my/if_myreg.h>
82
83 #ifndef lint
84 static const char rcsid[] =
85 "$Id: if_my.c,v 1.16 2003/04/15 06:37:25 mdodd Exp $";
86 #endif
87
88 /*
89 * Various supported device vendors/types and their names.
90 */
91 struct my_type *my_info_tmp;
92 static struct my_type my_devs[] = {
93 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
94 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
95 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
96 {0, 0, NULL}
97 };
98
99 /*
100 * Various supported PHY vendors/types and their names. Note that this driver
101 * will work with pretty much any MII-compliant PHY, so failure to positively
102 * identify the chip is not a fatal error.
103 */
104 static struct my_type my_phys[] = {
105 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
106 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
107 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
108 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
109 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
110 {0, 0, "<MII-compliant physical interface>"}
111 };
112
113 static int my_probe(device_t);
114 static int my_attach(device_t);
115 static int my_detach(device_t);
116 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
117 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
118 static void my_rxeof(struct my_softc *);
119 static void my_txeof(struct my_softc *);
120 static void my_txeoc(struct my_softc *);
121 static void my_intr(void *);
122 static void my_start(struct ifnet *);
123 static void my_start_locked(struct ifnet *);
124 static int my_ioctl(struct ifnet *, u_long, caddr_t);
125 static void my_init(void *);
126 static void my_init_locked(struct my_softc *);
127 static void my_stop(struct my_softc *);
128 static void my_autoneg_timeout(void *);
129 static void my_watchdog(void *);
130 static int my_shutdown(device_t);
131 static int my_ifmedia_upd(struct ifnet *);
132 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
133 static u_int16_t my_phy_readreg(struct my_softc *, int);
134 static void my_phy_writereg(struct my_softc *, int, int);
135 static void my_autoneg_xmit(struct my_softc *);
136 static void my_autoneg_mii(struct my_softc *, int, int);
137 static void my_setmode_mii(struct my_softc *, int);
138 static void my_getmode_mii(struct my_softc *);
139 static void my_setcfg(struct my_softc *, int);
140 static void my_setmulti(struct my_softc *);
141 static void my_reset(struct my_softc *);
142 static int my_list_rx_init(struct my_softc *);
143 static int my_list_tx_init(struct my_softc *);
144 static long my_send_cmd_to_phy(struct my_softc *, int, int);
145
146 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
147 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
148
149 static device_method_t my_methods[] = {
150 /* Device interface */
151 DEVMETHOD(device_probe, my_probe),
152 DEVMETHOD(device_attach, my_attach),
153 DEVMETHOD(device_detach, my_detach),
154 DEVMETHOD(device_shutdown, my_shutdown),
155
156 {0, 0}
157 };
158
159 static driver_t my_driver = {
160 "my",
161 my_methods,
162 sizeof(struct my_softc)
163 };
164
165 static devclass_t my_devclass;
166
167 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0);
168 MODULE_DEPEND(my, pci, 1, 1, 1);
169 MODULE_DEPEND(my, ether, 1, 1, 1);
170
171 static long
172 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
173 {
174 long miir;
175 int i;
176 int mask, data;
177
178 MY_LOCK_ASSERT(sc);
179
180 /* enable MII output */
181 miir = CSR_READ_4(sc, MY_MANAGEMENT);
182 miir &= 0xfffffff0;
183
184 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
185
186 /* send 32 1's preamble */
187 for (i = 0; i < 32; i++) {
188 /* low MDC; MDO is already high (miir) */
189 miir &= ~MY_MASK_MIIR_MII_MDC;
190 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
191
192 /* high MDC */
193 miir |= MY_MASK_MIIR_MII_MDC;
194 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
195 }
196
197 /* calculate ST+OP+PHYAD+REGAD+TA */
198 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
199
200 /* sent out */
201 mask = 0x8000;
202 while (mask) {
203 /* low MDC, prepare MDO */
204 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
205 if (mask & data)
206 miir |= MY_MASK_MIIR_MII_MDO;
207
208 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
209 /* high MDC */
210 miir |= MY_MASK_MIIR_MII_MDC;
211 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
212 DELAY(30);
213
214 /* next */
215 mask >>= 1;
216 if (mask == 0x2 && opcode == MY_OP_READ)
217 miir &= ~MY_MASK_MIIR_MII_WRITE;
218 }
219
220 return miir;
221 }
222
223
224 static u_int16_t
225 my_phy_readreg(struct my_softc * sc, int reg)
226 {
227 long miir;
228 int mask, data;
229
230 MY_LOCK_ASSERT(sc);
231
232 if (sc->my_info->my_did == MTD803ID)
233 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
234 else {
235 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
236
237 /* read data */
238 mask = 0x8000;
239 data = 0;
240 while (mask) {
241 /* low MDC */
242 miir &= ~MY_MASK_MIIR_MII_MDC;
243 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
244
245 /* read MDI */
246 miir = CSR_READ_4(sc, MY_MANAGEMENT);
247 if (miir & MY_MASK_MIIR_MII_MDI)
248 data |= mask;
249
250 /* high MDC, and wait */
251 miir |= MY_MASK_MIIR_MII_MDC;
252 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
253 DELAY(30);
254
255 /* next */
256 mask >>= 1;
257 }
258
259 /* low MDC */
260 miir &= ~MY_MASK_MIIR_MII_MDC;
261 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
262 }
263
264 return (u_int16_t) data;
265 }
266
267
268 static void
269 my_phy_writereg(struct my_softc * sc, int reg, int data)
270 {
271 long miir;
272 int mask;
273
274 MY_LOCK_ASSERT(sc);
275
276 if (sc->my_info->my_did == MTD803ID)
277 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
278 else {
279 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
280
281 /* write data */
282 mask = 0x8000;
283 while (mask) {
284 /* low MDC, prepare MDO */
285 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
286 if (mask & data)
287 miir |= MY_MASK_MIIR_MII_MDO;
288 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
289 DELAY(1);
290
291 /* high MDC */
292 miir |= MY_MASK_MIIR_MII_MDC;
293 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
294 DELAY(1);
295
296 /* next */
297 mask >>= 1;
298 }
299
300 /* low MDC */
301 miir &= ~MY_MASK_MIIR_MII_MDC;
302 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
303 }
304 return;
305 }
306
307
308 /*
309 * Program the 64-bit multicast hash filter.
310 */
311 static void
312 my_setmulti(struct my_softc * sc)
313 {
314 struct ifnet *ifp;
315 int h = 0;
316 u_int32_t hashes[2] = {0, 0};
317 struct ifmultiaddr *ifma;
318 u_int32_t rxfilt;
319 int mcnt = 0;
320
321 MY_LOCK_ASSERT(sc);
322
323 ifp = sc->my_ifp;
324
325 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
326
327 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
328 rxfilt |= MY_AM;
329 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
330 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
331 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
332
333 return;
334 }
335 /* first, zot all the existing hash bits */
336 CSR_WRITE_4(sc, MY_MAR0, 0);
337 CSR_WRITE_4(sc, MY_MAR1, 0);
338
339 /* now program new ones */
340 if_maddr_rlock(ifp);
341 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
342 if (ifma->ifma_addr->sa_family != AF_LINK)
343 continue;
344 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
345 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
346 if (h < 32)
347 hashes[0] |= (1 << h);
348 else
349 hashes[1] |= (1 << (h - 32));
350 mcnt++;
351 }
352 if_maddr_runlock(ifp);
353
354 if (mcnt)
355 rxfilt |= MY_AM;
356 else
357 rxfilt &= ~MY_AM;
358 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
359 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
360 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
361 return;
362 }
363
364 /*
365 * Initiate an autonegotiation session.
366 */
367 static void
368 my_autoneg_xmit(struct my_softc * sc)
369 {
370 u_int16_t phy_sts = 0;
371
372 MY_LOCK_ASSERT(sc);
373
374 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
375 DELAY(500);
376 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
377
378 phy_sts = my_phy_readreg(sc, PHY_BMCR);
379 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
380 my_phy_writereg(sc, PHY_BMCR, phy_sts);
381
382 return;
383 }
384
385 static void
386 my_autoneg_timeout(void *arg)
387 {
388 struct my_softc *sc;
389
390 sc = arg;
391 MY_LOCK_ASSERT(sc);
392 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
393 }
394
395 /*
396 * Invoke autonegotiation on a PHY.
397 */
398 static void
399 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
400 {
401 u_int16_t phy_sts = 0, media, advert, ability;
402 u_int16_t ability2 = 0;
403 struct ifnet *ifp;
404 struct ifmedia *ifm;
405
406 MY_LOCK_ASSERT(sc);
407
408 ifm = &sc->ifmedia;
409 ifp = sc->my_ifp;
410
411 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
412
413 #ifndef FORCE_AUTONEG_TFOUR
414 /*
415 * First, see if autoneg is supported. If not, there's no point in
416 * continuing.
417 */
418 phy_sts = my_phy_readreg(sc, PHY_BMSR);
419 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
420 if (verbose)
421 device_printf(sc->my_dev,
422 "autonegotiation not supported\n");
423 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
424 return;
425 }
426 #endif
427 switch (flag) {
428 case MY_FLAG_FORCEDELAY:
429 /*
430 * XXX Never use this option anywhere but in the probe
431 * routine: making the kernel stop dead in its tracks for
432 * three whole seconds after we've gone multi-user is really
433 * bad manners.
434 */
435 my_autoneg_xmit(sc);
436 DELAY(5000000);
437 break;
438 case MY_FLAG_SCHEDDELAY:
439 /*
440 * Wait for the transmitter to go idle before starting an
441 * autoneg session, otherwise my_start() may clobber our
442 * timeout, and we don't want to allow transmission during an
443 * autoneg session since that can screw it up.
444 */
445 if (sc->my_cdata.my_tx_head != NULL) {
446 sc->my_want_auto = 1;
447 MY_UNLOCK(sc);
448 return;
449 }
450 my_autoneg_xmit(sc);
451 callout_reset(&sc->my_autoneg_timer, hz * 5, my_autoneg_timeout,
452 sc);
453 sc->my_autoneg = 1;
454 sc->my_want_auto = 0;
455 return;
456 case MY_FLAG_DELAYTIMEO:
457 callout_stop(&sc->my_autoneg_timer);
458 sc->my_autoneg = 0;
459 break;
460 default:
461 device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag);
462 return;
463 }
464
465 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
466 if (verbose)
467 device_printf(sc->my_dev, "autoneg complete, ");
468 phy_sts = my_phy_readreg(sc, PHY_BMSR);
469 } else {
470 if (verbose)
471 device_printf(sc->my_dev, "autoneg not complete, ");
472 }
473
474 media = my_phy_readreg(sc, PHY_BMCR);
475
476 /* Link is good. Report modes and set duplex mode. */
477 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
478 if (verbose)
479 device_printf(sc->my_dev, "link status good. ");
480 advert = my_phy_readreg(sc, PHY_ANAR);
481 ability = my_phy_readreg(sc, PHY_LPAR);
482 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
483 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
484 ability2 = my_phy_readreg(sc, PHY_1000SR);
485 if (ability2 & PHY_1000SR_1000BTXFULL) {
486 advert = 0;
487 ability = 0;
488 /*
489 * this version did not support 1000M,
490 * ifm->ifm_media =
491 * IFM_ETHER|IFM_1000_T|IFM_FDX;
492 */
493 ifm->ifm_media =
494 IFM_ETHER | IFM_100_TX | IFM_FDX;
495 media &= ~PHY_BMCR_SPEEDSEL;
496 media |= PHY_BMCR_1000;
497 media |= PHY_BMCR_DUPLEX;
498 printf("(full-duplex, 1000Mbps)\n");
499 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
500 advert = 0;
501 ability = 0;
502 /*
503 * this version did not support 1000M,
504 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
505 */
506 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
507 media &= ~PHY_BMCR_SPEEDSEL;
508 media &= ~PHY_BMCR_DUPLEX;
509 media |= PHY_BMCR_1000;
510 printf("(half-duplex, 1000Mbps)\n");
511 }
512 }
513 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
514 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
515 media |= PHY_BMCR_SPEEDSEL;
516 media &= ~PHY_BMCR_DUPLEX;
517 printf("(100baseT4)\n");
518 } else if (advert & PHY_ANAR_100BTXFULL &&
519 ability & PHY_ANAR_100BTXFULL) {
520 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
521 media |= PHY_BMCR_SPEEDSEL;
522 media |= PHY_BMCR_DUPLEX;
523 printf("(full-duplex, 100Mbps)\n");
524 } else if (advert & PHY_ANAR_100BTXHALF &&
525 ability & PHY_ANAR_100BTXHALF) {
526 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
527 media |= PHY_BMCR_SPEEDSEL;
528 media &= ~PHY_BMCR_DUPLEX;
529 printf("(half-duplex, 100Mbps)\n");
530 } else if (advert & PHY_ANAR_10BTFULL &&
531 ability & PHY_ANAR_10BTFULL) {
532 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
533 media &= ~PHY_BMCR_SPEEDSEL;
534 media |= PHY_BMCR_DUPLEX;
535 printf("(full-duplex, 10Mbps)\n");
536 } else if (advert) {
537 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
538 media &= ~PHY_BMCR_SPEEDSEL;
539 media &= ~PHY_BMCR_DUPLEX;
540 printf("(half-duplex, 10Mbps)\n");
541 }
542 media &= ~PHY_BMCR_AUTONEGENBL;
543
544 /* Set ASIC's duplex mode to match the PHY. */
545 my_phy_writereg(sc, PHY_BMCR, media);
546 my_setcfg(sc, media);
547 } else {
548 if (verbose)
549 device_printf(sc->my_dev, "no carrier\n");
550 }
551
552 my_init_locked(sc);
553 if (sc->my_tx_pend) {
554 sc->my_autoneg = 0;
555 sc->my_tx_pend = 0;
556 my_start_locked(ifp);
557 }
558 return;
559 }
560
561 /*
562 * To get PHY ability.
563 */
564 static void
565 my_getmode_mii(struct my_softc * sc)
566 {
567 u_int16_t bmsr;
568 struct ifnet *ifp;
569
570 MY_LOCK_ASSERT(sc);
571 ifp = sc->my_ifp;
572 bmsr = my_phy_readreg(sc, PHY_BMSR);
573 if (bootverbose)
574 device_printf(sc->my_dev, "PHY status word: %x\n", bmsr);
575
576 /* fallback */
577 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
578
579 if (bmsr & PHY_BMSR_10BTHALF) {
580 if (bootverbose)
581 device_printf(sc->my_dev,
582 "10Mbps half-duplex mode supported\n");
583 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
584 0, NULL);
585 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
586 }
587 if (bmsr & PHY_BMSR_10BTFULL) {
588 if (bootverbose)
589 device_printf(sc->my_dev,
590 "10Mbps full-duplex mode supported\n");
591
592 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
593 0, NULL);
594 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
595 }
596 if (bmsr & PHY_BMSR_100BTXHALF) {
597 if (bootverbose)
598 device_printf(sc->my_dev,
599 "100Mbps half-duplex mode supported\n");
600 ifp->if_baudrate = 100000000;
601 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
602 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
603 0, NULL);
604 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
605 }
606 if (bmsr & PHY_BMSR_100BTXFULL) {
607 if (bootverbose)
608 device_printf(sc->my_dev,
609 "100Mbps full-duplex mode supported\n");
610 ifp->if_baudrate = 100000000;
611 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
612 0, NULL);
613 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
614 }
615 /* Some also support 100BaseT4. */
616 if (bmsr & PHY_BMSR_100BT4) {
617 if (bootverbose)
618 device_printf(sc->my_dev, "100baseT4 mode supported\n");
619 ifp->if_baudrate = 100000000;
620 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
621 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
622 #ifdef FORCE_AUTONEG_TFOUR
623 if (bootverbose)
624 device_printf(sc->my_dev,
625 "forcing on autoneg support for BT4\n");
626 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
627 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
628 #endif
629 }
630 #if 0 /* this version did not support 1000M, */
631 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
632 if (bootverbose)
633 device_printf(sc->my_dev,
634 "1000Mbps half-duplex mode supported\n");
635
636 ifp->if_baudrate = 1000000000;
637 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
638 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
639 0, NULL);
640 if (bootverbose)
641 device_printf(sc->my_dev,
642 "1000Mbps full-duplex mode supported\n");
643 ifp->if_baudrate = 1000000000;
644 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
645 0, NULL);
646 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
647 }
648 #endif
649 if (bmsr & PHY_BMSR_CANAUTONEG) {
650 if (bootverbose)
651 device_printf(sc->my_dev, "autoneg supported\n");
652 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
653 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
654 }
655 return;
656 }
657
658 /*
659 * Set speed and duplex mode.
660 */
661 static void
662 my_setmode_mii(struct my_softc * sc, int media)
663 {
664 u_int16_t bmcr;
665 struct ifnet *ifp;
666
667 MY_LOCK_ASSERT(sc);
668 ifp = sc->my_ifp;
669 /*
670 * If an autoneg session is in progress, stop it.
671 */
672 if (sc->my_autoneg) {
673 device_printf(sc->my_dev, "canceling autoneg session\n");
674 callout_stop(&sc->my_autoneg_timer);
675 sc->my_autoneg = sc->my_want_auto = 0;
676 bmcr = my_phy_readreg(sc, PHY_BMCR);
677 bmcr &= ~PHY_BMCR_AUTONEGENBL;
678 my_phy_writereg(sc, PHY_BMCR, bmcr);
679 }
680 device_printf(sc->my_dev, "selecting MII, ");
681 bmcr = my_phy_readreg(sc, PHY_BMCR);
682 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
683 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
684
685 #if 0 /* this version did not support 1000M, */
686 if (IFM_SUBTYPE(media) == IFM_1000_T) {
687 printf("1000Mbps/T4, half-duplex\n");
688 bmcr &= ~PHY_BMCR_SPEEDSEL;
689 bmcr &= ~PHY_BMCR_DUPLEX;
690 bmcr |= PHY_BMCR_1000;
691 }
692 #endif
693 if (IFM_SUBTYPE(media) == IFM_100_T4) {
694 printf("100Mbps/T4, half-duplex\n");
695 bmcr |= PHY_BMCR_SPEEDSEL;
696 bmcr &= ~PHY_BMCR_DUPLEX;
697 }
698 if (IFM_SUBTYPE(media) == IFM_100_TX) {
699 printf("100Mbps, ");
700 bmcr |= PHY_BMCR_SPEEDSEL;
701 }
702 if (IFM_SUBTYPE(media) == IFM_10_T) {
703 printf("10Mbps, ");
704 bmcr &= ~PHY_BMCR_SPEEDSEL;
705 }
706 if ((media & IFM_GMASK) == IFM_FDX) {
707 printf("full duplex\n");
708 bmcr |= PHY_BMCR_DUPLEX;
709 } else {
710 printf("half duplex\n");
711 bmcr &= ~PHY_BMCR_DUPLEX;
712 }
713 my_phy_writereg(sc, PHY_BMCR, bmcr);
714 my_setcfg(sc, bmcr);
715 return;
716 }
717
718 /*
719 * The Myson manual states that in order to fiddle with the 'full-duplex' and
720 * '100Mbps' bits in the netconfig register, we first have to put the
721 * transmit and/or receive logic in the idle state.
722 */
723 static void
724 my_setcfg(struct my_softc * sc, int bmcr)
725 {
726 int i, restart = 0;
727
728 MY_LOCK_ASSERT(sc);
729 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
730 restart = 1;
731 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
732 for (i = 0; i < MY_TIMEOUT; i++) {
733 DELAY(10);
734 if (!(CSR_READ_4(sc, MY_TCRRCR) &
735 (MY_TXRUN | MY_RXRUN)))
736 break;
737 }
738 if (i == MY_TIMEOUT)
739 device_printf(sc->my_dev,
740 "failed to force tx and rx to idle \n");
741 }
742 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
743 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
744 if (bmcr & PHY_BMCR_1000)
745 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
746 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
747 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
748 if (bmcr & PHY_BMCR_DUPLEX)
749 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
750 else
751 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
752 if (restart)
753 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
754 return;
755 }
756
757 static void
758 my_reset(struct my_softc * sc)
759 {
760 register int i;
761
762 MY_LOCK_ASSERT(sc);
763 MY_SETBIT(sc, MY_BCR, MY_SWR);
764 for (i = 0; i < MY_TIMEOUT; i++) {
765 DELAY(10);
766 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
767 break;
768 }
769 if (i == MY_TIMEOUT)
770 device_printf(sc->my_dev, "reset never completed!\n");
771
772 /* Wait a little while for the chip to get its brains in order. */
773 DELAY(1000);
774 return;
775 }
776
777 /*
778 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
779 * list and return a device name if we find a match.
780 */
781 static int
782 my_probe(device_t dev)
783 {
784 struct my_type *t;
785
786 t = my_devs;
787 while (t->my_name != NULL) {
788 if ((pci_get_vendor(dev) == t->my_vid) &&
789 (pci_get_device(dev) == t->my_did)) {
790 device_set_desc(dev, t->my_name);
791 my_info_tmp = t;
792 return (BUS_PROBE_DEFAULT);
793 }
794 t++;
795 }
796 return (ENXIO);
797 }
798
799 /*
800 * Attach the interface. Allocate softc structures, do ifmedia setup and
801 * ethernet/BPF attach.
802 */
803 static int
804 my_attach(device_t dev)
805 {
806 int i;
807 u_char eaddr[ETHER_ADDR_LEN];
808 u_int32_t iobase;
809 struct my_softc *sc;
810 struct ifnet *ifp;
811 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
812 unsigned int round;
813 caddr_t roundptr;
814 struct my_type *p;
815 u_int16_t phy_vid, phy_did, phy_sts = 0;
816 int rid, error = 0;
817
818 sc = device_get_softc(dev);
819 sc->my_dev = dev;
820 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
821 MTX_DEF);
822 callout_init_mtx(&sc->my_autoneg_timer, &sc->my_mtx, 0);
823 callout_init_mtx(&sc->my_watchdog, &sc->my_mtx, 0);
824
825 /*
826 * Map control/status registers.
827 */
828 pci_enable_busmaster(dev);
829
830 if (my_info_tmp->my_did == MTD800ID) {
831 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
832 if (iobase & 0x300)
833 MY_USEIOSPACE = 0;
834 }
835
836 rid = MY_RID;
837 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
838
839 if (sc->my_res == NULL) {
840 device_printf(dev, "couldn't map ports/memory\n");
841 error = ENXIO;
842 goto destroy_mutex;
843 }
844 sc->my_btag = rman_get_bustag(sc->my_res);
845 sc->my_bhandle = rman_get_bushandle(sc->my_res);
846
847 rid = 0;
848 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
849 RF_SHAREABLE | RF_ACTIVE);
850
851 if (sc->my_irq == NULL) {
852 device_printf(dev, "couldn't map interrupt\n");
853 error = ENXIO;
854 goto release_io;
855 }
856
857 sc->my_info = my_info_tmp;
858
859 /* Reset the adapter. */
860 MY_LOCK(sc);
861 my_reset(sc);
862 MY_UNLOCK(sc);
863
864 /*
865 * Get station address
866 */
867 for (i = 0; i < ETHER_ADDR_LEN; ++i)
868 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
869
870 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
871 M_DEVBUF, M_NOWAIT);
872 if (sc->my_ldata_ptr == NULL) {
873 device_printf(dev, "no memory for list buffers!\n");
874 error = ENXIO;
875 goto release_irq;
876 }
877 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
878 round = (uintptr_t)sc->my_ldata_ptr & 0xF;
879 roundptr = sc->my_ldata_ptr;
880 for (i = 0; i < 8; i++) {
881 if (round % 8) {
882 round++;
883 roundptr++;
884 } else
885 break;
886 }
887 sc->my_ldata = (struct my_list_data *) roundptr;
888 bzero(sc->my_ldata, sizeof(struct my_list_data));
889
890 ifp = sc->my_ifp = if_alloc(IFT_ETHER);
891 if (ifp == NULL) {
892 device_printf(dev, "can not if_alloc()\n");
893 error = ENOSPC;
894 goto free_ldata;
895 }
896 ifp->if_softc = sc;
897 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
898 ifp->if_mtu = ETHERMTU;
899 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
900 ifp->if_ioctl = my_ioctl;
901 ifp->if_start = my_start;
902 ifp->if_init = my_init;
903 ifp->if_baudrate = 10000000;
904 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
905 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
906 IFQ_SET_READY(&ifp->if_snd);
907
908 if (sc->my_info->my_did == MTD803ID)
909 sc->my_pinfo = my_phys;
910 else {
911 if (bootverbose)
912 device_printf(dev, "probing for a PHY\n");
913 MY_LOCK(sc);
914 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
915 if (bootverbose)
916 device_printf(dev, "checking address: %d\n", i);
917 sc->my_phy_addr = i;
918 phy_sts = my_phy_readreg(sc, PHY_BMSR);
919 if ((phy_sts != 0) && (phy_sts != 0xffff))
920 break;
921 else
922 phy_sts = 0;
923 }
924 if (phy_sts) {
925 phy_vid = my_phy_readreg(sc, PHY_VENID);
926 phy_did = my_phy_readreg(sc, PHY_DEVID);
927 if (bootverbose) {
928 device_printf(dev, "found PHY at address %d, ",
929 sc->my_phy_addr);
930 printf("vendor id: %x device id: %x\n",
931 phy_vid, phy_did);
932 }
933 p = my_phys;
934 while (p->my_vid) {
935 if (phy_vid == p->my_vid) {
936 sc->my_pinfo = p;
937 break;
938 }
939 p++;
940 }
941 if (sc->my_pinfo == NULL)
942 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
943 if (bootverbose)
944 device_printf(dev, "PHY type: %s\n",
945 sc->my_pinfo->my_name);
946 } else {
947 MY_UNLOCK(sc);
948 device_printf(dev, "MII without any phy!\n");
949 error = ENXIO;
950 goto free_if;
951 }
952 MY_UNLOCK(sc);
953 }
954
955 /* Do ifmedia setup. */
956 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
957 MY_LOCK(sc);
958 my_getmode_mii(sc);
959 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
960 media = sc->ifmedia.ifm_media;
961 my_stop(sc);
962 MY_UNLOCK(sc);
963 ifmedia_set(&sc->ifmedia, media);
964
965 ether_ifattach(ifp, eaddr);
966
967 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE,
968 NULL, my_intr, sc, &sc->my_intrhand);
969
970 if (error) {
971 device_printf(dev, "couldn't set up irq\n");
972 goto detach_if;
973 }
974
975 return (0);
976
977 detach_if:
978 ether_ifdetach(ifp);
979 free_if:
980 if_free(ifp);
981 free_ldata:
982 free(sc->my_ldata_ptr, M_DEVBUF);
983 release_irq:
984 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
985 release_io:
986 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
987 destroy_mutex:
988 mtx_destroy(&sc->my_mtx);
989 return (error);
990 }
991
992 static int
993 my_detach(device_t dev)
994 {
995 struct my_softc *sc;
996 struct ifnet *ifp;
997
998 sc = device_get_softc(dev);
999 ifp = sc->my_ifp;
1000 ether_ifdetach(ifp);
1001 MY_LOCK(sc);
1002 my_stop(sc);
1003 MY_UNLOCK(sc);
1004 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
1005 callout_drain(&sc->my_watchdog);
1006 callout_drain(&sc->my_autoneg_timer);
1007
1008 if_free(ifp);
1009 free(sc->my_ldata_ptr, M_DEVBUF);
1010
1011 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1012 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1013 mtx_destroy(&sc->my_mtx);
1014 return (0);
1015 }
1016
1017
1018 /*
1019 * Initialize the transmit descriptors.
1020 */
1021 static int
1022 my_list_tx_init(struct my_softc * sc)
1023 {
1024 struct my_chain_data *cd;
1025 struct my_list_data *ld;
1026 int i;
1027
1028 MY_LOCK_ASSERT(sc);
1029 cd = &sc->my_cdata;
1030 ld = sc->my_ldata;
1031 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1032 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1033 if (i == (MY_TX_LIST_CNT - 1))
1034 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1035 else
1036 cd->my_tx_chain[i].my_nextdesc =
1037 &cd->my_tx_chain[i + 1];
1038 }
1039 cd->my_tx_free = &cd->my_tx_chain[0];
1040 cd->my_tx_tail = cd->my_tx_head = NULL;
1041 return (0);
1042 }
1043
1044 /*
1045 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1046 * arrange the descriptors in a closed ring, so that the last descriptor
1047 * points back to the first.
1048 */
1049 static int
1050 my_list_rx_init(struct my_softc * sc)
1051 {
1052 struct my_chain_data *cd;
1053 struct my_list_data *ld;
1054 int i;
1055
1056 MY_LOCK_ASSERT(sc);
1057 cd = &sc->my_cdata;
1058 ld = sc->my_ldata;
1059 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1060 cd->my_rx_chain[i].my_ptr =
1061 (struct my_desc *) & ld->my_rx_list[i];
1062 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1063 MY_UNLOCK(sc);
1064 return (ENOBUFS);
1065 }
1066 if (i == (MY_RX_LIST_CNT - 1)) {
1067 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1068 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1069 } else {
1070 cd->my_rx_chain[i].my_nextdesc =
1071 &cd->my_rx_chain[i + 1];
1072 ld->my_rx_list[i].my_next =
1073 vtophys(&ld->my_rx_list[i + 1]);
1074 }
1075 }
1076 cd->my_rx_head = &cd->my_rx_chain[0];
1077 return (0);
1078 }
1079
1080 /*
1081 * Initialize an RX descriptor and attach an MBUF cluster.
1082 */
1083 static int
1084 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1085 {
1086 struct mbuf *m_new = NULL;
1087
1088 MY_LOCK_ASSERT(sc);
1089 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1090 if (m_new == NULL) {
1091 device_printf(sc->my_dev,
1092 "no memory for rx list -- packet dropped!\n");
1093 return (ENOBUFS);
1094 }
1095 MCLGET(m_new, M_DONTWAIT);
1096 if (!(m_new->m_flags & M_EXT)) {
1097 device_printf(sc->my_dev,
1098 "no memory for rx list -- packet dropped!\n");
1099 m_freem(m_new);
1100 return (ENOBUFS);
1101 }
1102 c->my_mbuf = m_new;
1103 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1104 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1105 c->my_ptr->my_status = MY_OWNByNIC;
1106 return (0);
1107 }
1108
1109 /*
1110 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1111 * level protocols.
1112 */
1113 static void
1114 my_rxeof(struct my_softc * sc)
1115 {
1116 struct ether_header *eh;
1117 struct mbuf *m;
1118 struct ifnet *ifp;
1119 struct my_chain_onefrag *cur_rx;
1120 int total_len = 0;
1121 u_int32_t rxstat;
1122
1123 MY_LOCK_ASSERT(sc);
1124 ifp = sc->my_ifp;
1125 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1126 & MY_OWNByNIC)) {
1127 cur_rx = sc->my_cdata.my_rx_head;
1128 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1129
1130 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1131 ifp->if_ierrors++;
1132 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1133 continue;
1134 }
1135 /* No errors; receive the packet. */
1136 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1137 total_len -= ETHER_CRC_LEN;
1138
1139 if (total_len < MINCLSIZE) {
1140 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1141 total_len, 0, ifp, NULL);
1142 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1143 if (m == NULL) {
1144 ifp->if_ierrors++;
1145 continue;
1146 }
1147 } else {
1148 m = cur_rx->my_mbuf;
1149 /*
1150 * Try to conjure up a new mbuf cluster. If that
1151 * fails, it means we have an out of memory condition
1152 * and should leave the buffer in place and continue.
1153 * This will result in a lost packet, but there's
1154 * little else we can do in this situation.
1155 */
1156 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1157 ifp->if_ierrors++;
1158 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1159 continue;
1160 }
1161 m->m_pkthdr.rcvif = ifp;
1162 m->m_pkthdr.len = m->m_len = total_len;
1163 }
1164 ifp->if_ipackets++;
1165 eh = mtod(m, struct ether_header *);
1166 #if NBPFILTER > 0
1167 /*
1168 * Handle BPF listeners. Let the BPF user see the packet, but
1169 * don't pass it up to the ether_input() layer unless it's a
1170 * broadcast packet, multicast packet, matches our ethernet
1171 * address or the interface is in promiscuous mode.
1172 */
1173 if (bpf_peers_present(ifp->if_bpf)) {
1174 bpf_mtap(ifp->if_bpf, m);
1175 if (ifp->if_flags & IFF_PROMISC &&
1176 (bcmp(eh->ether_dhost, IF_LLADDR(sc->my_ifp),
1177 ETHER_ADDR_LEN) &&
1178 (eh->ether_dhost[0] & 1) == 0)) {
1179 m_freem(m);
1180 continue;
1181 }
1182 }
1183 #endif
1184 MY_UNLOCK(sc);
1185 (*ifp->if_input)(ifp, m);
1186 MY_LOCK(sc);
1187 }
1188 return;
1189 }
1190
1191
1192 /*
1193 * A frame was downloaded to the chip. It's safe for us to clean up the list
1194 * buffers.
1195 */
1196 static void
1197 my_txeof(struct my_softc * sc)
1198 {
1199 struct my_chain *cur_tx;
1200 struct ifnet *ifp;
1201
1202 MY_LOCK_ASSERT(sc);
1203 ifp = sc->my_ifp;
1204 /* Clear the timeout timer. */
1205 sc->my_timer = 0;
1206 if (sc->my_cdata.my_tx_head == NULL) {
1207 return;
1208 }
1209 /*
1210 * Go through our tx list and free mbufs for those frames that have
1211 * been transmitted.
1212 */
1213 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1214 u_int32_t txstat;
1215
1216 cur_tx = sc->my_cdata.my_tx_head;
1217 txstat = MY_TXSTATUS(cur_tx);
1218 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1219 break;
1220 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1221 if (txstat & MY_TXERR) {
1222 ifp->if_oerrors++;
1223 if (txstat & MY_EC) /* excessive collision */
1224 ifp->if_collisions++;
1225 if (txstat & MY_LC) /* late collision */
1226 ifp->if_collisions++;
1227 }
1228 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1229 MY_NCRShift;
1230 }
1231 ifp->if_opackets++;
1232 m_freem(cur_tx->my_mbuf);
1233 cur_tx->my_mbuf = NULL;
1234 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1235 sc->my_cdata.my_tx_head = NULL;
1236 sc->my_cdata.my_tx_tail = NULL;
1237 break;
1238 }
1239 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1240 }
1241 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1242 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1243 }
1244 return;
1245 }
1246
1247 /*
1248 * TX 'end of channel' interrupt handler.
1249 */
1250 static void
1251 my_txeoc(struct my_softc * sc)
1252 {
1253 struct ifnet *ifp;
1254
1255 MY_LOCK_ASSERT(sc);
1256 ifp = sc->my_ifp;
1257 sc->my_timer = 0;
1258 if (sc->my_cdata.my_tx_head == NULL) {
1259 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1260 sc->my_cdata.my_tx_tail = NULL;
1261 if (sc->my_want_auto)
1262 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1263 } else {
1264 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1265 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1266 sc->my_timer = 5;
1267 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1268 }
1269 }
1270 return;
1271 }
1272
1273 static void
1274 my_intr(void *arg)
1275 {
1276 struct my_softc *sc;
1277 struct ifnet *ifp;
1278 u_int32_t status;
1279
1280 sc = arg;
1281 MY_LOCK(sc);
1282 ifp = sc->my_ifp;
1283 if (!(ifp->if_flags & IFF_UP)) {
1284 MY_UNLOCK(sc);
1285 return;
1286 }
1287 /* Disable interrupts. */
1288 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1289
1290 for (;;) {
1291 status = CSR_READ_4(sc, MY_ISR);
1292 status &= MY_INTRS;
1293 if (status)
1294 CSR_WRITE_4(sc, MY_ISR, status);
1295 else
1296 break;
1297
1298 if (status & MY_RI) /* receive interrupt */
1299 my_rxeof(sc);
1300
1301 if ((status & MY_RBU) || (status & MY_RxErr)) {
1302 /* rx buffer unavailable or rx error */
1303 ifp->if_ierrors++;
1304 #ifdef foo
1305 my_stop(sc);
1306 my_reset(sc);
1307 my_init_locked(sc);
1308 #endif
1309 }
1310 if (status & MY_TI) /* tx interrupt */
1311 my_txeof(sc);
1312 if (status & MY_ETI) /* tx early interrupt */
1313 my_txeof(sc);
1314 if (status & MY_TBU) /* tx buffer unavailable */
1315 my_txeoc(sc);
1316
1317 #if 0 /* 90/1/18 delete */
1318 if (status & MY_FBE) {
1319 my_reset(sc);
1320 my_init_locked(sc);
1321 }
1322 #endif
1323
1324 }
1325
1326 /* Re-enable interrupts. */
1327 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1328 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1329 my_start_locked(ifp);
1330 MY_UNLOCK(sc);
1331 return;
1332 }
1333
1334 /*
1335 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1336 * pointers to the fragment pointers.
1337 */
1338 static int
1339 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1340 {
1341 struct my_desc *f = NULL;
1342 int total_len;
1343 struct mbuf *m, *m_new = NULL;
1344
1345 MY_LOCK_ASSERT(sc);
1346 /* calculate the total tx pkt length */
1347 total_len = 0;
1348 for (m = m_head; m != NULL; m = m->m_next)
1349 total_len += m->m_len;
1350 /*
1351 * Start packing the mbufs in this chain into the fragment pointers.
1352 * Stop when we run out of fragments or hit the end of the mbuf
1353 * chain.
1354 */
1355 m = m_head;
1356 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1357 if (m_new == NULL) {
1358 device_printf(sc->my_dev, "no memory for tx list");
1359 return (1);
1360 }
1361 if (m_head->m_pkthdr.len > MHLEN) {
1362 MCLGET(m_new, M_DONTWAIT);
1363 if (!(m_new->m_flags & M_EXT)) {
1364 m_freem(m_new);
1365 device_printf(sc->my_dev, "no memory for tx list");
1366 return (1);
1367 }
1368 }
1369 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1370 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1371 m_freem(m_head);
1372 m_head = m_new;
1373 f = &c->my_ptr->my_frag[0];
1374 f->my_status = 0;
1375 f->my_data = vtophys(mtod(m_new, caddr_t));
1376 total_len = m_new->m_len;
1377 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1378 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1379 f->my_ctl |= total_len; /* buffer size */
1380 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1381 if (sc->my_info->my_did == MTD891ID)
1382 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1383 c->my_mbuf = m_head;
1384 c->my_lastdesc = 0;
1385 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1386 return (0);
1387 }
1388
1389 /*
1390 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1391 * to the mbuf data regions directly in the transmit lists. We also save a
1392 * copy of the pointers since the transmit list fragment pointers are
1393 * physical addresses.
1394 */
1395 static void
1396 my_start(struct ifnet * ifp)
1397 {
1398 struct my_softc *sc;
1399
1400 sc = ifp->if_softc;
1401 MY_LOCK(sc);
1402 my_start_locked(ifp);
1403 MY_UNLOCK(sc);
1404 }
1405
1406 static void
1407 my_start_locked(struct ifnet * ifp)
1408 {
1409 struct my_softc *sc;
1410 struct mbuf *m_head = NULL;
1411 struct my_chain *cur_tx = NULL, *start_tx;
1412
1413 sc = ifp->if_softc;
1414 MY_LOCK_ASSERT(sc);
1415 if (sc->my_autoneg) {
1416 sc->my_tx_pend = 1;
1417 return;
1418 }
1419 /*
1420 * Check for an available queue slot. If there are none, punt.
1421 */
1422 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1423 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1424 return;
1425 }
1426 start_tx = sc->my_cdata.my_tx_free;
1427 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1428 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1429 if (m_head == NULL)
1430 break;
1431
1432 /* Pick a descriptor off the free list. */
1433 cur_tx = sc->my_cdata.my_tx_free;
1434 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1435
1436 /* Pack the data into the descriptor. */
1437 my_encap(sc, cur_tx, m_head);
1438
1439 if (cur_tx != start_tx)
1440 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1441 #if NBPFILTER > 0
1442 /*
1443 * If there's a BPF listener, bounce a copy of this frame to
1444 * him.
1445 */
1446 BPF_MTAP(ifp, cur_tx->my_mbuf);
1447 #endif
1448 }
1449 /*
1450 * If there are no packets queued, bail.
1451 */
1452 if (cur_tx == NULL) {
1453 return;
1454 }
1455 /*
1456 * Place the request for the upload interrupt in the last descriptor
1457 * in the chain. This way, if we're chaining several packets at once,
1458 * we'll only get an interrupt once for the whole chain rather than
1459 * once for each packet.
1460 */
1461 MY_TXCTL(cur_tx) |= MY_TXIC;
1462 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1463 sc->my_cdata.my_tx_tail = cur_tx;
1464 if (sc->my_cdata.my_tx_head == NULL)
1465 sc->my_cdata.my_tx_head = start_tx;
1466 MY_TXOWN(start_tx) = MY_OWNByNIC;
1467 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1468
1469 /*
1470 * Set a timeout in case the chip goes out to lunch.
1471 */
1472 sc->my_timer = 5;
1473 return;
1474 }
1475
1476 static void
1477 my_init(void *xsc)
1478 {
1479 struct my_softc *sc = xsc;
1480
1481 MY_LOCK(sc);
1482 my_init_locked(sc);
1483 MY_UNLOCK(sc);
1484 }
1485
1486 static void
1487 my_init_locked(struct my_softc *sc)
1488 {
1489 struct ifnet *ifp = sc->my_ifp;
1490 u_int16_t phy_bmcr = 0;
1491
1492 MY_LOCK_ASSERT(sc);
1493 if (sc->my_autoneg) {
1494 return;
1495 }
1496 if (sc->my_pinfo != NULL)
1497 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1498 /*
1499 * Cancel pending I/O and free all RX/TX buffers.
1500 */
1501 my_stop(sc);
1502 my_reset(sc);
1503
1504 /*
1505 * Set cache alignment and burst length.
1506 */
1507 #if 0 /* 89/9/1 modify, */
1508 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1509 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1510 #endif
1511 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1512 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1513 /*
1514 * 89/12/29 add, for mtd891,
1515 */
1516 if (sc->my_info->my_did == MTD891ID) {
1517 MY_SETBIT(sc, MY_BCR, MY_PROG);
1518 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1519 }
1520 my_setcfg(sc, phy_bmcr);
1521 /* Init circular RX list. */
1522 if (my_list_rx_init(sc) == ENOBUFS) {
1523 device_printf(sc->my_dev, "init failed: no memory for rx buffers\n");
1524 my_stop(sc);
1525 return;
1526 }
1527 /* Init TX descriptors. */
1528 my_list_tx_init(sc);
1529
1530 /* If we want promiscuous mode, set the allframes bit. */
1531 if (ifp->if_flags & IFF_PROMISC)
1532 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1533 else
1534 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1535
1536 /*
1537 * Set capture broadcast bit to capture broadcast frames.
1538 */
1539 if (ifp->if_flags & IFF_BROADCAST)
1540 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1541 else
1542 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1543
1544 /*
1545 * Program the multicast filter, if necessary.
1546 */
1547 my_setmulti(sc);
1548
1549 /*
1550 * Load the address of the RX list.
1551 */
1552 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1553 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1554
1555 /*
1556 * Enable interrupts.
1557 */
1558 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1559 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1560
1561 /* Enable receiver and transmitter. */
1562 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1563 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1564 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1565 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1566
1567 /* Restore state of BMCR */
1568 if (sc->my_pinfo != NULL)
1569 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1570 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1571 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1572
1573 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1574 return;
1575 }
1576
1577 /*
1578 * Set media options.
1579 */
1580
1581 static int
1582 my_ifmedia_upd(struct ifnet * ifp)
1583 {
1584 struct my_softc *sc;
1585 struct ifmedia *ifm;
1586
1587 sc = ifp->if_softc;
1588 MY_LOCK(sc);
1589 ifm = &sc->ifmedia;
1590 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1591 MY_UNLOCK(sc);
1592 return (EINVAL);
1593 }
1594 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1595 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1596 else
1597 my_setmode_mii(sc, ifm->ifm_media);
1598 MY_UNLOCK(sc);
1599 return (0);
1600 }
1601
1602 /*
1603 * Report current media status.
1604 */
1605
1606 static void
1607 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1608 {
1609 struct my_softc *sc;
1610 u_int16_t advert = 0, ability = 0;
1611
1612 sc = ifp->if_softc;
1613 MY_LOCK(sc);
1614 ifmr->ifm_active = IFM_ETHER;
1615 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1616 #if 0 /* this version did not support 1000M, */
1617 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1618 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1619 #endif
1620 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1621 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1622 else
1623 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1624 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1625 ifmr->ifm_active |= IFM_FDX;
1626 else
1627 ifmr->ifm_active |= IFM_HDX;
1628
1629 MY_UNLOCK(sc);
1630 return;
1631 }
1632 ability = my_phy_readreg(sc, PHY_LPAR);
1633 advert = my_phy_readreg(sc, PHY_ANAR);
1634
1635 #if 0 /* this version did not support 1000M, */
1636 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1637 ability2 = my_phy_readreg(sc, PHY_1000SR);
1638 if (ability2 & PHY_1000SR_1000BTXFULL) {
1639 advert = 0;
1640 ability = 0;
1641 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1642 } else if (ability & PHY_1000SR_1000BTXHALF) {
1643 advert = 0;
1644 ability = 0;
1645 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1646 }
1647 }
1648 #endif
1649 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1650 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1651 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1652 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1653 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1654 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1655 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1656 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1657 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1658 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1659 MY_UNLOCK(sc);
1660 return;
1661 }
1662
1663 static int
1664 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1665 {
1666 struct my_softc *sc = ifp->if_softc;
1667 struct ifreq *ifr = (struct ifreq *) data;
1668 int error;
1669
1670 switch (command) {
1671 case SIOCSIFFLAGS:
1672 MY_LOCK(sc);
1673 if (ifp->if_flags & IFF_UP)
1674 my_init_locked(sc);
1675 else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1676 my_stop(sc);
1677 MY_UNLOCK(sc);
1678 error = 0;
1679 break;
1680 case SIOCADDMULTI:
1681 case SIOCDELMULTI:
1682 MY_LOCK(sc);
1683 my_setmulti(sc);
1684 MY_UNLOCK(sc);
1685 error = 0;
1686 break;
1687 case SIOCGIFMEDIA:
1688 case SIOCSIFMEDIA:
1689 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1690 break;
1691 default:
1692 error = ether_ioctl(ifp, command, data);
1693 break;
1694 }
1695 return (error);
1696 }
1697
1698 static void
1699 my_watchdog(void *arg)
1700 {
1701 struct my_softc *sc;
1702 struct ifnet *ifp;
1703
1704 sc = arg;
1705 MY_LOCK_ASSERT(sc);
1706 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc);
1707 if (sc->my_timer == 0 || --sc->my_timer > 0)
1708 return;
1709
1710 ifp = sc->my_ifp;
1711 ifp->if_oerrors++;
1712 if_printf(ifp, "watchdog timeout\n");
1713 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1714 if_printf(ifp, "no carrier - transceiver cable problem?\n");
1715 my_stop(sc);
1716 my_reset(sc);
1717 my_init_locked(sc);
1718 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1719 my_start_locked(ifp);
1720 }
1721
1722
1723 /*
1724 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1725 */
1726 static void
1727 my_stop(struct my_softc * sc)
1728 {
1729 register int i;
1730 struct ifnet *ifp;
1731
1732 MY_LOCK_ASSERT(sc);
1733 ifp = sc->my_ifp;
1734
1735 callout_stop(&sc->my_autoneg_timer);
1736 callout_stop(&sc->my_watchdog);
1737
1738 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1739 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1740 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1741 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1742
1743 /*
1744 * Free data in the RX lists.
1745 */
1746 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1747 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1748 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1749 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1750 }
1751 }
1752 bzero((char *)&sc->my_ldata->my_rx_list,
1753 sizeof(sc->my_ldata->my_rx_list));
1754 /*
1755 * Free the TX list buffers.
1756 */
1757 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1758 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1759 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1760 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1761 }
1762 }
1763 bzero((char *)&sc->my_ldata->my_tx_list,
1764 sizeof(sc->my_ldata->my_tx_list));
1765 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1766 return;
1767 }
1768
1769 /*
1770 * Stop all chip I/O so that the kernel's probe routines don't get confused
1771 * by errant DMAs when rebooting.
1772 */
1773 static int
1774 my_shutdown(device_t dev)
1775 {
1776 struct my_softc *sc;
1777
1778 sc = device_get_softc(dev);
1779 MY_LOCK(sc);
1780 my_stop(sc);
1781 MY_UNLOCK(sc);
1782 return 0;
1783 }
Cache object: fa028443bcefc235d046f49bee6894ed
|