The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/my/if_myreg.h

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    1 /*
    2  * Copyright (c) 2002 Myson Technology Inc.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions, and the following disclaimer,
   10  *    without modification, immediately at the beginning of the file.
   11  * 2. The name of the author may not be used to endorse or promote products
   12  *    derived from this software without specific prior written permission.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
   18  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * Written by: yen_cw@myson.com.tw  available at: http://www.myson.com.tw/
   27  *
   28  * $FreeBSD: releng/5.3/sys/dev/my/if_myreg.h 93746 2002-04-04 05:22:13Z julian $
   29  *
   30  * Myson MTD80x register definitions.
   31  *
   32  */
   33 #define MY_PAR0         0x0     /* physical address 0-3 */
   34 #define MY_PAR1         0x04    /* physical address 4-5 */
   35 #define MY_MAR0         0x08    /* multicast address 0-3 */
   36 #define MY_MAR1         0x0C    /* multicast address 4-7 */
   37 #define MY_FAR0         0x10    /* flow-control address 0-3 */
   38 #define MY_FAR1         0x14    /* flow-control address 4-5 */
   39 #define MY_TCRRCR       0x18    /* receive & transmit configuration */
   40 #define MY_BCR          0x1C    /* bus command */
   41 #define MY_TXPDR        0x20    /* transmit polling demand */
   42 #define MY_RXPDR        0x24    /* receive polling demand */
   43 #define MY_RXCWP        0x28    /* receive current word pointer */
   44 #define MY_TXLBA        0x2C    /* transmit list base address */
   45 #define MY_RXLBA        0x30    /* receive list base address */
   46 #define MY_ISR          0x34    /* interrupt status */
   47 #define MY_IMR          0x38    /* interrupt mask */
   48 #define MY_FTH          0x3C    /* flow control high/low threshold */
   49 #define MY_MANAGEMENT   0x40    /* bootrom/eeprom and mii management */
   50 #define MY_TALLY        0x44    /* tally counters for crc and mpa */
   51 #define MY_TSR          0x48    /* tally counter for transmit status */
   52 #define MY_PHYBASE      0x4c
   53 
   54 /*
   55  * Receive Configuration Register
   56  */
   57 #define MY_RXRUN        0x00008000      /* receive running status */
   58 #define MY_EIEN         0x00004000      /* early interrupt enable */
   59 #define MY_RFCEN        0x00002000      /* receive flow control packet enable */
   60 #define MY_NDFA         0x00001000      /* not defined flow control address */
   61 #define MY_RBLEN        0x00000800      /* receive burst length enable */
   62 #define MY_RPBLE1       0x00000000      /* 1 word */
   63 #define MY_RPBLE4       0x00000100      /* 4 words */
   64 #define MY_RPBLE8       0x00000200      /* 8 words */
   65 #define MY_RPBLE16      0x00000300      /* 16 words */
   66 #define MY_RPBLE32      0x00000400      /* 32 words */
   67 #define MY_RPBLE64      0x00000500      /* 64 words */
   68 #define MY_RPBLE128     0x00000600      /* 128 words */
   69 #define MY_RPBLE512     0x00000700      /* 512 words */
   70 #define MY_PROM         0x000000080     /* promiscuous mode */
   71 #define MY_AB           0x000000040     /* accept broadcast */
   72 #define MY_AM           0x000000020     /* accept mutlicast */
   73 #define MY_ARP          0x000000008     /* receive runt pkt */
   74 #define MY_ALP          0x000000004     /* receive long pkt */
   75 #define MY_SEP          0x000000002     /* receive error pkt */
   76 #define MY_RE           0x000000001     /* receive enable */
   77 
   78 /*
   79  * Transmit Configuration Register
   80  */
   81 #define MY_TXRUN        0x04000000      /* transmit running status */
   82 #define MY_Enhanced     0x02000000      /* transmit enhanced mode */
   83 #define MY_TFCEN        0x01000000      /* tx flow control packet enable */
   84 #define MY_TFT64        0x00000000      /* 64 bytes */
   85 #define MY_TFT32        0x00200000      /* 32 bytes */
   86 #define MY_TFT128       0x00400000      /* 128 bytes */
   87 #define MY_TFT256       0x00600000      /* 256 bytes */
   88 #define MY_TFT512       0x00800000      /* 512 bytes */
   89 #define MY_TFT768       0x00A00000      /* 768 bytes */
   90 #define MY_TFT1024      0x00C00000      /* 1024 bytes */
   91 #define MY_TFTSF        0x00E00000      /* store and forward */
   92 #define MY_FD           0x00100000      /* full duplex mode */
   93 #define MY_PS10         0x00080000      /* port speed is 10M */
   94 #define MY_TE           0x00040000      /* transmit enable */
   95 #define MY_PS1000       0x00010000      /* port speed is 1000M */
   96 /*
   97  * Bus Command Register
   98  */
   99 #define MY_PROG         0x00000200      /* programming */
  100 #define MY_RLE          0x00000100      /* read line command enable */
  101 #define MY_RME          0x00000080      /* read multiple command enable */
  102 #define MY_WIE          0x00000040      /* write and invalidate cmd enable */
  103 #define MY_PBL1         0x00000000      /* 1 dword */
  104 #define MY_PBL4         0x00000008      /* 4 dwords */
  105 #define MY_PBL8         0x00000010      /* 8 dwords */
  106 #define MY_PBL16        0x00000018      /* 16 dwords */
  107 #define MY_PBL32        0x00000020      /* 32 dwords */
  108 #define MY_PBL64        0x00000028      /* 64 dwords */
  109 #define MY_PBL128       0x00000030      /* 128 dwords */
  110 #define MY_PBL512       0x00000038      /* 512 dwords */
  111 #define MY_ABR          0x00000004      /* arbitration rule */
  112 #define MY_BLS          0x00000002      /* big/little endian select */
  113 #define MY_SWR          0x00000001      /* software reset */
  114 
  115 /*
  116  * Transmit Poll Demand Register
  117  */
  118 #define MY_TxPollDemand 0x1
  119 
  120 /*
  121  * Receive Poll Demand Register
  122  */
  123 #define MY_RxPollDemand 0x01
  124 
  125 /*
  126  * Interrupt Status Register
  127  */
  128 #define MY_RFCON        0x00020000      /* receive flow control xon packet */
  129 #define MY_RFCOFF       0x00010000      /* receive flow control xoff packet */
  130 #define MY_LSCStatus    0x00008000      /* link status change */
  131 #define MY_ANCStatus    0x00004000      /* autonegotiation completed */
  132 #define MY_FBE          0x00002000      /* fatal bus error */
  133 #define MY_FBEMask      0x00001800
  134 #define MY_ParityErr    0x00000000      /* parity error */
  135 #define MY_MasterErr    0x00000800      /* master error */
  136 #define MY_TargetErr    0x00001000      /* target abort */
  137 #define MY_TUNF         0x00000400      /* transmit underflow */
  138 #define MY_ROVF         0x00000200      /* receive overflow */
  139 #define MY_ETI          0x00000100      /* transmit early int */
  140 #define MY_ERI          0x00000080      /* receive early int */
  141 #define MY_CNTOVF       0x00000040      /* counter overflow */
  142 #define MY_RBU          0x00000020      /* receive buffer unavailable */
  143 #define MY_TBU          0x00000010      /* transmit buffer unavilable */
  144 #define MY_TI           0x00000008      /* transmit interrupt */
  145 #define MY_RI           0x00000004      /* receive interrupt */
  146 #define MY_RxErr        0x00000002      /* receive error */
  147 
  148 /*
  149  * Interrupt Mask Register
  150  */
  151 #define MY_MRFCON       0x00020000      /* receive flow control xon packet */
  152 #define MY_MRFCOFF      0x00010000      /* receive flow control xoff packet */
  153 #define MY_MLSCStatus   0x00008000      /* link status change */
  154 #define MY_MANCStatus   0x00004000      /* autonegotiation completed */
  155 #define MY_MFBE         0x00002000      /* fatal bus error */
  156 #define MY_MFBEMask     0x00001800
  157 #define MY_MTUNF        0x00000400      /* transmit underflow */
  158 #define MY_MROVF        0x00000200      /* receive overflow */
  159 #define MY_METI         0x00000100      /* transmit early int */
  160 #define MY_MERI         0x00000080      /* receive early int */
  161 #define MY_MCNTOVF      0x00000040      /* counter overflow */
  162 #define MY_MRBU         0x00000020      /* receive buffer unavailable */
  163 #define MY_MTBU         0x00000010      /* transmit buffer unavilable */
  164 #define MY_MTI          0x00000008      /* transmit interrupt */
  165 #define MY_MRI          0x00000004      /* receive interrupt */
  166 #define MY_MRxErr       0x00000002      /* receive error */
  167 
  168 /* 90/1/18 delete */
  169 /* #define MY_INTRS MY_FBE|MY_MRBU|MY_TBU|MY_MTI|MY_MRI|MY_METI */
  170 #define MY_INTRS MY_MRBU|MY_TBU|MY_MTI|MY_MRI|MY_METI
  171 
  172 /*
  173  * Flow Control High/Low Threshold Register
  174  */
  175 #define MY_FCHTShift    16      /* flow control high threshold */
  176 #define MY_FCLTShift    0       /* flow control low threshold */
  177 
  178 /*
  179  * BootROM/EEPROM/MII Management Register
  180  */
  181 #define MY_MASK_MIIR_MII_READ   0x00000000
  182 #define MY_MASK_MIIR_MII_WRITE  0x00000008
  183 #define MY_MASK_MIIR_MII_MDO    0x00000004
  184 #define MY_MASK_MIIR_MII_MDI    0x00000002
  185 #define MY_MASK_MIIR_MII_MDC    0x00000001
  186 
  187 /*
  188  * Tally Counter for CRC and MPA
  189  */
  190 #define MY_TCOVF        0x80000000      /* crc tally counter overflow */
  191 #define MY_CRCMask      0x7fff0000      /* crc number: bit 16-30 */
  192 #define MY_CRCShift     16
  193 #define MY_TMOVF        0x00008000      /* mpa tally counter overflow */
  194 #define MY_MPAMask      0x00007fff      /* mpa number: bit 0-14 */
  195 #define MY_MPAShift     0
  196 
  197 /*
  198  * Tally Counters for transmit status
  199  */
  200 #define MY_AbortMask      0xff000000    /* transmit abort number */
  201 #define MY_AbortShift     24
  202 #define MY_LColMask       0x00ff0000    /* transmit late collisions */
  203 #define MY_LColShift      16
  204 #define MY_NCRMask        0x0000ffff    /* transmit retry number */
  205 #define MY_NCRShift       0
  206 
  207 /*
  208  * Myson TX/RX descriptor structure.
  209  */
  210 
  211 struct my_desc {
  212         u_int32_t       my_status;
  213         u_int32_t       my_ctl;
  214         u_int32_t       my_data;
  215         u_int32_t       my_next;
  216 };
  217 
  218 /*
  219  * for tx/rx descriptors
  220  */
  221 #define MY_OWNByNIC     0x80000000
  222 #define MY_OWNByDriver  0x0
  223 
  224 /*
  225  * receive descriptor 0
  226  */
  227 #define MY_RXOWN        0x80000000      /* own bit */
  228 #define MY_FLNGMASK     0x0fff0000      /* frame length */
  229 #define MY_FLNGShift    16
  230 #define MY_MARSTATUS    0x00004000      /* multicast address received */
  231 #define MY_BARSTATUS    0x00002000      /* broadcast address received */
  232 #define MY_PHYSTATUS    0x00001000      /* physical address received */
  233 #define MY_RXFSD        0x00000800      /* first descriptor */
  234 #define MY_RXLSD        0x00000400      /* last descriptor */
  235 #define MY_ES           0x00000080      /* error summary */
  236 #define MY_RUNT         0x00000040      /* runt packet received */
  237 #define MY_LONG         0x00000020      /* long packet received */
  238 #define MY_FAE          0x00000010      /* frame align error */
  239 #define MY_CRC          0x00000008      /* crc error */
  240 #define MY_RXER         0x00000004      /* receive error */
  241 #define MY_RDES0CHECK   0x000078fc      /* only check MAR, BAR, PHY, ES, RUNT,
  242                                            LONG, FAE, CRC and RXER bits */
  243 
  244 /*
  245  * receive descriptor 1
  246  */
  247 #define MY_RXIC         0x00800000      /* interrupt control */
  248 #define MY_RBSMASK      0x000007ff      /* receive buffer size */
  249 #define MY_RBSShift     0
  250 
  251 /*
  252  * transmit descriptor 0
  253  */
  254 #define MY_TXERR        0x00008000      /* transmit error */
  255 #define MY_JABTO        0x00004000      /* jabber timeout */
  256 #define MY_CSL          0x00002000      /* carrier sense lost */
  257 #define MY_LC           0x00001000      /* late collision */
  258 #define MY_EC           0x00000800      /* excessive collision */
  259 #define MY_UDF          0x00000400      /* fifo underflow */
  260 #define MY_DFR          0x00000200      /* deferred */
  261 #define MY_HF           0x00000100      /* heartbeat fail */
  262 #define MY_NCRMASK      0x000000ff      /* collision retry count */
  263 #define MY_NCRShift     0
  264 
  265 /*
  266  * tx descriptor 1
  267  */
  268 #define MY_TXIC         0x80000000      /* interrupt control */
  269 #define MY_ETIControl   0x40000000      /* early transmit interrupt */
  270 #define MY_TXLD         0x20000000      /* last descriptor */
  271 #define MY_TXFD         0x10000000      /* first descriptor */
  272 #define MY_CRCDisable   0x00000000      /* crc control */
  273 #define MY_CRCEnable    0x08000000
  274 #define MY_PADDisable   0x00000000      /* padding control */
  275 #define MY_PADEnable    0x04000000
  276 #define MY_RetryTxLC    0x02000000      /* retry late collision */
  277 #define MY_PKTShift     11              /* transmit pkt size */
  278 #define MY_TBSMASK      0x000007ff
  279 #define MY_TBSShift     0               /* transmit buffer size */
  280 
  281 #define MY_MAXFRAGS     1
  282 #define MY_RX_LIST_CNT  64
  283 #define MY_TX_LIST_CNT  64
  284 #define MY_MIN_FRAMELEN 60
  285 
  286 /*
  287  * A transmit 'super descriptor' is actually MY_MAXFRAGS regular
  288  * descriptors clumped together. The idea here is to emulate the
  289  * multi-fragment descriptor layout found in devices such as the
  290  * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips.
  291  * The advantage to using this scheme is that it avoids buffer copies.
  292  * The disadvantage is that there's a certain amount of overhead due
  293  * to the fact that each 'fragment' is 16 bytes long. In my tests,
  294  * this limits top speed to about 10.5MB/sec. It should be more like
  295  * 11.5MB/sec. However, the upshot is that you can achieve better
  296  * results on slower machines: a Pentium 200 can pump out packets at
  297  * same speed as a PII 400.
  298  */
  299 struct my_txdesc {
  300         struct my_desc          my_frag[MY_MAXFRAGS];
  301 };
  302 
  303 #define MY_TXSTATUS(x)  x->my_ptr->my_frag[x->my_lastdesc].my_status
  304 #define MY_TXCTL(x)     x->my_ptr->my_frag[x->my_lastdesc].my_ctl
  305 #define MY_TXDATA(x)    x->my_ptr->my_frag[x->my_lastdesc].my_data
  306 #define MY_TXNEXT(x)    x->my_ptr->my_frag[x->my_lastdesc].my_next
  307 
  308 #define MY_TXOWN(x)     x->my_ptr->my_frag[0].my_status
  309 
  310 #define MY_UNSENT       0x1234
  311 
  312 struct my_list_data {
  313         struct my_desc          my_rx_list[MY_RX_LIST_CNT];
  314         struct my_txdesc        my_tx_list[MY_TX_LIST_CNT];
  315 };
  316 
  317 struct my_chain {
  318         struct my_txdesc        *my_ptr;
  319         struct mbuf             *my_mbuf;
  320         struct my_chain         *my_nextdesc;
  321         u_int8_t                my_lastdesc;
  322 };
  323 
  324 struct my_chain_onefrag {
  325         struct my_desc          *my_ptr;
  326         struct mbuf             *my_mbuf;
  327         struct my_chain_onefrag *my_nextdesc;
  328         u_int8_t                my_rlast;
  329 };
  330 
  331 struct my_chain_data {
  332         struct my_chain_onefrag my_rx_chain[MY_RX_LIST_CNT];
  333         struct my_chain         my_tx_chain[MY_TX_LIST_CNT];
  334 
  335         struct my_chain_onefrag *my_rx_head;
  336 
  337         struct my_chain         *my_tx_head;
  338         struct my_chain         *my_tx_tail;
  339         struct my_chain         *my_tx_free;
  340 };
  341 
  342 struct my_type {
  343         u_int16_t               my_vid;
  344         u_int16_t               my_did;
  345         char                    *my_name;
  346 };
  347 
  348 #define MY_FLAG_FORCEDELAY      1
  349 #define MY_FLAG_SCHEDDELAY      2
  350 #define MY_FLAG_DELAYTIMEO      3
  351 
  352 struct my_softc {
  353         struct arpcom           arpcom;         /* interface info */
  354         struct ifmedia          ifmedia;        /* media info */
  355         bus_space_handle_t      my_bhandle;
  356         bus_space_tag_t         my_btag;
  357         struct my_type          *my_info;       /* adapter info */
  358         struct my_type          *my_pinfo;      /* phy info */
  359         struct resource         *my_res;
  360         struct resource         *my_irq;
  361         void                    *my_intrhand;
  362         u_int8_t                my_unit;        /* interface number */
  363         u_int8_t                my_phy_addr;    /* PHY address */
  364         u_int8_t                my_tx_pend;     /* TX pending */
  365         u_int8_t                my_want_auto;
  366         u_int8_t                my_autoneg;
  367         u_int16_t               my_txthresh;
  368         u_int8_t                my_stats_no_timeout;        
  369         caddr_t                 my_ldata_ptr;
  370         struct my_list_data     *my_ldata;
  371         struct my_chain_data    my_cdata;
  372         device_t                my_miibus;
  373         struct callout_handle   my_stat_ch;
  374 /* Add by Surfer 2001/12/2 */
  375         struct mtx              my_mtx; 
  376 
  377 };
  378 
  379 /* Add by Surfer 2001/12/2 */
  380 #define MY_LOCK(_sc)            mtx_lock(&(_sc)->my_mtx)
  381 #define MY_UNLOCK(_sc)          mtx_unlock(&(_sc)->my_mtx)
  382 
  383 /*
  384  * register space access macros
  385  */
  386 #define CSR_WRITE_4(sc, reg, val)       \
  387         bus_space_write_4(sc->my_btag, sc->my_bhandle, reg, val)
  388 #define CSR_WRITE_2(sc, reg, val)       \
  389         bus_space_write_2(sc->my_btag, sc->my_bhandle, reg, val)
  390 #define CSR_WRITE_1(sc, reg, val)       \
  391         bus_space_write_1(sc->my_btag, sc->my_bhandle, reg, val)
  392 
  393 #define CSR_READ_4(sc, reg)     \
  394         bus_space_read_4(sc->my_btag, sc->my_bhandle, reg)
  395 #define CSR_READ_2(sc, reg)     \
  396         bus_space_read_2(sc->my_btag, sc->my_bhandle, reg)
  397 #define CSR_READ_1(sc, reg)     \
  398         bus_space_read_1(sc->my_btag, sc->my_bhandle, reg)
  399 
  400 #define MY_TIMEOUT              1000
  401 
  402 /*
  403  * General constants that are fun to know.
  404  *
  405  * MYSON PCI vendor ID
  406  */
  407 #define MYSONVENDORID           0x1516
  408 
  409 /*
  410  * MYSON device IDs.
  411  */
  412 #define MTD800ID                0x0800
  413 #define MTD803ID                0x0803
  414 #define MTD891ID                0x0891
  415 
  416 /*
  417  * ST+OP+PHYAD+REGAD+TA
  418  */
  419 #define MY_OP_READ      0x6000  /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
  420 #define MY_OP_WRITE     0x5002  /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
  421 
  422 /*
  423  * Constansts for Myson PHY
  424  */
  425 #define MysonPHYID0     0x0300
  426 
  427 /*
  428  * Constansts for Seeq 80225 PHY
  429  */
  430 #define SeeqPHYID0      0x0016
  431 
  432 #define SEEQ_MIIRegister18      18
  433 #define SEEQ_SPD_DET_100        0x80
  434 #define SEEQ_DPLX_DET_FULL      0x40
  435 
  436 /*
  437  * Constansts for Ahdoc 101 PHY
  438  */
  439 #define AhdocPHYID0     0x0022
  440 
  441 #define AHDOC_DiagnosticReg     18
  442 #define AHDOC_DPLX_FULL         0x0800
  443 #define AHDOC_Speed_100         0x0400
  444 
  445 /*
  446  * Constansts for Marvell 88E1000/88E1000S PHY and LevelOne PHY
  447  */
  448 #define MarvellPHYID0           0x0141
  449 #define LevelOnePHYID0          0x0013
  450 
  451 #define Marvell_SpecificStatus  17
  452 #define Marvell_Speed1000       0x8000
  453 #define Marvell_Speed100        0x4000
  454 #define Marvell_FullDuplex      0x2000
  455 
  456 /*
  457  * PCI low memory base and low I/O base register, and
  458  * other PCI registers. Note: some are only available on
  459  * the 3c905B, in particular those that related to power management.
  460  */
  461 #define MY_PCI_VENDOR_ID        0x00
  462 #define MY_PCI_DEVICE_ID        0x02
  463 #define MY_PCI_COMMAND          0x04
  464 #define MY_PCI_STATUS           0x06
  465 #define MY_PCI_CLASSCODE        0x09
  466 #define MY_PCI_LATENCY_TIMER    0x0D
  467 #define MY_PCI_HEADER_TYPE      0x0E
  468 #define MY_PCI_LOIO             0x10
  469 #define MY_PCI_LOMEM            0x14
  470 #define MY_PCI_BIOSROM          0x30
  471 #define MY_PCI_INTLINE          0x3C
  472 #define MY_PCI_INTPIN           0x3D
  473 #define MY_PCI_MINGNT           0x3E
  474 #define MY_PCI_MINLAT           0x0F
  475 #define MY_PCI_RESETOPT         0x48
  476 #define MY_PCI_EEPROM_DATA      0x4C
  477 
  478 #define PHY_UNKNOWN             3
  479 
  480 #define MY_PHYADDR_MIN          0x00
  481 #define MY_PHYADDR_MAX          0x1F
  482 
  483 #define PHY_BMCR                0x00
  484 #define PHY_BMSR                0x01
  485 #define PHY_VENID               0x02
  486 #define PHY_DEVID               0x03
  487 #define PHY_ANAR                0x04
  488 #define PHY_LPAR                0x05
  489 #define PHY_ANEXP               0x06
  490 #define PHY_NPTR                0x07
  491 #define PHY_LPNPR               0x08
  492 #define PHY_1000CR              0x09
  493 #define PHY_1000SR              0x0a
  494 
  495 #define PHY_ANAR_NEXTPAGE       0x8000
  496 #define PHY_ANAR_RSVD0          0x4000
  497 #define PHY_ANAR_TLRFLT         0x2000
  498 #define PHY_ANAR_RSVD1          0x1000
  499 #define PHY_ANAR_RSVD2          0x0800
  500 #define PHY_ANAR_RSVD3          0x0400
  501 #define PHY_ANAR_100BT4         0x0200L
  502 #define PHY_ANAR_100BTXFULL     0x0100
  503 #define PHY_ANAR_100BTXHALF     0x0080
  504 #define PHY_ANAR_10BTFULL       0x0040
  505 #define PHY_ANAR_10BTHALF       0x0020
  506 #define PHY_ANAR_PROTO4         0x0010
  507 #define PHY_ANAR_PROTO3         0x0008
  508 #define PHY_ANAR_PROTO2         0x0004
  509 #define PHY_ANAR_PROTO1         0x0002
  510 #define PHY_ANAR_PROTO0         0x0001
  511 
  512 #define PHY_1000SR_1000BTXFULL  0x0800
  513 #define PHY_1000SR_1000BTXHALF  0x0400
  514 
  515 /*
  516  * These are the register definitions for the PHY (physical layer
  517  * interface chip).
  518  */
  519 /*
  520  * PHY BMCR Basic Mode Control Register
  521  */
  522 #define PHY_BMCR_RESET                  0x8000
  523 #define PHY_BMCR_LOOPBK                 0x4000
  524 #define PHY_BMCR_SPEEDSEL               0x2000
  525 #define PHY_BMCR_AUTONEGENBL            0x1000
  526 #define PHY_BMCR_RSVD0                  0x0800  /* write as zero */
  527 #define PHY_BMCR_ISOLATE                0x0400
  528 #define PHY_BMCR_AUTONEGRSTR            0x0200
  529 #define PHY_BMCR_DUPLEX                 0x0100
  530 #define PHY_BMCR_COLLTEST               0x0080
  531 #define PHY_BMCR_1000                   0x0040  /* only used for Marvell PHY */
  532 #define PHY_BMCR_RSVD2                  0x0020  /* write as zero, don't care */
  533 #define PHY_BMCR_RSVD3                  0x0010  /* write as zero, don't care */
  534 #define PHY_BMCR_RSVD4                  0x0008  /* write as zero, don't care */
  535 #define PHY_BMCR_RSVD5                  0x0004  /* write as zero, don't care */
  536 #define PHY_BMCR_RSVD6                  0x0002  /* write as zero, don't care */
  537 #define PHY_BMCR_RSVD7                  0x0001  /* write as zero, don't care */
  538 
  539 /*
  540  * RESET: 1 == software reset, 0 == normal operation
  541  * Resets status and control registers to default values.
  542  * Relatches all hardware config values.
  543  *
  544  * LOOPBK: 1 == loopback operation enabled, 0 == normal operation
  545  *
  546  * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
  547  * Link speed is selected byt his bit or if auto-negotiation if bit
  548  * 12 (AUTONEGENBL) is set (in which case the value of this register
  549  * is ignored).
  550  *
  551  * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
  552  * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
  553  * determine speed and mode. Should be cleared and then set if PHY configured
  554  * for no autoneg on startup.
  555  *
  556  * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
  557  *
  558  * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
  559  *
  560  * DUPLEX: 1 == full duplex mode, 0 == half duplex mode
  561  *
  562  * COLLTEST: 1 == collision test enabled, 0 == normal operation
  563  */
  564 
  565 /*
  566  * PHY, BMSR Basic Mode Status Register
  567  */
  568 #define PHY_BMSR_100BT4                 0x8000
  569 #define PHY_BMSR_100BTXFULL             0x4000
  570 #define PHY_BMSR_100BTXHALF             0x2000
  571 #define PHY_BMSR_10BTFULL               0x1000
  572 #define PHY_BMSR_10BTHALF               0x0800
  573 #define PHY_BMSR_RSVD1                  0x0400  /* write as zero, don't care */
  574 #define PHY_BMSR_RSVD2                  0x0200  /* write as zero, don't care */
  575 #define PHY_BMSR_RSVD3                  0x0100  /* write as zero, don't care */
  576 #define PHY_BMSR_RSVD4                  0x0080  /* write as zero, don't care */
  577 #define PHY_BMSR_MFPRESUP               0x0040
  578 #define PHY_BMSR_AUTONEGCOMP            0x0020
  579 #define PHY_BMSR_REMFAULT               0x0010
  580 #define PHY_BMSR_CANAUTONEG             0x0008
  581 #define PHY_BMSR_LINKSTAT               0x0004
  582 #define PHY_BMSR_JABBER                 0x0002
  583 #define PHY_BMSR_EXTENDED               0x0001
  584 
  585 

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