Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/netif/alc/if_alcreg.h
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1 /*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMATES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMATE. 26 * 27 * $FreeBSD: src/sys/dev/alc/if_alcreg.h,v 1.1 2009/06/10 02:07:58 yongari Exp $ 28 */ 29 30 #ifndef _IF_ALCREG_H 31 #define _IF_ALCREG_H 32 33 /* 34 * Atheros Communucations, Inc. PCI vendor ID 35 */ 36 #define VENDORID_ATHEROS 0x1969 37 38 /* 39 * Atheros AR813x/AR815x device ID 40 */ 41 #define DEVICEID_ATHEROS_AR8131 0x1063 /* L1C */ 42 #define DEVICEID_ATHEROS_AR8132 0x1062 /* L2C */ 43 #define DEVICEID_ATHEROS_AR8151 0x1073 /* L1D V1.0 */ 44 #define DEVICEID_ATHEROS_AR8151_V2 0x1083 /* L1D V2.0 */ 45 #define DEVICEID_ATHEROS_AR8152_B 0x2060 /* L2C V1.1 */ 46 #define DEVICEID_ATHEROS_AR8152_B2 0x2062 /* L2C V2.0 */ 47 48 #define ATHEROS_AR8152_B_V10 0xC0 49 #define ATHEROS_AR8152_B_V11 0xC1 50 51 /* 52 * From FreeBSD dev/pci/pcireg.h 53 * 54 * PCIM_xxx: mask to locate subfield in register 55 * PCIR_xxx: config register offset 56 */ 57 #define PCIR_EXPRESS_DEVICE_CTL 0x8 58 #define PCIR_EXPRESS_LINK_CAP 0xc 59 #define PCIR_EXPRESS_LINK_CTL 0x10 60 #define PCIM_EXP_CTL_MAX_READ_REQUEST 0x7000 61 #define PCIM_EXP_CTL_MAX_PAYLOAD 0x00e0 62 #define PCIM_LINK_CAP_ASPM 0x00000c00 63 64 /* 0x0000 - 0x02FF : PCIe configuration space */ 65 66 #define ALC_PEX_UNC_ERR_SEV 0x10C 67 #define PEX_UNC_ERR_SEV_TRN 0x00000001 68 #define PEX_UNC_ERR_SEV_DLP 0x00000010 69 #define PEX_UNC_ERR_SEV_PSN_TLP 0x00001000 70 #define PEX_UNC_ERR_SEV_FCP 0x00002000 71 #define PEX_UNC_ERR_SEV_CPL_TO 0x00004000 72 #define PEX_UNC_ERR_SEV_CA 0x00008000 73 #define PEX_UNC_ERR_SEV_UC 0x00010000 74 #define PEX_UNC_ERR_SEV_ROV 0x00020000 75 #define PEX_UNC_ERR_SEV_MLFP 0x00040000 76 #define PEX_UNC_ERR_SEV_ECRC 0x00080000 77 #define PEX_UNC_ERR_SEV_UR 0x00100000 78 79 #define ALC_TWSI_CFG 0x218 80 #define TWSI_CFG_SW_LD_START 0x00000800 81 #define TWSI_CFG_HW_LD_START 0x00001000 82 #define TWSI_CFG_LD_EXIST 0x00400000 83 84 #define ALC_PCIE_PHYMISC 0x1000 85 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 86 87 #define ALC_PCIE_PHYMISC2 0x1004 88 #define PCIE_PHYMISC2_SERDES_CDR_MASK 0x00030000 89 #define PCIE_PHYMISC2_SERDES_TH_MASK 0x000C0000 90 #define PCIE_PHYMISC2_SERDES_CDR_SHIFT 16 91 #define PCIE_PHYMISC2_SERDES_TH_SHIFT 18 92 93 #define ALC_TWSI_DEBUG 0x1108 94 #define TWSI_DEBUG_DEV_EXIST 0x20000000 95 96 #define ALC_EEPROM_CFG 0x12C0 97 #define EEPROM_CFG_DATA_HI_MASK 0x0000FFFF 98 #define EEPROM_CFG_ADDR_MASK 0x03FF0000 99 #define EEPROM_CFG_ACK 0x40000000 100 #define EEPROM_CFG_RW 0x80000000 101 #define EEPROM_CFG_DATA_HI_SHIFT 0 102 #define EEPROM_CFG_ADDR_SHIFT 16 103 104 #define ALC_EEPROM_DATA_LO 0x12C4 105 106 #define ALC_OPT_CFG 0x12F0 107 #define OPT_CFG_CLK_ENB 0x00000002 108 109 #define ALC_PM_CFG 0x12F8 110 #define PM_CFG_SERDES_ENB 0x00000001 111 #define PM_CFG_RBER_ENB 0x00000002 112 #define PM_CFG_CLK_REQ_ENB 0x00000004 113 #define PM_CFG_ASPM_L1_ENB 0x00000008 114 #define PM_CFG_SERDES_L1_ENB 0x00000010 115 #define PM_CFG_SERDES_PLL_L1_ENB 0x00000020 116 #define PM_CFG_SERDES_PD_EX_L1 0x00000040 117 #define PM_CFG_SERDES_BUDS_RX_L1_ENB 0x00000080 118 #define PM_CFG_L0S_ENTRY_TIMER_MASK 0x00000F00 119 #define PM_CFG_ASPM_L0S_ENB 0x00001000 120 #define PM_CFG_CLK_SWH_L1 0x00002000 121 #define PM_CFG_CLK_PWM_VER1_1 0x00004000 122 #define PM_CFG_PCIE_RECV 0x00008000 123 #define PM_CFG_L1_ENTRY_TIMER_MASK 0x000F0000 124 #define PM_CFG_PM_REQ_TIMER_MASK 0x00F00000 125 #define PM_CFG_LCKDET_TIMER_MASK 0x3F000000 126 #define PM_CFG_EN_BUFS_RX_L0S 0x10000000 127 #define PM_CFG_SA_DLY_ENB 0x20000000 128 #define PM_CFG_MAC_ASPM_CHK 0x40000000 129 #define PM_CFG_HOTRST 0x80000000 130 #define PM_CFG_L0S_ENTRY_TIMER_SHIFT 8 131 #define PM_CFG_L1_ENTRY_TIMER_SHIFT 16 132 #define PM_CFG_PM_REQ_TIMER_SHIFT 20 133 #define PM_CFG_LCKDET_TIMER_SHIFT 24 134 135 #define PM_CFG_L0S_ENTRY_TIMER_DEFAULT 6 136 #define PM_CFG_L1_ENTRY_TIMER_DEFAULT 12 137 #define PM_CFG_PM_REQ_TIMER_DEFAULT 1 138 139 #define ALC_LTSSM_ID_CFG 0x12FC 140 #define LTSSM_ID_WRO_ENB 0x00001000 141 142 #define ALC_MASTER_CFG 0x1400 143 #define MASTER_RESET 0x00000001 144 #define MASTER_TEST_MODE_MASK 0x0000000C 145 #define MASTER_BERT_START 0x00000010 146 #define MASTER_OOB_DIS_OFF 0x00000040 147 #define MASTER_SA_TIMER_ENB 0x00000080 148 #define MASTER_MTIMER_ENB 0x00000100 149 #define MASTER_MANUAL_INTR_ENB 0x00000200 150 #define MASTER_IM_TX_TIMER_ENB 0x00000400 151 #define MASTER_IM_RX_TIMER_ENB 0x00000800 152 #define MASTER_CLK_SEL_DIS 0x00001000 153 #define MASTER_CLK_SWH_MODE 0x00002000 154 #define MASTER_INTR_RD_CLR 0x00004000 155 #define MASTER_CHIP_REV_MASK 0x00FF0000 156 #define MASTER_CHIP_ID_MASK 0x7F000000 157 #define MASTER_OTP_SEL 0x80000000 158 #define MASTER_TEST_MODE_SHIFT 2 159 #define MASTER_CHIP_REV_SHIFT 16 160 #define MASTER_CHIP_ID_SHIFT 24 161 162 /* Number of ticks per usec for AR813x/AR815x. */ 163 #define ALC_TICK_USECS 2 164 #define ALC_USECS(x) ((x) / ALC_TICK_USECS) 165 166 #define ALC_MANUAL_TIMER 0x1404 167 168 #define ALC_IM_TIMER 0x1408 169 #define IM_TIMER_TX_MASK 0x0000FFFF 170 #define IM_TIMER_RX_MASK 0xFFFF0000 171 #define IM_TIMER_TX_SHIFT 0 172 #define IM_TIMER_RX_SHIFT 16 173 #define ALC_IM_TIMER_MIN 0 174 #define ALC_IM_TIMER_MAX 130000 /* 130ms */ 175 /* 176 * 100us will ensure alc(4) wouldn't generate more than 10000 Rx 177 * interrupts in a second. 178 */ 179 #define ALC_IM_RX_TIMER_DEFAULT 100 /* 100us */ 180 /* 181 * alc(4) does not rely on Tx completion interrupts, so set it 182 * somewhat large value to reduce Tx completion interrupts. 183 */ 184 #define ALC_IM_TX_TIMER_DEFAULT 1000 /* 1ms */ 185 186 #define ALC_GPHY_CFG 0x140C /* 16bits */ 187 #define GPHY_CFG_EXT_RESET 0x0001 188 #define GPHY_CFG_RTL_MODE 0x0002 189 #define GPHY_CFG_LED_MODE 0x0004 190 #define GPHY_CFG_ANEG_NOW 0x0008 191 #define GPHY_CFG_RECV_ANEG 0x0010 192 #define GPHY_CFG_GATE_25M_ENB 0x0020 193 #define GPHY_CFG_LPW_EXIT 0x0040 194 #define GPHY_CFG_PHY_IDDQ 0x0080 195 #define GPHY_CFG_PHY_IDDQ_DIS 0x0100 196 #define GPHY_CFG_PCLK_SEL_DIS 0x0200 197 #define GPHY_CFG_HIB_EN 0x0400 198 #define GPHY_CFG_HIB_PULSE 0x0800 199 #define GPHY_CFG_SEL_ANA_RESET 0x1000 200 #define GPHY_CFG_PHY_PLL_ON 0x2000 201 #define GPHY_CFG_PWDOWN_HW 0x4000 202 #define GPHY_CFG_PHY_PLL_BYPASS 0x8000 203 204 #define ALC_IDLE_STATUS 0x1410 205 #define IDLE_STATUS_RXMAC 0x00000001 206 #define IDLE_STATUS_TXMAC 0x00000002 207 #define IDLE_STATUS_RXQ 0x00000004 208 #define IDLE_STATUS_TXQ 0x00000008 209 #define IDLE_STATUS_DMARD 0x00000010 210 #define IDLE_STATUS_DMAWR 0x00000020 211 #define IDLE_STATUS_SMB 0x00000040 212 #define IDLE_STATUS_CMB 0x00000080 213 214 #define ALC_MDIO 0x1414 215 #define MDIO_DATA_MASK 0x0000FFFF 216 #define MDIO_REG_ADDR_MASK 0x001F0000 217 #define MDIO_OP_READ 0x00200000 218 #define MDIO_OP_WRITE 0x00000000 219 #define MDIO_SUP_PREAMBLE 0x00400000 220 #define MDIO_OP_EXECUTE 0x00800000 221 #define MDIO_CLK_25_4 0x00000000 222 #define MDIO_CLK_25_6 0x02000000 223 #define MDIO_CLK_25_8 0x03000000 224 #define MDIO_CLK_25_10 0x04000000 225 #define MDIO_CLK_25_14 0x05000000 226 #define MDIO_CLK_25_20 0x06000000 227 #define MDIO_CLK_25_28 0x07000000 228 #define MDIO_OP_BUSY 0x08000000 229 #define MDIO_AP_ENB 0x10000000 230 #define MDIO_DATA_SHIFT 0 231 #define MDIO_REG_ADDR_SHIFT 16 232 233 #define MDIO_REG_ADDR(x) \ 234 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 235 /* Default PHY address. */ 236 #define ALC_PHY_ADDR 0 237 238 #define ALC_PHY_STATUS 0x1418 239 #define PHY_STATUS_RECV_ENB 0x00000001 240 #define PHY_STATUS_GENERAL_MASK 0x0000FFFF 241 #define PHY_STATUS_OE_PWSP_MASK 0x07FF0000 242 #define PHY_STATUS_LPW_STATE 0x80000000 243 #define PHY_STATIS_OE_PWSP_SHIFT 16 244 245 /* Packet memory BIST. */ 246 #define ALC_BIST0 0x141C 247 #define BIST0_ENB 0x00000001 248 #define BIST0_SRAM_FAIL 0x00000002 249 #define BIST0_FUSE_FLAG 0x00000004 250 251 /* PCIe retry buffer BIST. */ 252 #define ALC_BIST1 0x1420 253 #define BIST1_ENB 0x00000001 254 #define BIST1_SRAM_FAIL 0x00000002 255 #define BIST1_FUSE_FLAG 0x00000004 256 257 #define ALC_SERDES_LOCK 0x1424 258 #define SERDES_LOCK_DET 0x00000001 259 #define SERDES_LOCK_DET_ENB 0x00000002 260 #define SERDES_MAC_CLK_SLOWDOWN 0x00020000 261 #define SERDES_PHY_CLK_SLOWDOWN 0x00040000 262 263 #define ALC_MAC_CFG 0x1480 264 #define MAC_CFG_TX_ENB 0x00000001 265 #define MAC_CFG_RX_ENB 0x00000002 266 #define MAC_CFG_TX_FC 0x00000004 267 #define MAC_CFG_RX_FC 0x00000008 268 #define MAC_CFG_LOOP 0x00000010 269 #define MAC_CFG_FULL_DUPLEX 0x00000020 270 #define MAC_CFG_TX_CRC_ENB 0x00000040 271 #define MAC_CFG_TX_AUTO_PAD 0x00000080 272 #define MAC_CFG_TX_LENCHK 0x00000100 273 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 274 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 275 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 276 #define MAC_CFG_PROMISC 0x00008000 277 #define MAC_CFG_TX_PAUSE 0x00010000 278 #define MAC_CFG_SCNT 0x00020000 279 #define MAC_CFG_SYNC_RST_TX 0x00040000 280 #define MAC_CFG_SIM_RST_TX 0x00080000 281 #define MAC_CFG_SPEED_MASK 0x00300000 282 #define MAC_CFG_SPEED_10_100 0x00100000 283 #define MAC_CFG_SPEED_1000 0x00200000 284 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 285 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 286 #define MAC_CFG_RXCSUM_ENB 0x01000000 287 #define MAC_CFG_ALLMULTI 0x02000000 288 #define MAC_CFG_BCAST 0x04000000 289 #define MAC_CFG_DBG 0x08000000 290 #define MAC_CFG_SINGLE_PAUSE_ENB 0x10000000 291 #define MAC_CFG_HASH_ALG_CRC32 0x20000000 292 #define MAC_CFG_SPEED_MODE_SW 0x40000000 293 #define MAC_CFG_PREAMBLE_SHIFT 10 294 #define MAC_CFG_PREAMBLE_DEFAULT 7 295 296 #define ALC_IPG_IFG_CFG 0x1484 297 #define IPG_IFG_IPGT_MASK 0x0000007F 298 #define IPG_IFG_MIFG_MASK 0x0000FF00 299 #define IPG_IFG_IPG1_MASK 0x007F0000 300 #define IPG_IFG_IPG2_MASK 0x7F000000 301 #define IPG_IFG_IPGT_SHIFT 0 302 #define IPG_IFG_IPGT_DEFAULT 0x60 303 #define IPG_IFG_MIFG_SHIFT 8 304 #define IPG_IFG_MIFG_DEFAULT 0x50 305 #define IPG_IFG_IPG1_SHIFT 16 306 #define IPG_IFG_IPG1_DEFAULT 0x40 307 #define IPG_IFG_IPG2_SHIFT 24 308 #define IPG_IFG_IPG2_DEFAULT 0x60 309 310 /* Station address. */ 311 #define ALC_PAR0 0x1488 312 #define ALC_PAR1 0x148C 313 314 /* 64bit multicast hash register. */ 315 #define ALC_MAR0 0x1490 316 #define ALC_MAR1 0x1494 317 318 /* half-duplex parameter configuration. */ 319 #define ALC_HDPX_CFG 0x1498 320 #define HDPX_CFG_LCOL_MASK 0x000003FF 321 #define HDPX_CFG_RETRY_MASK 0x0000F000 322 #define HDPX_CFG_EXC_DEF_EN 0x00010000 323 #define HDPX_CFG_NO_BACK_C 0x00020000 324 #define HDPX_CFG_NO_BACK_P 0x00040000 325 #define HDPX_CFG_ABEBE 0x00080000 326 #define HDPX_CFG_ABEBT_MASK 0x00F00000 327 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 328 #define HDPX_CFG_LCOL_SHIFT 0 329 #define HDPX_CFG_LCOL_DEFAULT 0x37 330 #define HDPX_CFG_RETRY_SHIFT 12 331 #define HDPX_CFG_RETRY_DEFAULT 0x0F 332 #define HDPX_CFG_ABEBT_SHIFT 20 333 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 334 #define HDPX_CFG_JAMIPG_SHIFT 24 335 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 336 337 #define ALC_FRAME_SIZE 0x149C 338 339 #define ALC_WOL_CFG 0x14A0 340 #define WOL_CFG_PATTERN 0x00000001 341 #define WOL_CFG_PATTERN_ENB 0x00000002 342 #define WOL_CFG_MAGIC 0x00000004 343 #define WOL_CFG_MAGIC_ENB 0x00000008 344 #define WOL_CFG_LINK_CHG 0x00000010 345 #define WOL_CFG_LINK_CHG_ENB 0x00000020 346 #define WOL_CFG_PATTERN_DET 0x00000100 347 #define WOL_CFG_MAGIC_DET 0x00000200 348 #define WOL_CFG_LINK_CHG_DET 0x00000400 349 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 350 #define WOL_CFG_PATTERN0 0x00010000 351 #define WOL_CFG_PATTERN1 0x00020000 352 #define WOL_CFG_PATTERN2 0x00040000 353 #define WOL_CFG_PATTERN3 0x00080000 354 #define WOL_CFG_PATTERN4 0x00100000 355 #define WOL_CFG_PATTERN5 0x00200000 356 #define WOL_CFG_PATTERN6 0x00400000 357 358 /* WOL pattern length. */ 359 #define ALC_PATTERN_CFG0 0x14A4 360 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 361 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 362 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 363 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 364 365 #define ALC_PATTERN_CFG1 0x14A8 366 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 367 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 368 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 369 370 /* RSS */ 371 #define ALC_RSS_KEY0 0x14B0 372 373 #define ALC_RSS_KEY1 0x14B4 374 375 #define ALC_RSS_KEY2 0x14B8 376 377 #define ALC_RSS_KEY3 0x14BC 378 379 #define ALC_RSS_KEY4 0x14C0 380 381 #define ALC_RSS_KEY5 0x14C4 382 383 #define ALC_RSS_KEY6 0x14C8 384 385 #define ALC_RSS_KEY7 0x14CC 386 387 #define ALC_RSS_KEY8 0x14D0 388 389 #define ALC_RSS_KEY9 0x14D4 390 391 #define ALC_RSS_IDT_TABLE0 0x14E0 392 393 #define ALC_RSS_IDT_TABLE1 0x14E4 394 395 #define ALC_RSS_IDT_TABLE2 0x14E8 396 397 #define ALC_RSS_IDT_TABLE3 0x14EC 398 399 #define ALC_RSS_IDT_TABLE4 0x14F0 400 401 #define ALC_RSS_IDT_TABLE5 0x14F4 402 403 #define ALC_RSS_IDT_TABLE6 0x14F8 404 405 #define ALC_RSS_IDT_TABLE7 0x14FC 406 407 #define ALC_SRAM_RD0_ADDR 0x1500 408 409 #define ALC_SRAM_RD1_ADDR 0x1504 410 411 #define ALC_SRAM_RD2_ADDR 0x1508 412 413 #define ALC_SRAM_RD3_ADDR 0x150C 414 415 #define RD_HEAD_ADDR_MASK 0x000003FF 416 #define RD_TAIL_ADDR_MASK 0x03FF0000 417 #define RD_HEAD_ADDR_SHIFT 0 418 #define RD_TAIL_ADDR_SHIFT 16 419 420 #define ALC_RD_NIC_LEN0 0x1510 /* 8 bytes unit */ 421 #define RD_NIC_LEN_MASK 0x000003FF 422 423 #define ALC_RD_NIC_LEN1 0x1514 424 425 #define ALC_SRAM_TD_ADDR 0x1518 426 #define TD_HEAD_ADDR_MASK 0x000003FF 427 #define TD_TAIL_ADDR_MASK 0x03FF0000 428 #define TD_HEAD_ADDR_SHIFT 0 429 #define TD_TAIL_ADDR_SHIFT 16 430 431 #define ALC_SRAM_TD_LEN 0x151C /* 8 bytes unit */ 432 #define SRAM_TD_LEN_MASK 0x000003FF 433 434 #define ALC_SRAM_RX_FIFO_ADDR 0x1520 435 436 #define ALC_SRAM_RX_FIFO_LEN 0x1524 437 438 #define ALC_SRAM_TX_FIFO_ADDR 0x1528 439 440 #define ALC_SRAM_TX_FIFO_LEN 0x152C 441 442 #define ALC_SRAM_TCPH_ADDR 0x1530 443 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 444 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 445 #define SRAM_TCPH_ADDR_SHIFT 0 446 #define SRAM_PKTH_ADDR_SHIFT 16 447 448 #define ALC_DMA_BLOCK 0x1534 449 #define DMA_BLOCK_LOAD 0x00000001 450 451 #define ALC_RX_BASE_ADDR_HI 0x1540 452 453 #define ALC_TX_BASE_ADDR_HI 0x1544 454 455 #define ALC_SMB_BASE_ADDR_HI 0x1548 456 457 #define ALC_SMB_BASE_ADDR_LO 0x154C 458 459 #define ALC_RD0_HEAD_ADDR_LO 0x1550 460 461 #define ALC_RD1_HEAD_ADDR_LO 0x1554 462 463 #define ALC_RD2_HEAD_ADDR_LO 0x1558 464 465 #define ALC_RD3_HEAD_ADDR_LO 0x155C 466 467 #define ALC_RD_RING_CNT 0x1560 468 #define RD_RING_CNT_MASK 0x00000FFF 469 #define RD_RING_CNT_SHIFT 0 470 471 #define ALC_RX_BUF_SIZE 0x1564 472 #define RX_BUF_SIZE_MASK 0x0000FFFF 473 /* 474 * If larger buffer size than 1536 is specified the controller 475 * will be locked up. This is hardware limitation. 476 */ 477 #define RX_BUF_SIZE_MAX 1536 478 479 #define ALC_RRD0_HEAD_ADDR_LO 0x1568 480 481 #define ALC_RRD1_HEAD_ADDR_LO 0x156C 482 483 #define ALC_RRD2_HEAD_ADDR_LO 0x1570 484 485 #define ALC_RRD3_HEAD_ADDR_LO 0x1574 486 487 #define ALC_RRD_RING_CNT 0x1578 488 #define RRD_RING_CNT_MASK 0x00000FFF 489 #define RRD_RING_CNT_SHIFT 0 490 491 #define ALC_TDH_HEAD_ADDR_LO 0x157C 492 493 #define ALC_TDL_HEAD_ADDR_LO 0x1580 494 495 #define ALC_TD_RING_CNT 0x1584 496 #define TD_RING_CNT_MASK 0x0000FFFF 497 #define TD_RING_CNT_SHIFT 0 498 499 #define ALC_CMB_BASE_ADDR_LO 0x1588 500 501 #define ALC_TXQ_CFG 0x1590 502 #define TXQ_CFG_TD_BURST_MASK 0x0000000F 503 #define TXQ_CFG_IP_OPTION_ENB 0x00000010 504 #define TXQ_CFG_ENB 0x00000020 505 #define TXQ_CFG_ENHANCED_MODE 0x00000040 506 #define TXQ_CFG_8023_ENB 0x00000080 507 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 508 #define TXQ_CFG_TD_BURST_SHIFT 0 509 #define TXQ_CFG_TD_BURST_DEFAULT 5 510 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 511 512 #define ALC_TSO_OFFLOAD_THRESH 0x1594 /* 8 bytes unit */ 513 #define TSO_OFFLOAD_THRESH_MASK 0x000007FF 514 #define TSO_OFFLOAD_THRESH_SHIFT 0 515 #define TSO_OFFLOAD_THRESH_UNIT 8 516 #define TSO_OFFLOAD_THRESH_UNIT_SHIFT 3 517 518 #define ALC_TXF_WATER_MARK 0x1598 /* 8 bytes unit */ 519 #define TXF_WATER_MARK_HI_MASK 0x00000FFF 520 #define TXF_WATER_MARK_LO_MASK 0x0FFF0000 521 #define TXF_WATER_MARK_BURST_ENB 0x80000000 522 #define TXF_WATER_MARK_LO_SHIFT 0 523 #define TXF_WATER_MARK_HI_SHIFT 16 524 525 #define ALC_THROUGHPUT_MON 0x159C 526 #define THROUGHPUT_MON_RATE_MASK 0x00000003 527 #define THROUGHPUT_MON_ENB 0x00000080 528 #define THROUGHPUT_MON_RATE_SHIFT 0 529 530 #define ALC_RXQ_CFG 0x15A0 531 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_MASK 0x00000003 532 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_NONE 0x00000000 533 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M 0x00000001 534 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_10M 0x00000002 535 #define RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M 0x00000003 536 #define RXQ_CFG_QUEUE1_ENB 0x00000010 537 #define RXQ_CFG_QUEUE2_ENB 0x00000020 538 #define RXQ_CFG_QUEUE3_ENB 0x00000040 539 #define RXQ_CFG_IPV6_CSUM_ENB 0x00000080 540 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 541 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 542 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 543 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 544 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 545 #define RXQ_CFG_RD_BURST_MASK 0x03F00000 546 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 547 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 548 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 549 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 550 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 551 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 552 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 553 #define RXQ_CFG_QUEUE0_ENB 0x80000000 554 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 555 #define RXQ_CFG_RD_BURST_DEFAULT 8 556 #define RXQ_CFG_RD_BURST_SHIFT 20 557 #define RXQ_CFG_ENB \ 558 (RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | \ 559 RXQ_CFG_QUEUE2_ENB | RXQ_CFG_QUEUE3_ENB) 560 561 #define ALC_RX_RD_FREE_THRESH 0x15A4 /* 8 bytes unit. */ 562 #define RX_RD_FREE_THRESH_HI_MASK 0x0000003F 563 #define RX_RD_FREE_THRESH_LO_MASK 0x00000FC0 564 #define RX_RD_FREE_THRESH_HI_SHIFT 0 565 #define RX_RD_FREE_THRESH_LO_SHIFT 6 566 #define RX_RD_FREE_THRESH_HI_DEFAULT 16 567 #define RX_RD_FREE_THRESH_LO_DEFAULT 8 568 569 #define ALC_RX_FIFO_PAUSE_THRESH 0x15A8 570 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 571 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 572 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 573 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 574 575 #define ALC_RD_DMA_CFG 0x15AC 576 #define RD_DMA_CFG_THRESH_MASK 0x00000FFF /* 8 bytes unit */ 577 #define RD_DMA_CFG_TIMER_MASK 0xFFFF0000 578 #define RD_DMA_CFG_THRESH_SHIFT 0 579 #define RD_DMA_CFG_TIMER_SHIFT 16 580 #define RD_DMA_CFG_THRESH_DEFAULT 0x100 581 #define RD_DMA_CFG_TIMER_DEFAULT 0 582 #define RD_DMA_CFG_TICK_USECS 8 583 #define ALC_RD_DMA_CFG_USECS(x) ((x) / RD_DMA_CFG_TICK_USECS) 584 585 #define ALC_RSS_HASH_VALUE 0x15B0 586 587 #define ALC_RSS_HASH_FLAG 0x15B4 588 589 #define ALC_RSS_CPU 0x15B8 590 591 #define ALC_DMA_CFG 0x15C0 592 #define DMA_CFG_IN_ORDER 0x00000001 593 #define DMA_CFG_ENH_ORDER 0x00000002 594 #define DMA_CFG_OUT_ORDER 0x00000004 595 #define DMA_CFG_RCB_64 0x00000000 596 #define DMA_CFG_RCB_128 0x00000008 597 #define DMA_CFG_RD_BURST_128 0x00000000 598 #define DMA_CFG_RD_BURST_256 0x00000010 599 #define DMA_CFG_RD_BURST_512 0x00000020 600 #define DMA_CFG_RD_BURST_1024 0x00000030 601 #define DMA_CFG_RD_BURST_2048 0x00000040 602 #define DMA_CFG_RD_BURST_4096 0x00000050 603 #define DMA_CFG_WR_BURST_128 0x00000000 604 #define DMA_CFG_WR_BURST_256 0x00000080 605 #define DMA_CFG_WR_BURST_512 0x00000100 606 #define DMA_CFG_WR_BURST_1024 0x00000180 607 #define DMA_CFG_WR_BURST_2048 0x00000200 608 #define DMA_CFG_WR_BURST_4096 0x00000280 609 #define DMA_CFG_RD_REQ_PRI 0x00000400 610 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 611 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 612 #define DMA_CFG_CMB_ENB 0x00100000 613 #define DMA_CFG_SMB_ENB 0x00200000 614 #define DMA_CFG_CMB_NOW 0x00400000 615 #define DMA_CFG_SMB_DIS 0x01000000 616 #define DMA_CFG_SMB_NOW 0x80000000 617 #define DMA_CFG_RD_BURST_MASK 0x07 618 #define DMA_CFG_RD_BURST_SHIFT 4 619 #define DMA_CFG_WR_BURST_MASK 0x07 620 #define DMA_CFG_WR_BURST_SHIFT 7 621 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 622 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 623 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 624 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 625 626 #define ALC_SMB_STAT_TIMER 0x15C4 627 #define SMB_STAT_TIMER_MASK 0x00FFFFFF 628 #define SMB_STAT_TIMER_SHIFT 0 629 630 #define ALC_CMB_TD_THRESH 0x15C8 631 #define CMB_TD_THRESH_MASK 0x0000FFFF 632 #define CMB_TD_THRESH_SHIFT 0 633 634 #define ALC_CMB_TX_TIMER 0x15CC 635 #define CMB_TX_TIMER_MASK 0x0000FFFF 636 #define CMB_TX_TIMER_SHIFT 0 637 638 #define ALC_MBOX_RD0_PROD_IDX 0x15E0 639 640 #define ALC_MBOX_RD1_PROD_IDX 0x15E4 641 642 #define ALC_MBOX_RD2_PROD_IDX 0x15E8 643 644 #define ALC_MBOX_RD3_PROD_IDX 0x15EC 645 646 #define ALC_MBOX_RD_PROD_MASK 0x0000FFFF 647 #define MBOX_RD_PROD_SHIFT 0 648 649 #define ALC_MBOX_TD_PROD_IDX 0x15F0 650 #define MBOX_TD_PROD_HI_IDX_MASK 0x0000FFFF 651 #define MBOX_TD_PROD_LO_IDX_MASK 0xFFFF0000 652 #define MBOX_TD_PROD_HI_IDX_SHIFT 0 653 #define MBOX_TD_PROD_LO_IDX_SHIFT 16 654 655 #define ALC_MBOX_TD_CONS_IDX 0x15F4 656 #define MBOX_TD_CONS_HI_IDX_MASK 0x0000FFFF 657 #define MBOX_TD_CONS_LO_IDX_MASK 0xFFFF0000 658 #define MBOX_TD_CONS_HI_IDX_SHIFT 0 659 #define MBOX_TD_CONS_LO_IDX_SHIFT 16 660 661 #define ALC_MBOX_RD01_CONS_IDX 0x15F8 662 #define MBOX_RD0_CONS_IDX_MASK 0x0000FFFF 663 #define MBOX_RD1_CONS_IDX_MASK 0xFFFF0000 664 #define MBOX_RD0_CONS_IDX_SHIFT 0 665 #define MBOX_RD1_CONS_IDX_SHIFT 16 666 667 #define ALC_MBOX_RD23_CONS_IDX 0x15FC 668 #define MBOX_RD2_CONS_IDX_MASK 0x0000FFFF 669 #define MBOX_RD3_CONS_IDX_MASK 0xFFFF0000 670 #define MBOX_RD2_CONS_IDX_SHIFT 0 671 #define MBOX_RD3_CONS_IDX_SHIFT 16 672 673 #define ALC_INTR_STATUS 0x1600 674 #define INTR_SMB 0x00000001 675 #define INTR_TIMER 0x00000002 676 #define INTR_MANUAL_TIMER 0x00000004 677 #define INTR_RX_FIFO_OFLOW 0x00000008 678 #define INTR_RD0_UNDERRUN 0x00000010 679 #define INTR_RD1_UNDERRUN 0x00000020 680 #define INTR_RD2_UNDERRUN 0x00000040 681 #define INTR_RD3_UNDERRUN 0x00000080 682 #define INTR_TX_FIFO_UNDERRUN 0x00000100 683 #define INTR_DMA_RD_TO_RST 0x00000200 684 #define INTR_DMA_WR_TO_RST 0x00000400 685 #define INTR_TX_CREDIT 0x00000800 686 #define INTR_GPHY 0x00001000 687 #define INTR_GPHY_LOW_PW 0x00002000 688 #define INTR_TXQ_TO_RST 0x00004000 689 #define INTR_TX_PKT 0x00008000 690 #define INTR_RX_PKT0 0x00010000 691 #define INTR_RX_PKT1 0x00020000 692 #define INTR_RX_PKT2 0x00040000 693 #define INTR_RX_PKT3 0x00080000 694 #define INTR_MAC_RX 0x00100000 695 #define INTR_MAC_TX 0x00200000 696 #define INTR_UNDERRUN 0x00400000 697 #define INTR_FRAME_ERROR 0x00800000 698 #define INTR_FRAME_OK 0x01000000 699 #define INTR_CSUM_ERROR 0x02000000 700 #define INTR_PHY_LINK_DOWN 0x04000000 701 #define INTR_DIS_INT 0x80000000 702 703 /* Interrupt Mask Register */ 704 #define ALC_INTR_MASK 0x1604 705 706 #ifdef notyet 707 #define INTR_RX_PKT \ 708 (INTR_RX_PKT0 | INTR_RX_PKT1 | INTR_RX_PKT2 | \ 709 INTR_RX_PKT3) 710 #define INTR_RD_UNDERRUN \ 711 (INTR_RD0_UNDERRUN | INTR_RD1_UNDERRUN | \ 712 INTR_RD2_UNDERRUN | INTR_RD3_UNDERRUN) 713 #else 714 #define INTR_RX_PKT INTR_RX_PKT0 715 #define INTR_RD_UNDERRUN INTR_RD0_UNDERRUN 716 #endif 717 718 #define ALC_INTRS \ 719 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 720 INTR_TXQ_TO_RST | INTR_RX_PKT | INTR_TX_PKT | \ 721 INTR_RX_FIFO_OFLOW | INTR_RD_UNDERRUN | \ 722 INTR_TX_FIFO_UNDERRUN) 723 724 #define ALC_INTR_RETRIG_TIMER 0x1608 725 #define INTR_RETRIG_TIMER_MASK 0x0000FFFF 726 #define INTR_RETRIG_TIMER_SHIFT 0 727 728 #define ALC_HDS_CFG 0x160C 729 #define HDS_CFG_ENB 0x00000001 730 #define HDS_CFG_BACKFILLSIZE_MASK 0x000FFF00 731 #define HDS_CFG_MAX_HDRSIZE_MASK 0xFFF00000 732 #define HDS_CFG_BACKFILLSIZE_SHIFT 8 733 #define HDS_CFG_MAX_HDRSIZE_SHIFT 20 734 735 /* AR813x/AR815x registers for MAC statistics */ 736 #define ALC_RX_MIB_BASE 0x1700 737 738 #define ALC_TX_MIB_BASE 0x1760 739 740 #define ALC_DEBUG_DATA0 0x1900 741 742 #define ALC_DEBUG_DATA1 0x1904 743 744 #define ALC_MII_DBG_ADDR 0x1D 745 #define ALC_MII_DBG_DATA 0x1E 746 747 #define MII_ANA_CFG0 0x00 748 #define ANA_RESTART_CAL 0x0001 749 #define ANA_MANUL_SWICH_ON_MASK 0x001E 750 #define ANA_MAN_ENABLE 0x0020 751 #define ANA_SEL_HSP 0x0040 752 #define ANA_EN_HB 0x0080 753 #define ANA_EN_HBIAS 0x0100 754 #define ANA_OEN_125M 0x0200 755 #define ANA_EN_LCKDT 0x0400 756 #define ANA_LCKDT_PHY 0x0800 757 #define ANA_AFE_MODE 0x1000 758 #define ANA_VCO_SLOW 0x2000 759 #define ANA_VCO_FAST 0x4000 760 #define ANA_SEL_CLK125M_DSP 0x8000 761 #define ANA_MANUL_SWICH_ON_SHIFT 1 762 763 #define MII_ANA_CFG4 0x04 764 #define ANA_IECHO_ADJ_MASK 0x0F 765 #define ANA_IECHO_ADJ_3_MASK 0x000F 766 #define ANA_IECHO_ADJ_2_MASK 0x00F0 767 #define ANA_IECHO_ADJ_1_MASK 0x0F00 768 #define ANA_IECHO_ADJ_0_MASK 0xF000 769 #define ANA_IECHO_ADJ_3_SHIFT 0 770 #define ANA_IECHO_ADJ_2_SHIFT 4 771 #define ANA_IECHO_ADJ_1_SHIFT 8 772 #define ANA_IECHO_ADJ_0_SHIFT 12 773 774 #define MII_ANA_CFG5 0x05 775 #define ANA_SERDES_CDR_BW_MASK 0x0003 776 #define ANA_MS_PAD_DBG 0x0004 777 #define ANA_SPEEDUP_DBG 0x0008 778 #define ANA_SERDES_TH_LOS_MASK 0x0030 779 #define ANA_SERDES_EN_DEEM 0x0040 780 #define ANA_SERDES_TXELECIDLE 0x0080 781 #define ANA_SERDES_BEACON 0x0100 782 #define ANA_SERDES_HALFTXDR 0x0200 783 #define ANA_SERDES_SEL_HSP 0x0400 784 #define ANA_SERDES_EN_PLL 0x0800 785 #define ANA_SERDES_EN 0x1000 786 #define ANA_SERDES_EN_LCKDT 0x2000 787 #define ANA_SERDES_CDR_BW_SHIFT 0 788 #define ANA_SERDES_TH_LOS_SHIFT 4 789 790 #define MII_ANA_CFG11 0x0B 791 #define ANA_PS_HIB_EN 0x8000 792 793 #define MII_ANA_CFG18 0x12 794 #define ANA_TEST_MODE_10BT_01MASK 0x0003 795 #define ANA_LOOP_SEL_10BT 0x0004 796 #define ANA_RGMII_MODE_SW 0x0008 797 #define ANA_EN_LONGECABLE 0x0010 798 #define ANA_TEST_MODE_10BT_2 0x0020 799 #define ANA_EN_10BT_IDLE 0x0400 800 #define ANA_EN_MASK_TB 0x0800 801 #define ANA_TRIGGER_SEL_TIMER_MASK 0x3000 802 #define ANA_INTERVAL_SEL_TIMER_MASK 0xC000 803 #define ANA_TEST_MODE_10BT_01SHIFT 0 804 #define ANA_TRIGGER_SEL_TIMER_SHIFT 12 805 #define ANA_INTERVAL_SEL_TIMER_SHIFT 14 806 807 #define MII_ANA_CFG41 0x29 808 #define ANA_TOP_PS_EN 0x8000 809 810 #define MII_ANA_CFG54 0x36 811 #define ANA_LONG_CABLE_TH_100_MASK 0x003F 812 #define ANA_DESERVED 0x0040 813 #define ANA_EN_LIT_CH 0x0080 814 #define ANA_SHORT_CABLE_TH_100_MASK 0x3F00 815 #define ANA_BP_BAD_LINK_ACCUM 0x4000 816 #define ANA_BP_SMALL_BW 0x8000 817 #define ANA_LONG_CABLE_TH_100_SHIFT 0 818 #define ANA_SHORT_CABLE_TH_100_SHIFT 8 819 820 /* Statistics counters collected by the MAC. */ 821 struct smb { 822 /* Rx stats. */ 823 uint32_t rx_frames; 824 uint32_t rx_bcast_frames; 825 uint32_t rx_mcast_frames; 826 uint32_t rx_pause_frames; 827 uint32_t rx_control_frames; 828 uint32_t rx_crcerrs; 829 uint32_t rx_lenerrs; 830 uint32_t rx_bytes; 831 uint32_t rx_runts; 832 uint32_t rx_fragments; 833 uint32_t rx_pkts_64; 834 uint32_t rx_pkts_65_127; 835 uint32_t rx_pkts_128_255; 836 uint32_t rx_pkts_256_511; 837 uint32_t rx_pkts_512_1023; 838 uint32_t rx_pkts_1024_1518; 839 uint32_t rx_pkts_1519_max; 840 uint32_t rx_pkts_truncated; 841 uint32_t rx_fifo_oflows; 842 uint32_t rx_rrs_errs; 843 uint32_t rx_alignerrs; 844 uint32_t rx_bcast_bytes; 845 uint32_t rx_mcast_bytes; 846 uint32_t rx_pkts_filtered; 847 /* Tx stats. */ 848 uint32_t tx_frames; 849 uint32_t tx_bcast_frames; 850 uint32_t tx_mcast_frames; 851 uint32_t tx_pause_frames; 852 uint32_t tx_excess_defer; 853 uint32_t tx_control_frames; 854 uint32_t tx_deferred; 855 uint32_t tx_bytes; 856 uint32_t tx_pkts_64; 857 uint32_t tx_pkts_65_127; 858 uint32_t tx_pkts_128_255; 859 uint32_t tx_pkts_256_511; 860 uint32_t tx_pkts_512_1023; 861 uint32_t tx_pkts_1024_1518; 862 uint32_t tx_pkts_1519_max; 863 uint32_t tx_single_colls; 864 uint32_t tx_multi_colls; 865 uint32_t tx_late_colls; 866 uint32_t tx_excess_colls; 867 uint32_t tx_abort; 868 uint32_t tx_underrun; 869 uint32_t tx_desc_underrun; 870 uint32_t tx_lenerrs; 871 uint32_t tx_pkts_truncated; 872 uint32_t tx_bcast_bytes; 873 uint32_t tx_mcast_bytes; 874 uint32_t updated; 875 }; 876 877 /* CMB(Coalesing message block) */ 878 struct cmb { 879 uint32_t cons; 880 }; 881 882 /* Rx free descriptor */ 883 struct rx_desc { 884 uint64_t addr; 885 }; 886 887 /* Rx return descriptor */ 888 struct rx_rdesc { 889 uint32_t rdinfo; 890 #define RRD_CSUM_MASK 0x0000FFFF 891 #define RRD_RD_CNT_MASK 0x000F0000 892 #define RRD_RD_IDX_MASK 0xFFF00000 893 #define RRD_CSUM_SHIFT 0 894 #define RRD_RD_CNT_SHIFT 16 895 #define RRD_RD_IDX_SHIFT 20 896 #define RRD_CSUM(x) \ 897 (((x) & RRD_CSUM_MASK) >> RRD_CSUM_SHIFT) 898 #define RRD_RD_CNT(x) \ 899 (((x) & RRD_RD_CNT_MASK) >> RRD_RD_CNT_SHIFT) 900 #define RRD_RD_IDX(x) \ 901 (((x) & RRD_RD_IDX_MASK) >> RRD_RD_IDX_SHIFT) 902 uint32_t rss; 903 uint32_t vtag; 904 #define RRD_VLAN_MASK 0x0000FFFF 905 #define RRD_HEAD_LEN_MASK 0x00FF0000 906 #define RRD_HDS_MASK 0x03000000 907 #define RRD_HDS_NONE 0x00000000 908 #define RRD_HDS_HEAD 0x01000000 909 #define RRD_HDS_DATA 0x02000000 910 #define RRD_CPU_MASK 0x0C000000 911 #define RRD_HASH_FLAG_MASK 0xF0000000 912 #define RRD_VLAN_SHIFT 0 913 #define RRD_HEAD_LEN_SHIFT 16 914 #define RRD_HDS_SHIFT 24 915 #define RRD_CPU_SHIFT 26 916 #define RRD_HASH_FLAG_SHIFT 28 917 #define RRD_VLAN(x) \ 918 (((x) & RRD_VLAN_MASK) >> RRD_VLAN_SHIFT) 919 #define RRD_HEAD_LEN(x) \ 920 (((x) & RRD_HEAD_LEN_MASK) >> RRD_HEAD_LEN_SHIFT) 921 #define RRD_CPU(x) \ 922 (((x) & RRD_CPU_MASK) >> RRD_CPU_SHIFT) 923 uint32_t status; 924 #define RRD_LEN_MASK 0x00003FFF 925 #define RRD_LEN_SHIFT 0 926 #define RRD_TCP_UDPCSUM_NOK 0x00004000 927 #define RRD_IPCSUM_NOK 0x00008000 928 #define RRD_VLAN_TAG 0x00010000 929 #define RRD_PROTO_MASK 0x000E0000 930 #define RRD_PROTO_IPV4 0x00020000 931 #define RRD_PROTO_IPV6 0x000C0000 932 #define RRD_ERR_SUM 0x00100000 933 #define RRD_ERR_CRC 0x00200000 934 #define RRD_ERR_ALIGN 0x00400000 935 #define RRD_ERR_TRUNC 0x00800000 936 #define RRD_ERR_RUNT 0x01000000 937 #define RRD_ERR_ICMP 0x02000000 938 #define RRD_BCAST 0x04000000 939 #define RRD_MCAST 0x08000000 940 #define RRD_SNAP_LLC 0x10000000 941 #define RRD_ETHER 0x00000000 942 #define RRD_FIFO_FULL 0x20000000 943 #define RRD_ERR_LENGTH 0x40000000 944 #define RRD_VALID 0x80000000 945 #define RRD_BYTES(x) \ 946 (((x) & RRD_LEN_MASK) >> RRD_LEN_SHIFT) 947 #define RRD_IPV4(x) \ 948 (((x) & RRD_PROTO_MASK) == RRD_PROTO_IPV4) 949 }; 950 951 /* Tx descriptor */ 952 struct tx_desc { 953 uint32_t len; 954 #define TD_BUFLEN_MASK 0x00003FFF 955 #define TD_VLAN_MASK 0xFFFF0000 956 #define TD_BUFLEN_SHIFT 0 957 #define TX_BYTES(x) \ 958 (((x) << TD_BUFLEN_SHIFT) & TD_BUFLEN_MASK) 959 #define TD_VLAN_SHIFT 16 960 uint32_t flags; 961 #define TD_L4HDR_OFFSET_MASK 0x000000FF /* byte unit */ 962 #define TD_TCPHDR_OFFSET_MASK 0x000000FF /* byte unit */ 963 #define TD_PLOAD_OFFSET_MASK 0x000000FF /* 2 bytes unit */ 964 #define TD_CUSTOM_CSUM 0x00000100 965 #define TD_IPCSUM 0x00000200 966 #define TD_TCPCSUM 0x00000400 967 #define TD_UDPCSUM 0x00000800 968 #define TD_TSO 0x00001000 969 #define TD_TSO_DESCV1 0x00000000 970 #define TD_TSO_DESCV2 0x00002000 971 #define TD_CON_VLAN_TAG 0x00004000 972 #define TD_INS_VLAN_TAG 0x00008000 973 #define TD_IPV4_DESCV2 0x00010000 974 #define TD_LLC_SNAP 0x00020000 975 #define TD_ETHERNET 0x00000000 976 #define TD_CUSTOM_CSUM_OFFSET_MASK 0x03FC0000 /* 2 bytes unit */ 977 #define TD_CUSTOM_CSUM_EVEN_PAD 0x40000000 978 #define TD_MSS_MASK 0x7FFC0000 979 #define TD_EOP 0x80000000 980 #define TD_L4HDR_OFFSET_SHIFT 0 981 #define TD_TCPHDR_OFFSET_SHIFT 0 982 #define TD_PLOAD_OFFSET_SHIFT 0 983 #define TD_CUSTOM_CSUM_OFFSET_SHIFT 18 984 #define TD_MSS_SHIFT 18 985 uint64_t addr; 986 }; 987 988 #endif /* _IF_ALCREG_H */
Cache object: 4ab889666655be3443a494480c5822e3
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