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sys/dev/netif/ale/if_ale.c
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1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/ale/if_ale.c,v 1.3 2008/12/03 09:01:12 yongari Exp $ 28 */ 29 30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/endian.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/interrupt.h> 37 #include <sys/malloc.h> 38 #include <sys/proc.h> 39 #include <sys/rman.h> 40 #include <sys/serialize.h> 41 #include <sys/socket.h> 42 #include <sys/sockio.h> 43 #include <sys/sysctl.h> 44 45 #include <net/ethernet.h> 46 #include <net/if.h> 47 #include <net/bpf.h> 48 #include <net/if_arp.h> 49 #include <net/if_dl.h> 50 #include <net/if_llc.h> 51 #include <net/if_media.h> 52 #include <net/ifq_var.h> 53 #include <net/vlan/if_vlan_var.h> 54 #include <net/vlan/if_vlan_ether.h> 55 56 #include <netinet/ip.h> 57 58 #include <dev/netif/mii_layer/mii.h> 59 #include <dev/netif/mii_layer/miivar.h> 60 61 #include <bus/pci/pcireg.h> 62 #include <bus/pci/pcivar.h> 63 #include "pcidevs.h" 64 65 #include <dev/netif/ale/if_alereg.h> 66 #include <dev/netif/ale/if_alevar.h> 67 68 /* "device miibus" required. See GENERIC if you get errors here. */ 69 #include "miibus_if.h" 70 71 /* For more information about Tx checksum offload issues see ale_encap(). */ 72 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 73 74 struct ale_dmamap_ctx { 75 int nsegs; 76 bus_dma_segment_t *segs; 77 }; 78 79 static int ale_probe(device_t); 80 static int ale_attach(device_t); 81 static int ale_detach(device_t); 82 static int ale_shutdown(device_t); 83 static int ale_suspend(device_t); 84 static int ale_resume(device_t); 85 86 static int ale_miibus_readreg(device_t, int, int); 87 static int ale_miibus_writereg(device_t, int, int, int); 88 static void ale_miibus_statchg(device_t); 89 90 static void ale_init(void *); 91 static void ale_start(struct ifnet *, struct ifaltq_subque *); 92 static int ale_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 93 static void ale_watchdog(struct ifnet *); 94 static int ale_mediachange(struct ifnet *); 95 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 96 97 static void ale_intr(void *); 98 static int ale_rxeof(struct ale_softc *sc); 99 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 100 uint32_t, uint32_t *); 101 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 102 static void ale_txeof(struct ale_softc *); 103 104 static int ale_dma_alloc(struct ale_softc *); 105 static void ale_dma_free(struct ale_softc *); 106 static int ale_check_boundary(struct ale_softc *); 107 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 108 static void ale_dmamap_buf_cb(void *, bus_dma_segment_t *, int, 109 bus_size_t, int); 110 static int ale_encap(struct ale_softc *, struct mbuf **); 111 static void ale_init_rx_pages(struct ale_softc *); 112 static void ale_init_tx_ring(struct ale_softc *); 113 114 static void ale_stop(struct ale_softc *); 115 static void ale_tick(void *); 116 static void ale_get_macaddr(struct ale_softc *); 117 static void ale_mac_config(struct ale_softc *); 118 static void ale_phy_reset(struct ale_softc *); 119 static void ale_reset(struct ale_softc *); 120 static void ale_rxfilter(struct ale_softc *); 121 static void ale_rxvlan(struct ale_softc *); 122 static void ale_stats_clear(struct ale_softc *); 123 static void ale_stats_update(struct ale_softc *); 124 static void ale_stop_mac(struct ale_softc *); 125 #ifdef notyet 126 static void ale_setlinkspeed(struct ale_softc *); 127 static void ale_setwol(struct ale_softc *); 128 #endif 129 130 static void ale_sysctl_node(struct ale_softc *); 131 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 132 133 /* 134 * Devices supported by this driver. 135 */ 136 static struct ale_dev { 137 uint16_t ale_vendorid; 138 uint16_t ale_deviceid; 139 const char *ale_name; 140 } ale_devs[] = { 141 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 142 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 143 }; 144 145 static device_method_t ale_methods[] = { 146 /* Device interface. */ 147 DEVMETHOD(device_probe, ale_probe), 148 DEVMETHOD(device_attach, ale_attach), 149 DEVMETHOD(device_detach, ale_detach), 150 DEVMETHOD(device_shutdown, ale_shutdown), 151 DEVMETHOD(device_suspend, ale_suspend), 152 DEVMETHOD(device_resume, ale_resume), 153 154 /* Bus interface. */ 155 DEVMETHOD(bus_print_child, bus_generic_print_child), 156 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 157 158 /* MII interface. */ 159 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 160 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 161 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 162 163 { NULL, NULL } 164 }; 165 166 static driver_t ale_driver = { 167 "ale", 168 ale_methods, 169 sizeof(struct ale_softc) 170 }; 171 172 static devclass_t ale_devclass; 173 174 DECLARE_DUMMY_MODULE(if_ale); 175 MODULE_VERSION(if_ale, 1); 176 MODULE_DEPEND(if_ale, miibus, 1, 1, 1); 177 DRIVER_MODULE(if_ale, pci, ale_driver, ale_devclass, NULL, NULL); 178 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL); 179 180 static int 181 ale_miibus_readreg(device_t dev, int phy, int reg) 182 { 183 struct ale_softc *sc; 184 uint32_t v; 185 int i; 186 187 sc = device_get_softc(dev); 188 189 if (phy != sc->ale_phyaddr) 190 return (0); 191 192 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 193 if (reg == MII_100T2CR || reg == MII_100T2SR || 194 reg == MII_EXTSR) 195 return (0); 196 } 197 198 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 199 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 200 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 201 DELAY(5); 202 v = CSR_READ_4(sc, ALE_MDIO); 203 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 204 break; 205 } 206 207 if (i == 0) { 208 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 209 return (0); 210 } 211 212 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 213 } 214 215 static int 216 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 217 { 218 struct ale_softc *sc; 219 uint32_t v; 220 int i; 221 222 sc = device_get_softc(dev); 223 224 if (phy != sc->ale_phyaddr) 225 return (0); 226 227 if (sc->ale_flags & ALE_FLAG_FASTETHER) { 228 if (reg == MII_100T2CR || reg == MII_100T2SR || 229 reg == MII_EXTSR) 230 return (0); 231 } 232 233 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 234 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 235 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 236 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 237 DELAY(5); 238 v = CSR_READ_4(sc, ALE_MDIO); 239 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 240 break; 241 } 242 243 if (i == 0) 244 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 245 246 return (0); 247 } 248 249 static void 250 ale_miibus_statchg(device_t dev) 251 { 252 struct ale_softc *sc = device_get_softc(dev); 253 struct ifnet *ifp = &sc->arpcom.ac_if; 254 struct mii_data *mii; 255 uint32_t reg; 256 257 ASSERT_SERIALIZED(ifp->if_serializer); 258 259 if ((ifp->if_flags & IFF_RUNNING) == 0) 260 return; 261 262 mii = device_get_softc(sc->ale_miibus); 263 264 sc->ale_flags &= ~ALE_FLAG_LINK; 265 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 266 (IFM_ACTIVE | IFM_AVALID)) { 267 switch (IFM_SUBTYPE(mii->mii_media_active)) { 268 case IFM_10_T: 269 case IFM_100_TX: 270 sc->ale_flags |= ALE_FLAG_LINK; 271 break; 272 273 case IFM_1000_T: 274 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 275 sc->ale_flags |= ALE_FLAG_LINK; 276 break; 277 278 default: 279 break; 280 } 281 } 282 283 /* Stop Rx/Tx MACs. */ 284 ale_stop_mac(sc); 285 286 /* Program MACs with resolved speed/duplex/flow-control. */ 287 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 288 ale_mac_config(sc); 289 /* Reenable Tx/Rx MACs. */ 290 reg = CSR_READ_4(sc, ALE_MAC_CFG); 291 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 293 } 294 } 295 296 static void 297 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 298 { 299 struct ale_softc *sc = ifp->if_softc; 300 struct mii_data *mii = device_get_softc(sc->ale_miibus); 301 302 ASSERT_SERIALIZED(ifp->if_serializer); 303 304 mii_pollstat(mii); 305 ifmr->ifm_status = mii->mii_media_status; 306 ifmr->ifm_active = mii->mii_media_active; 307 } 308 309 static int 310 ale_mediachange(struct ifnet *ifp) 311 { 312 struct ale_softc *sc = ifp->if_softc; 313 struct mii_data *mii = device_get_softc(sc->ale_miibus); 314 int error; 315 316 ASSERT_SERIALIZED(ifp->if_serializer); 317 318 if (mii->mii_instance != 0) { 319 struct mii_softc *miisc; 320 321 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 322 mii_phy_reset(miisc); 323 } 324 error = mii_mediachg(mii); 325 326 return (error); 327 } 328 329 static int 330 ale_probe(device_t dev) 331 { 332 struct ale_dev *sp; 333 int i; 334 uint16_t vendor, devid; 335 336 vendor = pci_get_vendor(dev); 337 devid = pci_get_device(dev); 338 sp = ale_devs; 339 for (i = 0; i < NELEM(ale_devs); i++) { 340 if (vendor == sp->ale_vendorid && 341 devid == sp->ale_deviceid) { 342 device_set_desc(dev, sp->ale_name); 343 return (0); 344 } 345 sp++; 346 } 347 348 return (ENXIO); 349 } 350 351 static void 352 ale_get_macaddr(struct ale_softc *sc) 353 { 354 uint32_t ea[2], reg; 355 int i, vpdc; 356 357 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 358 if ((reg & SPI_VPD_ENB) != 0) { 359 reg &= ~SPI_VPD_ENB; 360 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 361 } 362 363 vpdc = pci_get_vpdcap_ptr(sc->ale_dev); 364 if (vpdc) { 365 /* 366 * PCI VPD capability found, let TWSI reload EEPROM. 367 * This will set ethernet address of controller. 368 */ 369 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 370 TWSI_CTRL_SW_LD_START); 371 for (i = 100; i > 0; i--) { 372 DELAY(1000); 373 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 374 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 375 break; 376 } 377 if (i == 0) 378 device_printf(sc->ale_dev, 379 "reloading EEPROM timeout!\n"); 380 } else { 381 if (bootverbose) 382 device_printf(sc->ale_dev, 383 "PCI VPD capability not found!\n"); 384 } 385 386 ea[0] = CSR_READ_4(sc, ALE_PAR0); 387 ea[1] = CSR_READ_4(sc, ALE_PAR1); 388 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 389 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 390 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 391 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 392 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 393 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 394 } 395 396 static void 397 ale_phy_reset(struct ale_softc *sc) 398 { 399 /* Reset magic from Linux. */ 400 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 401 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 402 GPHY_CTRL_PHY_PLL_ON); 403 DELAY(1000); 404 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 405 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 406 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 407 DELAY(1000); 408 409 #define ATPHY_DBG_ADDR 0x1D 410 #define ATPHY_DBG_DATA 0x1E 411 412 /* Enable hibernation mode. */ 413 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 414 ATPHY_DBG_ADDR, 0x0B); 415 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 416 ATPHY_DBG_DATA, 0xBC00); 417 /* Set Class A/B for all modes. */ 418 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 419 ATPHY_DBG_ADDR, 0x00); 420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 421 ATPHY_DBG_DATA, 0x02EF); 422 /* Enable 10BT power saving. */ 423 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 424 ATPHY_DBG_ADDR, 0x12); 425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 426 ATPHY_DBG_DATA, 0x4C04); 427 /* Adjust 1000T power. */ 428 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 429 ATPHY_DBG_ADDR, 0x04); 430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 431 ATPHY_DBG_ADDR, 0x8BBB); 432 /* 10BT center tap voltage. */ 433 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 434 ATPHY_DBG_ADDR, 0x05); 435 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 436 ATPHY_DBG_ADDR, 0x2C46); 437 438 #undef ATPHY_DBG_ADDR 439 #undef ATPHY_DBG_DATA 440 DELAY(1000); 441 } 442 443 static int 444 ale_attach(device_t dev) 445 { 446 struct ale_softc *sc = device_get_softc(dev); 447 struct ifnet *ifp = &sc->arpcom.ac_if; 448 int error = 0; 449 uint32_t rxf_len, txf_len; 450 uint8_t pcie_ptr; 451 452 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 453 sc->ale_dev = dev; 454 455 callout_init(&sc->ale_tick_ch); 456 457 #ifndef BURN_BRIDGES 458 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 459 uint32_t irq, mem; 460 461 irq = pci_read_config(dev, PCIR_INTLINE, 4); 462 mem = pci_read_config(dev, ALE_PCIR_BAR, 4); 463 464 device_printf(dev, "chip is in D%d power mode " 465 "-- setting to D0\n", pci_get_powerstate(dev)); 466 467 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 468 469 pci_write_config(dev, PCIR_INTLINE, irq, 4); 470 pci_write_config(dev, ALE_PCIR_BAR, mem, 4); 471 } 472 #endif /* !BURN_BRIDGE */ 473 474 /* Enable bus mastering */ 475 pci_enable_busmaster(dev); 476 477 /* 478 * Allocate memory mapped IO 479 */ 480 sc->ale_mem_rid = ALE_PCIR_BAR; 481 sc->ale_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 482 &sc->ale_mem_rid, RF_ACTIVE); 483 if (sc->ale_mem_res == NULL) { 484 device_printf(dev, "can't allocate IO memory\n"); 485 return ENXIO; 486 } 487 sc->ale_mem_bt = rman_get_bustag(sc->ale_mem_res); 488 sc->ale_mem_bh = rman_get_bushandle(sc->ale_mem_res); 489 490 /* 491 * Allocate IRQ 492 */ 493 sc->ale_irq_rid = 0; 494 sc->ale_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 495 &sc->ale_irq_rid, 496 RF_SHAREABLE | RF_ACTIVE); 497 if (sc->ale_irq_res == NULL) { 498 device_printf(dev, "can't allocate irq\n"); 499 error = ENXIO; 500 goto fail; 501 } 502 503 /* Set PHY address. */ 504 sc->ale_phyaddr = ALE_PHY_ADDR; 505 506 /* Reset PHY. */ 507 ale_phy_reset(sc); 508 509 /* Reset the ethernet controller. */ 510 ale_reset(sc); 511 512 /* Get PCI and chip id/revision. */ 513 sc->ale_rev = pci_get_revid(dev); 514 if (sc->ale_rev >= 0xF0) { 515 /* L2E Rev. B. AR8114 */ 516 sc->ale_flags |= ALE_FLAG_FASTETHER; 517 } else { 518 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 519 /* L1E AR8121 */ 520 sc->ale_flags |= ALE_FLAG_JUMBO; 521 } else { 522 /* L2E Rev. A. AR8113 */ 523 sc->ale_flags |= ALE_FLAG_FASTETHER; 524 } 525 } 526 527 /* 528 * All known controllers seems to require 4 bytes alignment 529 * of Tx buffers to make Tx checksum offload with custom 530 * checksum generation method work. 531 */ 532 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 533 534 /* 535 * All known controllers seems to have issues on Rx checksum 536 * offload for fragmented IP datagrams. 537 */ 538 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 539 540 /* 541 * Don't use Tx CMB. It is known to cause RRS update failure 542 * under certain circumstances. Typical phenomenon of the 543 * issue would be unexpected sequence number encountered in 544 * Rx handler. 545 */ 546 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 547 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 548 MASTER_CHIP_REV_SHIFT; 549 if (bootverbose) { 550 device_printf(dev, "PCI device revision : 0x%04x\n", 551 sc->ale_rev); 552 device_printf(dev, "Chip id/revision : 0x%04x\n", 553 sc->ale_chip_rev); 554 } 555 556 /* 557 * Uninitialized hardware returns an invalid chip id/revision 558 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 559 */ 560 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 561 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 562 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 563 rxf_len == 0xFFFFFFF) { 564 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 565 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 566 txf_len, rxf_len); 567 error = ENXIO; 568 goto fail; 569 } 570 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 571 572 /* Get DMA parameters from PCIe device control register. */ 573 pcie_ptr = pci_get_pciecap_ptr(dev); 574 if (pcie_ptr) { 575 uint16_t devctl; 576 577 sc->ale_flags |= ALE_FLAG_PCIE; 578 devctl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2); 579 /* Max read request size. */ 580 sc->ale_dma_rd_burst = ((devctl >> 12) & 0x07) << 581 DMA_CFG_RD_BURST_SHIFT; 582 /* Max payload size. */ 583 sc->ale_dma_wr_burst = ((devctl >> 5) & 0x07) << 584 DMA_CFG_WR_BURST_SHIFT; 585 if (bootverbose) { 586 device_printf(dev, "Read request size : %d bytes.\n", 587 128 << ((devctl >> 12) & 0x07)); 588 device_printf(dev, "TLP payload size : %d bytes.\n", 589 128 << ((devctl >> 5) & 0x07)); 590 } 591 } else { 592 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 593 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 594 } 595 596 /* Create device sysctl node. */ 597 ale_sysctl_node(sc); 598 599 if ((error = ale_dma_alloc(sc) != 0)) 600 goto fail; 601 602 /* Load station address. */ 603 ale_get_macaddr(sc); 604 605 ifp->if_softc = sc; 606 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 607 ifp->if_ioctl = ale_ioctl; 608 ifp->if_start = ale_start; 609 ifp->if_init = ale_init; 610 ifp->if_watchdog = ale_watchdog; 611 ifq_set_maxlen(&ifp->if_snd, ALE_TX_RING_CNT - 1); 612 ifq_set_ready(&ifp->if_snd); 613 614 ifp->if_capabilities = IFCAP_RXCSUM | 615 IFCAP_VLAN_MTU | 616 IFCAP_VLAN_HWTAGGING; 617 #ifdef notyet 618 ifp->if_capabilities |= IFCAP_TXCSUM; 619 ifp->if_hwassist = ALE_CSUM_FEATURES; 620 #endif 621 ifp->if_capenable = ifp->if_capabilities; 622 623 /* Set up MII bus. */ 624 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange, 625 ale_mediastatus)) != 0) { 626 device_printf(dev, "no PHY found!\n"); 627 goto fail; 628 } 629 630 ether_ifattach(ifp, sc->ale_eaddr, NULL); 631 632 /* Tell the upper layer(s) we support long frames. */ 633 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 634 635 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->ale_irq_res)); 636 637 error = bus_setup_intr(dev, sc->ale_irq_res, INTR_MPSAFE, ale_intr, sc, 638 &sc->ale_irq_handle, ifp->if_serializer); 639 if (error) { 640 device_printf(dev, "could not set up interrupt handler.\n"); 641 ether_ifdetach(ifp); 642 goto fail; 643 } 644 645 return 0; 646 fail: 647 ale_detach(dev); 648 return (error); 649 } 650 651 static int 652 ale_detach(device_t dev) 653 { 654 struct ale_softc *sc = device_get_softc(dev); 655 656 if (device_is_attached(dev)) { 657 struct ifnet *ifp = &sc->arpcom.ac_if; 658 659 lwkt_serialize_enter(ifp->if_serializer); 660 sc->ale_flags |= ALE_FLAG_DETACH; 661 ale_stop(sc); 662 bus_teardown_intr(dev, sc->ale_irq_res, sc->ale_irq_handle); 663 lwkt_serialize_exit(ifp->if_serializer); 664 665 ether_ifdetach(ifp); 666 } 667 668 if (sc->ale_sysctl_tree != NULL) 669 sysctl_ctx_free(&sc->ale_sysctl_ctx); 670 671 if (sc->ale_miibus != NULL) 672 device_delete_child(dev, sc->ale_miibus); 673 bus_generic_detach(dev); 674 675 if (sc->ale_irq_res != NULL) { 676 bus_release_resource(dev, SYS_RES_IRQ, sc->ale_irq_rid, 677 sc->ale_irq_res); 678 } 679 if (sc->ale_mem_res != NULL) { 680 bus_release_resource(dev, SYS_RES_MEMORY, sc->ale_mem_rid, 681 sc->ale_mem_res); 682 } 683 684 ale_dma_free(sc); 685 686 return (0); 687 } 688 689 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 690 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 691 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 692 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 693 694 static void 695 ale_sysctl_node(struct ale_softc *sc) 696 { 697 struct sysctl_ctx_list *ctx; 698 struct sysctl_oid_list *child, *parent; 699 struct sysctl_oid *tree; 700 struct ale_hw_stats *stats; 701 int error; 702 703 sysctl_ctx_init(&sc->ale_sysctl_ctx); 704 sc->ale_sysctl_tree = SYSCTL_ADD_NODE(&sc->ale_sysctl_ctx, 705 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO, 706 device_get_nameunit(sc->ale_dev), 707 CTLFLAG_RD, 0, ""); 708 if (sc->ale_sysctl_tree == NULL) { 709 device_printf(sc->ale_dev, "can't add sysctl node\n"); 710 return; 711 } 712 713 stats = &sc->ale_stats; 714 ctx = &sc->ale_sysctl_ctx; 715 child = SYSCTL_CHILDREN(sc->ale_sysctl_tree); 716 717 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 718 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 719 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 720 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 721 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 722 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 723 724 /* 725 * Pull in device tunables. 726 */ 727 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 728 error = resource_int_value(device_get_name(sc->ale_dev), 729 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 730 if (error == 0) { 731 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 732 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 733 device_printf(sc->ale_dev, "int_rx_mod value out of " 734 "range; using default: %d\n", 735 ALE_IM_RX_TIMER_DEFAULT); 736 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 737 } 738 } 739 740 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 741 error = resource_int_value(device_get_name(sc->ale_dev), 742 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 743 if (error == 0) { 744 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 745 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 746 device_printf(sc->ale_dev, "int_tx_mod value out of " 747 "range; using default: %d\n", 748 ALE_IM_TX_TIMER_DEFAULT); 749 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 750 } 751 } 752 753 /* Misc statistics. */ 754 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 755 &stats->reset_brk_seq, 756 "Controller resets due to broken Rx sequnce number"); 757 758 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 759 NULL, "ATE statistics"); 760 parent = SYSCTL_CHILDREN(tree); 761 762 /* Rx statistics. */ 763 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 764 NULL, "Rx MAC statistics"); 765 child = SYSCTL_CHILDREN(tree); 766 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 767 &stats->rx_frames, "Good frames"); 768 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 769 &stats->rx_bcast_frames, "Good broadcast frames"); 770 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 771 &stats->rx_mcast_frames, "Good multicast frames"); 772 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 773 &stats->rx_pause_frames, "Pause control frames"); 774 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 775 &stats->rx_control_frames, "Control frames"); 776 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 777 &stats->rx_crcerrs, "CRC errors"); 778 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 779 &stats->rx_lenerrs, "Frames with length mismatched"); 780 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 781 &stats->rx_bytes, "Good octets"); 782 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 783 &stats->rx_bcast_bytes, "Good broadcast octets"); 784 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 785 &stats->rx_mcast_bytes, "Good multicast octets"); 786 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 787 &stats->rx_runts, "Too short frames"); 788 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 789 &stats->rx_fragments, "Fragmented frames"); 790 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 791 &stats->rx_pkts_64, "64 bytes frames"); 792 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 793 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 794 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 795 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 796 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 797 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 798 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 799 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 800 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 801 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 802 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 803 &stats->rx_pkts_1519_max, "1519 to max frames"); 804 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 805 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 806 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 807 &stats->rx_fifo_oflows, "FIFO overflows"); 808 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 809 &stats->rx_rrs_errs, "Return status write-back errors"); 810 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 811 &stats->rx_alignerrs, "Alignment errors"); 812 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 813 &stats->rx_pkts_filtered, 814 "Frames dropped due to address filtering"); 815 816 /* Tx statistics. */ 817 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 818 NULL, "Tx MAC statistics"); 819 child = SYSCTL_CHILDREN(tree); 820 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 821 &stats->tx_frames, "Good frames"); 822 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 823 &stats->tx_bcast_frames, "Good broadcast frames"); 824 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 825 &stats->tx_mcast_frames, "Good multicast frames"); 826 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 827 &stats->tx_pause_frames, "Pause control frames"); 828 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 829 &stats->tx_control_frames, "Control frames"); 830 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 831 &stats->tx_excess_defer, "Frames with excessive derferrals"); 832 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 833 &stats->tx_excess_defer, "Frames with derferrals"); 834 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 835 &stats->tx_bytes, "Good octets"); 836 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 837 &stats->tx_bcast_bytes, "Good broadcast octets"); 838 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 839 &stats->tx_mcast_bytes, "Good multicast octets"); 840 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 841 &stats->tx_pkts_64, "64 bytes frames"); 842 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 843 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 844 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 845 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 846 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 847 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 848 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 849 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 850 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 851 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 852 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 853 &stats->tx_pkts_1519_max, "1519 to max frames"); 854 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 855 &stats->tx_single_colls, "Single collisions"); 856 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 857 &stats->tx_multi_colls, "Multiple collisions"); 858 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 859 &stats->tx_late_colls, "Late collisions"); 860 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 861 &stats->tx_excess_colls, "Excessive collisions"); 862 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 863 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 864 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 865 &stats->tx_underrun, "FIFO underruns"); 866 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 867 &stats->tx_desc_underrun, "Descriptor write-back errors"); 868 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 869 &stats->tx_lenerrs, "Frames with length mismatched"); 870 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 871 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 872 } 873 874 #undef ALE_SYSCTL_STAT_ADD32 875 #undef ALE_SYSCTL_STAT_ADD64 876 877 struct ale_dmamap_arg { 878 bus_addr_t ale_busaddr; 879 }; 880 881 static void 882 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 883 { 884 struct ale_dmamap_arg *ctx; 885 886 if (error != 0) 887 return; 888 889 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 890 891 ctx = (struct ale_dmamap_arg *)arg; 892 ctx->ale_busaddr = segs[0].ds_addr; 893 } 894 895 /* 896 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 897 * which specifies high address region of DMA blocks. Therefore these 898 * blocks should have the same high address of given 4GB address 899 * space(i.e. crossing 4GB boundary is not allowed). 900 */ 901 static int 902 ale_check_boundary(struct ale_softc *sc) 903 { 904 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 905 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 906 907 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 908 sc->ale_pagesize; 909 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 910 sc->ale_pagesize; 911 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 912 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 913 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 914 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 915 916 if ((ALE_ADDR_HI(tx_ring_end) != 917 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 918 (ALE_ADDR_HI(rx_page_end[0]) != 919 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 920 (ALE_ADDR_HI(rx_page_end[1]) != 921 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 922 (ALE_ADDR_HI(tx_cmb_end) != 923 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 924 (ALE_ADDR_HI(rx_cmb_end[0]) != 925 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 926 (ALE_ADDR_HI(rx_cmb_end[1]) != 927 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 928 return (EFBIG); 929 930 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 931 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 932 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 933 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 934 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 935 return (EFBIG); 936 937 return (0); 938 } 939 940 static int 941 ale_dma_alloc(struct ale_softc *sc) 942 { 943 struct ale_txdesc *txd; 944 bus_addr_t lowaddr; 945 struct ale_dmamap_arg ctx; 946 int error, guard_size, i; 947 948 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 949 guard_size = ALE_JUMBO_FRAMELEN; 950 else 951 guard_size = ALE_MAX_FRAMELEN; 952 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 953 ALE_RX_PAGE_ALIGN); 954 lowaddr = BUS_SPACE_MAXADDR; 955 again: 956 /* Create parent DMA tag. */ 957 error = bus_dma_tag_create( 958 NULL, /* parent */ 959 1, 0, /* alignment, boundary */ 960 lowaddr, /* lowaddr */ 961 BUS_SPACE_MAXADDR, /* highaddr */ 962 NULL, NULL, /* filter, filterarg */ 963 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 964 0, /* nsegments */ 965 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 966 0, /* flags */ 967 &sc->ale_cdata.ale_parent_tag); 968 if (error != 0) { 969 device_printf(sc->ale_dev, 970 "could not create parent DMA tag.\n"); 971 goto fail; 972 } 973 974 /* Create DMA tag for Tx descriptor ring. */ 975 error = bus_dma_tag_create( 976 sc->ale_cdata.ale_parent_tag, /* parent */ 977 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 978 BUS_SPACE_MAXADDR, /* lowaddr */ 979 BUS_SPACE_MAXADDR, /* highaddr */ 980 NULL, NULL, /* filter, filterarg */ 981 ALE_TX_RING_SZ, /* maxsize */ 982 1, /* nsegments */ 983 ALE_TX_RING_SZ, /* maxsegsize */ 984 0, /* flags */ 985 &sc->ale_cdata.ale_tx_ring_tag); 986 if (error != 0) { 987 device_printf(sc->ale_dev, 988 "could not create Tx ring DMA tag.\n"); 989 goto fail; 990 } 991 992 /* Create DMA tag for Rx pages. */ 993 for (i = 0; i < ALE_RX_PAGES; i++) { 994 error = bus_dma_tag_create( 995 sc->ale_cdata.ale_parent_tag, /* parent */ 996 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 997 BUS_SPACE_MAXADDR, /* lowaddr */ 998 BUS_SPACE_MAXADDR, /* highaddr */ 999 NULL, NULL, /* filter, filterarg */ 1000 sc->ale_pagesize, /* maxsize */ 1001 1, /* nsegments */ 1002 sc->ale_pagesize, /* maxsegsize */ 1003 0, /* flags */ 1004 &sc->ale_cdata.ale_rx_page[i].page_tag); 1005 if (error != 0) { 1006 device_printf(sc->ale_dev, 1007 "could not create Rx page %d DMA tag.\n", i); 1008 goto fail; 1009 } 1010 } 1011 1012 /* Create DMA tag for Tx coalescing message block. */ 1013 error = bus_dma_tag_create( 1014 sc->ale_cdata.ale_parent_tag, /* parent */ 1015 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1016 BUS_SPACE_MAXADDR, /* lowaddr */ 1017 BUS_SPACE_MAXADDR, /* highaddr */ 1018 NULL, NULL, /* filter, filterarg */ 1019 ALE_TX_CMB_SZ, /* maxsize */ 1020 1, /* nsegments */ 1021 ALE_TX_CMB_SZ, /* maxsegsize */ 1022 0, /* flags */ 1023 &sc->ale_cdata.ale_tx_cmb_tag); 1024 if (error != 0) { 1025 device_printf(sc->ale_dev, 1026 "could not create Tx CMB DMA tag.\n"); 1027 goto fail; 1028 } 1029 1030 /* Create DMA tag for Rx coalescing message block. */ 1031 for (i = 0; i < ALE_RX_PAGES; i++) { 1032 error = bus_dma_tag_create( 1033 sc->ale_cdata.ale_parent_tag, /* parent */ 1034 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1035 BUS_SPACE_MAXADDR, /* lowaddr */ 1036 BUS_SPACE_MAXADDR, /* highaddr */ 1037 NULL, NULL, /* filter, filterarg */ 1038 ALE_RX_CMB_SZ, /* maxsize */ 1039 1, /* nsegments */ 1040 ALE_RX_CMB_SZ, /* maxsegsize */ 1041 0, /* flags */ 1042 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1043 if (error != 0) { 1044 device_printf(sc->ale_dev, 1045 "could not create Rx page %d CMB DMA tag.\n", i); 1046 goto fail; 1047 } 1048 } 1049 1050 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1051 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1052 (void **)&sc->ale_cdata.ale_tx_ring, 1053 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1054 &sc->ale_cdata.ale_tx_ring_map); 1055 if (error != 0) { 1056 device_printf(sc->ale_dev, 1057 "could not allocate DMA'able memory for Tx ring.\n"); 1058 goto fail; 1059 } 1060 ctx.ale_busaddr = 0; 1061 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1062 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1063 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1064 if (error != 0 || ctx.ale_busaddr == 0) { 1065 device_printf(sc->ale_dev, 1066 "could not load DMA'able memory for Tx ring.\n"); 1067 goto fail; 1068 } 1069 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1070 1071 /* Rx pages. */ 1072 for (i = 0; i < ALE_RX_PAGES; i++) { 1073 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1074 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1075 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1076 &sc->ale_cdata.ale_rx_page[i].page_map); 1077 if (error != 0) { 1078 device_printf(sc->ale_dev, 1079 "could not allocate DMA'able memory for " 1080 "Rx page %d.\n", i); 1081 goto fail; 1082 } 1083 ctx.ale_busaddr = 0; 1084 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1085 sc->ale_cdata.ale_rx_page[i].page_map, 1086 sc->ale_cdata.ale_rx_page[i].page_addr, 1087 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1088 if (error != 0 || ctx.ale_busaddr == 0) { 1089 device_printf(sc->ale_dev, 1090 "could not load DMA'able memory for " 1091 "Rx page %d.\n", i); 1092 goto fail; 1093 } 1094 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1095 } 1096 1097 /* Tx CMB. */ 1098 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1099 (void **)&sc->ale_cdata.ale_tx_cmb, 1100 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1101 &sc->ale_cdata.ale_tx_cmb_map); 1102 if (error != 0) { 1103 device_printf(sc->ale_dev, 1104 "could not allocate DMA'able memory for Tx CMB.\n"); 1105 goto fail; 1106 } 1107 ctx.ale_busaddr = 0; 1108 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1109 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1110 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1111 if (error != 0 || ctx.ale_busaddr == 0) { 1112 device_printf(sc->ale_dev, 1113 "could not load DMA'able memory for Tx CMB.\n"); 1114 goto fail; 1115 } 1116 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1117 1118 /* Rx CMB. */ 1119 for (i = 0; i < ALE_RX_PAGES; i++) { 1120 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1121 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1122 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1123 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1124 if (error != 0) { 1125 device_printf(sc->ale_dev, "could not allocate " 1126 "DMA'able memory for Rx page %d CMB.\n", i); 1127 goto fail; 1128 } 1129 ctx.ale_busaddr = 0; 1130 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1131 sc->ale_cdata.ale_rx_page[i].cmb_map, 1132 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1133 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1134 if (error != 0 || ctx.ale_busaddr == 0) { 1135 device_printf(sc->ale_dev, "could not load DMA'able " 1136 "memory for Rx page %d CMB.\n", i); 1137 goto fail; 1138 } 1139 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1140 } 1141 1142 /* 1143 * Tx descriptors/RXF0/CMB DMA blocks share the same 1144 * high address region of 64bit DMA address space. 1145 */ 1146 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1147 (error = ale_check_boundary(sc)) != 0) { 1148 device_printf(sc->ale_dev, "4GB boundary crossed, " 1149 "switching to 32bit DMA addressing mode.\n"); 1150 ale_dma_free(sc); 1151 /* 1152 * Limit max allowable DMA address space to 32bit 1153 * and try again. 1154 */ 1155 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1156 goto again; 1157 } 1158 1159 /* 1160 * Create Tx buffer parent tag. 1161 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1162 * needs separate parent DMA tag as parent DMA address space 1163 * could be restricted to be within 32bit address space by 1164 * 4GB boundary crossing. 1165 */ 1166 error = bus_dma_tag_create( 1167 NULL, /* parent */ 1168 1, 0, /* alignment, boundary */ 1169 BUS_SPACE_MAXADDR, /* lowaddr */ 1170 BUS_SPACE_MAXADDR, /* highaddr */ 1171 NULL, NULL, /* filter, filterarg */ 1172 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1173 0, /* nsegments */ 1174 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1175 0, /* flags */ 1176 &sc->ale_cdata.ale_buffer_tag); 1177 if (error != 0) { 1178 device_printf(sc->ale_dev, 1179 "could not create parent buffer DMA tag.\n"); 1180 goto fail; 1181 } 1182 1183 /* Create DMA tag for Tx buffers. */ 1184 error = bus_dma_tag_create( 1185 sc->ale_cdata.ale_buffer_tag, /* parent */ 1186 1, 0, /* alignment, boundary */ 1187 BUS_SPACE_MAXADDR, /* lowaddr */ 1188 BUS_SPACE_MAXADDR, /* highaddr */ 1189 NULL, NULL, /* filter, filterarg */ 1190 ALE_TSO_MAXSIZE, /* maxsize */ 1191 ALE_MAXTXSEGS, /* nsegments */ 1192 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1193 0, /* flags */ 1194 &sc->ale_cdata.ale_tx_tag); 1195 if (error != 0) { 1196 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1197 goto fail; 1198 } 1199 1200 /* Create DMA maps for Tx buffers. */ 1201 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1202 txd = &sc->ale_cdata.ale_txdesc[i]; 1203 txd->tx_m = NULL; 1204 txd->tx_dmamap = NULL; 1205 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1206 &txd->tx_dmamap); 1207 if (error != 0) { 1208 device_printf(sc->ale_dev, 1209 "could not create Tx dmamap.\n"); 1210 goto fail; 1211 } 1212 } 1213 fail: 1214 return (error); 1215 } 1216 1217 static void 1218 ale_dma_free(struct ale_softc *sc) 1219 { 1220 struct ale_txdesc *txd; 1221 int i; 1222 1223 /* Tx buffers. */ 1224 if (sc->ale_cdata.ale_tx_tag != NULL) { 1225 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1226 txd = &sc->ale_cdata.ale_txdesc[i]; 1227 if (txd->tx_dmamap != NULL) { 1228 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1229 txd->tx_dmamap); 1230 txd->tx_dmamap = NULL; 1231 } 1232 } 1233 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1234 sc->ale_cdata.ale_tx_tag = NULL; 1235 } 1236 /* Tx descriptor ring. */ 1237 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1238 if (sc->ale_cdata.ale_tx_ring_map != NULL) 1239 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1240 sc->ale_cdata.ale_tx_ring_map); 1241 if (sc->ale_cdata.ale_tx_ring_map != NULL && 1242 sc->ale_cdata.ale_tx_ring != NULL) 1243 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1244 sc->ale_cdata.ale_tx_ring, 1245 sc->ale_cdata.ale_tx_ring_map); 1246 sc->ale_cdata.ale_tx_ring = NULL; 1247 sc->ale_cdata.ale_tx_ring_map = NULL; 1248 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1249 sc->ale_cdata.ale_tx_ring_tag = NULL; 1250 } 1251 /* Rx page block. */ 1252 for (i = 0; i < ALE_RX_PAGES; i++) { 1253 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1254 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1255 bus_dmamap_unload( 1256 sc->ale_cdata.ale_rx_page[i].page_tag, 1257 sc->ale_cdata.ale_rx_page[i].page_map); 1258 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1259 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1260 bus_dmamem_free( 1261 sc->ale_cdata.ale_rx_page[i].page_tag, 1262 sc->ale_cdata.ale_rx_page[i].page_addr, 1263 sc->ale_cdata.ale_rx_page[i].page_map); 1264 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1265 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1266 bus_dma_tag_destroy( 1267 sc->ale_cdata.ale_rx_page[i].page_tag); 1268 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1269 } 1270 } 1271 /* Rx CMB. */ 1272 for (i = 0; i < ALE_RX_PAGES; i++) { 1273 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1274 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1275 bus_dmamap_unload( 1276 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1277 sc->ale_cdata.ale_rx_page[i].cmb_map); 1278 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1279 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1280 bus_dmamem_free( 1281 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1282 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1283 sc->ale_cdata.ale_rx_page[i].cmb_map); 1284 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1285 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1286 bus_dma_tag_destroy( 1287 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1288 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1289 } 1290 } 1291 /* Tx CMB. */ 1292 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1293 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1294 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1295 sc->ale_cdata.ale_tx_cmb_map); 1296 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1297 sc->ale_cdata.ale_tx_cmb != NULL) 1298 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1299 sc->ale_cdata.ale_tx_cmb, 1300 sc->ale_cdata.ale_tx_cmb_map); 1301 sc->ale_cdata.ale_tx_cmb = NULL; 1302 sc->ale_cdata.ale_tx_cmb_map = NULL; 1303 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1304 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1305 } 1306 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1307 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1308 sc->ale_cdata.ale_buffer_tag = NULL; 1309 } 1310 if (sc->ale_cdata.ale_parent_tag != NULL) { 1311 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1312 sc->ale_cdata.ale_parent_tag = NULL; 1313 } 1314 } 1315 1316 static int 1317 ale_shutdown(device_t dev) 1318 { 1319 return (ale_suspend(dev)); 1320 } 1321 1322 #ifdef notyet 1323 1324 /* 1325 * Note, this driver resets the link speed to 10/100Mbps by 1326 * restarting auto-negotiation in suspend/shutdown phase but we 1327 * don't know whether that auto-negotiation would succeed or not 1328 * as driver has no control after powering off/suspend operation. 1329 * If the renegotiation fail WOL may not work. Running at 1Gbps 1330 * will draw more power than 375mA at 3.3V which is specified in 1331 * PCI specification and that would result in complete 1332 * shutdowning power to ethernet controller. 1333 * 1334 * TODO 1335 * Save current negotiated media speed/duplex/flow-control to 1336 * softc and restore the same link again after resuming. PHY 1337 * handling such as power down/resetting to 100Mbps may be better 1338 * handled in suspend method in phy driver. 1339 */ 1340 static void 1341 ale_setlinkspeed(struct ale_softc *sc) 1342 { 1343 struct mii_data *mii; 1344 int aneg, i; 1345 1346 mii = device_get_softc(sc->ale_miibus); 1347 mii_pollstat(mii); 1348 aneg = 0; 1349 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1350 (IFM_ACTIVE | IFM_AVALID)) { 1351 switch IFM_SUBTYPE(mii->mii_media_active) { 1352 case IFM_10_T: 1353 case IFM_100_TX: 1354 return; 1355 case IFM_1000_T: 1356 aneg++; 1357 break; 1358 default: 1359 break; 1360 } 1361 } 1362 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1363 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1364 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1365 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1366 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1367 DELAY(1000); 1368 if (aneg != 0) { 1369 /* 1370 * Poll link state until ale(4) get a 10/100Mbps link. 1371 */ 1372 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1373 mii_pollstat(mii); 1374 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1375 == (IFM_ACTIVE | IFM_AVALID)) { 1376 switch (IFM_SUBTYPE( 1377 mii->mii_media_active)) { 1378 case IFM_10_T: 1379 case IFM_100_TX: 1380 ale_mac_config(sc); 1381 return; 1382 default: 1383 break; 1384 } 1385 } 1386 ALE_UNLOCK(sc); 1387 pause("alelnk", hz); 1388 ALE_LOCK(sc); 1389 } 1390 if (i == MII_ANEGTICKS_GIGE) 1391 device_printf(sc->ale_dev, 1392 "establishing a link failed, WOL may not work!"); 1393 } 1394 /* 1395 * No link, force MAC to have 100Mbps, full-duplex link. 1396 * This is the last resort and may/may not work. 1397 */ 1398 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1399 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1400 ale_mac_config(sc); 1401 } 1402 1403 static void 1404 ale_setwol(struct ale_softc *sc) 1405 { 1406 struct ifnet *ifp; 1407 uint32_t reg, pmcs; 1408 uint16_t pmstat; 1409 int pmc; 1410 1411 ALE_LOCK_ASSERT(sc); 1412 1413 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1414 /* Disable WOL. */ 1415 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1416 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1417 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1418 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1419 /* Force PHY power down. */ 1420 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1421 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1422 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1423 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1424 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1425 return; 1426 } 1427 1428 ifp = sc->ale_ifp; 1429 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1430 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1431 ale_setlinkspeed(sc); 1432 } 1433 1434 pmcs = 0; 1435 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1436 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1437 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1438 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1439 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1440 MAC_CFG_BCAST); 1441 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1442 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1443 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1444 reg |= MAC_CFG_RX_ENB; 1445 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1446 1447 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1448 /* WOL disabled, PHY power down. */ 1449 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1450 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1451 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1452 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1453 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1454 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1455 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1456 GPHY_CTRL_PWDOWN_HW); 1457 } 1458 /* Request PME. */ 1459 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1460 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1461 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1462 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1463 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1464 } 1465 1466 #endif /* notyet */ 1467 1468 static int 1469 ale_suspend(device_t dev) 1470 { 1471 struct ale_softc *sc = device_get_softc(dev); 1472 struct ifnet *ifp = &sc->arpcom.ac_if; 1473 1474 lwkt_serialize_enter(ifp->if_serializer); 1475 ale_stop(sc); 1476 #ifdef notyet 1477 ale_setwol(sc); 1478 #endif 1479 lwkt_serialize_exit(ifp->if_serializer); 1480 return (0); 1481 } 1482 1483 static int 1484 ale_resume(device_t dev) 1485 { 1486 struct ale_softc *sc = device_get_softc(dev); 1487 struct ifnet *ifp = &sc->arpcom.ac_if; 1488 uint16_t cmd; 1489 1490 lwkt_serialize_enter(ifp->if_serializer); 1491 1492 /* 1493 * Clear INTx emulation disable for hardwares that 1494 * is set in resume event. From Linux. 1495 */ 1496 cmd = pci_read_config(sc->ale_dev, PCIR_COMMAND, 2); 1497 if ((cmd & 0x0400) != 0) { 1498 cmd &= ~0x0400; 1499 pci_write_config(sc->ale_dev, PCIR_COMMAND, cmd, 2); 1500 } 1501 1502 #ifdef notyet 1503 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1504 uint16_t pmstat; 1505 int pmc; 1506 1507 /* Disable PME and clear PME status. */ 1508 pmstat = pci_read_config(sc->ale_dev, 1509 pmc + PCIR_POWER_STATUS, 2); 1510 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1511 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1512 pci_write_config(sc->ale_dev, 1513 pmc + PCIR_POWER_STATUS, pmstat, 2); 1514 } 1515 } 1516 #endif 1517 1518 /* Reset PHY. */ 1519 ale_phy_reset(sc); 1520 if ((ifp->if_flags & IFF_UP) != 0) 1521 ale_init(sc); 1522 1523 lwkt_serialize_exit(ifp->if_serializer); 1524 return (0); 1525 } 1526 1527 static int 1528 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1529 { 1530 struct ale_txdesc *txd, *txd_last; 1531 struct tx_desc *desc; 1532 struct mbuf *m; 1533 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1534 struct ale_dmamap_ctx ctx; 1535 bus_dmamap_t map; 1536 uint32_t cflags, poff, vtag; 1537 int error, i, nsegs, prod; 1538 1539 M_ASSERTPKTHDR((*m_head)); 1540 1541 m = *m_head; 1542 cflags = vtag = 0; 1543 poff = 0; 1544 1545 prod = sc->ale_cdata.ale_tx_prod; 1546 txd = &sc->ale_cdata.ale_txdesc[prod]; 1547 txd_last = txd; 1548 map = txd->tx_dmamap; 1549 1550 ctx.nsegs = ALE_MAXTXSEGS; 1551 ctx.segs = txsegs; 1552 error = bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map, 1553 *m_head, ale_dmamap_buf_cb, &ctx, 1554 BUS_DMA_NOWAIT); 1555 if (error == EFBIG) { 1556 m = m_defrag(*m_head, MB_DONTWAIT); 1557 if (m == NULL) { 1558 m_freem(*m_head); 1559 *m_head = NULL; 1560 return (ENOMEM); 1561 } 1562 *m_head = m; 1563 1564 ctx.nsegs = ALE_MAXTXSEGS; 1565 ctx.segs = txsegs; 1566 error = bus_dmamap_load_mbuf(sc->ale_cdata.ale_tx_tag, map, 1567 *m_head, ale_dmamap_buf_cb, &ctx, 1568 BUS_DMA_NOWAIT); 1569 if (error != 0) { 1570 m_freem(*m_head); 1571 *m_head = NULL; 1572 return (error); 1573 } 1574 } else if (error != 0) { 1575 return (error); 1576 } 1577 nsegs = ctx.nsegs; 1578 1579 if (nsegs == 0) { 1580 m_freem(*m_head); 1581 *m_head = NULL; 1582 return (EIO); 1583 } 1584 1585 /* Check descriptor overrun. */ 1586 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 1587 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1588 return (ENOBUFS); 1589 } 1590 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1591 1592 m = *m_head; 1593 /* Configure Tx checksum offload. */ 1594 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1595 /* 1596 * AR81xx supports Tx custom checksum offload feature 1597 * that offloads single 16bit checksum computation. 1598 * So you can choose one among IP, TCP and UDP. 1599 * Normally driver sets checksum start/insertion 1600 * position from the information of TCP/UDP frame as 1601 * TCP/UDP checksum takes more time than that of IP. 1602 * However it seems that custom checksum offload 1603 * requires 4 bytes aligned Tx buffers due to hardware 1604 * bug. 1605 * AR81xx also supports explicit Tx checksum computation 1606 * if it is told that the size of IP header and TCP 1607 * header(for UDP, the header size does not matter 1608 * because it's fixed length). However with this scheme 1609 * TSO does not work so you have to choose one either 1610 * TSO or explicit Tx checksum offload. I chosen TSO 1611 * plus custom checksum offload with work-around which 1612 * will cover most common usage for this consumer 1613 * ethernet controller. The work-around takes a lot of 1614 * CPU cycles if Tx buffer is not aligned on 4 bytes 1615 * boundary, though. 1616 */ 1617 cflags |= ALE_TD_CXSUM; 1618 /* Set checksum start offset. */ 1619 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1620 /* Set checksum insertion position of TCP/UDP. */ 1621 cflags |= ((poff + m->m_pkthdr.csum_data) << 1622 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1623 } 1624 1625 /* Configure VLAN hardware tag insertion. */ 1626 if ((m->m_flags & M_VLANTAG) != 0) { 1627 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vlantag); 1628 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1629 cflags |= ALE_TD_INSERT_VLAN_TAG; 1630 } 1631 1632 desc = NULL; 1633 for (i = 0; i < nsegs; i++) { 1634 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1635 desc->addr = htole64(txsegs[i].ds_addr); 1636 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1637 desc->flags = htole32(cflags); 1638 sc->ale_cdata.ale_tx_cnt++; 1639 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1640 } 1641 /* Update producer index. */ 1642 sc->ale_cdata.ale_tx_prod = prod; 1643 1644 /* Finally set EOP on the last descriptor. */ 1645 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1646 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1647 desc->flags |= htole32(ALE_TD_EOP); 1648 1649 /* Swap dmamap of the first and the last. */ 1650 txd = &sc->ale_cdata.ale_txdesc[prod]; 1651 map = txd_last->tx_dmamap; 1652 txd_last->tx_dmamap = txd->tx_dmamap; 1653 txd->tx_dmamap = map; 1654 txd->tx_m = m; 1655 1656 /* Sync descriptors. */ 1657 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1658 sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_PREWRITE); 1659 1660 return (0); 1661 } 1662 1663 static void 1664 ale_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 1665 { 1666 struct ale_softc *sc = ifp->if_softc; 1667 struct mbuf *m_head; 1668 int enq; 1669 1670 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 1671 ASSERT_SERIALIZED(ifp->if_serializer); 1672 1673 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1674 ifq_purge(&ifp->if_snd); 1675 return; 1676 } 1677 1678 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd)) 1679 return; 1680 1681 /* Reclaim transmitted frames. */ 1682 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1683 ale_txeof(sc); 1684 1685 enq = 0; 1686 while (!ifq_is_empty(&ifp->if_snd)) { 1687 m_head = ifq_dequeue(&ifp->if_snd); 1688 if (m_head == NULL) 1689 break; 1690 1691 /* 1692 * Pack the data into the transmit ring. If we 1693 * don't have room, set the OACTIVE flag and wait 1694 * for the NIC to drain the ring. 1695 */ 1696 if (ale_encap(sc, &m_head)) { 1697 if (m_head == NULL) 1698 break; 1699 ifq_prepend(&ifp->if_snd, m_head); 1700 ifq_set_oactive(&ifp->if_snd); 1701 break; 1702 } 1703 enq = 1; 1704 1705 /* 1706 * If there's a BPF listener, bounce a copy of this frame 1707 * to him. 1708 */ 1709 ETHER_BPF_MTAP(ifp, m_head); 1710 } 1711 1712 if (enq) { 1713 /* Kick. */ 1714 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1715 sc->ale_cdata.ale_tx_prod); 1716 1717 /* Set a timeout in case the chip goes out to lunch. */ 1718 ifp->if_timer = ALE_TX_TIMEOUT; 1719 } 1720 } 1721 1722 static void 1723 ale_watchdog(struct ifnet *ifp) 1724 { 1725 struct ale_softc *sc = ifp->if_softc; 1726 1727 ASSERT_SERIALIZED(ifp->if_serializer); 1728 1729 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1730 if_printf(ifp, "watchdog timeout (lost link)\n"); 1731 IFNET_STAT_INC(ifp, oerrors, 1); 1732 ale_init(sc); 1733 return; 1734 } 1735 1736 if_printf(ifp, "watchdog timeout -- resetting\n"); 1737 IFNET_STAT_INC(ifp, oerrors, 1); 1738 ale_init(sc); 1739 1740 if (!ifq_is_empty(&ifp->if_snd)) 1741 if_devstart(ifp); 1742 } 1743 1744 static int 1745 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr) 1746 { 1747 struct ale_softc *sc; 1748 struct ifreq *ifr; 1749 struct mii_data *mii; 1750 int error, mask; 1751 1752 ASSERT_SERIALIZED(ifp->if_serializer); 1753 1754 sc = ifp->if_softc; 1755 ifr = (struct ifreq *)data; 1756 error = 0; 1757 1758 switch (cmd) { 1759 case SIOCSIFMTU: 1760 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1761 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1762 ifr->ifr_mtu > ETHERMTU)) 1763 error = EINVAL; 1764 else if (ifp->if_mtu != ifr->ifr_mtu) { 1765 ifp->if_mtu = ifr->ifr_mtu; 1766 if ((ifp->if_flags & IFF_RUNNING) != 0) 1767 ale_init(sc); 1768 } 1769 break; 1770 1771 case SIOCSIFFLAGS: 1772 if ((ifp->if_flags & IFF_UP) != 0) { 1773 if ((ifp->if_flags & IFF_RUNNING) != 0) { 1774 if (((ifp->if_flags ^ sc->ale_if_flags) 1775 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1776 ale_rxfilter(sc); 1777 } else { 1778 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0) 1779 ale_init(sc); 1780 } 1781 } else { 1782 if ((ifp->if_flags & IFF_RUNNING) != 0) 1783 ale_stop(sc); 1784 } 1785 sc->ale_if_flags = ifp->if_flags; 1786 break; 1787 1788 case SIOCADDMULTI: 1789 case SIOCDELMULTI: 1790 if ((ifp->if_flags & IFF_RUNNING) != 0) 1791 ale_rxfilter(sc); 1792 break; 1793 1794 case SIOCSIFMEDIA: 1795 case SIOCGIFMEDIA: 1796 mii = device_get_softc(sc->ale_miibus); 1797 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1798 break; 1799 1800 case SIOCSIFCAP: 1801 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1802 if ((mask & IFCAP_TXCSUM) != 0 && 1803 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1804 ifp->if_capenable ^= IFCAP_TXCSUM; 1805 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1806 ifp->if_hwassist |= ALE_CSUM_FEATURES; 1807 else 1808 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 1809 } 1810 if ((mask & IFCAP_RXCSUM) != 0 && 1811 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 1812 ifp->if_capenable ^= IFCAP_RXCSUM; 1813 1814 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1815 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1816 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1817 ale_rxvlan(sc); 1818 } 1819 break; 1820 1821 default: 1822 error = ether_ioctl(ifp, cmd, data); 1823 break; 1824 } 1825 return (error); 1826 } 1827 1828 static void 1829 ale_mac_config(struct ale_softc *sc) 1830 { 1831 struct mii_data *mii; 1832 uint32_t reg; 1833 1834 mii = device_get_softc(sc->ale_miibus); 1835 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1836 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 1837 MAC_CFG_SPEED_MASK); 1838 /* Reprogram MAC with resolved speed/duplex. */ 1839 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1840 case IFM_10_T: 1841 case IFM_100_TX: 1842 reg |= MAC_CFG_SPEED_10_100; 1843 break; 1844 case IFM_1000_T: 1845 reg |= MAC_CFG_SPEED_1000; 1846 break; 1847 } 1848 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1849 reg |= MAC_CFG_FULL_DUPLEX; 1850 #ifdef notyet 1851 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1852 reg |= MAC_CFG_TX_FC; 1853 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1854 reg |= MAC_CFG_RX_FC; 1855 #endif 1856 } 1857 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1858 } 1859 1860 static void 1861 ale_stats_clear(struct ale_softc *sc) 1862 { 1863 struct smb sb; 1864 uint32_t *reg; 1865 int i; 1866 1867 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1868 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1869 i += sizeof(uint32_t); 1870 } 1871 /* Read Tx statistics. */ 1872 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1873 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1874 i += sizeof(uint32_t); 1875 } 1876 } 1877 1878 static void 1879 ale_stats_update(struct ale_softc *sc) 1880 { 1881 struct ale_hw_stats *stat; 1882 struct smb sb, *smb; 1883 struct ifnet *ifp; 1884 uint32_t *reg; 1885 int i; 1886 1887 ifp = &sc->arpcom.ac_if; 1888 stat = &sc->ale_stats; 1889 smb = &sb; 1890 1891 /* Read Rx statistics. */ 1892 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 1893 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 1894 i += sizeof(uint32_t); 1895 } 1896 /* Read Tx statistics. */ 1897 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 1898 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 1899 i += sizeof(uint32_t); 1900 } 1901 1902 /* Rx stats. */ 1903 stat->rx_frames += smb->rx_frames; 1904 stat->rx_bcast_frames += smb->rx_bcast_frames; 1905 stat->rx_mcast_frames += smb->rx_mcast_frames; 1906 stat->rx_pause_frames += smb->rx_pause_frames; 1907 stat->rx_control_frames += smb->rx_control_frames; 1908 stat->rx_crcerrs += smb->rx_crcerrs; 1909 stat->rx_lenerrs += smb->rx_lenerrs; 1910 stat->rx_bytes += smb->rx_bytes; 1911 stat->rx_runts += smb->rx_runts; 1912 stat->rx_fragments += smb->rx_fragments; 1913 stat->rx_pkts_64 += smb->rx_pkts_64; 1914 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 1915 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 1916 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 1917 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 1918 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 1919 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 1920 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 1921 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 1922 stat->rx_rrs_errs += smb->rx_rrs_errs; 1923 stat->rx_alignerrs += smb->rx_alignerrs; 1924 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 1925 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 1926 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 1927 1928 /* Tx stats. */ 1929 stat->tx_frames += smb->tx_frames; 1930 stat->tx_bcast_frames += smb->tx_bcast_frames; 1931 stat->tx_mcast_frames += smb->tx_mcast_frames; 1932 stat->tx_pause_frames += smb->tx_pause_frames; 1933 stat->tx_excess_defer += smb->tx_excess_defer; 1934 stat->tx_control_frames += smb->tx_control_frames; 1935 stat->tx_deferred += smb->tx_deferred; 1936 stat->tx_bytes += smb->tx_bytes; 1937 stat->tx_pkts_64 += smb->tx_pkts_64; 1938 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 1939 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 1940 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 1941 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 1942 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 1943 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 1944 stat->tx_single_colls += smb->tx_single_colls; 1945 stat->tx_multi_colls += smb->tx_multi_colls; 1946 stat->tx_late_colls += smb->tx_late_colls; 1947 stat->tx_excess_colls += smb->tx_excess_colls; 1948 stat->tx_abort += smb->tx_abort; 1949 stat->tx_underrun += smb->tx_underrun; 1950 stat->tx_desc_underrun += smb->tx_desc_underrun; 1951 stat->tx_lenerrs += smb->tx_lenerrs; 1952 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 1953 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 1954 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 1955 1956 /* Update counters in ifnet. */ 1957 IFNET_STAT_INC(ifp, opackets, smb->tx_frames); 1958 1959 IFNET_STAT_INC(ifp, collisions, smb->tx_single_colls + 1960 smb->tx_multi_colls * 2 + smb->tx_late_colls + 1961 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT); 1962 1963 /* 1964 * XXX 1965 * tx_pkts_truncated counter looks suspicious. It constantly 1966 * increments with no sign of Tx errors. This may indicate 1967 * the counter name is not correct one so I've removed the 1968 * counter in output errors. 1969 */ 1970 IFNET_STAT_INC(ifp, oerrors, smb->tx_abort + smb->tx_late_colls + 1971 smb->tx_underrun); 1972 1973 IFNET_STAT_INC(ifp, ipackets, smb->rx_frames); 1974 1975 IFNET_STAT_INC(ifp, ierrors, smb->rx_crcerrs + smb->rx_lenerrs + 1976 smb->rx_runts + smb->rx_pkts_truncated + 1977 smb->rx_fifo_oflows + smb->rx_rrs_errs + 1978 smb->rx_alignerrs); 1979 } 1980 1981 static void 1982 ale_intr(void *xsc) 1983 { 1984 struct ale_softc *sc = xsc; 1985 struct ifnet *ifp = &sc->arpcom.ac_if; 1986 uint32_t status; 1987 1988 ASSERT_SERIALIZED(ifp->if_serializer); 1989 1990 status = CSR_READ_4(sc, ALE_INTR_STATUS); 1991 if ((status & ALE_INTRS) == 0) 1992 return; 1993 1994 /* Acknowledge and disable interrupts. */ 1995 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 1996 1997 if ((ifp->if_flags & IFF_RUNNING) != 0) { 1998 int error; 1999 2000 error = ale_rxeof(sc); 2001 if (error) { 2002 sc->ale_stats.reset_brk_seq++; 2003 ale_init(sc); 2004 return; 2005 } 2006 2007 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2008 if ((status & INTR_DMA_RD_TO_RST) != 0) 2009 device_printf(sc->ale_dev, 2010 "DMA read error! -- resetting\n"); 2011 if ((status & INTR_DMA_WR_TO_RST) != 0) 2012 device_printf(sc->ale_dev, 2013 "DMA write error! -- resetting\n"); 2014 ale_init(sc); 2015 return; 2016 } 2017 2018 ale_txeof(sc); 2019 if (!ifq_is_empty(&ifp->if_snd)) 2020 if_devstart(ifp); 2021 } 2022 2023 /* Re-enable interrupts. */ 2024 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2025 } 2026 2027 static void 2028 ale_txeof(struct ale_softc *sc) 2029 { 2030 struct ifnet *ifp = &sc->arpcom.ac_if; 2031 struct ale_txdesc *txd; 2032 uint32_t cons, prod; 2033 int prog; 2034 2035 if (sc->ale_cdata.ale_tx_cnt == 0) 2036 return; 2037 2038 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2039 sc->ale_cdata.ale_tx_ring_map, BUS_DMASYNC_POSTREAD); 2040 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2041 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2042 sc->ale_cdata.ale_tx_cmb_map, BUS_DMASYNC_POSTREAD); 2043 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2044 } else 2045 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2046 cons = sc->ale_cdata.ale_tx_cons; 2047 /* 2048 * Go through our Tx list and free mbufs for those 2049 * frames which have been transmitted. 2050 */ 2051 for (prog = 0; cons != prod; prog++, 2052 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2053 if (sc->ale_cdata.ale_tx_cnt <= 0) 2054 break; 2055 prog++; 2056 ifq_clr_oactive(&ifp->if_snd); 2057 sc->ale_cdata.ale_tx_cnt--; 2058 txd = &sc->ale_cdata.ale_txdesc[cons]; 2059 if (txd->tx_m != NULL) { 2060 /* Reclaim transmitted mbufs. */ 2061 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2062 txd->tx_dmamap); 2063 m_freem(txd->tx_m); 2064 txd->tx_m = NULL; 2065 } 2066 } 2067 2068 if (prog > 0) { 2069 sc->ale_cdata.ale_tx_cons = cons; 2070 /* 2071 * Unarm watchdog timer only when there is no pending 2072 * Tx descriptors in queue. 2073 */ 2074 if (sc->ale_cdata.ale_tx_cnt == 0) 2075 ifp->if_timer = 0; 2076 } 2077 } 2078 2079 static void 2080 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2081 uint32_t length, uint32_t *prod) 2082 { 2083 struct ale_rx_page *rx_page; 2084 2085 rx_page = *page; 2086 /* Update consumer position. */ 2087 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2088 ALE_RX_PAGE_ALIGN); 2089 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2090 /* 2091 * End of Rx page reached, let hardware reuse 2092 * this page. 2093 */ 2094 rx_page->cons = 0; 2095 *rx_page->cmb_addr = 0; 2096 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2097 BUS_DMASYNC_PREWRITE); 2098 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2099 RXF_VALID); 2100 /* Switch to alternate Rx page. */ 2101 sc->ale_cdata.ale_rx_curp ^= 1; 2102 rx_page = *page = 2103 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2104 /* Page flipped, sync CMB and Rx page. */ 2105 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2106 BUS_DMASYNC_POSTREAD); 2107 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2108 BUS_DMASYNC_POSTREAD); 2109 /* Sync completed, cache updated producer index. */ 2110 *prod = *rx_page->cmb_addr; 2111 } 2112 } 2113 2114 2115 /* 2116 * It seems that AR81xx controller can compute partial checksum. 2117 * The partial checksum value can be used to accelerate checksum 2118 * computation for fragmented TCP/UDP packets. Upper network stack 2119 * already takes advantage of the partial checksum value in IP 2120 * reassembly stage. But I'm not sure the correctness of the 2121 * partial hardware checksum assistance due to lack of data sheet. 2122 * In addition, the Rx feature of controller that requires copying 2123 * for every frames effectively nullifies one of most nice offload 2124 * capability of controller. 2125 */ 2126 static void 2127 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2128 { 2129 struct ifnet *ifp = &sc->arpcom.ac_if; 2130 struct ip *ip; 2131 char *p; 2132 2133 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2134 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2135 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2136 2137 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2138 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2139 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2140 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2141 m->m_pkthdr.csum_flags |= 2142 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2143 m->m_pkthdr.csum_data = 0xffff; 2144 } 2145 } else { 2146 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2147 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2148 p = mtod(m, char *); 2149 p += ETHER_HDR_LEN; 2150 if ((status & ALE_RD_802_3) != 0) 2151 p += LLC_SNAPFRAMELEN; 2152 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2153 (status & ALE_RD_VLAN) != 0) 2154 p += EVL_ENCAPLEN; 2155 ip = (struct ip *)p; 2156 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2157 return; 2158 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2159 CSUM_PSEUDO_HDR; 2160 m->m_pkthdr.csum_data = 0xffff; 2161 } 2162 } 2163 /* 2164 * Don't mark bad checksum for TCP/UDP frames 2165 * as fragmented frames may always have set 2166 * bad checksummed bit of frame status. 2167 */ 2168 } 2169 2170 /* Process received frames. */ 2171 static int 2172 ale_rxeof(struct ale_softc *sc) 2173 { 2174 struct ifnet *ifp = &sc->arpcom.ac_if; 2175 struct ale_rx_page *rx_page; 2176 struct rx_rs *rs; 2177 struct mbuf *m; 2178 uint32_t length, prod, seqno, status, vtags; 2179 int prog; 2180 2181 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2182 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2183 BUS_DMASYNC_POSTREAD); 2184 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2185 BUS_DMASYNC_POSTREAD); 2186 /* 2187 * Don't directly access producer index as hardware may 2188 * update it while Rx handler is in progress. It would 2189 * be even better if there is a way to let hardware 2190 * know how far driver processed its received frames. 2191 * Alternatively, hardware could provide a way to disable 2192 * CMB updates until driver acknowledges the end of CMB 2193 * access. 2194 */ 2195 prod = *rx_page->cmb_addr; 2196 for (prog = 0; ; prog++) { 2197 if (rx_page->cons >= prod) 2198 break; 2199 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2200 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2201 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2202 /* 2203 * Normally I believe this should not happen unless 2204 * severe driver bug or corrupted memory. However 2205 * it seems to happen under certain conditions which 2206 * is triggered by abrupt Rx events such as initiation 2207 * of bulk transfer of remote host. It's not easy to 2208 * reproduce this and I doubt it could be related 2209 * with FIFO overflow of hardware or activity of Tx 2210 * CMB updates. I also remember similar behaviour 2211 * seen on RealTek 8139 which uses resembling Rx 2212 * scheme. 2213 */ 2214 if (bootverbose) 2215 device_printf(sc->ale_dev, 2216 "garbled seq: %u, expected: %u -- " 2217 "resetting!\n", seqno, 2218 sc->ale_cdata.ale_rx_seqno); 2219 return (EIO); 2220 } 2221 /* Frame received. */ 2222 sc->ale_cdata.ale_rx_seqno++; 2223 length = ALE_RX_BYTES(le32toh(rs->length)); 2224 status = le32toh(rs->flags); 2225 if ((status & ALE_RD_ERROR) != 0) { 2226 /* 2227 * We want to pass the following frames to upper 2228 * layer regardless of error status of Rx return 2229 * status. 2230 * 2231 * o IP/TCP/UDP checksum is bad. 2232 * o frame length and protocol specific length 2233 * does not match. 2234 */ 2235 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2236 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2237 ALE_RD_TRUNC)) != 0) { 2238 ale_rx_update_page(sc, &rx_page, length, &prod); 2239 continue; 2240 } 2241 } 2242 /* 2243 * m_devget(9) is major bottle-neck of ale(4)(It comes 2244 * from hardware limitation). For jumbo frames we could 2245 * get a slightly better performance if driver use 2246 * m_getjcl(9) with proper buffer size argument. However 2247 * that would make code more complicated and I don't 2248 * think users would expect good Rx performance numbers 2249 * on these low-end consumer ethernet controller. 2250 */ 2251 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2252 ETHER_ALIGN, ifp, NULL); 2253 if (m == NULL) { 2254 IFNET_STAT_INC(ifp, iqdrops, 1); 2255 ale_rx_update_page(sc, &rx_page, length, &prod); 2256 continue; 2257 } 2258 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2259 (status & ALE_RD_IPV4) != 0) 2260 ale_rxcsum(sc, m, status); 2261 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2262 (status & ALE_RD_VLAN) != 0) { 2263 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2264 m->m_pkthdr.ether_vlantag = ALE_RX_VLAN_TAG(vtags); 2265 m->m_flags |= M_VLANTAG; 2266 } 2267 2268 /* Pass it to upper layer. */ 2269 ifp->if_input(ifp, m); 2270 2271 ale_rx_update_page(sc, &rx_page, length, &prod); 2272 } 2273 return 0; 2274 } 2275 2276 static void 2277 ale_tick(void *xsc) 2278 { 2279 struct ale_softc *sc = xsc; 2280 struct ifnet *ifp = &sc->arpcom.ac_if; 2281 struct mii_data *mii; 2282 2283 lwkt_serialize_enter(ifp->if_serializer); 2284 2285 mii = device_get_softc(sc->ale_miibus); 2286 mii_tick(mii); 2287 ale_stats_update(sc); 2288 2289 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2290 2291 lwkt_serialize_exit(ifp->if_serializer); 2292 } 2293 2294 static void 2295 ale_reset(struct ale_softc *sc) 2296 { 2297 uint32_t reg; 2298 int i; 2299 2300 /* Initialize PCIe module. From Linux. */ 2301 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2302 2303 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2304 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2305 DELAY(10); 2306 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2307 break; 2308 } 2309 if (i == 0) 2310 device_printf(sc->ale_dev, "master reset timeout!\n"); 2311 2312 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2313 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2314 break; 2315 DELAY(10); 2316 } 2317 2318 if (i == 0) 2319 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2320 } 2321 2322 static void 2323 ale_init(void *xsc) 2324 { 2325 struct ale_softc *sc = xsc; 2326 struct ifnet *ifp = &sc->arpcom.ac_if; 2327 struct mii_data *mii; 2328 uint8_t eaddr[ETHER_ADDR_LEN]; 2329 bus_addr_t paddr; 2330 uint32_t reg, rxf_hi, rxf_lo; 2331 2332 ASSERT_SERIALIZED(ifp->if_serializer); 2333 2334 mii = device_get_softc(sc->ale_miibus); 2335 2336 /* 2337 * Cancel any pending I/O. 2338 */ 2339 ale_stop(sc); 2340 2341 /* 2342 * Reset the chip to a known state. 2343 */ 2344 ale_reset(sc); 2345 2346 /* Initialize Tx descriptors, DMA memory blocks. */ 2347 ale_init_rx_pages(sc); 2348 ale_init_tx_ring(sc); 2349 2350 /* Reprogram the station address. */ 2351 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2352 CSR_WRITE_4(sc, ALE_PAR0, 2353 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2354 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2355 2356 /* 2357 * Clear WOL status and disable all WOL feature as WOL 2358 * would interfere Rx operation under normal environments. 2359 */ 2360 CSR_READ_4(sc, ALE_WOL_CFG); 2361 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2362 2363 /* 2364 * Set Tx descriptor/RXF0/CMB base addresses. They share 2365 * the same high address part of DMAable region. 2366 */ 2367 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2368 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2369 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2370 CSR_WRITE_4(sc, ALE_TPD_CNT, 2371 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2372 2373 /* Set Rx page base address, note we use single queue. */ 2374 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2375 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2376 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2377 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2378 2379 /* Set Tx/Rx CMB addresses. */ 2380 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2381 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2382 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2383 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2384 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2385 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2386 2387 /* Mark RXF0 is valid. */ 2388 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2389 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2390 /* 2391 * No need to initialize RFX1/RXF2/RXF3. We don't use 2392 * multi-queue yet. 2393 */ 2394 2395 /* Set Rx page size, excluding guard frame size. */ 2396 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2397 2398 /* Tell hardware that we're ready to load DMA blocks. */ 2399 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2400 2401 /* Set Rx/Tx interrupt trigger threshold. */ 2402 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2403 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2404 /* 2405 * XXX 2406 * Set interrupt trigger timer, its purpose and relation 2407 * with interrupt moderation mechanism is not clear yet. 2408 */ 2409 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2410 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2411 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2412 2413 /* Configure interrupt moderation timer. */ 2414 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2415 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2416 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2417 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2418 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2419 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2420 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2421 reg |= MASTER_IM_RX_TIMER_ENB; 2422 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2423 reg |= MASTER_IM_TX_TIMER_ENB; 2424 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2425 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2426 2427 /* Set Maximum frame size of controller. */ 2428 if (ifp->if_mtu < ETHERMTU) 2429 sc->ale_max_frame_size = ETHERMTU; 2430 else 2431 sc->ale_max_frame_size = ifp->if_mtu; 2432 sc->ale_max_frame_size += ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN; 2433 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2434 2435 /* Configure IPG/IFG parameters. */ 2436 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2437 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2438 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2439 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2440 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2441 2442 /* Set parameters for half-duplex media. */ 2443 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2444 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2445 HDPX_CFG_LCOL_MASK) | 2446 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2447 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2448 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2449 HDPX_CFG_ABEBT_MASK) | 2450 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2451 HDPX_CFG_JAMIPG_MASK)); 2452 2453 /* Configure Tx jumbo frame parameters. */ 2454 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2455 if (ifp->if_mtu < ETHERMTU) 2456 reg = sc->ale_max_frame_size; 2457 else if (ifp->if_mtu < 6 * 1024) 2458 reg = (sc->ale_max_frame_size * 2) / 3; 2459 else 2460 reg = sc->ale_max_frame_size / 2; 2461 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2462 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2463 TX_JUMBO_THRESH_UNIT_SHIFT); 2464 } 2465 2466 /* Configure TxQ. */ 2467 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2468 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2469 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2470 TXQ_CFG_TPD_BURST_MASK; 2471 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2472 2473 /* Configure Rx jumbo frame & flow control parameters. */ 2474 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2475 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2476 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2477 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2478 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2479 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2480 RX_JUMBO_LKAH_MASK)); 2481 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2482 rxf_hi = (reg * 7) / 10; 2483 rxf_lo = (reg * 3)/ 10; 2484 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2485 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2486 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2487 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2488 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2489 } 2490 2491 /* Disable RSS. */ 2492 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2493 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2494 2495 /* Configure RxQ. */ 2496 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2497 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2498 2499 /* Configure DMA parameters. */ 2500 reg = 0; 2501 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2502 reg |= DMA_CFG_TXCMB_ENB; 2503 CSR_WRITE_4(sc, ALE_DMA_CFG, 2504 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2505 sc->ale_dma_rd_burst | reg | 2506 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2507 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2508 DMA_CFG_RD_DELAY_CNT_MASK) | 2509 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2510 DMA_CFG_WR_DELAY_CNT_MASK)); 2511 2512 /* 2513 * Hardware can be configured to issue SMB interrupt based 2514 * on programmed interval. Since there is a callout that is 2515 * invoked for every hz in driver we use that instead of 2516 * relying on periodic SMB interrupt. 2517 */ 2518 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2519 2520 /* Clear MAC statistics. */ 2521 ale_stats_clear(sc); 2522 2523 /* 2524 * Configure Tx/Rx MACs. 2525 * - Auto-padding for short frames. 2526 * - Enable CRC generation. 2527 * Actual reconfiguration of MAC for resolved speed/duplex 2528 * is followed after detection of link establishment. 2529 * AR81xx always does checksum computation regardless of 2530 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2531 * cause Rx handling issue for fragmented IP datagrams due 2532 * to silicon bug. 2533 */ 2534 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2535 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2536 MAC_CFG_PREAMBLE_MASK); 2537 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2538 reg |= MAC_CFG_SPEED_10_100; 2539 else 2540 reg |= MAC_CFG_SPEED_1000; 2541 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2542 2543 /* Set up the receive filter. */ 2544 ale_rxfilter(sc); 2545 ale_rxvlan(sc); 2546 2547 /* Acknowledge all pending interrupts and clear it. */ 2548 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2549 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2550 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2551 2552 sc->ale_flags &= ~ALE_FLAG_LINK; 2553 2554 /* Switch to the current media. */ 2555 mii_mediachg(mii); 2556 2557 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2558 2559 ifp->if_flags |= IFF_RUNNING; 2560 ifq_clr_oactive(&ifp->if_snd); 2561 } 2562 2563 static void 2564 ale_stop(struct ale_softc *sc) 2565 { 2566 struct ifnet *ifp = &sc->arpcom.ac_if; 2567 struct ale_txdesc *txd; 2568 uint32_t reg; 2569 int i; 2570 2571 ASSERT_SERIALIZED(ifp->if_serializer); 2572 2573 /* 2574 * Mark the interface down and cancel the watchdog timer. 2575 */ 2576 ifp->if_flags &= ~IFF_RUNNING; 2577 ifq_clr_oactive(&ifp->if_snd); 2578 ifp->if_timer = 0; 2579 2580 callout_stop(&sc->ale_tick_ch); 2581 sc->ale_flags &= ~ALE_FLAG_LINK; 2582 2583 ale_stats_update(sc); 2584 2585 /* Disable interrupts. */ 2586 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2587 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2588 2589 /* Disable queue processing and DMA. */ 2590 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2591 reg &= ~TXQ_CFG_ENB; 2592 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2593 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2594 reg &= ~RXQ_CFG_ENB; 2595 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2596 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2597 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2598 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2599 DELAY(1000); 2600 2601 /* Stop Rx/Tx MACs. */ 2602 ale_stop_mac(sc); 2603 2604 /* Disable interrupts again? XXX */ 2605 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2606 2607 /* 2608 * Free TX mbufs still in the queues. 2609 */ 2610 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2611 txd = &sc->ale_cdata.ale_txdesc[i]; 2612 if (txd->tx_m != NULL) { 2613 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2614 txd->tx_dmamap); 2615 m_freem(txd->tx_m); 2616 txd->tx_m = NULL; 2617 } 2618 } 2619 } 2620 2621 static void 2622 ale_stop_mac(struct ale_softc *sc) 2623 { 2624 uint32_t reg; 2625 int i; 2626 2627 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2628 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2629 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2630 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2631 } 2632 2633 for (i = ALE_TIMEOUT; i > 0; i--) { 2634 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2635 if (reg == 0) 2636 break; 2637 DELAY(10); 2638 } 2639 if (i == 0) 2640 device_printf(sc->ale_dev, 2641 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2642 } 2643 2644 static void 2645 ale_init_tx_ring(struct ale_softc *sc) 2646 { 2647 struct ale_txdesc *txd; 2648 int i; 2649 2650 sc->ale_cdata.ale_tx_prod = 0; 2651 sc->ale_cdata.ale_tx_cons = 0; 2652 sc->ale_cdata.ale_tx_cnt = 0; 2653 2654 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2655 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2656 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2657 txd = &sc->ale_cdata.ale_txdesc[i]; 2658 txd->tx_m = NULL; 2659 } 2660 *sc->ale_cdata.ale_tx_cmb = 0; 2661 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2662 sc->ale_cdata.ale_tx_cmb_map, 2663 BUS_DMASYNC_PREWRITE); 2664 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2665 sc->ale_cdata.ale_tx_ring_map, 2666 BUS_DMASYNC_PREWRITE); 2667 } 2668 2669 static void 2670 ale_init_rx_pages(struct ale_softc *sc) 2671 { 2672 struct ale_rx_page *rx_page; 2673 int i; 2674 2675 sc->ale_cdata.ale_rx_seqno = 0; 2676 sc->ale_cdata.ale_rx_curp = 0; 2677 2678 for (i = 0; i < ALE_RX_PAGES; i++) { 2679 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2680 bzero(rx_page->page_addr, sc->ale_pagesize); 2681 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2682 rx_page->cons = 0; 2683 *rx_page->cmb_addr = 0; 2684 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2685 BUS_DMASYNC_PREWRITE); 2686 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2687 BUS_DMASYNC_PREWRITE); 2688 } 2689 } 2690 2691 static void 2692 ale_rxvlan(struct ale_softc *sc) 2693 { 2694 struct ifnet *ifp; 2695 uint32_t reg; 2696 2697 ifp = &sc->arpcom.ac_if; 2698 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2699 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2700 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2701 reg |= MAC_CFG_VLAN_TAG_STRIP; 2702 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2703 } 2704 2705 static void 2706 ale_rxfilter(struct ale_softc *sc) 2707 { 2708 struct ifnet *ifp; 2709 struct ifmultiaddr *ifma; 2710 uint32_t crc; 2711 uint32_t mchash[2]; 2712 uint32_t rxcfg; 2713 2714 ifp = &sc->arpcom.ac_if; 2715 2716 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2717 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2718 if ((ifp->if_flags & IFF_BROADCAST) != 0) 2719 rxcfg |= MAC_CFG_BCAST; 2720 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2721 if ((ifp->if_flags & IFF_PROMISC) != 0) 2722 rxcfg |= MAC_CFG_PROMISC; 2723 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 2724 rxcfg |= MAC_CFG_ALLMULTI; 2725 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 2726 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 2727 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2728 return; 2729 } 2730 2731 /* Program new filter. */ 2732 bzero(mchash, sizeof(mchash)); 2733 2734 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 2735 if (ifma->ifma_addr->sa_family != AF_LINK) 2736 continue; 2737 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2738 ifma->ifma_addr), ETHER_ADDR_LEN); 2739 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2740 } 2741 2742 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 2743 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 2744 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2745 } 2746 2747 static int 2748 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 2749 { 2750 return (sysctl_int_range(oidp, arg1, arg2, req, 2751 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 2752 } 2753 2754 static void 2755 ale_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs, 2756 bus_size_t mapsz __unused, int error) 2757 { 2758 struct ale_dmamap_ctx *ctx = xctx; 2759 int i; 2760 2761 if (error) 2762 return; 2763 2764 if (nsegs > ctx->nsegs) { 2765 ctx->nsegs = 0; 2766 return; 2767 } 2768 2769 ctx->nsegs = nsegs; 2770 for (i = 0; i < nsegs; ++i) 2771 ctx->segs[i] = segs[i]; 2772 }
Cache object: 958df0aa16a300cd27db67d6c46f7d42
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