1 /*
2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
4 * Modifications for FreeBSD-stable by Edwin Groothuis
5 * <edwin at mavetju.org
6 * < http://lists.freebsd.org/mailman/listinfo/freebsd-bugs>>
7 */
8
9 /*
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * $FreeBSD: src/sys/dev/bfe/if_bfe.c 1.4.4.7 2004/03/02 08:41:33 julian Exp v
32 */
33
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/sockio.h>
37 #include <sys/mbuf.h>
38 #include <sys/malloc.h>
39 #include <sys/interrupt.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
43 #include <sys/bus.h>
44 #include <sys/rman.h>
45 #include <sys/thread2.h>
46
47 #include <net/if.h>
48 #include <net/ifq_var.h>
49 #include <net/if_arp.h>
50 #include <net/ethernet.h>
51 #include <net/if_dl.h>
52 #include <net/if_media.h>
53
54 #include <net/bpf.h>
55
56 #include <net/if_types.h>
57 #include <net/vlan/if_vlan_var.h>
58
59 #include <netinet/in_systm.h>
60 #include <netinet/in.h>
61 #include <netinet/ip.h>
62
63 #include <bus/pci/pcireg.h>
64 #include <bus/pci/pcivar.h>
65 #include "pcidevs.h"
66
67 #include <dev/netif/mii_layer/mii.h>
68 #include <dev/netif/mii_layer/miivar.h>
69
70 #include <dev/netif/bfe/if_bfereg.h>
71
72 MODULE_DEPEND(bfe, pci, 1, 1, 1);
73 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
74
75 /* "controller miibus0" required. See GENERIC if you get errors here. */
76 #include "miibus_if.h"
77
78 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
79
80 static struct bfe_type bfe_devs[] = {
81 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401,
82 "Broadcom BCM4401 Fast Ethernet" },
83 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4401B0,
84 "Broadcom BCM4401-B0 Fast Ethernet" },
85 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4402,
86 "Broadcom BCM4402 Fast Ethernet" },
87 { 0, 0, NULL }
88 };
89
90 static int bfe_probe(device_t);
91 static int bfe_attach(device_t);
92 static int bfe_detach(device_t);
93 static void bfe_intr(void *);
94 static void bfe_start(struct ifnet *, struct ifaltq_subque *);
95 static int bfe_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
96 static void bfe_init(void *);
97 static void bfe_stop(struct bfe_softc *);
98 static void bfe_watchdog(struct ifnet *);
99 static void bfe_shutdown(device_t);
100 static void bfe_tick(void *);
101 static void bfe_txeof(struct bfe_softc *);
102 static void bfe_rxeof(struct bfe_softc *);
103 static void bfe_set_rx_mode(struct bfe_softc *);
104 static int bfe_list_rx_init(struct bfe_softc *);
105 static int bfe_newbuf(struct bfe_softc *, int, int);
106 static void bfe_setup_rxdesc(struct bfe_softc *, int);
107 static void bfe_rx_ring_free(struct bfe_softc *);
108
109 static void bfe_pci_setup(struct bfe_softc *, uint32_t);
110 static int bfe_ifmedia_upd(struct ifnet *);
111 static void bfe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
112 static int bfe_miibus_readreg(device_t, int, int);
113 static int bfe_miibus_writereg(device_t, int, int, int);
114 static int bfe_wait_bit(struct bfe_softc *, uint32_t, uint32_t,
115 u_long, const int);
116 static void bfe_get_config(struct bfe_softc *sc);
117 static void bfe_read_eeprom(struct bfe_softc *, uint8_t *);
118 static void bfe_stats_update(struct bfe_softc *);
119 static void bfe_clear_stats (struct bfe_softc *);
120 static int bfe_readphy(struct bfe_softc *, uint32_t, uint32_t*);
121 static int bfe_writephy(struct bfe_softc *, uint32_t, uint32_t);
122 static int bfe_resetphy(struct bfe_softc *);
123 static int bfe_setupphy(struct bfe_softc *);
124 static void bfe_chip_reset(struct bfe_softc *);
125 static void bfe_chip_halt(struct bfe_softc *);
126 static void bfe_core_reset(struct bfe_softc *);
127 static void bfe_core_disable(struct bfe_softc *);
128 static int bfe_dma_alloc(device_t);
129 static void bfe_dma_free(struct bfe_softc *);
130 static void bfe_cam_write(struct bfe_softc *, u_char *, int);
131
132 static device_method_t bfe_methods[] = {
133 /* Device interface */
134 DEVMETHOD(device_probe, bfe_probe),
135 DEVMETHOD(device_attach, bfe_attach),
136 DEVMETHOD(device_detach, bfe_detach),
137 DEVMETHOD(device_shutdown, bfe_shutdown),
138
139 /* bus interface */
140 DEVMETHOD(bus_print_child, bus_generic_print_child),
141 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
142
143 /* MII interface */
144 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
145 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
146
147 DEVMETHOD_END
148 };
149
150 static driver_t bfe_driver = {
151 "bfe",
152 bfe_methods,
153 sizeof(struct bfe_softc)
154 };
155
156 static devclass_t bfe_devclass;
157
158 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, NULL, NULL);
159 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, NULL, NULL);
160
161 /*
162 * Probe for a Broadcom 4401 chip.
163 */
164 static int
165 bfe_probe(device_t dev)
166 {
167 struct bfe_type *t;
168 uint16_t vendor, product;
169
170 vendor = pci_get_vendor(dev);
171 product = pci_get_device(dev);
172
173 for (t = bfe_devs; t->bfe_name != NULL; t++) {
174 if (vendor == t->bfe_vid && product == t->bfe_did) {
175 device_set_desc(dev, t->bfe_name);
176 return(0);
177 }
178 }
179
180 return(ENXIO);
181 }
182
183 static int
184 bfe_dma_alloc(device_t dev)
185 {
186 struct bfe_softc *sc = device_get_softc(dev);
187 bus_dmamem_t dmem;
188 int error, i, tx_pos = 0, rx_pos = 0;
189
190 /*
191 * Parent tag. Apparently the chip cannot handle any DMA address
192 * greater than BFE_BUS_SPACE_MAXADDR (1GB).
193 */
194 error = bus_dma_tag_create(NULL, /* parent */
195 1, 0, /* alignment, boundary */
196 BFE_BUS_SPACE_MAXADDR, /* lowaddr */
197 BUS_SPACE_MAXADDR, /* highaddr */
198 NULL, NULL, /* filter, filterarg */
199 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
200 0, /* num of segments */
201 BUS_SPACE_MAXSIZE_32BIT, /* max segment size */
202 0, /* flags */
203 &sc->bfe_parent_tag);
204 if (error) {
205 device_printf(dev, "could not allocate parent dma tag\n");
206 return(error);
207 }
208
209 /* Allocate TX ring */
210 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0,
211 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
212 BFE_TX_LIST_SIZE,
213 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
214 if (error) {
215 device_printf(dev, "could not allocate TX list\n");
216 return(error);
217 }
218 sc->bfe_tx_tag = dmem.dmem_tag;
219 sc->bfe_tx_map = dmem.dmem_map;
220 sc->bfe_tx_list = dmem.dmem_addr;
221 sc->bfe_tx_dma = dmem.dmem_busaddr;
222
223 /* Allocate RX ring */
224 error = bus_dmamem_coherent(sc->bfe_parent_tag, PAGE_SIZE, 0,
225 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
226 BFE_RX_LIST_SIZE,
227 BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
228 if (error) {
229 device_printf(dev, "could not allocate RX list\n");
230 return(error);
231 }
232 sc->bfe_rx_tag = dmem.dmem_tag;
233 sc->bfe_rx_map = dmem.dmem_map;
234 sc->bfe_rx_list = dmem.dmem_addr;
235 sc->bfe_rx_dma = dmem.dmem_busaddr;
236
237 /* Tag for RX mbufs */
238 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0,
239 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
240 NULL, NULL,
241 MCLBYTES, 1, MCLBYTES,
242 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
243 &sc->bfe_rxbuf_tag);
244 if (error) {
245 device_printf(dev, "could not allocate dma tag for RX mbufs\n");
246 return(error);
247 }
248
249 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK,
250 &sc->bfe_rx_tmpmap);
251 if (error) {
252 device_printf(dev, "could not create RX mbuf tmp map\n");
253 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
254 sc->bfe_rxbuf_tag = NULL;
255 return error;
256 }
257
258 /* Allocate dma maps for RX list */
259 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
260 error = bus_dmamap_create(sc->bfe_rxbuf_tag, BUS_DMA_WAITOK,
261 &sc->bfe_rx_ring[i].bfe_map);
262 if (error) {
263 rx_pos = i;
264 device_printf(dev, "cannot create DMA map for RX\n");
265 goto ring_fail;
266 }
267 }
268 rx_pos = BFE_RX_LIST_CNT;
269
270 /* Tag for TX mbufs */
271 error = bus_dma_tag_create(sc->bfe_parent_tag, 1, 0,
272 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
273 NULL, NULL,
274 MCLBYTES, BFE_MAXSEGS, MCLBYTES,
275 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
276 &sc->bfe_txbuf_tag);
277 if (error) {
278 device_printf(dev, "could not allocate dma tag for TX mbufs\n");
279 return(error);
280 }
281
282 /* Allocate dmamaps for TX list */
283 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
284 error = bus_dmamap_create(sc->bfe_txbuf_tag, BUS_DMA_WAITOK,
285 &sc->bfe_tx_ring[i].bfe_map);
286 if (error) {
287 tx_pos = i;
288 device_printf(dev, "cannot create DMA map for TX\n");
289 goto ring_fail;
290 }
291 }
292
293 return(0);
294
295 ring_fail:
296 if (sc->bfe_rxbuf_tag != NULL) {
297 for (i = 0; i < rx_pos; ++i) {
298 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
299 sc->bfe_rx_ring[i].bfe_map);
300 }
301 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
302 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
303 sc->bfe_rxbuf_tag = NULL;
304 }
305
306 if (sc->bfe_txbuf_tag != NULL) {
307 for (i = 0; i < tx_pos; ++i) {
308 bus_dmamap_destroy(sc->bfe_txbuf_tag,
309 sc->bfe_tx_ring[i].bfe_map);
310 }
311 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
312 sc->bfe_txbuf_tag = NULL;
313 }
314 return error;
315 }
316
317 static int
318 bfe_attach(device_t dev)
319 {
320 struct ifnet *ifp;
321 struct bfe_softc *sc;
322 int error = 0, rid;
323
324 sc = device_get_softc(dev);
325
326 sc->bfe_dev = dev;
327 callout_init(&sc->bfe_stat_timer);
328
329 #ifndef BURN_BRIDGES
330 /*
331 * Handle power management nonsense.
332 */
333 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
334 uint32_t membase, irq;
335
336 /* Save important PCI config data. */
337 membase = pci_read_config(dev, BFE_PCI_MEMLO, 4);
338 irq = pci_read_config(dev, BFE_PCI_INTLINE, 4);
339
340 /* Reset the power state. */
341 device_printf(dev, "chip is in D%d power mode"
342 " -- setting to D0\n", pci_get_powerstate(dev));
343
344 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
345
346 /* Restore PCI config data. */
347 pci_write_config(dev, BFE_PCI_MEMLO, membase, 4);
348 pci_write_config(dev, BFE_PCI_INTLINE, irq, 4);
349 }
350 #endif /* !BURN_BRIDGE */
351
352 /*
353 * Map control/status registers.
354 */
355 pci_enable_busmaster(dev);
356
357 rid = BFE_PCI_MEMLO;
358 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
359 RF_ACTIVE);
360 if (sc->bfe_res == NULL) {
361 device_printf(dev, "couldn't map memory\n");
362 return ENXIO;
363 }
364
365 sc->bfe_btag = rman_get_bustag(sc->bfe_res);
366 sc->bfe_bhandle = rman_get_bushandle(sc->bfe_res);
367
368 /* Allocate interrupt */
369 rid = 0;
370
371 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
372 RF_SHAREABLE | RF_ACTIVE);
373 if (sc->bfe_irq == NULL) {
374 device_printf(dev, "couldn't map interrupt\n");
375 error = ENXIO;
376 goto fail;
377 }
378
379 error = bfe_dma_alloc(dev);
380 if (error != 0) {
381 device_printf(dev, "failed to allocate DMA resources\n");
382 goto fail;
383 }
384
385 /* Set up ifnet structure */
386 ifp = &sc->arpcom.ac_if;
387 ifp->if_softc = sc;
388 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
389 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
390 ifp->if_ioctl = bfe_ioctl;
391 ifp->if_start = bfe_start;
392 ifp->if_watchdog = bfe_watchdog;
393 ifp->if_init = bfe_init;
394 ifp->if_mtu = ETHERMTU;
395 ifp->if_baudrate = 100000000;
396 ifp->if_capabilities |= IFCAP_VLAN_MTU;
397 ifp->if_capenable |= IFCAP_VLAN_MTU;
398 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
399 ifq_set_maxlen(&ifp->if_snd, BFE_TX_QLEN);
400 ifq_set_ready(&ifp->if_snd);
401
402 bfe_get_config(sc);
403
404 /* Reset the chip and turn on the PHY */
405 bfe_chip_reset(sc);
406
407 if (mii_phy_probe(dev, &sc->bfe_miibus,
408 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
409 device_printf(dev, "MII without any PHY!\n");
410 error = ENXIO;
411 goto fail;
412 }
413
414 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL);
415
416 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bfe_irq));
417
418 /*
419 * Hook interrupt last to avoid having to lock softc
420 */
421 error = bus_setup_intr(dev, sc->bfe_irq, INTR_MPSAFE,
422 bfe_intr, sc, &sc->bfe_intrhand,
423 sc->arpcom.ac_if.if_serializer);
424
425 if (error) {
426 ether_ifdetach(ifp);
427 device_printf(dev, "couldn't set up irq\n");
428 goto fail;
429 }
430 return 0;
431 fail:
432 bfe_detach(dev);
433 return(error);
434 }
435
436 static int
437 bfe_detach(device_t dev)
438 {
439 struct bfe_softc *sc = device_get_softc(dev);
440 struct ifnet *ifp = &sc->arpcom.ac_if;
441
442 if (device_is_attached(dev)) {
443 lwkt_serialize_enter(ifp->if_serializer);
444 bfe_stop(sc);
445 bfe_chip_reset(sc);
446 bus_teardown_intr(dev, sc->bfe_irq, sc->bfe_intrhand);
447 lwkt_serialize_exit(ifp->if_serializer);
448
449 ether_ifdetach(ifp);
450 }
451 if (sc->bfe_miibus != NULL)
452 device_delete_child(dev, sc->bfe_miibus);
453 bus_generic_detach(dev);
454
455 if (sc->bfe_irq != NULL)
456 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bfe_irq);
457
458 if (sc->bfe_res != NULL) {
459 bus_release_resource(dev, SYS_RES_MEMORY, BFE_PCI_MEMLO,
460 sc->bfe_res);
461 }
462 bfe_dma_free(sc);
463
464 return(0);
465 }
466
467 /*
468 * Stop all chip I/O so that the kernel's probe routines don't
469 * get confused by errant DMAs when rebooting.
470 */
471 static void
472 bfe_shutdown(device_t dev)
473 {
474 struct bfe_softc *sc = device_get_softc(dev);
475 struct ifnet *ifp = &sc->arpcom.ac_if;
476
477 lwkt_serialize_enter(ifp->if_serializer);
478 bfe_stop(sc);
479 lwkt_serialize_exit(ifp->if_serializer);
480 }
481
482 static int
483 bfe_miibus_readreg(device_t dev, int phy, int reg)
484 {
485 struct bfe_softc *sc;
486 uint32_t ret;
487
488 sc = device_get_softc(dev);
489 if (phy != sc->bfe_phyaddr)
490 return(0);
491 bfe_readphy(sc, reg, &ret);
492
493 return(ret);
494 }
495
496 static int
497 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
498 {
499 struct bfe_softc *sc;
500
501 sc = device_get_softc(dev);
502 if (phy != sc->bfe_phyaddr)
503 return(0);
504 bfe_writephy(sc, reg, val);
505
506 return(0);
507 }
508
509 static void
510 bfe_tx_ring_free(struct bfe_softc *sc)
511 {
512 int i;
513
514 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
515 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
516 bus_dmamap_unload(sc->bfe_txbuf_tag,
517 sc->bfe_tx_ring[i].bfe_map);
518 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
519 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
520 }
521 }
522 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
523 }
524
525 static void
526 bfe_rx_ring_free(struct bfe_softc *sc)
527 {
528 int i;
529
530 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
531 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
532 bus_dmamap_unload(sc->bfe_rxbuf_tag,
533 sc->bfe_rx_ring[i].bfe_map);
534 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
535 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
536 }
537 }
538 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
539 }
540
541 static int
542 bfe_list_rx_init(struct bfe_softc *sc)
543 {
544 int i, error;
545
546 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
547 error = bfe_newbuf(sc, i, 1);
548 if (error)
549 return(error);
550 }
551
552 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
553
554 sc->bfe_rx_cons = 0;
555
556 return(0);
557 }
558
559 static int
560 bfe_newbuf(struct bfe_softc *sc, int c, int init)
561 {
562 struct bfe_data *r;
563 bus_dmamap_t map;
564 bus_dma_segment_t seg;
565 struct mbuf *m;
566 int error, nsegs;
567
568 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
569 if (m == NULL)
570 return ENOBUFS;
571 m->m_len = m->m_pkthdr.len = MCLBYTES;
572
573 error = bus_dmamap_load_mbuf_segment(sc->bfe_rxbuf_tag,
574 sc->bfe_rx_tmpmap, m,
575 &seg, 1, &nsegs, BUS_DMA_NOWAIT);
576 if (error) {
577 m_freem(m);
578 if (init)
579 if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
580 return error;
581 }
582
583 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
584 r = &sc->bfe_rx_ring[c];
585
586 if (r->bfe_mbuf != NULL)
587 bus_dmamap_unload(sc->bfe_rxbuf_tag, r->bfe_map);
588
589 map = r->bfe_map;
590 r->bfe_map = sc->bfe_rx_tmpmap;
591 sc->bfe_rx_tmpmap = map;
592
593 r->bfe_mbuf = m;
594 r->bfe_paddr = seg.ds_addr;
595
596 bfe_setup_rxdesc(sc, c);
597 return 0;
598 }
599
600 static void
601 bfe_setup_rxdesc(struct bfe_softc *sc, int c)
602 {
603 struct bfe_rxheader *rx_header;
604 struct mbuf *m;
605 struct bfe_desc *d;
606 struct bfe_data *r;
607 uint32_t ctrl;
608
609 KKASSERT(c >= 0 && c < BFE_RX_LIST_CNT);
610 r = &sc->bfe_rx_ring[c];
611 d = &sc->bfe_rx_list[c];
612
613 KKASSERT(r->bfe_mbuf != NULL && r->bfe_paddr != 0);
614
615 m = r->bfe_mbuf;
616 rx_header = mtod(m, struct bfe_rxheader *);
617 rx_header->len = 0;
618 rx_header->flags = 0;
619 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map, BUS_DMASYNC_PREWRITE);
620
621 ctrl = ETHER_MAX_LEN + 32;
622 if (c == BFE_RX_LIST_CNT - 1)
623 ctrl |= BFE_DESC_EOT;
624
625 d->bfe_addr = r->bfe_paddr + BFE_PCI_DMA;
626 d->bfe_ctrl = ctrl;
627 }
628
629 static void
630 bfe_get_config(struct bfe_softc *sc)
631 {
632 uint8_t eeprom[128];
633
634 bfe_read_eeprom(sc, eeprom);
635
636 sc->arpcom.ac_enaddr[0] = eeprom[79];
637 sc->arpcom.ac_enaddr[1] = eeprom[78];
638 sc->arpcom.ac_enaddr[2] = eeprom[81];
639 sc->arpcom.ac_enaddr[3] = eeprom[80];
640 sc->arpcom.ac_enaddr[4] = eeprom[83];
641 sc->arpcom.ac_enaddr[5] = eeprom[82];
642
643 sc->bfe_phyaddr = eeprom[90] & 0x1f;
644 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
645
646 sc->bfe_core_unit = 0;
647 sc->bfe_dma_offset = BFE_PCI_DMA;
648 }
649
650 static void
651 bfe_pci_setup(struct bfe_softc *sc, uint32_t cores)
652 {
653 uint32_t bar_orig, val;
654
655 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
656 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
657
658 val = CSR_READ_4(sc, BFE_SBINTVEC);
659 val |= cores;
660 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
661
662 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
663 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
664 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
665
666 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
667 }
668
669 static void
670 bfe_clear_stats(struct bfe_softc *sc)
671 {
672 u_long reg;
673
674 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
675 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
676 CSR_READ_4(sc, reg);
677 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
678 CSR_READ_4(sc, reg);
679 }
680
681 static int
682 bfe_resetphy(struct bfe_softc *sc)
683 {
684 uint32_t val;
685
686 bfe_writephy(sc, 0, BMCR_RESET);
687 DELAY(100);
688 bfe_readphy(sc, 0, &val);
689 if (val & BMCR_RESET) {
690 if_printf(&sc->arpcom.ac_if,
691 "PHY Reset would not complete.\n");
692 return(ENXIO);
693 }
694 return(0);
695 }
696
697 static void
698 bfe_chip_halt(struct bfe_softc *sc)
699 {
700 /* disable interrupts - not that it actually does..*/
701 CSR_WRITE_4(sc, BFE_IMASK, 0);
702 CSR_READ_4(sc, BFE_IMASK);
703
704 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
705 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
706
707 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
708 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
709 DELAY(10);
710 }
711
712 static void
713 bfe_chip_reset(struct bfe_softc *sc)
714 {
715 uint32_t val;
716
717 /* Set the interrupt vector for the enet core */
718 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
719
720 /* is core up? */
721 val = CSR_READ_4(sc, BFE_SBTMSLOW) & (BFE_RESET | BFE_REJECT | BFE_CLOCK);
722 if (val == BFE_CLOCK) {
723 /* It is, so shut it down */
724 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
725 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
726 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
727 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
728 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
729 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
730 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE, 100, 0);
731 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
732 sc->bfe_rx_cons = 0;
733 }
734
735 bfe_core_reset(sc);
736 bfe_clear_stats(sc);
737
738 /*
739 * We want the phy registers to be accessible even when
740 * the driver is "downed" so initialize MDC preamble, frequency,
741 * and whether internal or external phy here.
742 */
743
744 /* 4402 has 62.5Mhz SB clock and internal phy */
745 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
746
747 /* Internal or external PHY? */
748 val = CSR_READ_4(sc, BFE_DEVCTRL);
749 if (!(val & BFE_IPP))
750 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
751 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
752 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
753 DELAY(100);
754 }
755
756 /* Enable CRC32 generation and set proper LED modes */
757 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
758
759 /* Reset or clear powerdown control bit */
760 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
761
762 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
763 BFE_LAZY_FC_MASK));
764
765 /*
766 * We don't want lazy interrupts, so just send them at the end of a
767 * frame, please
768 */
769 BFE_OR(sc, BFE_RCV_LAZY, 0);
770
771 /* Set max lengths, accounting for VLAN tags */
772 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
773 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
774
775 /* Set watermark XXX - magic */
776 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
777
778 /*
779 * Initialise DMA channels - not forgetting dma addresses need to be
780 * added to BFE_PCI_DMA
781 */
782 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
783 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
784
785 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
786 BFE_RX_CTRL_ENABLE);
787 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
788
789 bfe_resetphy(sc);
790 bfe_setupphy(sc);
791 }
792
793 static void
794 bfe_core_disable(struct bfe_softc *sc)
795 {
796 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
797 return;
798
799 /*
800 * Set reject, wait for it set, then wait for the core to stop being busy
801 * Then set reset and reject and enable the clocks
802 */
803 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
804 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
805 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
806 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
807 BFE_RESET));
808 CSR_READ_4(sc, BFE_SBTMSLOW);
809 DELAY(10);
810 /* Leave reset and reject set */
811 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
812 DELAY(10);
813 }
814
815 static void
816 bfe_core_reset(struct bfe_softc *sc)
817 {
818 uint32_t val;
819
820 /* Disable the core */
821 bfe_core_disable(sc);
822
823 /* and bring it back up */
824 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
825 CSR_READ_4(sc, BFE_SBTMSLOW);
826 DELAY(10);
827
828 /* Chip bug, clear SERR, IB and TO if they are set. */
829 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
830 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
831 val = CSR_READ_4(sc, BFE_SBIMSTATE);
832 if (val & (BFE_IBE | BFE_TO))
833 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
834
835 /* Clear reset and allow it to move through the core */
836 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
837 CSR_READ_4(sc, BFE_SBTMSLOW);
838 DELAY(10);
839
840 /* Leave the clock set */
841 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
842 CSR_READ_4(sc, BFE_SBTMSLOW);
843 DELAY(10);
844 }
845
846 static void
847 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
848 {
849 uint32_t val;
850
851 val = ((uint32_t) data[2]) << 24;
852 val |= ((uint32_t) data[3]) << 16;
853 val |= ((uint32_t) data[4]) << 8;
854 val |= ((uint32_t) data[5]);
855 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
856 val = (BFE_CAM_HI_VALID |
857 (((uint32_t) data[0]) << 8) |
858 (((uint32_t) data[1])));
859 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
860 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
861 ((uint32_t)index << BFE_CAM_INDEX_SHIFT)));
862 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
863 }
864
865 static void
866 bfe_set_rx_mode(struct bfe_softc *sc)
867 {
868 struct ifnet *ifp = &sc->arpcom.ac_if;
869 struct ifmultiaddr *ifma;
870 uint32_t val;
871 int i = 0;
872
873 val = CSR_READ_4(sc, BFE_RXCONF);
874
875 if (ifp->if_flags & IFF_PROMISC)
876 val |= BFE_RXCONF_PROMISC;
877 else
878 val &= ~BFE_RXCONF_PROMISC;
879
880 if (ifp->if_flags & IFF_BROADCAST)
881 val &= ~BFE_RXCONF_DBCAST;
882 else
883 val |= BFE_RXCONF_DBCAST;
884
885
886 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
887 bfe_cam_write(sc, sc->arpcom.ac_enaddr, i++);
888
889 if (ifp->if_flags & IFF_ALLMULTI) {
890 val |= BFE_RXCONF_ALLMULTI;
891 } else {
892 val &= ~BFE_RXCONF_ALLMULTI;
893 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
894 if (ifma->ifma_addr->sa_family != AF_LINK)
895 continue;
896 bfe_cam_write(sc,
897 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
898 }
899 }
900
901 CSR_WRITE_4(sc, BFE_RXCONF, val);
902 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
903 }
904
905 static void
906 bfe_dma_free(struct bfe_softc *sc)
907 {
908 int i;
909
910 if (sc->bfe_tx_tag != NULL) {
911 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
912 if (sc->bfe_tx_list != NULL) {
913 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
914 sc->bfe_tx_map);
915 sc->bfe_tx_list = NULL;
916 }
917 bus_dma_tag_destroy(sc->bfe_tx_tag);
918 sc->bfe_tx_tag = NULL;
919 }
920
921 if (sc->bfe_rx_tag != NULL) {
922 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
923 if (sc->bfe_rx_list != NULL) {
924 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
925 sc->bfe_rx_map);
926 sc->bfe_rx_list = NULL;
927 }
928 bus_dma_tag_destroy(sc->bfe_rx_tag);
929 sc->bfe_rx_tag = NULL;
930 }
931
932 if (sc->bfe_txbuf_tag != NULL) {
933 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
934 bus_dmamap_destroy(sc->bfe_txbuf_tag,
935 sc->bfe_tx_ring[i].bfe_map);
936 }
937 bus_dma_tag_destroy(sc->bfe_txbuf_tag);
938 sc->bfe_txbuf_tag = NULL;
939 }
940
941 if (sc->bfe_rxbuf_tag != NULL) {
942 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
943 bus_dmamap_destroy(sc->bfe_rxbuf_tag,
944 sc->bfe_rx_ring[i].bfe_map);
945 }
946 bus_dmamap_destroy(sc->bfe_rxbuf_tag, sc->bfe_rx_tmpmap);
947 bus_dma_tag_destroy(sc->bfe_rxbuf_tag);
948 sc->bfe_rxbuf_tag = NULL;
949 }
950
951 if (sc->bfe_parent_tag != NULL) {
952 bus_dma_tag_destroy(sc->bfe_parent_tag);
953 sc->bfe_parent_tag = NULL;
954 }
955 }
956
957 static void
958 bfe_read_eeprom(struct bfe_softc *sc, uint8_t *data)
959 {
960 long i;
961 uint16_t *ptr = (uint16_t *)data;
962
963 for (i = 0; i < 128; i += 2)
964 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
965 }
966
967 static int
968 bfe_wait_bit(struct bfe_softc *sc, uint32_t reg, uint32_t bit,
969 u_long timeout, const int clear)
970 {
971 u_long i;
972
973 for (i = 0; i < timeout; i++) {
974 uint32_t val = CSR_READ_4(sc, reg);
975
976 if (clear && !(val & bit))
977 break;
978 if (!clear && (val & bit))
979 break;
980 DELAY(10);
981 }
982 if (i == timeout) {
983 if_printf(&sc->arpcom.ac_if,
984 "BUG! Timeout waiting for bit %08x of register "
985 "%x to %s.\n", bit, reg,
986 (clear ? "clear" : "set"));
987 return -1;
988 }
989 return 0;
990 }
991
992 static int
993 bfe_readphy(struct bfe_softc *sc, uint32_t reg, uint32_t *val)
994 {
995 int err;
996
997 /* Clear MII ISR */
998 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
999 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1000 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1001 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1002 (reg << BFE_MDIO_RA_SHIFT) |
1003 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1004 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1005 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1006 return(err);
1007 }
1008
1009 static int
1010 bfe_writephy(struct bfe_softc *sc, uint32_t reg, uint32_t val)
1011 {
1012 int status;
1013
1014 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1015 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1016 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1017 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1018 (reg << BFE_MDIO_RA_SHIFT) |
1019 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1020 (val & BFE_MDIO_DATA_DATA)));
1021 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1022
1023 return status;
1024 }
1025
1026 /*
1027 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1028 * twice
1029 */
1030 static int
1031 bfe_setupphy(struct bfe_softc *sc)
1032 {
1033 uint32_t val;
1034
1035 /* Enable activity LED */
1036 bfe_readphy(sc, 26, &val);
1037 bfe_writephy(sc, 26, val & 0x7fff);
1038 bfe_readphy(sc, 26, &val);
1039
1040 /* Enable traffic meter LED mode */
1041 bfe_readphy(sc, 27, &val);
1042 bfe_writephy(sc, 27, val | (1 << 6));
1043
1044 return(0);
1045 }
1046
1047 static void
1048 bfe_stats_update(struct bfe_softc *sc)
1049 {
1050 u_long reg;
1051 uint32_t *val;
1052
1053 val = &sc->bfe_hwstats.tx_good_octets;
1054 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1055 *val++ += CSR_READ_4(sc, reg);
1056 val = &sc->bfe_hwstats.rx_good_octets;
1057 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1058 *val++ += CSR_READ_4(sc, reg);
1059 }
1060
1061 static void
1062 bfe_txeof(struct bfe_softc *sc)
1063 {
1064 struct ifnet *ifp = &sc->arpcom.ac_if;
1065 uint32_t i, chipidx;
1066
1067 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1068 chipidx /= sizeof(struct bfe_desc);
1069
1070 i = sc->bfe_tx_cons;
1071
1072 /* Go through the mbufs and free those that have been transmitted */
1073 while (i != chipidx) {
1074 struct bfe_data *r = &sc->bfe_tx_ring[i];
1075
1076 if (r->bfe_mbuf != NULL) {
1077 IFNET_STAT_INC(ifp, opackets, 1);
1078 bus_dmamap_unload(sc->bfe_txbuf_tag, r->bfe_map);
1079 m_freem(r->bfe_mbuf);
1080 r->bfe_mbuf = NULL;
1081 }
1082
1083 KKASSERT(sc->bfe_tx_cnt > 0);
1084 sc->bfe_tx_cnt--;
1085 BFE_INC(i, BFE_TX_LIST_CNT);
1086 }
1087
1088 if (i != sc->bfe_tx_cons) {
1089 sc->bfe_tx_cons = i;
1090
1091 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT)
1092 ifq_clr_oactive(&ifp->if_snd);
1093 }
1094 if (sc->bfe_tx_cnt == 0)
1095 ifp->if_timer = 0;
1096 }
1097
1098 /* Pass a received packet up the stack */
1099 static void
1100 bfe_rxeof(struct bfe_softc *sc)
1101 {
1102 struct ifnet *ifp = &sc->arpcom.ac_if;
1103 struct mbuf *m;
1104 struct bfe_rxheader *rxheader;
1105 struct bfe_data *r;
1106 uint32_t cons, status, current, len, flags;
1107
1108 cons = sc->bfe_rx_cons;
1109 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1110 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1111
1112 while (current != cons) {
1113 r = &sc->bfe_rx_ring[cons];
1114 bus_dmamap_sync(sc->bfe_rxbuf_tag, r->bfe_map,
1115 BUS_DMASYNC_POSTREAD);
1116
1117 KKASSERT(r->bfe_mbuf != NULL);
1118 m = r->bfe_mbuf;
1119 rxheader = mtod(m, struct bfe_rxheader*);
1120 len = rxheader->len - ETHER_CRC_LEN;
1121 flags = rxheader->flags;
1122
1123 /* flag an error and try again */
1124 if (len > ETHER_MAX_LEN + 32 || (flags & BFE_RX_FLAG_ERRORS)) {
1125 IFNET_STAT_INC(ifp, ierrors, 1);
1126 if (flags & BFE_RX_FLAG_SERR)
1127 IFNET_STAT_INC(ifp, collisions, 1);
1128
1129 bfe_setup_rxdesc(sc, cons);
1130 BFE_INC(cons, BFE_RX_LIST_CNT);
1131 continue;
1132 }
1133
1134 /* Go past the rx header */
1135 if (bfe_newbuf(sc, cons, 0) != 0) {
1136 bfe_setup_rxdesc(sc, cons);
1137 IFNET_STAT_INC(ifp, ierrors, 1);
1138 BFE_INC(cons, BFE_RX_LIST_CNT);
1139 continue;
1140 }
1141
1142 m_adj(m, BFE_RX_OFFSET);
1143 m->m_len = m->m_pkthdr.len = len;
1144
1145 IFNET_STAT_INC(ifp, ipackets, 1);
1146 m->m_pkthdr.rcvif = ifp;
1147
1148 ifp->if_input(ifp, m);
1149 BFE_INC(cons, BFE_RX_LIST_CNT);
1150 }
1151
1152 sc->bfe_rx_cons = cons;
1153 }
1154
1155 static void
1156 bfe_intr(void *xsc)
1157 {
1158 struct bfe_softc *sc = xsc;
1159 struct ifnet *ifp = &sc->arpcom.ac_if;
1160 uint32_t istat, imask, flag;
1161
1162 istat = CSR_READ_4(sc, BFE_ISTAT);
1163 imask = CSR_READ_4(sc, BFE_IMASK);
1164
1165 /*
1166 * Defer unsolicited interrupts - This is necessary because setting the
1167 * chips interrupt mask register to 0 doesn't actually stop the
1168 * interrupts
1169 */
1170 istat &= imask;
1171 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1172 CSR_READ_4(sc, BFE_ISTAT);
1173
1174 /* not expecting this interrupt, disregard it */
1175 if (istat == 0) {
1176 return;
1177 }
1178
1179 if (istat & BFE_ISTAT_ERRORS) {
1180 flag = CSR_READ_4(sc, BFE_DMATX_STAT);
1181 if (flag & BFE_STAT_EMASK)
1182 IFNET_STAT_INC(ifp, oerrors, 1);
1183
1184 flag = CSR_READ_4(sc, BFE_DMARX_STAT);
1185 if (flag & BFE_RX_FLAG_ERRORS)
1186 IFNET_STAT_INC(ifp, ierrors, 1);
1187
1188 ifp->if_flags &= ~IFF_RUNNING;
1189 bfe_init(sc);
1190 }
1191
1192 /* A packet was received */
1193 if (istat & BFE_ISTAT_RX)
1194 bfe_rxeof(sc);
1195
1196 /* A packet was sent */
1197 if (istat & BFE_ISTAT_TX)
1198 bfe_txeof(sc);
1199
1200 /* We have packets pending, fire them out */
1201 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
1202 if_devstart(ifp);
1203 }
1204
1205 static int
1206 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head, uint32_t *txidx)
1207 {
1208 bus_dma_segment_t segs[BFE_MAXSEGS];
1209 bus_dmamap_t map;
1210 int i, first_idx, last_idx, cur, error, maxsegs, nsegs;
1211
1212 KKASSERT(sc->bfe_tx_cnt + BFE_SPARE_TXDESC < BFE_TX_LIST_CNT);
1213 maxsegs = BFE_TX_LIST_CNT - sc->bfe_tx_cnt - BFE_SPARE_TXDESC;
1214 if (maxsegs > BFE_MAXSEGS)
1215 maxsegs = BFE_MAXSEGS;
1216
1217 first_idx = *txidx;
1218 map = sc->bfe_tx_ring[first_idx].bfe_map;
1219
1220 error = bus_dmamap_load_mbuf_defrag(sc->bfe_txbuf_tag, map, m_head,
1221 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1222 if (error)
1223 goto fail;
1224 bus_dmamap_sync(sc->bfe_txbuf_tag, map, BUS_DMASYNC_PREWRITE);
1225
1226 last_idx = -1;
1227 cur = first_idx;
1228 for (i = 0; i < nsegs; ++i) {
1229 struct bfe_desc *d;
1230 uint32_t ctrl;
1231
1232 ctrl = BFE_DESC_LEN & segs[i].ds_len;
1233 ctrl |= BFE_DESC_IOC; /* always interrupt */
1234 if (cur == BFE_TX_LIST_CNT - 1) {
1235 /*
1236 * Tell the chip to wrap to the
1237 * start of the descriptor list.
1238 */
1239 ctrl |= BFE_DESC_EOT;
1240 }
1241
1242 d = &sc->bfe_tx_list[cur];
1243 d->bfe_addr = segs[i].ds_addr + BFE_PCI_DMA;
1244 d->bfe_ctrl = ctrl;
1245
1246 last_idx = cur;
1247 BFE_INC(cur, BFE_TX_LIST_CNT);
1248 }
1249 KKASSERT(last_idx >= 0);
1250
1251 /* End of the frame */
1252 sc->bfe_tx_list[last_idx].bfe_ctrl |= BFE_DESC_EOF;
1253
1254 /*
1255 * Set start of the frame on the first fragment,
1256 * _after_ all of the fragments are setup.
1257 */
1258 sc->bfe_tx_list[first_idx].bfe_ctrl |= BFE_DESC_SOF;
1259
1260 sc->bfe_tx_ring[first_idx].bfe_map = sc->bfe_tx_ring[last_idx].bfe_map;
1261 sc->bfe_tx_ring[last_idx].bfe_map = map;
1262 sc->bfe_tx_ring[last_idx].bfe_mbuf = *m_head;
1263
1264 *txidx = cur;
1265 sc->bfe_tx_cnt += nsegs;
1266 return 0;
1267 fail:
1268 m_freem(*m_head);
1269 *m_head = NULL;
1270 return error;
1271 }
1272
1273 /*
1274 * Set up to transmit a packet
1275 */
1276 static void
1277 bfe_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1278 {
1279 struct bfe_softc *sc = ifp->if_softc;
1280 struct mbuf *m_head = NULL;
1281 int idx, need_trans;
1282
1283 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1284 ASSERT_SERIALIZED(ifp->if_serializer);
1285
1286 /*
1287 * Not much point trying to send if the link is down
1288 * or we have nothing to send.
1289 */
1290 if (!sc->bfe_link) {
1291 ifq_purge(&ifp->if_snd);
1292 return;
1293 }
1294
1295 if (ifq_is_oactive(&ifp->if_snd))
1296 return;
1297
1298 idx = sc->bfe_tx_prod;
1299
1300 need_trans = 0;
1301 while (!ifq_is_empty(&ifp->if_snd)) {
1302 if (sc->bfe_tx_cnt + BFE_SPARE_TXDESC >= BFE_TX_LIST_CNT) {
1303 ifq_set_oactive(&ifp->if_snd);
1304 break;
1305 }
1306
1307 m_head = ifq_dequeue(&ifp->if_snd);
1308 if (m_head == NULL)
1309 break;
1310
1311 /*
1312 * Pack the data into the tx ring. If we don't have
1313 * enough room, let the chip drain the ring.
1314 */
1315 if (bfe_encap(sc, &m_head, &idx)) {
1316 /* m_head is freed by re_encap(), if we reach here */
1317 IFNET_STAT_INC(ifp, oerrors, 1);
1318
1319 if (sc->bfe_tx_cnt > 0) {
1320 ifq_set_oactive(&ifp->if_snd);
1321 break;
1322 } else {
1323 /*
1324 * ifq_set_oactive could not be called under
1325 * this situation, since except up/down,
1326 * nothing will call ifq_clr_oactive.
1327 *
1328 * Let's just keep draining the ifq ...
1329 */
1330 continue;
1331 }
1332 }
1333 need_trans = 1;
1334
1335 /*
1336 * If there's a BPF listener, bounce a copy of this frame
1337 * to him.
1338 */
1339 BPF_MTAP(ifp, m_head);
1340 }
1341
1342 if (!need_trans)
1343 return;
1344
1345 sc->bfe_tx_prod = idx;
1346
1347 /* Transmit - twice due to apparent hardware bug */
1348 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1349 CSR_WRITE_4(sc, BFE_DMATX_PTR, idx * sizeof(struct bfe_desc));
1350
1351 /*
1352 * Set a timeout in case the chip goes out to lunch.
1353 */
1354 ifp->if_timer = 5;
1355 }
1356
1357 static void
1358 bfe_init(void *xsc)
1359 {
1360 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1361 struct ifnet *ifp = &sc->arpcom.ac_if;
1362
1363 ASSERT_SERIALIZED(ifp->if_serializer);
1364
1365 if (ifp->if_flags & IFF_RUNNING)
1366 return;
1367
1368 bfe_stop(sc);
1369 bfe_chip_reset(sc);
1370
1371 if (bfe_list_rx_init(sc) == ENOBUFS) {
1372 if_printf(ifp, "bfe_init failed. "
1373 " Not enough memory for list buffers\n");
1374 bfe_stop(sc);
1375 return;
1376 }
1377
1378 bfe_set_rx_mode(sc);
1379
1380 /* Enable the chip and core */
1381 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1382 /* Enable interrupts */
1383 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1384
1385 bfe_ifmedia_upd(ifp);
1386 ifp->if_flags |= IFF_RUNNING;
1387 ifq_clr_oactive(&ifp->if_snd);
1388
1389 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1390 }
1391
1392 /*
1393 * Set media options.
1394 */
1395 static int
1396 bfe_ifmedia_upd(struct ifnet *ifp)
1397 {
1398 struct bfe_softc *sc = ifp->if_softc;
1399 struct mii_data *mii;
1400
1401 ASSERT_SERIALIZED(ifp->if_serializer);
1402
1403 mii = device_get_softc(sc->bfe_miibus);
1404 sc->bfe_link = 0;
1405 if (mii->mii_instance) {
1406 struct mii_softc *miisc;
1407 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1408 miisc = LIST_NEXT(miisc, mii_list))
1409 mii_phy_reset(miisc);
1410 }
1411 mii_mediachg(mii);
1412
1413 bfe_setupphy(sc);
1414
1415 return(0);
1416 }
1417
1418 /*
1419 * Report current media status.
1420 */
1421 static void
1422 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1423 {
1424 struct bfe_softc *sc = ifp->if_softc;
1425 struct mii_data *mii;
1426
1427 ASSERT_SERIALIZED(ifp->if_serializer);
1428
1429 mii = device_get_softc(sc->bfe_miibus);
1430 mii_pollstat(mii);
1431 ifmr->ifm_active = mii->mii_media_active;
1432 ifmr->ifm_status = mii->mii_media_status;
1433 }
1434
1435 static int
1436 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1437 {
1438 struct bfe_softc *sc = ifp->if_softc;
1439 struct ifreq *ifr = (struct ifreq *) data;
1440 struct mii_data *mii;
1441 int error = 0;
1442
1443 ASSERT_SERIALIZED(ifp->if_serializer);
1444
1445 switch (command) {
1446 case SIOCSIFFLAGS:
1447 if (ifp->if_flags & IFF_UP)
1448 if (ifp->if_flags & IFF_RUNNING)
1449 bfe_set_rx_mode(sc);
1450 else
1451 bfe_init(sc);
1452 else if (ifp->if_flags & IFF_RUNNING)
1453 bfe_stop(sc);
1454 break;
1455 case SIOCADDMULTI:
1456 case SIOCDELMULTI:
1457 if (ifp->if_flags & IFF_RUNNING)
1458 bfe_set_rx_mode(sc);
1459 break;
1460 case SIOCGIFMEDIA:
1461 case SIOCSIFMEDIA:
1462 mii = device_get_softc(sc->bfe_miibus);
1463 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
1464 command);
1465 break;
1466 default:
1467 error = ether_ioctl(ifp, command, data);
1468 break;
1469 }
1470 return error;
1471 }
1472
1473 static void
1474 bfe_watchdog(struct ifnet *ifp)
1475 {
1476 struct bfe_softc *sc = ifp->if_softc;
1477
1478 ASSERT_SERIALIZED(ifp->if_serializer);
1479
1480 if_printf(ifp, "watchdog timeout -- resetting\n");
1481
1482 ifp->if_flags &= ~IFF_RUNNING;
1483 bfe_init(sc);
1484
1485 IFNET_STAT_INC(ifp, oerrors, 1);
1486 }
1487
1488 static void
1489 bfe_tick(void *xsc)
1490 {
1491 struct bfe_softc *sc = xsc;
1492 struct mii_data *mii;
1493 struct ifnet *ifp = &sc->arpcom.ac_if;
1494
1495 mii = device_get_softc(sc->bfe_miibus);
1496
1497 lwkt_serialize_enter(ifp->if_serializer);
1498
1499 bfe_stats_update(sc);
1500 callout_reset(&sc->bfe_stat_timer, hz, bfe_tick, sc);
1501
1502 if (sc->bfe_link == 0) {
1503 mii_tick(mii);
1504 if (!sc->bfe_link && mii->mii_media_status & IFM_ACTIVE &&
1505 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1506 sc->bfe_link++;
1507 }
1508 if (!sc->bfe_link)
1509 sc->bfe_link++;
1510 }
1511 lwkt_serialize_exit(ifp->if_serializer);
1512 }
1513
1514 /*
1515 * Stop the adapter and free any mbufs allocated to the
1516 * RX and TX lists.
1517 */
1518 static void
1519 bfe_stop(struct bfe_softc *sc)
1520 {
1521 struct ifnet *ifp = &sc->arpcom.ac_if;
1522
1523 ASSERT_SERIALIZED(ifp->if_serializer);
1524
1525 callout_stop(&sc->bfe_stat_timer);
1526
1527 bfe_chip_halt(sc);
1528 bfe_tx_ring_free(sc);
1529 bfe_rx_ring_free(sc);
1530
1531 ifp->if_flags &= ~IFF_RUNNING;
1532 ifq_clr_oactive(&ifp->if_snd);
1533 }
Cache object: e059cfb80b862fff3301894562f43322
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