The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/netif/bge/if_bge.c

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    1 /*
    2  * Copyright (c) 2001 Wind River Systems
    3  * Copyright (c) 1997, 1998, 1999, 2001
    4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. All advertising materials mentioning features or use of this software
   15  *    must display the following acknowledgement:
   16  *      This product includes software developed by Bill Paul.
   17  * 4. Neither the name of the author nor the names of any co-contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
   25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   31  * THE POSSIBILITY OF SUCH DAMAGE.
   32  *
   33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
   34  */
   35 
   36 /*
   37  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
   38  * 
   39  * Written by Bill Paul <wpaul@windriver.com>
   40  * Senior Engineer, Wind River Systems
   41  */
   42 
   43 /*
   44  * The Broadcom BCM5700 is based on technology originally developed by
   45  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
   46  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
   47  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
   48  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
   49  * frames, highly configurable RX filtering, and 16 RX and TX queues
   50  * (which, along with RX filter rules, can be used for QOS applications).
   51  * Other features, such as TCP segmentation, may be available as part
   52  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
   53  * firmware images can be stored in hardware and need not be compiled
   54  * into the driver.
   55  *
   56  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
   57  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
   58  * 
   59  * The BCM5701 is a single-chip solution incorporating both the BCM5700
   60  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
   61  * does not support external SSRAM.
   62  *
   63  * Broadcom also produces a variation of the BCM5700 under the "Altima"
   64  * brand name, which is functionally similar but lacks PCI-X support.
   65  *
   66  * Without external SSRAM, you can only have at most 4 TX rings,
   67  * and the use of the mini RX ring is disabled. This seems to imply
   68  * that these features are simply not available on the BCM5701. As a
   69  * result, this driver does not implement any support for the mini RX
   70  * ring.
   71  */
   72 
   73 #include "opt_ifpoll.h"
   74 
   75 #include <sys/param.h>
   76 #include <sys/bus.h>
   77 #include <sys/endian.h>
   78 #include <sys/kernel.h>
   79 #include <sys/ktr.h>
   80 #include <sys/interrupt.h>
   81 #include <sys/mbuf.h>
   82 #include <sys/malloc.h>
   83 #include <sys/queue.h>
   84 #include <sys/rman.h>
   85 #include <sys/serialize.h>
   86 #include <sys/socket.h>
   87 #include <sys/sockio.h>
   88 #include <sys/sysctl.h>
   89 
   90 #include <netinet/ip.h>
   91 #include <netinet/tcp.h>
   92 
   93 #include <net/bpf.h>
   94 #include <net/ethernet.h>
   95 #include <net/if.h>
   96 #include <net/if_arp.h>
   97 #include <net/if_dl.h>
   98 #include <net/if_media.h>
   99 #include <net/if_poll.h>
  100 #include <net/if_types.h>
  101 #include <net/ifq_var.h>
  102 #include <net/vlan/if_vlan_var.h>
  103 #include <net/vlan/if_vlan_ether.h>
  104 
  105 #include <dev/netif/mii_layer/mii.h>
  106 #include <dev/netif/mii_layer/miivar.h>
  107 #include <dev/netif/mii_layer/brgphyreg.h>
  108 
  109 #include "pcidevs.h"
  110 #include <bus/pci/pcireg.h>
  111 #include <bus/pci/pcivar.h>
  112 
  113 #include <dev/netif/bge/if_bgereg.h>
  114 #include <dev/netif/bge/if_bgevar.h>
  115 
  116 /* "device miibus" required.  See GENERIC if you get errors here. */
  117 #include "miibus_if.h"
  118 
  119 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP)
  120 
  121 #define BGE_RESET_SHUTDOWN      0
  122 #define BGE_RESET_START         1
  123 #define BGE_RESET_SUSPEND       2
  124 
  125 static const struct bge_type {
  126         uint16_t                bge_vid;
  127         uint16_t                bge_did;
  128         char                    *bge_name;
  129 } bge_devs[] = {
  130         { PCI_VENDOR_3COM, PCI_PRODUCT_3COM_3C996,
  131                 "3COM 3C996 Gigabit Ethernet" },
  132 
  133         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
  134                 "Alteon BCM5700 Gigabit Ethernet" },
  135         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
  136                 "Alteon BCM5701 Gigabit Ethernet" },
  137 
  138         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
  139                 "Altima AC1000 Gigabit Ethernet" },
  140         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
  141                 "Altima AC1002 Gigabit Ethernet" },
  142         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
  143                 "Altima AC9100 Gigabit Ethernet" },
  144 
  145         { PCI_VENDOR_APPLE, PCI_PRODUCT_APPLE_BCM5701,
  146                 "Apple BCM5701 Gigabit Ethernet" },
  147 
  148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
  149                 "Broadcom BCM5700 Gigabit Ethernet" },
  150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
  151                 "Broadcom BCM5701 Gigabit Ethernet" },
  152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702,
  153                 "Broadcom BCM5702 Gigabit Ethernet" },
  154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
  155                 "Broadcom BCM5702X Gigabit Ethernet" },
  156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
  157                 "Broadcom BCM5702 Gigabit Ethernet" },
  158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703,
  159                 "Broadcom BCM5703 Gigabit Ethernet" },
  160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
  161                 "Broadcom BCM5703X Gigabit Ethernet" },
  162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
  163                 "Broadcom BCM5703 Gigabit Ethernet" },
  164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
  165                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
  166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
  167                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
  168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S_ALT,
  169                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
  170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
  171                 "Broadcom BCM5705 Gigabit Ethernet" },
  172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705F,
  173                 "Broadcom BCM5705F Gigabit Ethernet" },
  174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
  175                 "Broadcom BCM5705K Gigabit Ethernet" },
  176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
  177                 "Broadcom BCM5705M Gigabit Ethernet" },
  178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
  179                 "Broadcom BCM5705M Gigabit Ethernet" },
  180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
  181                 "Broadcom BCM5714C Gigabit Ethernet" },
  182         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714S,
  183                 "Broadcom BCM5714S Gigabit Ethernet" },
  184         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715,
  185                 "Broadcom BCM5715 Gigabit Ethernet" },
  186         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5715S,
  187                 "Broadcom BCM5715S Gigabit Ethernet" },
  188         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5720,
  189                 "Broadcom BCM5720 Gigabit Ethernet" },
  190         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
  191                 "Broadcom BCM5721 Gigabit Ethernet" },
  192         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5722,
  193                 "Broadcom BCM5722 Gigabit Ethernet" },
  194         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5723,
  195                 "Broadcom BCM5723 Gigabit Ethernet" },
  196         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
  197                 "Broadcom BCM5750 Gigabit Ethernet" },
  198         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
  199                 "Broadcom BCM5750M Gigabit Ethernet" },
  200         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
  201                 "Broadcom BCM5751 Gigabit Ethernet" },
  202         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751F,
  203                 "Broadcom BCM5751F Gigabit Ethernet" },
  204         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
  205                 "Broadcom BCM5751M Gigabit Ethernet" },
  206         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752,
  207                 "Broadcom BCM5752 Gigabit Ethernet" },
  208         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5752M,
  209                 "Broadcom BCM5752M Gigabit Ethernet" },
  210         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753,
  211                 "Broadcom BCM5753 Gigabit Ethernet" },
  212         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753F,
  213                 "Broadcom BCM5753F Gigabit Ethernet" },
  214         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5753M,
  215                 "Broadcom BCM5753M Gigabit Ethernet" },
  216         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754,
  217                 "Broadcom BCM5754 Gigabit Ethernet" },
  218         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5754M,
  219                 "Broadcom BCM5754M Gigabit Ethernet" },
  220         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755,
  221                 "Broadcom BCM5755 Gigabit Ethernet" },
  222         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5755M,
  223                 "Broadcom BCM5755M Gigabit Ethernet" },
  224         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5756,
  225                 "Broadcom BCM5756 Gigabit Ethernet" },
  226         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761,
  227                 "Broadcom BCM5761 Gigabit Ethernet" },
  228         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761E,
  229                 "Broadcom BCM5761E Gigabit Ethernet" },
  230         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761S,
  231                 "Broadcom BCM5761S Gigabit Ethernet" },
  232         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5761SE,
  233                 "Broadcom BCM5761SE Gigabit Ethernet" },
  234         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5764,
  235                 "Broadcom BCM5764 Gigabit Ethernet" },
  236         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780,
  237                 "Broadcom BCM5780 Gigabit Ethernet" },
  238         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5780S,
  239                 "Broadcom BCM5780S Gigabit Ethernet" },
  240         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5781,
  241                 "Broadcom BCM5781 Gigabit Ethernet" },
  242         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
  243                 "Broadcom BCM5782 Gigabit Ethernet" },
  244         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5784,
  245                 "Broadcom BCM5784 Gigabit Ethernet" },
  246         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785F,
  247                 "Broadcom BCM5785F Gigabit Ethernet" },
  248         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5785G,
  249                 "Broadcom BCM5785G Gigabit Ethernet" },
  250         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5786,
  251                 "Broadcom BCM5786 Gigabit Ethernet" },
  252         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787,
  253                 "Broadcom BCM5787 Gigabit Ethernet" },
  254         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787F,
  255                 "Broadcom BCM5787F Gigabit Ethernet" },
  256         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5787M,
  257                 "Broadcom BCM5787M Gigabit Ethernet" },
  258         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
  259                 "Broadcom BCM5788 Gigabit Ethernet" },
  260         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
  261                 "Broadcom BCM5789 Gigabit Ethernet" },
  262         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
  263                 "Broadcom BCM5901 Fast Ethernet" },
  264         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
  265                 "Broadcom BCM5901A2 Fast Ethernet" },
  266         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5903M,
  267                 "Broadcom BCM5903M Fast Ethernet" },
  268         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906,
  269                 "Broadcom BCM5906 Fast Ethernet"},
  270         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5906M,
  271                 "Broadcom BCM5906M Fast Ethernet"},
  272         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57760,
  273                 "Broadcom BCM57760 Gigabit Ethernet"},
  274         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57780,
  275                 "Broadcom BCM57780 Gigabit Ethernet"},
  276         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57788,
  277                 "Broadcom BCM57788 Gigabit Ethernet"},
  278         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM57790,
  279                 "Broadcom BCM57790 Gigabit Ethernet"},
  280         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
  281                 "SysKonnect Gigabit Ethernet" },
  282 
  283         { 0, 0, NULL }
  284 };
  285 
  286 #define BGE_IS_JUMBO_CAPABLE(sc)        ((sc)->bge_flags & BGE_FLAG_JUMBO)
  287 #define BGE_IS_5700_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
  288 #define BGE_IS_5705_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5705_PLUS)
  289 #define BGE_IS_5714_FAMILY(sc)          ((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
  290 #define BGE_IS_575X_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_575X_PLUS)
  291 #define BGE_IS_5755_PLUS(sc)            ((sc)->bge_flags & BGE_FLAG_5755_PLUS)
  292 #define BGE_IS_5788(sc)                 ((sc)->bge_flags & BGE_FLAG_5788)
  293 
  294 #define BGE_IS_CRIPPLED(sc)             \
  295         (BGE_IS_5788((sc)) || (sc)->bge_asicrev == BGE_ASICREV_BCM5700)
  296 
  297 typedef int     (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
  298 
  299 static int      bge_probe(device_t);
  300 static int      bge_attach(device_t);
  301 static int      bge_detach(device_t);
  302 static void     bge_txeof(struct bge_softc *, uint16_t);
  303 static void     bge_rxeof(struct bge_softc *, uint16_t, int);
  304 
  305 static void     bge_tick(void *);
  306 static void     bge_stats_update(struct bge_softc *);
  307 static void     bge_stats_update_regs(struct bge_softc *);
  308 static struct mbuf *
  309                 bge_defrag_shortdma(struct mbuf *);
  310 static int      bge_encap(struct bge_softc *, struct mbuf **,
  311                     uint32_t *, int *);
  312 static void     bge_xmit(struct bge_softc *, uint32_t);
  313 static int      bge_setup_tso(struct bge_softc *, struct mbuf **,
  314                     uint16_t *, uint16_t *);
  315 
  316 #ifdef IFPOLL_ENABLE
  317 static void     bge_npoll(struct ifnet *, struct ifpoll_info *);
  318 static void     bge_npoll_compat(struct ifnet *, void *, int );
  319 #endif
  320 static void     bge_intr_crippled(void *);
  321 static void     bge_intr_legacy(void *);
  322 static void     bge_msi(void *);
  323 static void     bge_msi_oneshot(void *);
  324 static void     bge_intr(struct bge_softc *);
  325 static void     bge_enable_intr(struct bge_softc *);
  326 static void     bge_disable_intr(struct bge_softc *);
  327 static void     bge_start(struct ifnet *, struct ifaltq_subque *);
  328 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
  329 static void     bge_init(void *);
  330 static void     bge_stop(struct bge_softc *);
  331 static void     bge_watchdog(struct ifnet *);
  332 static void     bge_shutdown(device_t);
  333 static int      bge_suspend(device_t);
  334 static int      bge_resume(device_t);
  335 static int      bge_ifmedia_upd(struct ifnet *);
  336 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
  337 
  338 static uint8_t  bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
  339 static int      bge_read_nvram(struct bge_softc *, caddr_t, int, int);
  340 
  341 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
  342 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
  343 
  344 static void     bge_setmulti(struct bge_softc *);
  345 static void     bge_setpromisc(struct bge_softc *);
  346 static void     bge_enable_msi(struct bge_softc *sc);
  347 
  348 static int      bge_alloc_jumbo_mem(struct bge_softc *);
  349 static void     bge_free_jumbo_mem(struct bge_softc *);
  350 static struct bge_jslot
  351                 *bge_jalloc(struct bge_softc *);
  352 static void     bge_jfree(void *);
  353 static void     bge_jref(void *);
  354 static int      bge_newbuf_std(struct bge_softc *, int, int);
  355 static int      bge_newbuf_jumbo(struct bge_softc *, int, int);
  356 static void     bge_setup_rxdesc_std(struct bge_softc *, int);
  357 static void     bge_setup_rxdesc_jumbo(struct bge_softc *, int);
  358 static int      bge_init_rx_ring_std(struct bge_softc *);
  359 static void     bge_free_rx_ring_std(struct bge_softc *);
  360 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
  361 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
  362 static void     bge_free_tx_ring(struct bge_softc *);
  363 static int      bge_init_tx_ring(struct bge_softc *);
  364 
  365 static int      bge_chipinit(struct bge_softc *);
  366 static int      bge_blockinit(struct bge_softc *);
  367 static void     bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
  368 
  369 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
  370 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
  371 #ifdef notdef
  372 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
  373 #endif
  374 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
  375 static void     bge_writemem_direct(struct bge_softc *, uint32_t, uint32_t);
  376 static void     bge_writembx(struct bge_softc *, int, int);
  377 
  378 static int      bge_miibus_readreg(device_t, int, int);
  379 static int      bge_miibus_writereg(device_t, int, int, int);
  380 static void     bge_miibus_statchg(device_t);
  381 static void     bge_bcm5700_link_upd(struct bge_softc *, uint32_t);
  382 static void     bge_tbi_link_upd(struct bge_softc *, uint32_t);
  383 static void     bge_copper_link_upd(struct bge_softc *, uint32_t);
  384 static void     bge_autopoll_link_upd(struct bge_softc *, uint32_t);
  385 static void     bge_link_poll(struct bge_softc *);
  386 
  387 static void     bge_reset(struct bge_softc *);
  388 
  389 static int      bge_dma_alloc(struct bge_softc *);
  390 static void     bge_dma_free(struct bge_softc *);
  391 static int      bge_dma_block_alloc(struct bge_softc *, bus_size_t,
  392                                     bus_dma_tag_t *, bus_dmamap_t *,
  393                                     void **, bus_addr_t *);
  394 static void     bge_dma_block_free(bus_dma_tag_t, bus_dmamap_t, void *);
  395 
  396 static int      bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
  397 static int      bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
  398 static int      bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
  399 static int      bge_get_eaddr(struct bge_softc *, uint8_t[]);
  400 
  401 static void     bge_coal_change(struct bge_softc *);
  402 static int      bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS);
  403 static int      bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS);
  404 static int      bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS);
  405 static int      bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS);
  406 static int      bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
  407 static int      bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS);
  408 static int      bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS);
  409 static int      bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS);
  410 static int      bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *,
  411                     int, int, uint32_t);
  412 
  413 static void     bge_sig_post_reset(struct bge_softc *, int);
  414 static void     bge_sig_legacy(struct bge_softc *, int);
  415 static void     bge_sig_pre_reset(struct bge_softc *, int);
  416 static void     bge_stop_fw(struct bge_softc *);
  417 static void     bge_asf_driver_up(struct bge_softc *);
  418 
  419 /*
  420  * Set following tunable to 1 for some IBM blade servers with the DNLK
  421  * switch module. Auto negotiation is broken for those configurations.
  422  */
  423 static int      bge_fake_autoneg = 0;
  424 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
  425 
  426 static int      bge_msi_enable = 1;
  427 TUNABLE_INT("hw.bge.msi.enable", &bge_msi_enable);
  428 
  429 static int      bge_allow_asf = 1;
  430 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf);
  431 
  432 #if !defined(KTR_IF_BGE)
  433 #define KTR_IF_BGE      KTR_ALL
  434 #endif
  435 KTR_INFO_MASTER(if_bge);
  436 KTR_INFO(KTR_IF_BGE, if_bge, intr, 0, "intr");
  437 KTR_INFO(KTR_IF_BGE, if_bge, rx_pkt, 1, "rx_pkt");
  438 KTR_INFO(KTR_IF_BGE, if_bge, tx_pkt, 2, "tx_pkt");
  439 #define logif(name)     KTR_LOG(if_bge_ ## name)
  440 
  441 static device_method_t bge_methods[] = {
  442         /* Device interface */
  443         DEVMETHOD(device_probe,         bge_probe),
  444         DEVMETHOD(device_attach,        bge_attach),
  445         DEVMETHOD(device_detach,        bge_detach),
  446         DEVMETHOD(device_shutdown,      bge_shutdown),
  447         DEVMETHOD(device_suspend,       bge_suspend),
  448         DEVMETHOD(device_resume,        bge_resume),
  449 
  450         /* bus interface */
  451         DEVMETHOD(bus_print_child,      bus_generic_print_child),
  452         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
  453 
  454         /* MII interface */
  455         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
  456         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
  457         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
  458 
  459         DEVMETHOD_END
  460 };
  461 
  462 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
  463 static devclass_t bge_devclass;
  464 
  465 DECLARE_DUMMY_MODULE(if_bge);
  466 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, NULL, NULL);
  467 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, NULL, NULL);
  468 
  469 static uint32_t
  470 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
  471 {
  472         device_t dev = sc->bge_dev;
  473         uint32_t val;
  474 
  475         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
  476             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
  477                 return 0;
  478 
  479         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
  480         val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
  481         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
  482         return (val);
  483 }
  484 
  485 static void
  486 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
  487 {
  488         device_t dev = sc->bge_dev;
  489 
  490         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
  491             off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
  492                 return;
  493 
  494         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
  495         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
  496         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
  497 }
  498 
  499 #ifdef notdef
  500 static uint32_t
  501 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
  502 {
  503         device_t dev = sc->bge_dev;
  504 
  505         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
  506         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
  507 }
  508 #endif
  509 
  510 static void
  511 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
  512 {
  513         device_t dev = sc->bge_dev;
  514 
  515         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
  516         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
  517 }
  518 
  519 static void
  520 bge_writemem_direct(struct bge_softc *sc, uint32_t off, uint32_t val)
  521 {
  522         CSR_WRITE_4(sc, off, val);
  523 }
  524 
  525 static void
  526 bge_writembx(struct bge_softc *sc, int off, int val)
  527 {
  528         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
  529                 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
  530 
  531         CSR_WRITE_4(sc, off, val);
  532         if (sc->bge_mbox_reorder)
  533                 CSR_READ_4(sc, off);
  534 }
  535 
  536 static uint8_t
  537 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
  538 {
  539         uint32_t access, byte = 0;
  540         int i;
  541 
  542         /* Lock. */
  543         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
  544         for (i = 0; i < 8000; i++) {
  545                 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
  546                         break;
  547                 DELAY(20);
  548         }
  549         if (i == 8000)
  550                 return (1);
  551 
  552         /* Enable access. */
  553         access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
  554         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
  555 
  556         CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
  557         CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
  558         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
  559                 DELAY(10);
  560                 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
  561                         DELAY(10);
  562                         break;
  563                 }
  564         }
  565 
  566         if (i == BGE_TIMEOUT * 10) {
  567                 if_printf(&sc->arpcom.ac_if, "nvram read timed out\n");
  568                 return (1);
  569         }
  570 
  571         /* Get result. */
  572         byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
  573 
  574         *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
  575 
  576         /* Disable access. */
  577         CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
  578 
  579         /* Unlock. */
  580         CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
  581         CSR_READ_4(sc, BGE_NVRAM_SWARB);
  582 
  583         return (0);
  584 }
  585 
  586 /*
  587  * Read a sequence of bytes from NVRAM.
  588  */
  589 static int
  590 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
  591 {
  592         int err = 0, i;
  593         uint8_t byte = 0;
  594 
  595         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
  596                 return (1);
  597 
  598         for (i = 0; i < cnt; i++) {
  599                 err = bge_nvram_getbyte(sc, off + i, &byte);
  600                 if (err)
  601                         break;
  602                 *(dest + i) = byte;
  603         }
  604 
  605         return (err ? 1 : 0);
  606 }
  607 
  608 /*
  609  * Read a byte of data stored in the EEPROM at address 'addr.' The
  610  * BCM570x supports both the traditional bitbang interface and an
  611  * auto access interface for reading the EEPROM. We use the auto
  612  * access method.
  613  */
  614 static uint8_t
  615 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
  616 {
  617         int i;
  618         uint32_t byte = 0;
  619 
  620         /*
  621          * Enable use of auto EEPROM access so we can avoid
  622          * having to use the bitbang method.
  623          */
  624         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
  625 
  626         /* Reset the EEPROM, load the clock period. */
  627         CSR_WRITE_4(sc, BGE_EE_ADDR,
  628             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
  629         DELAY(20);
  630 
  631         /* Issue the read EEPROM command. */
  632         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
  633 
  634         /* Wait for completion */
  635         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
  636                 DELAY(10);
  637                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
  638                         break;
  639         }
  640 
  641         if (i == BGE_TIMEOUT) {
  642                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
  643                 return(1);
  644         }
  645 
  646         /* Get result. */
  647         byte = CSR_READ_4(sc, BGE_EE_DATA);
  648 
  649         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
  650 
  651         return(0);
  652 }
  653 
  654 /*
  655  * Read a sequence of bytes from the EEPROM.
  656  */
  657 static int
  658 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
  659 {
  660         size_t i;
  661         int err;
  662         uint8_t byte;
  663 
  664         for (byte = 0, err = 0, i = 0; i < len; i++) {
  665                 err = bge_eeprom_getbyte(sc, off + i, &byte);
  666                 if (err)
  667                         break;
  668                 *(dest + i) = byte;
  669         }
  670 
  671         return(err ? 1 : 0);
  672 }
  673 
  674 static int
  675 bge_miibus_readreg(device_t dev, int phy, int reg)
  676 {
  677         struct bge_softc *sc = device_get_softc(dev);
  678         uint32_t val;
  679         int i;
  680 
  681         KASSERT(phy == sc->bge_phyno,
  682             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
  683 
  684         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
  685         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
  686                 CSR_WRITE_4(sc, BGE_MI_MODE,
  687                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
  688                 DELAY(80);
  689         }
  690 
  691         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
  692             BGE_MIPHY(phy) | BGE_MIREG(reg));
  693 
  694         /* Poll for the PHY register access to complete. */
  695         for (i = 0; i < BGE_TIMEOUT; i++) {
  696                 DELAY(10);
  697                 val = CSR_READ_4(sc, BGE_MI_COMM);
  698                 if ((val & BGE_MICOMM_BUSY) == 0) {
  699                         DELAY(5);
  700                         val = CSR_READ_4(sc, BGE_MI_COMM);
  701                         break;
  702                 }
  703         }
  704         if (i == BGE_TIMEOUT) {
  705                 if_printf(&sc->arpcom.ac_if, "PHY read timed out "
  706                     "(phy %d, reg %d, val 0x%08x)\n", phy, reg, val);
  707                 val = 0;
  708         }
  709 
  710         /* Restore the autopoll bit if necessary. */
  711         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
  712                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
  713                 DELAY(80);
  714         }
  715 
  716         if (val & BGE_MICOMM_READFAIL)
  717                 return 0;
  718 
  719         return (val & 0xFFFF);
  720 }
  721 
  722 static int
  723 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
  724 {
  725         struct bge_softc *sc = device_get_softc(dev);
  726         int i;
  727 
  728         KASSERT(phy == sc->bge_phyno,
  729             ("invalid phyno %d, should be %d", phy, sc->bge_phyno));
  730 
  731         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
  732             (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
  733                return 0;
  734 
  735         /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
  736         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
  737                 CSR_WRITE_4(sc, BGE_MI_MODE,
  738                     sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
  739                 DELAY(80);
  740         }
  741 
  742         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
  743             BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
  744 
  745         for (i = 0; i < BGE_TIMEOUT; i++) {
  746                 DELAY(10);
  747                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
  748                         DELAY(5);
  749                         CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
  750                         break;
  751                 }
  752         }
  753         if (i == BGE_TIMEOUT) {
  754                 if_printf(&sc->arpcom.ac_if, "PHY write timed out "
  755                     "(phy %d, reg %d, val %d)\n", phy, reg, val);
  756         }
  757 
  758         /* Restore the autopoll bit if necessary. */
  759         if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
  760                 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
  761                 DELAY(80);
  762         }
  763 
  764         return 0;
  765 }
  766 
  767 static void
  768 bge_miibus_statchg(device_t dev)
  769 {
  770         struct bge_softc *sc;
  771         struct mii_data *mii;
  772         uint32_t mac_mode;
  773 
  774         sc = device_get_softc(dev);
  775         if ((sc->arpcom.ac_if.if_flags & IFF_RUNNING) == 0)
  776                 return;
  777 
  778         mii = device_get_softc(sc->bge_miibus);
  779 
  780         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
  781             (IFM_ACTIVE | IFM_AVALID)) {
  782                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
  783                 case IFM_10_T:
  784                 case IFM_100_TX:
  785                         sc->bge_link = 1;
  786                         break;
  787                 case IFM_1000_T:
  788                 case IFM_1000_SX:
  789                 case IFM_2500_SX:
  790                         if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
  791                                 sc->bge_link = 1;
  792                         else
  793                                 sc->bge_link = 0;
  794                         break;
  795                 default:
  796                         sc->bge_link = 0;
  797                         break;
  798                 }
  799         } else {
  800                 sc->bge_link = 0;
  801         }
  802         if (sc->bge_link == 0)
  803                 return;
  804 
  805         /*
  806          * APE firmware touches these registers to keep the MAC
  807          * connected to the outside world.  Try to keep the
  808          * accesses atomic.
  809          */
  810 
  811         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
  812             ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
  813 
  814         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
  815             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
  816                 mac_mode |= BGE_PORTMODE_GMII;
  817         else
  818                 mac_mode |= BGE_PORTMODE_MII;
  819 
  820         if ((mii->mii_media_active & IFM_GMASK) != IFM_FDX)
  821                 mac_mode |= BGE_MACMODE_HALF_DUPLEX;
  822 
  823         CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
  824         DELAY(40);
  825 }
  826 
  827 /*
  828  * Memory management for jumbo frames.
  829  */
  830 static int
  831 bge_alloc_jumbo_mem(struct bge_softc *sc)
  832 {
  833         struct ifnet *ifp = &sc->arpcom.ac_if;
  834         struct bge_jslot *entry;
  835         uint8_t *ptr;
  836         bus_addr_t paddr;
  837         int i, error;
  838 
  839         /*
  840          * Create tag for jumbo mbufs.
  841          * This is really a bit of a kludge. We allocate a special
  842          * jumbo buffer pool which (thanks to the way our DMA
  843          * memory allocation works) will consist of contiguous
  844          * pages. This means that even though a jumbo buffer might
  845          * be larger than a page size, we don't really need to
  846          * map it into more than one DMA segment. However, the
  847          * default mbuf tag will result in multi-segment mappings,
  848          * so we have to create a special jumbo mbuf tag that
  849          * lets us get away with mapping the jumbo buffers as
  850          * a single segment. I think eventually the driver should
  851          * be changed so that it uses ordinary mbufs and cluster
  852          * buffers, i.e. jumbo frames can span multiple DMA
  853          * descriptors. But that's a project for another day.
  854          */
  855 
  856         /*
  857          * Create DMA stuffs for jumbo RX ring.
  858          */
  859         error = bge_dma_block_alloc(sc, BGE_JUMBO_RX_RING_SZ,
  860                                     &sc->bge_cdata.bge_rx_jumbo_ring_tag,
  861                                     &sc->bge_cdata.bge_rx_jumbo_ring_map,
  862                                     (void *)&sc->bge_ldata.bge_rx_jumbo_ring,
  863                                     &sc->bge_ldata.bge_rx_jumbo_ring_paddr);
  864         if (error) {
  865                 if_printf(ifp, "could not create jumbo RX ring\n");
  866                 return error;
  867         }
  868 
  869         /*
  870          * Create DMA stuffs for jumbo buffer block.
  871          */
  872         error = bge_dma_block_alloc(sc, BGE_JMEM,
  873                                     &sc->bge_cdata.bge_jumbo_tag,
  874                                     &sc->bge_cdata.bge_jumbo_map,
  875                                     (void **)&sc->bge_ldata.bge_jumbo_buf,
  876                                     &paddr);
  877         if (error) {
  878                 if_printf(ifp, "could not create jumbo buffer\n");
  879                 return error;
  880         }
  881 
  882         SLIST_INIT(&sc->bge_jfree_listhead);
  883 
  884         /*
  885          * Now divide it up into 9K pieces and save the addresses
  886          * in an array. Note that we play an evil trick here by using
  887          * the first few bytes in the buffer to hold the the address
  888          * of the softc structure for this interface. This is because
  889          * bge_jfree() needs it, but it is called by the mbuf management
  890          * code which will not pass it to us explicitly.
  891          */
  892         for (i = 0, ptr = sc->bge_ldata.bge_jumbo_buf; i < BGE_JSLOTS; i++) {
  893                 entry = &sc->bge_cdata.bge_jslots[i];
  894                 entry->bge_sc = sc;
  895                 entry->bge_buf = ptr;
  896                 entry->bge_paddr = paddr;
  897                 entry->bge_inuse = 0;
  898                 entry->bge_slot = i;
  899                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
  900 
  901                 ptr += BGE_JLEN;
  902                 paddr += BGE_JLEN;
  903         }
  904         return 0;
  905 }
  906 
  907 static void
  908 bge_free_jumbo_mem(struct bge_softc *sc)
  909 {
  910         /* Destroy jumbo RX ring. */
  911         bge_dma_block_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
  912                            sc->bge_cdata.bge_rx_jumbo_ring_map,
  913                            sc->bge_ldata.bge_rx_jumbo_ring);
  914 
  915         /* Destroy jumbo buffer block. */
  916         bge_dma_block_free(sc->bge_cdata.bge_jumbo_tag,
  917                            sc->bge_cdata.bge_jumbo_map,
  918                            sc->bge_ldata.bge_jumbo_buf);
  919 }
  920 
  921 /*
  922  * Allocate a jumbo buffer.
  923  */
  924 static struct bge_jslot *
  925 bge_jalloc(struct bge_softc *sc)
  926 {
  927         struct bge_jslot *entry;
  928 
  929         lwkt_serialize_enter(&sc->bge_jslot_serializer);
  930         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
  931         if (entry) {
  932                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
  933                 entry->bge_inuse = 1;
  934         } else {
  935                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
  936         }
  937         lwkt_serialize_exit(&sc->bge_jslot_serializer);
  938         return(entry);
  939 }
  940 
  941 /*
  942  * Adjust usage count on a jumbo buffer.
  943  */
  944 static void
  945 bge_jref(void *arg)
  946 {
  947         struct bge_jslot *entry = (struct bge_jslot *)arg;
  948         struct bge_softc *sc = entry->bge_sc;
  949 
  950         if (sc == NULL)
  951                 panic("bge_jref: can't find softc pointer!");
  952 
  953         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
  954                 panic("bge_jref: asked to reference buffer "
  955                     "that we don't manage!");
  956         } else if (entry->bge_inuse == 0) {
  957                 panic("bge_jref: buffer already free!");
  958         } else {
  959                 atomic_add_int(&entry->bge_inuse, 1);
  960         }
  961 }
  962 
  963 /*
  964  * Release a jumbo buffer.
  965  */
  966 static void
  967 bge_jfree(void *arg)
  968 {
  969         struct bge_jslot *entry = (struct bge_jslot *)arg;
  970         struct bge_softc *sc = entry->bge_sc;
  971 
  972         if (sc == NULL)
  973                 panic("bge_jfree: can't find softc pointer!");
  974 
  975         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
  976                 panic("bge_jfree: asked to free buffer that we don't manage!");
  977         } else if (entry->bge_inuse == 0) {
  978                 panic("bge_jfree: buffer already free!");
  979         } else {
  980                 /*
  981                  * Possible MP race to 0, use the serializer.  The atomic insn
  982                  * is still needed for races against bge_jref().
  983                  */
  984                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
  985                 atomic_subtract_int(&entry->bge_inuse, 1);
  986                 if (entry->bge_inuse == 0) {
  987                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 
  988                                           entry, jslot_link);
  989                 }
  990                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
  991         }
  992 }
  993 
  994 
  995 /*
  996  * Intialize a standard receive ring descriptor.
  997  */
  998 static int
  999 bge_newbuf_std(struct bge_softc *sc, int i, int init)
 1000 {
 1001         struct mbuf *m_new = NULL;
 1002         bus_dma_segment_t seg;
 1003         bus_dmamap_t map;
 1004         int error, nsegs;
 1005 
 1006         m_new = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
 1007         if (m_new == NULL)
 1008                 return ENOBUFS;
 1009         m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 1010 
 1011         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
 1012                 m_adj(m_new, ETHER_ALIGN);
 1013 
 1014         error = bus_dmamap_load_mbuf_segment(sc->bge_cdata.bge_rx_mtag,
 1015                         sc->bge_cdata.bge_rx_tmpmap, m_new,
 1016                         &seg, 1, &nsegs, BUS_DMA_NOWAIT);
 1017         if (error) {
 1018                 m_freem(m_new);
 1019                 return error;
 1020         }
 1021 
 1022         if (!init) {
 1023                 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
 1024                                 sc->bge_cdata.bge_rx_std_dmamap[i],
 1025                                 BUS_DMASYNC_POSTREAD);
 1026                 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 1027                         sc->bge_cdata.bge_rx_std_dmamap[i]);
 1028         }
 1029 
 1030         map = sc->bge_cdata.bge_rx_tmpmap;
 1031         sc->bge_cdata.bge_rx_tmpmap = sc->bge_cdata.bge_rx_std_dmamap[i];
 1032         sc->bge_cdata.bge_rx_std_dmamap[i] = map;
 1033 
 1034         sc->bge_cdata.bge_rx_std_chain[i].bge_mbuf = m_new;
 1035         sc->bge_cdata.bge_rx_std_chain[i].bge_paddr = seg.ds_addr;
 1036 
 1037         bge_setup_rxdesc_std(sc, i);
 1038         return 0;
 1039 }
 1040 
 1041 static void
 1042 bge_setup_rxdesc_std(struct bge_softc *sc, int i)
 1043 {
 1044         struct bge_rxchain *rc;
 1045         struct bge_rx_bd *r;
 1046 
 1047         rc = &sc->bge_cdata.bge_rx_std_chain[i];
 1048         r = &sc->bge_ldata.bge_rx_std_ring[i];
 1049 
 1050         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
 1051         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
 1052         r->bge_len = rc->bge_mbuf->m_len;
 1053         r->bge_idx = i;
 1054         r->bge_flags = BGE_RXBDFLAG_END;
 1055 }
 1056 
 1057 /*
 1058  * Initialize a jumbo receive ring descriptor. This allocates
 1059  * a jumbo buffer from the pool managed internally by the driver.
 1060  */
 1061 static int
 1062 bge_newbuf_jumbo(struct bge_softc *sc, int i, int init)
 1063 {
 1064         struct mbuf *m_new = NULL;
 1065         struct bge_jslot *buf;
 1066         bus_addr_t paddr;
 1067 
 1068         /* Allocate the mbuf. */
 1069         MGETHDR(m_new, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
 1070         if (m_new == NULL)
 1071                 return ENOBUFS;
 1072 
 1073         /* Allocate the jumbo buffer */
 1074         buf = bge_jalloc(sc);
 1075         if (buf == NULL) {
 1076                 m_freem(m_new);
 1077                 return ENOBUFS;
 1078         }
 1079 
 1080         /* Attach the buffer to the mbuf. */
 1081         m_new->m_ext.ext_arg = buf;
 1082         m_new->m_ext.ext_buf = buf->bge_buf;
 1083         m_new->m_ext.ext_free = bge_jfree;
 1084         m_new->m_ext.ext_ref = bge_jref;
 1085         m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 1086 
 1087         m_new->m_flags |= M_EXT;
 1088 
 1089         m_new->m_data = m_new->m_ext.ext_buf;
 1090         m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 1091 
 1092         paddr = buf->bge_paddr;
 1093         if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) {
 1094                 m_adj(m_new, ETHER_ALIGN);
 1095                 paddr += ETHER_ALIGN;
 1096         }
 1097 
 1098         /* Save necessary information */
 1099         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_mbuf = m_new;
 1100         sc->bge_cdata.bge_rx_jumbo_chain[i].bge_paddr = paddr;
 1101 
 1102         /* Set up the descriptor. */
 1103         bge_setup_rxdesc_jumbo(sc, i);
 1104         return 0;
 1105 }
 1106 
 1107 static void
 1108 bge_setup_rxdesc_jumbo(struct bge_softc *sc, int i)
 1109 {
 1110         struct bge_rx_bd *r;
 1111         struct bge_rxchain *rc;
 1112 
 1113         r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
 1114         rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
 1115 
 1116         r->bge_addr.bge_addr_lo = BGE_ADDR_LO(rc->bge_paddr);
 1117         r->bge_addr.bge_addr_hi = BGE_ADDR_HI(rc->bge_paddr);
 1118         r->bge_len = rc->bge_mbuf->m_len;
 1119         r->bge_idx = i;
 1120         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 1121 }
 1122 
 1123 static int
 1124 bge_init_rx_ring_std(struct bge_softc *sc)
 1125 {
 1126         int i, error;
 1127 
 1128         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 1129                 error = bge_newbuf_std(sc, i, 1);
 1130                 if (error)
 1131                         return error;
 1132         }
 1133 
 1134         sc->bge_std = BGE_STD_RX_RING_CNT - 1;
 1135         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 1136 
 1137         return(0);
 1138 }
 1139 
 1140 static void
 1141 bge_free_rx_ring_std(struct bge_softc *sc)
 1142 {
 1143         int i;
 1144 
 1145         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 1146                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_std_chain[i];
 1147 
 1148                 if (rc->bge_mbuf != NULL) {
 1149                         bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
 1150                                           sc->bge_cdata.bge_rx_std_dmamap[i]);
 1151                         m_freem(rc->bge_mbuf);
 1152                         rc->bge_mbuf = NULL;
 1153                 }
 1154                 bzero(&sc->bge_ldata.bge_rx_std_ring[i],
 1155                     sizeof(struct bge_rx_bd));
 1156         }
 1157 }
 1158 
 1159 static int
 1160 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 1161 {
 1162         struct bge_rcb *rcb;
 1163         int i, error;
 1164 
 1165         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 1166                 error = bge_newbuf_jumbo(sc, i, 1);
 1167                 if (error)
 1168                         return error;
 1169         }
 1170 
 1171         sc->bge_jumbo = BGE_JUMBO_RX_RING_CNT - 1;
 1172 
 1173         rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
 1174         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 1175         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 1176 
 1177         bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 1178 
 1179         return(0);
 1180 }
 1181 
 1182 static void
 1183 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 1184 {
 1185         int i;
 1186 
 1187         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 1188                 struct bge_rxchain *rc = &sc->bge_cdata.bge_rx_jumbo_chain[i];
 1189 
 1190                 if (rc->bge_mbuf != NULL) {
 1191                         m_freem(rc->bge_mbuf);
 1192                         rc->bge_mbuf = NULL;
 1193                 }
 1194                 bzero(&sc->bge_ldata.bge_rx_jumbo_ring[i],
 1195                     sizeof(struct bge_rx_bd));
 1196         }
 1197 }
 1198 
 1199 static void
 1200 bge_free_tx_ring(struct bge_softc *sc)
 1201 {
 1202         int i;
 1203 
 1204         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 1205                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
 1206                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
 1207                                           sc->bge_cdata.bge_tx_dmamap[i]);
 1208                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
 1209                         sc->bge_cdata.bge_tx_chain[i] = NULL;
 1210                 }
 1211                 bzero(&sc->bge_ldata.bge_tx_ring[i],
 1212                     sizeof(struct bge_tx_bd));
 1213         }
 1214 }
 1215 
 1216 static int
 1217 bge_init_tx_ring(struct bge_softc *sc)
 1218 {
 1219         sc->bge_txcnt = 0;
 1220         sc->bge_tx_saved_considx = 0;
 1221         sc->bge_tx_prodidx = 0;
 1222 
 1223         /* Initialize transmit producer index for host-memory send ring. */
 1224         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
 1225 
 1226         /* 5700 b2 errata */
 1227         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 1228                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
 1229 
 1230         bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 1231         /* 5700 b2 errata */
 1232         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 1233                 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 1234 
 1235         return(0);
 1236 }
 1237 
 1238 static void
 1239 bge_setmulti(struct bge_softc *sc)
 1240 {
 1241         struct ifnet *ifp;
 1242         struct ifmultiaddr *ifma;
 1243         uint32_t hashes[4] = { 0, 0, 0, 0 };
 1244         int h, i;
 1245 
 1246         ifp = &sc->arpcom.ac_if;
 1247 
 1248         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 1249                 for (i = 0; i < 4; i++)
 1250                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 1251                 return;
 1252         }
 1253 
 1254         /* First, zot all the existing filters. */
 1255         for (i = 0; i < 4; i++)
 1256                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 1257 
 1258         /* Now program new ones. */
 1259         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 1260                 if (ifma->ifma_addr->sa_family != AF_LINK)
 1261                         continue;
 1262                 h = ether_crc32_le(
 1263                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 1264                     ETHER_ADDR_LEN) & 0x7f;
 1265                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 1266         }
 1267 
 1268         for (i = 0; i < 4; i++)
 1269                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 1270 }
 1271 
 1272 /*
 1273  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 1274  * self-test results.
 1275  */
 1276 static int
 1277 bge_chipinit(struct bge_softc *sc)
 1278 {
 1279         int i;
 1280         uint32_t dma_rw_ctl, mode_ctl;
 1281         uint16_t val;
 1282 
 1283         /* Set endian type before we access any non-PCI registers. */
 1284         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 1285             BGE_INIT | sc->bge_pci_miscctl, 4);
 1286 
 1287         /*
 1288          * Clear the MAC statistics block in the NIC's
 1289          * internal memory.
 1290          */
 1291         for (i = BGE_STATS_BLOCK;
 1292             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
 1293                 BGE_MEMWIN_WRITE(sc, i, 0);
 1294 
 1295         for (i = BGE_STATUS_BLOCK;
 1296             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
 1297                 BGE_MEMWIN_WRITE(sc, i, 0);
 1298 
 1299         if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
 1300                 /*
 1301                  * Fix data corruption caused by non-qword write with WB.
 1302                  * Fix master abort in PCI mode.
 1303                  * Fix PCI latency timer.
 1304                  */
 1305                 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
 1306                 val |= (1 << 10) | (1 << 12) | (1 << 13);
 1307                 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
 1308         }
 1309 
 1310         /* Set up the PCI DMA control register. */
 1311         dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD;
 1312         if (sc->bge_flags & BGE_FLAG_PCIE) {
 1313                 /* PCI-E bus */
 1314                 /* DMA read watermark not used on PCI-E */
 1315                 dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 1316         } else if (sc->bge_flags & BGE_FLAG_PCIX) {
 1317                 /* PCI-X bus */
 1318                 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) {
 1319                         dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 1320                             (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 1321                         dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
 1322                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5714) {
 1323                         dma_rw_ctl |= (0x4 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 1324                             (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 1325                         dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
 1326                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
 1327                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 1328                         uint32_t rd_wat = 0x7;
 1329                         uint32_t clkctl;
 1330 
 1331                         clkctl = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
 1332                         if ((sc->bge_flags & BGE_FLAG_MAXADDR_40BIT) &&
 1333                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 1334                                 dma_rw_ctl |=
 1335                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
 1336                         } else if (clkctl == 0x6 || clkctl == 0x7) {
 1337                                 dma_rw_ctl |=
 1338                                     BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
 1339                         }
 1340                         if (sc->bge_asicrev == BGE_ASICREV_BCM5703)
 1341                                 rd_wat = 0x4;
 1342 
 1343                         dma_rw_ctl |= (rd_wat << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 1344                             (3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 1345                         dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
 1346                 } else {
 1347                         dma_rw_ctl |= (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 1348                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 1349                         dma_rw_ctl |= 0xf;
 1350                 }
 1351         } else {
 1352                 /* Conventional PCI bus */
 1353                 dma_rw_ctl |= (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
 1354                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
 1355                 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
 1356                     sc->bge_asicrev != BGE_ASICREV_BCM5750)
 1357                         dma_rw_ctl |= 0xf;
 1358         }
 1359 
 1360         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
 1361             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 1362                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
 1363         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
 1364             sc->bge_asicrev == BGE_ASICREV_BCM5701) {
 1365                 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
 1366                     BGE_PCIDMARWCTL_ASRT_ALL_BE;
 1367         }
 1368         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
 1369 
 1370         /*
 1371          * Set up general mode register.
 1372          */
 1373         mode_ctl = BGE_DMA_SWAP_OPTIONS|
 1374             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
 1375             BGE_MODECTL_TX_NO_PHDR_CSUM;
 1376 
 1377         /*
 1378          * BCM5701 B5 have a bug causing data corruption when using
 1379          * 64-bit DMA reads, which can be terminated early and then
 1380          * completed later as 32-bit accesses, in combination with
 1381          * certain bridges.
 1382          */
 1383         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
 1384             sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
 1385                 mode_ctl |= BGE_MODECTL_FORCE_PCI32;
 1386 
 1387         /*
 1388          * Tell the firmware the driver is running
 1389          */
 1390         if (sc->bge_asf_mode & ASF_STACKUP)
 1391                 mode_ctl |= BGE_MODECTL_STACKUP;
 1392 
 1393         CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
 1394 
 1395         /*
 1396          * Disable memory write invalidate.  Apparently it is not supported
 1397          * properly by these devices.  Also ensure that INTx isn't disabled,
 1398          * as these chips need it even when using MSI.
 1399          */
 1400         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD,
 1401             (PCIM_CMD_MWRICEN | PCIM_CMD_INTxDIS), 4);
 1402 
 1403         /* Set the timer prescaler (always 66Mhz) */
 1404         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
 1405 
 1406         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 1407                 DELAY(40);      /* XXX */
 1408 
 1409                 /* Put PHY into ready state */
 1410                 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
 1411                 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
 1412                 DELAY(40);
 1413         }
 1414 
 1415         return(0);
 1416 }
 1417 
 1418 static int
 1419 bge_blockinit(struct bge_softc *sc)
 1420 {
 1421         struct bge_rcb *rcb;
 1422         bus_size_t vrcb;
 1423         bge_hostaddr taddr;
 1424         uint32_t val;
 1425         int i, limit;
 1426 
 1427         /*
 1428          * Initialize the memory window pointer register so that
 1429          * we can access the first 32K of internal NIC RAM. This will
 1430          * allow us to set up the TX send ring RCBs and the RX return
 1431          * ring RCBs, plus other things which live in NIC memory.
 1432          */
 1433         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
 1434 
 1435         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
 1436 
 1437         if (!BGE_IS_5705_PLUS(sc)) {
 1438                 /* Configure mbuf memory pool */
 1439                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
 1440                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
 1441                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
 1442                 else
 1443                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
 1444 
 1445                 /* Configure DMA resource pool */
 1446                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
 1447                     BGE_DMA_DESCRIPTORS);
 1448                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
 1449         }
 1450 
 1451         /* Configure mbuf pool watermarks */
 1452         if (!BGE_IS_5705_PLUS(sc)) {
 1453                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
 1454                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
 1455                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
 1456         } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 1457                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
 1458                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
 1459                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
 1460         } else {
 1461                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
 1462                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
 1463                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
 1464         }
 1465 
 1466         /* Configure DMA resource watermarks */
 1467         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
 1468         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
 1469 
 1470         /* Enable buffer manager */
 1471         CSR_WRITE_4(sc, BGE_BMAN_MODE,
 1472             BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
 1473 
 1474         /* Poll for buffer manager start indication */
 1475         for (i = 0; i < BGE_TIMEOUT; i++) {
 1476                 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
 1477                         break;
 1478                 DELAY(10);
 1479         }
 1480 
 1481         if (i == BGE_TIMEOUT) {
 1482                 if_printf(&sc->arpcom.ac_if,
 1483                           "buffer manager failed to start\n");
 1484                 return(ENXIO);
 1485         }
 1486 
 1487         /* Enable flow-through queues */
 1488         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
 1489         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
 1490 
 1491         /* Wait until queue initialization is complete */
 1492         for (i = 0; i < BGE_TIMEOUT; i++) {
 1493                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
 1494                         break;
 1495                 DELAY(10);
 1496         }
 1497 
 1498         if (i == BGE_TIMEOUT) {
 1499                 if_printf(&sc->arpcom.ac_if,
 1500                           "flow-through queue init failed\n");
 1501                 return(ENXIO);
 1502         }
 1503 
 1504         /*
 1505          * Summary of rings supported by the controller:
 1506          *
 1507          * Standard Receive Producer Ring
 1508          * - This ring is used to feed receive buffers for "standard"
 1509          *   sized frames (typically 1536 bytes) to the controller.
 1510          *
 1511          * Jumbo Receive Producer Ring
 1512          * - This ring is used to feed receive buffers for jumbo sized
 1513          *   frames (i.e. anything bigger than the "standard" frames)
 1514          *   to the controller.
 1515          *
 1516          * Mini Receive Producer Ring
 1517          * - This ring is used to feed receive buffers for "mini"
 1518          *   sized frames to the controller.
 1519          * - This feature required external memory for the controller
 1520          *   but was never used in a production system.  Should always
 1521          *   be disabled.
 1522          *
 1523          * Receive Return Ring
 1524          * - After the controller has placed an incoming frame into a
 1525          *   receive buffer that buffer is moved into a receive return
 1526          *   ring.  The driver is then responsible to passing the
 1527          *   buffer up to the stack.  Many versions of the controller
 1528          *   support multiple RR rings.
 1529          *
 1530          * Send Ring
 1531          * - This ring is used for outgoing frames.  Many versions of
 1532          *   the controller support multiple send rings.
 1533          */
 1534 
 1535         /* Initialize the standard receive producer ring control block. */
 1536         rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
 1537         rcb->bge_hostaddr.bge_addr_lo =
 1538             BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
 1539         rcb->bge_hostaddr.bge_addr_hi =
 1540             BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
 1541         if (BGE_IS_5705_PLUS(sc)) {
 1542                 /*
 1543                  * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
 1544                  * Bits 15-2 : Reserved (should be 0)
 1545                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
 1546                  * Bit 0     : Reserved
 1547                  */
 1548                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
 1549         } else {
 1550                 /*
 1551                  * Ring size is always XXX entries
 1552                  * Bits 31-16: Maximum RX frame size
 1553                  * Bits 15-2 : Reserved (should be 0)
 1554                  * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
 1555                  * Bit 0     : Reserved
 1556                  */
 1557                 rcb->bge_maxlen_flags =
 1558                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
 1559         }
 1560         rcb->bge_nicaddr = BGE_STD_RX_RINGS;
 1561         /* Write the standard receive producer ring control block. */
 1562         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
 1563         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
 1564         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 1565         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
 1566         /* Reset the standard receive producer ring producer index. */
 1567         bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
 1568 
 1569         /*
 1570          * Initialize the jumbo RX producer ring control
 1571          * block.  We set the 'ring disabled' bit in the
 1572          * flags field until we're actually ready to start
 1573          * using this ring (i.e. once we set the MTU
 1574          * high enough to require it).
 1575          */
 1576         if (BGE_IS_JUMBO_CAPABLE(sc)) {
 1577                 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
 1578                 /* Get the jumbo receive producer ring RCB parameters. */
 1579                 rcb->bge_hostaddr.bge_addr_lo =
 1580                     BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 1581                 rcb->bge_hostaddr.bge_addr_hi =
 1582                     BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
 1583                 rcb->bge_maxlen_flags =
 1584                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
 1585                     BGE_RCB_FLAG_RING_DISABLED);
 1586                 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
 1587                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
 1588                     rcb->bge_hostaddr.bge_addr_hi);
 1589                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
 1590                     rcb->bge_hostaddr.bge_addr_lo);
 1591                 /* Program the jumbo receive producer ring RCB parameters. */
 1592                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
 1593                     rcb->bge_maxlen_flags);
 1594                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
 1595                 /* Reset the jumbo receive producer ring producer index. */
 1596                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
 1597         }
 1598 
 1599         /* Disable the mini receive producer ring RCB. */
 1600         if (BGE_IS_5700_FAMILY(sc)) {
 1601                 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
 1602                 rcb->bge_maxlen_flags =
 1603                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
 1604                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
 1605                     rcb->bge_maxlen_flags);
 1606                 /* Reset the mini receive producer ring producer index. */
 1607                 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
 1608         }
 1609 
 1610         /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
 1611         if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
 1612             (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
 1613              sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
 1614              sc->bge_chipid == BGE_CHIPID_BCM5906_A2)) {
 1615                 CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
 1616                     (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
 1617         }
 1618 
 1619         /*
 1620          * The BD ring replenish thresholds control how often the
 1621          * hardware fetches new BD's from the producer rings in host
 1622          * memory.  Setting the value too low on a busy system can
 1623          * starve the hardware and recue the throughpout.
 1624          *
 1625          * Set the BD ring replentish thresholds. The recommended
 1626          * values are 1/8th the number of descriptors allocated to
 1627          * each ring.
 1628          */
 1629         if (BGE_IS_5705_PLUS(sc))
 1630                 val = 8;
 1631         else
 1632                 val = BGE_STD_RX_RING_CNT / 8;
 1633         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
 1634         if (BGE_IS_JUMBO_CAPABLE(sc)) {
 1635                 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
 1636                     BGE_JUMBO_RX_RING_CNT/8);
 1637         }
 1638 
 1639         /*
 1640          * Disable all send rings by setting the 'ring disabled' bit
 1641          * in the flags field of all the TX send ring control blocks,
 1642          * located in NIC memory.
 1643          */
 1644         if (!BGE_IS_5705_PLUS(sc)) {
 1645                 /* 5700 to 5704 had 16 send rings. */
 1646                 limit = BGE_TX_RINGS_EXTSSRAM_MAX;
 1647         } else {
 1648                 limit = 1;
 1649         }
 1650         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
 1651         for (i = 0; i < limit; i++) {
 1652                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
 1653                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
 1654                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
 1655                 vrcb += sizeof(struct bge_rcb);
 1656         }
 1657 
 1658         /* Configure send ring RCB 0 (we use only the first ring) */
 1659         vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
 1660         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
 1661         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
 1662         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
 1663         RCB_WRITE_4(sc, vrcb, bge_nicaddr,
 1664             BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
 1665         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
 1666             BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
 1667 
 1668         /*
 1669          * Disable all receive return rings by setting the
 1670          * 'ring diabled' bit in the flags field of all the receive
 1671          * return ring control blocks, located in NIC memory.
 1672          */
 1673         if (!BGE_IS_5705_PLUS(sc))
 1674                 limit = BGE_RX_RINGS_MAX;
 1675         else if (sc->bge_asicrev == BGE_ASICREV_BCM5755)
 1676                 limit = 4;
 1677         else
 1678                 limit = 1;
 1679         /* Disable all receive return rings. */
 1680         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
 1681         for (i = 0; i < limit; i++) {
 1682                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
 1683                 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
 1684                 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
 1685                     BGE_RCB_FLAG_RING_DISABLED);
 1686                 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
 1687                 bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
 1688                     (i * (sizeof(uint64_t))), 0);
 1689                 vrcb += sizeof(struct bge_rcb);
 1690         }
 1691 
 1692         /*
 1693          * Set up receive return ring 0.  Note that the NIC address
 1694          * for RX return rings is 0x0.  The return rings live entirely
 1695          * within the host, so the nicaddr field in the RCB isn't used.
 1696          */
 1697         vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
 1698         BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
 1699         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
 1700         RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
 1701         RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
 1702         RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
 1703             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
 1704 
 1705         /* Set random backoff seed for TX */
 1706         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
 1707             (sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
 1708              sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
 1709              sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5]) &
 1710             BGE_TX_BACKOFF_SEED_MASK);
 1711 
 1712         /* Set inter-packet gap */
 1713         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
 1714 
 1715         /*
 1716          * Specify which ring to use for packets that don't match
 1717          * any RX rules.
 1718          */
 1719         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
 1720 
 1721         /*
 1722          * Configure number of RX lists. One interrupt distribution
 1723          * list, sixteen active lists, one bad frames class.
 1724          */
 1725         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
 1726 
 1727         /* Inialize RX list placement stats mask. */
 1728         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
 1729         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
 1730 
 1731         /* Disable host coalescing until we get it set up */
 1732         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
 1733 
 1734         /* Poll to make sure it's shut down. */
 1735         for (i = 0; i < BGE_TIMEOUT; i++) {
 1736                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
 1737                         break;
 1738                 DELAY(10);
 1739         }
 1740 
 1741         if (i == BGE_TIMEOUT) {
 1742                 if_printf(&sc->arpcom.ac_if,
 1743                           "host coalescing engine failed to idle\n");
 1744                 return(ENXIO);
 1745         }
 1746 
 1747         /* Set up host coalescing defaults */
 1748         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
 1749         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
 1750         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_coal_bds);
 1751         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_coal_bds);
 1752         if (!BGE_IS_5705_PLUS(sc)) {
 1753                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
 1754                     sc->bge_rx_coal_ticks_int);
 1755                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
 1756                     sc->bge_tx_coal_ticks_int);
 1757         }
 1758         /*
 1759          * NOTE:
 1760          * The datasheet (57XX-PG105-R) says BCM5705+ do not
 1761          * have following two registers; obviously it is wrong.
 1762          */
 1763         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, sc->bge_rx_coal_bds_int);
 1764         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, sc->bge_tx_coal_bds_int);
 1765 
 1766         /* Set up address of statistics block */
 1767         if (!BGE_IS_5705_PLUS(sc)) {
 1768                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
 1769                     BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
 1770                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
 1771                     BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
 1772 
 1773                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
 1774                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
 1775                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
 1776         }
 1777 
 1778         /* Set up address of status block */
 1779         bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
 1780         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
 1781             BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
 1782         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
 1783             BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
 1784 
 1785         /*
 1786          * Set up status block partail update size.
 1787          *
 1788          * Because only single TX ring, RX produce ring and Rx return ring
 1789          * are used, ask device to update only minimum part of status block
 1790          * except for BCM5700 AX/BX, whose status block partial update size
 1791          * can't be configured.
 1792          */
 1793         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
 1794             sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
 1795                 /* XXX Actually reserved on BCM5700 AX/BX */
 1796                 val = BGE_STATBLKSZ_FULL;
 1797         } else {
 1798                 val = BGE_STATBLKSZ_32BYTE;
 1799         }
 1800 #if 0
 1801         /*
 1802          * Does not seem to have visible effect in both
 1803          * bulk data (1472B UDP datagram) and tiny data
 1804          * (18B UDP datagram) TX tests.
 1805          */
 1806         if (!BGE_IS_CRIPPLED(sc))
 1807                 val |= BGE_HCCMODE_CLRTICK_TX;
 1808 #endif
 1809 
 1810         /* Turn on host coalescing state machine */
 1811         CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
 1812 
 1813         /* Turn on RX BD completion state machine and enable attentions */
 1814         CSR_WRITE_4(sc, BGE_RBDC_MODE,
 1815             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
 1816 
 1817         /* Turn on RX list placement state machine */
 1818         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
 1819 
 1820         /* Turn on RX list selector state machine. */
 1821         if (!BGE_IS_5705_PLUS(sc))
 1822                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
 1823 
 1824         val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
 1825             BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
 1826             BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
 1827             BGE_MACMODE_FRMHDR_DMA_ENB;
 1828 
 1829         if (sc->bge_flags & BGE_FLAG_TBI)
 1830                 val |= BGE_PORTMODE_TBI;
 1831         else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
 1832                 val |= BGE_PORTMODE_GMII;
 1833         else
 1834                 val |= BGE_PORTMODE_MII;
 1835 
 1836         /* Turn on DMA, clear stats */
 1837         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
 1838         DELAY(40);
 1839 
 1840         /* Set misc. local control, enable interrupts on attentions */
 1841         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
 1842 
 1843 #ifdef notdef
 1844         /* Assert GPIO pins for PHY reset */
 1845         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
 1846             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
 1847         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
 1848             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
 1849 #endif
 1850 
 1851         /* Turn on DMA completion state machine */
 1852         if (!BGE_IS_5705_PLUS(sc))
 1853                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
 1854 
 1855         /* Turn on write DMA state machine */
 1856         val = BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS;
 1857         if (BGE_IS_5755_PLUS(sc)) {
 1858                 /* Enable host coalescing bug fix. */
 1859                 val |= BGE_WDMAMODE_STATUS_TAG_FIX;
 1860         }
 1861         if (sc->bge_asicrev == BGE_ASICREV_BCM5785) {
 1862                 /* Request larger DMA burst size to get better performance. */
 1863                 val |= BGE_WDMAMODE_BURST_ALL_DATA;
 1864         }
 1865         CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
 1866         DELAY(40);
 1867 
 1868         if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
 1869             sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
 1870             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
 1871             sc->bge_asicrev == BGE_ASICREV_BCM57780) {
 1872                 /*
 1873                  * Enable fix for read DMA FIFO overruns.
 1874                  * The fix is to limit the number of RX BDs
 1875                  * the hardware would fetch at a fime.
 1876                  */
 1877                 val = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL);
 1878                 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL,
 1879                     val| BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
 1880         }
 1881 
 1882         /* Turn on read DMA state machine */
 1883         val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
 1884         if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
 1885             sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
 1886             sc->bge_asicrev == BGE_ASICREV_BCM57780)
 1887                 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
 1888                   BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
 1889                   BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
 1890         if (sc->bge_flags & BGE_FLAG_PCIE)
 1891                 val |= BGE_RDMAMODE_FIFO_LONG_BURST;
 1892         if (sc->bge_flags & BGE_FLAG_TSO)
 1893                 val |= BGE_RDMAMODE_TSO4_ENABLE;
 1894         CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
 1895         DELAY(40);
 1896 
 1897         /* Turn on RX data completion state machine */
 1898         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
 1899 
 1900         /* Turn on RX BD initiator state machine */
 1901         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
 1902 
 1903         /* Turn on RX data and RX BD initiator state machine */
 1904         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
 1905 
 1906         /* Turn on Mbuf cluster free state machine */
 1907         if (!BGE_IS_5705_PLUS(sc))
 1908                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
 1909 
 1910         /* Turn on send BD completion state machine */
 1911         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
 1912 
 1913         /* Turn on send data completion state machine */
 1914         val = BGE_SDCMODE_ENABLE;
 1915         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 1916                 val |= BGE_SDCMODE_CDELAY; 
 1917         CSR_WRITE_4(sc, BGE_SDC_MODE, val);
 1918 
 1919         /* Turn on send data initiator state machine */
 1920         if (sc->bge_flags & BGE_FLAG_TSO)
 1921                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
 1922                     BGE_SDIMODE_HW_LSO_PRE_DMA);
 1923         else
 1924                 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
 1925 
 1926         /* Turn on send BD initiator state machine */
 1927         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
 1928 
 1929         /* Turn on send BD selector state machine */
 1930         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
 1931 
 1932         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
 1933         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
 1934             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
 1935 
 1936         /* ack/clear link change events */
 1937         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
 1938             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
 1939             BGE_MACSTAT_LINK_CHANGED);
 1940         CSR_WRITE_4(sc, BGE_MI_STS, 0);
 1941 
 1942         /*
 1943          * Enable attention when the link has changed state for
 1944          * devices that use auto polling.
 1945          */
 1946         if (sc->bge_flags & BGE_FLAG_TBI) {
 1947                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
 1948         } else {
 1949                 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 1950                         CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
 1951                         DELAY(80);
 1952                 }
 1953                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
 1954                     sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
 1955                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
 1956                             BGE_EVTENB_MI_INTERRUPT);
 1957                 }
 1958         }
 1959 
 1960         /*
 1961          * Clear any pending link state attention.
 1962          * Otherwise some link state change events may be lost until attention
 1963          * is cleared by bge_intr() -> bge_softc.bge_link_upd() sequence.
 1964          * It's not necessary on newer BCM chips - perhaps enabling link
 1965          * state change attentions implies clearing pending attention.
 1966          */
 1967         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
 1968             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
 1969             BGE_MACSTAT_LINK_CHANGED);
 1970 
 1971         /* Enable link state change attentions. */
 1972         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
 1973 
 1974         return(0);
 1975 }
 1976 
 1977 /*
 1978  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
 1979  * against our list and return its name if we find a match. Note
 1980  * that since the Broadcom controller contains VPD support, we
 1981  * can get the device name string from the controller itself instead
 1982  * of the compiled-in string. This is a little slow, but it guarantees
 1983  * we'll always announce the right product name.
 1984  */
 1985 static int
 1986 bge_probe(device_t dev)
 1987 {
 1988         const struct bge_type *t;
 1989         uint16_t product, vendor;
 1990 
 1991         product = pci_get_device(dev);
 1992         vendor = pci_get_vendor(dev);
 1993 
 1994         for (t = bge_devs; t->bge_name != NULL; t++) {
 1995                 if (vendor == t->bge_vid && product == t->bge_did)
 1996                         break;
 1997         }
 1998         if (t->bge_name == NULL)
 1999                 return(ENXIO);
 2000 
 2001         device_set_desc(dev, t->bge_name);
 2002         return(0);
 2003 }
 2004 
 2005 static int
 2006 bge_attach(device_t dev)
 2007 {
 2008         struct ifnet *ifp;
 2009         struct bge_softc *sc;
 2010         uint32_t hwcfg = 0, misccfg;
 2011         int error = 0, rid, capmask;
 2012         uint8_t ether_addr[ETHER_ADDR_LEN];
 2013         uint16_t product, vendor;
 2014         driver_intr_t *intr_func;
 2015         uintptr_t mii_priv = 0;
 2016         u_int intr_flags;
 2017         int msi_enable;
 2018 
 2019         sc = device_get_softc(dev);
 2020         sc->bge_dev = dev;
 2021         callout_init_mp(&sc->bge_stat_timer);
 2022         lwkt_serialize_init(&sc->bge_jslot_serializer);
 2023 
 2024         product = pci_get_device(dev);
 2025         vendor = pci_get_vendor(dev);
 2026 
 2027 #ifndef BURN_BRIDGES
 2028         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 2029                 uint32_t irq, mem;
 2030 
 2031                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
 2032                 mem = pci_read_config(dev, BGE_PCI_BAR0, 4);
 2033 
 2034                 device_printf(dev, "chip is in D%d power mode "
 2035                     "-- setting to D0\n", pci_get_powerstate(dev));
 2036 
 2037                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 2038 
 2039                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
 2040                 pci_write_config(dev, BGE_PCI_BAR0, mem, 4);
 2041         }
 2042 #endif  /* !BURN_BRIDGE */
 2043 
 2044         /*
 2045          * Map control/status registers.
 2046          */
 2047         pci_enable_busmaster(dev);
 2048 
 2049         rid = BGE_PCI_BAR0;
 2050         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
 2051             RF_ACTIVE);
 2052 
 2053         if (sc->bge_res == NULL) {
 2054                 device_printf(dev, "couldn't map memory\n");
 2055                 return ENXIO;
 2056         }
 2057 
 2058         sc->bge_btag = rman_get_bustag(sc->bge_res);
 2059         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
 2060 
 2061         /* Save various chip information */
 2062         sc->bge_chipid =
 2063             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
 2064             BGE_PCIMISCCTL_ASICREV_SHIFT;
 2065         if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) {
 2066                 /* All chips, which use BGE_PCI_PRODID_ASICREV, have CPMU */
 2067                 sc->bge_flags |= BGE_FLAG_CPMU;
 2068                 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
 2069         }
 2070         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
 2071         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
 2072 
 2073         /* Save chipset family. */
 2074         switch (sc->bge_asicrev) {
 2075         case BGE_ASICREV_BCM5755:
 2076         case BGE_ASICREV_BCM5761:
 2077         case BGE_ASICREV_BCM5784:
 2078         case BGE_ASICREV_BCM5785:
 2079         case BGE_ASICREV_BCM5787:
 2080         case BGE_ASICREV_BCM57780:
 2081             sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
 2082                 BGE_FLAG_5705_PLUS;
 2083             break;
 2084 
 2085         case BGE_ASICREV_BCM5700:
 2086         case BGE_ASICREV_BCM5701:
 2087         case BGE_ASICREV_BCM5703:
 2088         case BGE_ASICREV_BCM5704:
 2089                 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
 2090                 break;
 2091 
 2092         case BGE_ASICREV_BCM5714_A0:
 2093         case BGE_ASICREV_BCM5780:
 2094         case BGE_ASICREV_BCM5714:
 2095                 sc->bge_flags |= BGE_FLAG_5714_FAMILY;
 2096                 /* Fall through */
 2097 
 2098         case BGE_ASICREV_BCM5750:
 2099         case BGE_ASICREV_BCM5752:
 2100         case BGE_ASICREV_BCM5906:
 2101                 sc->bge_flags |= BGE_FLAG_575X_PLUS;
 2102                 /* Fall through */
 2103 
 2104         case BGE_ASICREV_BCM5705:
 2105                 sc->bge_flags |= BGE_FLAG_5705_PLUS;
 2106                 break;
 2107         }
 2108 
 2109         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 2110                 sc->bge_flags |= BGE_FLAG_NO_EEPROM;
 2111 
 2112         if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
 2113                 sc->bge_flags |= BGE_FLAG_APE;
 2114 
 2115         misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
 2116         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
 2117             (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
 2118              misccfg == BGE_MISCCFG_BOARD_ID_5788M))
 2119                 sc->bge_flags |= BGE_FLAG_5788;
 2120 
 2121         /* BCM5755 or higher and BCM5906 have short DMA bug. */
 2122         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
 2123                 sc->bge_flags |= BGE_FLAG_SHORTDMA;
 2124 
 2125         /*
 2126          * Increase STD RX ring prod index by at most 8 for BCM5750,
 2127          * BCM5752 and BCM5755 to workaround hardware errata.
 2128          */
 2129         if (sc->bge_asicrev == BGE_ASICREV_BCM5750 ||
 2130             sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
 2131             sc->bge_asicrev == BGE_ASICREV_BCM5755)
 2132                 sc->bge_rx_wreg = 8;
 2133 
 2134         /*
 2135          * Check if this is a PCI-X or PCI Express device.
 2136          */
 2137         if (BGE_IS_5705_PLUS(sc)) {
 2138                 if (pci_is_pcie(dev)) {
 2139                         sc->bge_flags |= BGE_FLAG_PCIE;
 2140                         sc->bge_pciecap = pci_get_pciecap_ptr(sc->bge_dev);
 2141                         pcie_set_max_readrq(dev, PCIEM_DEVCTL_MAX_READRQ_4096);
 2142                 }
 2143         } else {
 2144                 /*
 2145                  * Check if the device is in PCI-X Mode.
 2146                  * (This bit is not valid on PCI Express controllers.)
 2147                  */
 2148                 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
 2149                     BGE_PCISTATE_PCI_BUSMODE) == 0) {
 2150                         sc->bge_flags |= BGE_FLAG_PCIX;
 2151                         sc->bge_pcixcap = pci_get_pcixcap_ptr(sc->bge_dev);
 2152                         sc->bge_mbox_reorder = device_getenv_int(sc->bge_dev,
 2153                             "mbox_reorder", 0);
 2154                 }
 2155         }
 2156         device_printf(dev, "CHIP ID 0x%08x; "
 2157                       "ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
 2158                       sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
 2159                       (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X"
 2160                       : ((sc->bge_flags & BGE_FLAG_PCIE) ?
 2161                         "PCI-E" : "PCI"));
 2162 
 2163         /*
 2164          * The 40bit DMA bug applies to the 5714/5715 controllers and is
 2165          * not actually a MAC controller bug but an issue with the embedded
 2166          * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
 2167          */
 2168         if ((sc->bge_flags & BGE_FLAG_PCIX) &&
 2169             (BGE_IS_5714_FAMILY(sc) || device_getenv_int(dev, "dma40b", 0)))
 2170                 sc->bge_flags |= BGE_FLAG_MAXADDR_40BIT;
 2171 
 2172         /*
 2173          * When using the BCM5701 in PCI-X mode, data corruption has
 2174          * been observed in the first few bytes of some received packets.
 2175          * Aligning the packet buffer in memory eliminates the corruption.
 2176          * Unfortunately, this misaligns the packet payloads.  On platforms
 2177          * which do not support unaligned accesses, we will realign the
 2178          * payloads by copying the received packets.
 2179          */
 2180         if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
 2181             (sc->bge_flags & BGE_FLAG_PCIX))
 2182                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
 2183 
 2184         if (!BGE_IS_CRIPPLED(sc)) {
 2185                 if (device_getenv_int(dev, "status_tag", 1)) {
 2186                         sc->bge_flags |= BGE_FLAG_STATUS_TAG;
 2187                         sc->bge_pci_miscctl = BGE_PCIMISCCTL_TAGGED_STATUS;
 2188                         if (bootverbose)
 2189                                 device_printf(dev, "enable status tag\n");
 2190                 }
 2191         }
 2192 
 2193         if (BGE_IS_5755_PLUS(sc)) {
 2194                 /*
 2195                  * BCM5754 and BCM5787 shares the same ASIC id so
 2196                  * explicit device id check is required.
 2197                  * Due to unknown reason TSO does not work on BCM5755M.
 2198                  */
 2199                 if (product != PCI_PRODUCT_BROADCOM_BCM5754 &&
 2200                     product != PCI_PRODUCT_BROADCOM_BCM5754M &&
 2201                     product != PCI_PRODUCT_BROADCOM_BCM5755M)
 2202                         sc->bge_flags |= BGE_FLAG_TSO;
 2203         }
 2204 
 2205         /*
 2206          * Set various PHY quirk flags.
 2207          */
 2208 
 2209         if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
 2210              sc->bge_asicrev == BGE_ASICREV_BCM5701) &&
 2211             pci_get_subvendor(dev) == PCI_VENDOR_DELL)
 2212                 mii_priv |= BRGPHY_FLAG_NO_3LED;
 2213 
 2214         capmask = MII_CAPMASK_DEFAULT;
 2215         if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
 2216              (misccfg == 0x4000 || misccfg == 0x8000)) ||
 2217             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
 2218              vendor == PCI_VENDOR_BROADCOM &&
 2219              (product == PCI_PRODUCT_BROADCOM_BCM5901 ||
 2220               product == PCI_PRODUCT_BROADCOM_BCM5901A2 ||
 2221               product == PCI_PRODUCT_BROADCOM_BCM5705F)) ||
 2222             (vendor == PCI_VENDOR_BROADCOM &&
 2223              (product == PCI_PRODUCT_BROADCOM_BCM5751F ||
 2224               product == PCI_PRODUCT_BROADCOM_BCM5753F ||
 2225               product == PCI_PRODUCT_BROADCOM_BCM5787F)) ||
 2226             product == PCI_PRODUCT_BROADCOM_BCM57790 ||
 2227             sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 2228                 /* 10/100 only */
 2229                 capmask &= ~BMSR_EXTSTAT;
 2230         }
 2231 
 2232         mii_priv |= BRGPHY_FLAG_WIRESPEED;
 2233         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
 2234             (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
 2235              (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
 2236               sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) ||
 2237             sc->bge_asicrev == BGE_ASICREV_BCM5906)
 2238                 mii_priv &= ~BRGPHY_FLAG_WIRESPEED;
 2239 
 2240         if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
 2241             sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
 2242                 mii_priv |= BRGPHY_FLAG_CRC_BUG;
 2243 
 2244         if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
 2245             sc->bge_chiprev == BGE_CHIPREV_5704_AX)
 2246                 mii_priv |= BRGPHY_FLAG_ADC_BUG;
 2247 
 2248         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
 2249                 mii_priv |= BRGPHY_FLAG_5704_A0;
 2250 
 2251         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 2252                 mii_priv |= BRGPHY_FLAG_5906;
 2253 
 2254         if (BGE_IS_5705_PLUS(sc) &&
 2255             sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
 2256             /* sc->bge_asicrev != BGE_ASICREV_BCM5717 && */
 2257             sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
 2258             /* sc->bge_asicrev != BGE_ASICREV_BCM57765 && */
 2259             sc->bge_asicrev != BGE_ASICREV_BCM57780) {
 2260                 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
 2261                     sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
 2262                     sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
 2263                     sc->bge_asicrev == BGE_ASICREV_BCM5787) {
 2264                         if (product != PCI_PRODUCT_BROADCOM_BCM5722 &&
 2265                             product != PCI_PRODUCT_BROADCOM_BCM5756)
 2266                                 mii_priv |= BRGPHY_FLAG_JITTER_BUG;
 2267                         if (product == PCI_PRODUCT_BROADCOM_BCM5755M)
 2268                                 mii_priv |= BRGPHY_FLAG_ADJUST_TRIM;
 2269                 } else {
 2270                         mii_priv |= BRGPHY_FLAG_BER_BUG;
 2271                 }
 2272         }
 2273 
 2274         /*
 2275          * Allocate interrupt
 2276          */
 2277         msi_enable = bge_msi_enable;
 2278         if ((sc->bge_flags & BGE_FLAG_STATUS_TAG) == 0) {
 2279                 /* If "tagged status" is disabled, don't enable MSI */
 2280                 msi_enable = 0;
 2281         } else if (msi_enable) {
 2282                 msi_enable = 0; /* Disable by default */
 2283                 if (BGE_IS_575X_PLUS(sc)) {
 2284                         msi_enable = 1;
 2285                         /* XXX we filter all 5714 chips */
 2286                         if (sc->bge_asicrev == BGE_ASICREV_BCM5714 ||
 2287                             (sc->bge_asicrev == BGE_ASICREV_BCM5750 &&
 2288                              (sc->bge_chiprev == BGE_CHIPREV_5750_AX ||
 2289                               sc->bge_chiprev == BGE_CHIPREV_5750_BX)))
 2290                                 msi_enable = 0;
 2291                         else if (BGE_IS_5755_PLUS(sc) ||
 2292                             sc->bge_asicrev == BGE_ASICREV_BCM5906)
 2293                                 sc->bge_flags |= BGE_FLAG_ONESHOT_MSI;
 2294                 }
 2295         }
 2296         if (msi_enable) {
 2297                 if (pci_find_extcap(dev, PCIY_MSI, &sc->bge_msicap)) {
 2298                         device_printf(dev, "no MSI capability\n");
 2299                         msi_enable = 0;
 2300                 }
 2301         }
 2302 
 2303         sc->bge_irq_type = pci_alloc_1intr(dev, msi_enable, &sc->bge_irq_rid,
 2304             &intr_flags);
 2305 
 2306         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->bge_irq_rid,
 2307             intr_flags);
 2308         if (sc->bge_irq == NULL) {
 2309                 device_printf(dev, "couldn't map interrupt\n");
 2310                 error = ENXIO;
 2311                 goto fail;
 2312         }
 2313 
 2314         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
 2315                 bge_enable_msi(sc);
 2316         else
 2317                 sc->bge_flags &= ~BGE_FLAG_ONESHOT_MSI;
 2318 
 2319         /* Initialize if_name earlier, so if_printf could be used */
 2320         ifp = &sc->arpcom.ac_if;
 2321         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 2322 
 2323         sc->bge_asf_mode = 0;
 2324         /* No ASF if APE present. */
 2325         if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
 2326                 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
 2327                     BGE_SRAM_DATA_SIG_MAGIC)) {
 2328                         if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
 2329                             BGE_HWCFG_ASF) {
 2330                                 sc->bge_asf_mode |= ASF_ENABLE;
 2331                                 sc->bge_asf_mode |= ASF_STACKUP;
 2332                                 if (BGE_IS_575X_PLUS(sc))
 2333                                         sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
 2334                         }
 2335                 }
 2336         }
 2337 
 2338         /*
 2339          * Try to reset the chip.
 2340          */
 2341         bge_stop_fw(sc);
 2342         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
 2343         bge_reset(sc);
 2344         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
 2345         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
 2346 
 2347         if (bge_chipinit(sc)) {
 2348                 device_printf(dev, "chip initialization failed\n");
 2349                 error = ENXIO;
 2350                 goto fail;
 2351         }
 2352 
 2353         /*
 2354          * Get station address
 2355          */
 2356         error = bge_get_eaddr(sc, ether_addr);
 2357         if (error) {
 2358                 device_printf(dev, "failed to read station address\n");
 2359                 goto fail;
 2360         }
 2361 
 2362         /* 5705/5750 limits RX return ring to 512 entries. */
 2363         if (BGE_IS_5705_PLUS(sc))
 2364                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
 2365         else
 2366                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
 2367 
 2368         error = bge_dma_alloc(sc);
 2369         if (error)
 2370                 goto fail;
 2371 
 2372         /* Set default tuneable values. */
 2373         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
 2374         sc->bge_rx_coal_ticks = BGE_RX_COAL_TICKS_DEF;
 2375         sc->bge_tx_coal_ticks = BGE_TX_COAL_TICKS_DEF;
 2376         sc->bge_rx_coal_bds = BGE_RX_COAL_BDS_DEF;
 2377         sc->bge_tx_coal_bds = BGE_TX_COAL_BDS_DEF;
 2378         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
 2379                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_DEF;
 2380                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_DEF;
 2381                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_DEF;
 2382                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_DEF;
 2383         } else {
 2384                 sc->bge_rx_coal_ticks_int = BGE_RX_COAL_TICKS_MIN;
 2385                 sc->bge_tx_coal_ticks_int = BGE_TX_COAL_TICKS_MIN;
 2386                 sc->bge_rx_coal_bds_int = BGE_RX_COAL_BDS_MIN;
 2387                 sc->bge_tx_coal_bds_int = BGE_TX_COAL_BDS_MIN;
 2388         }
 2389         sc->bge_tx_wreg = BGE_TX_WREG_NSEGS;
 2390 
 2391         /* Set up TX spare and reserved descriptor count */
 2392         if (sc->bge_flags & BGE_FLAG_TSO) {
 2393                 sc->bge_txspare = BGE_NSEG_SPARE_TSO;
 2394                 sc->bge_txrsvd = BGE_NSEG_RSVD_TSO;
 2395         } else {
 2396                 sc->bge_txspare = BGE_NSEG_SPARE;
 2397                 sc->bge_txrsvd = BGE_NSEG_RSVD;
 2398         }
 2399 
 2400         /* Set up ifnet structure */
 2401         ifp->if_softc = sc;
 2402         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 2403         ifp->if_ioctl = bge_ioctl;
 2404         ifp->if_start = bge_start;
 2405 #ifdef IFPOLL_ENABLE
 2406         ifp->if_npoll = bge_npoll;
 2407 #endif
 2408         ifp->if_watchdog = bge_watchdog;
 2409         ifp->if_init = bge_init;
 2410         ifp->if_mtu = ETHERMTU;
 2411         ifp->if_capabilities = IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
 2412         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
 2413         ifq_set_ready(&ifp->if_snd);
 2414 
 2415         /*
 2416          * 5700 B0 chips do not support checksumming correctly due
 2417          * to hardware bugs.
 2418          */
 2419         if (sc->bge_chipid != BGE_CHIPID_BCM5700_B0) {
 2420                 ifp->if_capabilities |= IFCAP_HWCSUM;
 2421                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
 2422         }
 2423         if (sc->bge_flags & BGE_FLAG_TSO) {
 2424                 ifp->if_capabilities |= IFCAP_TSO;
 2425                 ifp->if_hwassist |= CSUM_TSO;
 2426         }
 2427         ifp->if_capenable = ifp->if_capabilities;
 2428 
 2429         /*
 2430          * Figure out what sort of media we have by checking the
 2431          * hardware config word in the first 32k of NIC internal memory,
 2432          * or fall back to examining the EEPROM if necessary.
 2433          * Note: on some BCM5700 cards, this value appears to be unset.
 2434          * If that's the case, we have to rely on identifying the NIC
 2435          * by its PCI subsystem ID, as we do below for the SysKonnect
 2436          * SK-9D41.
 2437          */
 2438         if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) {
 2439                 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
 2440         } else {
 2441                 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
 2442                                     sizeof(hwcfg))) {
 2443                         device_printf(dev, "failed to read EEPROM\n");
 2444                         error = ENXIO;
 2445                         goto fail;
 2446                 }
 2447                 hwcfg = ntohl(hwcfg);
 2448         }
 2449 
 2450         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
 2451         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41 ||
 2452             (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
 2453                 if (BGE_IS_5714_FAMILY(sc))
 2454                         sc->bge_flags |= BGE_FLAG_MII_SERDES;
 2455                 else
 2456                         sc->bge_flags |= BGE_FLAG_TBI;
 2457         }
 2458 
 2459         /* Setup MI MODE */
 2460         if (sc->bge_flags & BGE_FLAG_CPMU)
 2461                 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
 2462         else
 2463                 sc->bge_mi_mode = BGE_MIMODE_BASE;
 2464         if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) {
 2465                 /* Enable auto polling for BCM570[0-5]. */
 2466                 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
 2467         }
 2468 
 2469         /* Setup link status update stuffs */
 2470         if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
 2471             sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
 2472                 sc->bge_link_upd = bge_bcm5700_link_upd;
 2473                 sc->bge_link_chg = BGE_MACSTAT_MI_INTERRUPT;
 2474         } else if (sc->bge_flags & BGE_FLAG_TBI) {
 2475                 sc->bge_link_upd = bge_tbi_link_upd;
 2476                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
 2477         } else if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
 2478                 sc->bge_link_upd = bge_autopoll_link_upd;
 2479                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
 2480         } else {
 2481                 sc->bge_link_upd = bge_copper_link_upd;
 2482                 sc->bge_link_chg = BGE_MACSTAT_LINK_CHANGED;
 2483         }
 2484 
 2485         /*
 2486          * Broadcom's own driver always assumes the internal
 2487          * PHY is at GMII address 1.  On some chips, the PHY responds
 2488          * to accesses at all addresses, which could cause us to
 2489          * bogusly attach the PHY 32 times at probe type.  Always
 2490          * restricting the lookup to address 1 is simpler than
 2491          * trying to figure out which chips revisions should be
 2492          * special-cased.
 2493          */
 2494         sc->bge_phyno = 1;
 2495 
 2496         if (sc->bge_flags & BGE_FLAG_TBI) {
 2497                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
 2498                     bge_ifmedia_upd, bge_ifmedia_sts);
 2499                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
 2500                 ifmedia_add(&sc->bge_ifmedia,
 2501                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
 2502                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
 2503                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
 2504                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
 2505         } else {
 2506                 struct mii_probe_args mii_args;
 2507                 int tries;
 2508 
 2509                 /*
 2510                  * Do transceiver setup and tell the firmware the
 2511                  * driver is down so we can try to get access the
 2512                  * probe if ASF is running.  Retry a couple of times
 2513                  * if we get a conflict with the ASF firmware accessing
 2514                  * the PHY.
 2515                  */
 2516                 tries = 0;
 2517                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 2518 again:
 2519                 bge_asf_driver_up(sc);
 2520 
 2521                 mii_probe_args_init(&mii_args, bge_ifmedia_upd, bge_ifmedia_sts);
 2522                 mii_args.mii_probemask = 1 << sc->bge_phyno;
 2523                 mii_args.mii_capmask = capmask;
 2524                 mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
 2525                 mii_args.mii_priv = mii_priv;
 2526 
 2527                 error = mii_probe(dev, &sc->bge_miibus, &mii_args);
 2528                 if (error) {
 2529                         if (tries++ < 4) {
 2530                                 device_printf(sc->bge_dev, "Probe MII again\n");
 2531                                 bge_miibus_writereg(sc->bge_dev,
 2532                                     sc->bge_phyno, MII_BMCR, BMCR_RESET);
 2533                                 goto again;
 2534                         }
 2535                         device_printf(dev, "MII without any PHY!\n");
 2536                         goto fail;
 2537                 }
 2538 
 2539                 /*
 2540                  * Now tell the firmware we are going up after probing the PHY
 2541                  */
 2542                 if (sc->bge_asf_mode & ASF_STACKUP)
 2543                         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 2544         }
 2545 
 2546         /*
 2547          * Create sysctl nodes.
 2548          */
 2549         sysctl_ctx_init(&sc->bge_sysctl_ctx);
 2550         sc->bge_sysctl_tree = SYSCTL_ADD_NODE(&sc->bge_sysctl_ctx,
 2551                                               SYSCTL_STATIC_CHILDREN(_hw),
 2552                                               OID_AUTO,
 2553                                               device_get_nameunit(dev),
 2554                                               CTLFLAG_RD, 0, "");
 2555         if (sc->bge_sysctl_tree == NULL) {
 2556                 device_printf(dev, "can't add sysctl node\n");
 2557                 error = ENXIO;
 2558                 goto fail;
 2559         }
 2560 
 2561         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
 2562                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
 2563                         OID_AUTO, "rx_coal_ticks",
 2564                         CTLTYPE_INT | CTLFLAG_RW,
 2565                         sc, 0, bge_sysctl_rx_coal_ticks, "I",
 2566                         "Receive coalescing ticks (usec).");
 2567         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
 2568                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
 2569                         OID_AUTO, "tx_coal_ticks",
 2570                         CTLTYPE_INT | CTLFLAG_RW,
 2571                         sc, 0, bge_sysctl_tx_coal_ticks, "I",
 2572                         "Transmit coalescing ticks (usec).");
 2573         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
 2574                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
 2575                         OID_AUTO, "rx_coal_bds",
 2576                         CTLTYPE_INT | CTLFLAG_RW,
 2577                         sc, 0, bge_sysctl_rx_coal_bds, "I",
 2578                         "Receive max coalesced BD count.");
 2579         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
 2580                         SYSCTL_CHILDREN(sc->bge_sysctl_tree),
 2581                         OID_AUTO, "tx_coal_bds",
 2582                         CTLTYPE_INT | CTLFLAG_RW,
 2583                         sc, 0, bge_sysctl_tx_coal_bds, "I",
 2584                         "Transmit max coalesced BD count.");
 2585 
 2586         SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
 2587                        SYSCTL_CHILDREN(sc->bge_sysctl_tree),
 2588                        OID_AUTO, "tx_wreg", CTLFLAG_RW,
 2589                        &sc->bge_tx_wreg, 0,
 2590                        "# of segments before writing to hardware register");
 2591 
 2592         if (sc->bge_flags & BGE_FLAG_PCIE) {
 2593                 /*
 2594                  * A common design characteristic for many Broadcom
 2595                  * client controllers is that they only support a
 2596                  * single outstanding DMA read operation on the PCIe
 2597                  * bus. This means that it will take twice as long to
 2598                  * fetch a TX frame that is split into header and
 2599                  * payload buffers as it does to fetch a single,
 2600                  * contiguous TX frame (2 reads vs. 1 read). For these
 2601                  * controllers, coalescing buffers to reduce the number
 2602                  * of memory reads is effective way to get maximum
 2603                  * performance(about 940Mbps).  Without collapsing TX
 2604                  * buffers the maximum TCP bulk transfer performance
 2605                  * is about 850Mbps. However forcing coalescing mbufs
 2606                  * consumes a lot of CPU cycles, so leave it off by
 2607                  * default.
 2608                  */
 2609                 SYSCTL_ADD_INT(&sc->bge_sysctl_ctx,
 2610                                SYSCTL_CHILDREN(sc->bge_sysctl_tree),
 2611                                OID_AUTO, "force_defrag", CTLFLAG_RW,
 2612                                &sc->bge_force_defrag, 0,
 2613                                "Force defragment on TX path");
 2614         }
 2615         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
 2616                 if (!BGE_IS_5705_PLUS(sc)) {
 2617                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
 2618                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
 2619                             "rx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
 2620                             sc, 0, bge_sysctl_rx_coal_ticks_int, "I",
 2621                             "Receive coalescing ticks "
 2622                             "during interrupt (usec).");
 2623                         SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
 2624                             SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
 2625                             "tx_coal_ticks_int", CTLTYPE_INT | CTLFLAG_RW,
 2626                             sc, 0, bge_sysctl_tx_coal_ticks_int, "I",
 2627                             "Transmit coalescing ticks "
 2628                             "during interrupt (usec).");
 2629                 }
 2630                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
 2631                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
 2632                     "rx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
 2633                     sc, 0, bge_sysctl_rx_coal_bds_int, "I",
 2634                     "Receive max coalesced BD count during interrupt.");
 2635                 SYSCTL_ADD_PROC(&sc->bge_sysctl_ctx,
 2636                     SYSCTL_CHILDREN(sc->bge_sysctl_tree), OID_AUTO,
 2637                     "tx_coal_bds_int", CTLTYPE_INT | CTLFLAG_RW,
 2638                     sc, 0, bge_sysctl_tx_coal_bds_int, "I",
 2639                     "Transmit max coalesced BD count during interrupt.");
 2640         }
 2641 
 2642         /*
 2643          * Call MI attach routine.
 2644          */
 2645         ether_ifattach(ifp, ether_addr, NULL);
 2646 
 2647         ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq));
 2648 
 2649 #ifdef IFPOLL_ENABLE
 2650         /* Polling setup */
 2651         ifpoll_compat_setup(&sc->bge_npoll,
 2652             &sc->bge_sysctl_ctx, sc->bge_sysctl_tree, device_get_unit(dev),
 2653             ifp->if_serializer);
 2654 #endif
 2655 
 2656         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
 2657                 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
 2658                         intr_func = bge_msi_oneshot;
 2659                         if (bootverbose)
 2660                                 device_printf(dev, "oneshot MSI\n");
 2661                 } else {
 2662                         intr_func = bge_msi;
 2663                 }
 2664         } else if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
 2665                 intr_func = bge_intr_legacy;
 2666         } else {
 2667                 intr_func = bge_intr_crippled;
 2668         }
 2669         error = bus_setup_intr(dev, sc->bge_irq, INTR_MPSAFE, intr_func, sc,
 2670             &sc->bge_intrhand, ifp->if_serializer);
 2671         if (error) {
 2672                 ether_ifdetach(ifp);
 2673                 device_printf(dev, "couldn't set up irq\n");
 2674                 goto fail;
 2675         }
 2676 
 2677         return(0);
 2678 fail:
 2679         bge_detach(dev);
 2680         return(error);
 2681 }
 2682 
 2683 static int
 2684 bge_detach(device_t dev)
 2685 {
 2686         struct bge_softc *sc = device_get_softc(dev);
 2687 
 2688         if (device_is_attached(dev)) {
 2689                 struct ifnet *ifp = &sc->arpcom.ac_if;
 2690 
 2691                 lwkt_serialize_enter(ifp->if_serializer);
 2692                 bge_stop(sc);
 2693                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
 2694                 lwkt_serialize_exit(ifp->if_serializer);
 2695 
 2696                 ether_ifdetach(ifp);
 2697         }
 2698 
 2699         if (sc->bge_flags & BGE_FLAG_TBI)
 2700                 ifmedia_removeall(&sc->bge_ifmedia);
 2701         if (sc->bge_miibus)
 2702                 device_delete_child(dev, sc->bge_miibus);
 2703         bus_generic_detach(dev);
 2704 
 2705         if (sc->bge_irq != NULL) {
 2706                 bus_release_resource(dev, SYS_RES_IRQ, sc->bge_irq_rid,
 2707                     sc->bge_irq);
 2708         }
 2709         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI)
 2710                 pci_release_msi(dev);
 2711 
 2712         if (sc->bge_res != NULL) {
 2713                 bus_release_resource(dev, SYS_RES_MEMORY,
 2714                     BGE_PCI_BAR0, sc->bge_res);
 2715         }
 2716 
 2717         if (sc->bge_sysctl_tree != NULL)
 2718                 sysctl_ctx_free(&sc->bge_sysctl_ctx);
 2719 
 2720         bge_dma_free(sc);
 2721 
 2722         return 0;
 2723 }
 2724 
 2725 static void
 2726 bge_reset(struct bge_softc *sc)
 2727 {
 2728         device_t dev = sc->bge_dev;
 2729         uint32_t cachesize, command, reset, mac_mode, mac_mode_mask;
 2730         void (*write_op)(struct bge_softc *, uint32_t, uint32_t);
 2731         int i, val = 0;
 2732 
 2733         mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
 2734         mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
 2735 
 2736         if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
 2737             sc->bge_asicrev != BGE_ASICREV_BCM5906) {
 2738                 if (sc->bge_flags & BGE_FLAG_PCIE)
 2739                         write_op = bge_writemem_direct;
 2740                 else
 2741                         write_op = bge_writemem_ind;
 2742         } else {
 2743                 write_op = bge_writereg_ind;
 2744         }
 2745 
 2746         /* Save some important PCI state. */
 2747         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
 2748         command = pci_read_config(dev, BGE_PCI_CMD, 4);
 2749 
 2750         pci_write_config(dev, BGE_PCI_MISC_CTL,
 2751             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
 2752             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
 2753             sc->bge_pci_miscctl, 4);
 2754 
 2755         /* Disable fastboot on controllers that support it. */
 2756         if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
 2757             BGE_IS_5755_PLUS(sc)) {
 2758                 if (bootverbose)
 2759                         if_printf(&sc->arpcom.ac_if, "Disabling fastboot\n");
 2760                 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
 2761         }
 2762 
 2763         /*
 2764          * Write the magic number to SRAM at offset 0xB50.
 2765          * When firmware finishes its initialization it will
 2766          * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
 2767          */
 2768         bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
 2769 
 2770         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
 2771 
 2772         /* XXX: Broadcom Linux driver. */
 2773         if (sc->bge_flags & BGE_FLAG_PCIE) {
 2774                 /* Force PCI-E 1.0a mode */
 2775                 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
 2776                     CSR_READ_4(sc, BGE_PCIE_PHY_TSTCTL) ==
 2777                     (BGE_PCIE_PHY_TSTCTL_PSCRAM |
 2778                      BGE_PCIE_PHY_TSTCTL_PCIE10)) {
 2779                         CSR_WRITE_4(sc, BGE_PCIE_PHY_TSTCTL,
 2780                             BGE_PCIE_PHY_TSTCTL_PSCRAM);
 2781                 }
 2782                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
 2783                         /* Prevent PCIE link training during global reset */
 2784                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
 2785                         reset |= (1<<29);
 2786                 }
 2787         }
 2788 
 2789         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 2790                 uint32_t status, ctrl;
 2791 
 2792                 status = CSR_READ_4(sc, BGE_VCPU_STATUS);
 2793                 CSR_WRITE_4(sc, BGE_VCPU_STATUS,
 2794                     status | BGE_VCPU_STATUS_DRV_RESET);
 2795                 ctrl = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
 2796                 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
 2797                     ctrl & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
 2798         }
 2799 
 2800         /* 
 2801          * Set GPHY Power Down Override to leave GPHY
 2802          * powered up in D0 uninitialized.
 2803          */
 2804         if (BGE_IS_5705_PLUS(sc) && (sc->bge_flags & BGE_FLAG_CPMU) == 0)
 2805                 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
 2806 
 2807         /* Issue global reset */
 2808         write_op(sc, BGE_MISC_CFG, reset);
 2809 
 2810         if (sc->bge_flags & BGE_FLAG_PCIE)
 2811                 DELAY(100 * 1000);
 2812         else
 2813                 DELAY(1000);
 2814 
 2815         /* XXX: Broadcom Linux driver. */
 2816         if (sc->bge_flags & BGE_FLAG_PCIE) {
 2817                 uint16_t devctl;
 2818 
 2819                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
 2820                         uint32_t v;
 2821 
 2822                         DELAY(500000); /* wait for link training to complete */
 2823                         v = pci_read_config(dev, 0xc4, 4);
 2824                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
 2825                 }
 2826 
 2827                 devctl = pci_read_config(dev,
 2828                     sc->bge_pciecap + PCIER_DEVCTRL, 2);
 2829 
 2830                 /* Disable no snoop and disable relaxed ordering. */
 2831                 devctl &= ~(PCIEM_DEVCTL_RELAX_ORDER | PCIEM_DEVCTL_NOSNOOP);
 2832 
 2833                 /* Old PCI-E chips only support 128 bytes Max PayLoad Size. */
 2834                 if ((sc->bge_flags & BGE_FLAG_CPMU) == 0) {
 2835                         devctl &= ~PCIEM_DEVCTL_MAX_PAYLOAD_MASK;
 2836                         devctl |= PCIEM_DEVCTL_MAX_PAYLOAD_128;
 2837                 }
 2838 
 2839                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVCTRL,
 2840                     devctl, 2);
 2841 
 2842                 /* Clear error status. */
 2843                 pci_write_config(dev, sc->bge_pciecap + PCIER_DEVSTS,
 2844                     PCIEM_DEVSTS_CORR_ERR |
 2845                     PCIEM_DEVSTS_NFATAL_ERR |
 2846                     PCIEM_DEVSTS_FATAL_ERR |
 2847                     PCIEM_DEVSTS_UNSUPP_REQ, 2);
 2848         }
 2849 
 2850         /* Reset some of the PCI state that got zapped by reset */
 2851         pci_write_config(dev, BGE_PCI_MISC_CTL,
 2852             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
 2853             BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW|
 2854             sc->bge_pci_miscctl, 4);
 2855         val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
 2856         if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
 2857             (sc->bge_flags & BGE_FLAG_PCIX))
 2858                 val |= BGE_PCISTATE_RETRY_SAME_DMA;
 2859         pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
 2860         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
 2861         pci_write_config(dev, BGE_PCI_CMD, command, 4);
 2862 
 2863         /*
 2864          * Disable PCI-X relaxed ordering to ensure status block update
 2865          * comes first then packet buffer DMA. Otherwise driver may
 2866          * read stale status block.
 2867          */
 2868         if (sc->bge_flags & BGE_FLAG_PCIX) {
 2869                 uint16_t devctl;
 2870 
 2871                 devctl = pci_read_config(dev,
 2872                     sc->bge_pcixcap + PCIXR_COMMAND, 2);
 2873                 devctl &= ~PCIXM_COMMAND_ERO;
 2874                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
 2875                         devctl &= ~PCIXM_COMMAND_MAX_READ;
 2876                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
 2877                 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 2878                         devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
 2879                             PCIXM_COMMAND_MAX_READ);
 2880                         devctl |= PCIXM_COMMAND_MAX_READ_2048;
 2881                 }
 2882                 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
 2883                     devctl, 2);
 2884         }
 2885 
 2886         /*
 2887          * Enable memory arbiter and re-enable MSI if necessary.
 2888          */
 2889         if (BGE_IS_5714_FAMILY(sc)) {
 2890                 uint32_t val;
 2891 
 2892                 if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
 2893                         /*
 2894                          * Resetting BCM5714 family will clear MSI
 2895                          * enable bit; restore it after resetting.
 2896                          */
 2897                         PCI_SETBIT(sc->bge_dev, sc->bge_msicap + PCIR_MSI_CTRL,
 2898                             PCIM_MSICTRL_MSI_ENABLE, 2);
 2899                         BGE_SETBIT(sc, BGE_MSI_MODE, BGE_MSIMODE_ENABLE);
 2900                 }
 2901                 val = CSR_READ_4(sc, BGE_MARB_MODE);
 2902                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
 2903         } else {
 2904                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
 2905         }
 2906 
 2907         /* Fix up byte swapping. */
 2908         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS |
 2909             BGE_MODECTL_BYTESWAP_DATA);
 2910 
 2911         val = CSR_READ_4(sc, BGE_MAC_MODE);
 2912         val = (val & ~mac_mode_mask) | mac_mode;
 2913         CSR_WRITE_4(sc, BGE_MAC_MODE, val);
 2914         DELAY(40);
 2915 
 2916         if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
 2917                 for (i = 0; i < BGE_TIMEOUT; i++) {
 2918                         val = CSR_READ_4(sc, BGE_VCPU_STATUS);
 2919                         if (val & BGE_VCPU_STATUS_INIT_DONE)
 2920                                 break;
 2921                         DELAY(100);
 2922                 }
 2923                 if (i == BGE_TIMEOUT) {
 2924                         if_printf(&sc->arpcom.ac_if, "reset timed out\n");
 2925                         return;
 2926                 }
 2927         } else {
 2928                 /*
 2929                  * Poll until we see the 1's complement of the magic number.
 2930                  * This indicates that the firmware initialization
 2931                  * is complete.
 2932                  */
 2933                 for (i = 0; i < BGE_FIRMWARE_TIMEOUT; i++) {
 2934                         val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
 2935                         if (val == ~BGE_SRAM_FW_MB_MAGIC)
 2936                                 break;
 2937                         DELAY(10);
 2938                 }
 2939                 if (i == BGE_FIRMWARE_TIMEOUT) {
 2940                         if_printf(&sc->arpcom.ac_if, "firmware handshake "
 2941                                   "timed out, found 0x%08x\n", val);
 2942                 }
 2943         }
 2944 
 2945         /*
 2946          * The 5704 in TBI mode apparently needs some special
 2947          * adjustment to insure the SERDES drive level is set
 2948          * to 1.2V.
 2949          */
 2950         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
 2951             (sc->bge_flags & BGE_FLAG_TBI)) {
 2952                 uint32_t serdescfg;
 2953 
 2954                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
 2955                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
 2956                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
 2957         }
 2958 
 2959         /* XXX: Broadcom Linux driver. */
 2960         if ((sc->bge_flags & BGE_FLAG_PCIE) &&
 2961             sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
 2962             sc->bge_asicrev != BGE_ASICREV_BCM5785) {
 2963                 uint32_t v;
 2964 
 2965                 /* Enable Data FIFO protection. */
 2966                 v = CSR_READ_4(sc, BGE_PCIE_TLDLPL_PORT);
 2967                 CSR_WRITE_4(sc, BGE_PCIE_TLDLPL_PORT, v | (1 << 25));
 2968         }
 2969 
 2970         DELAY(10000);
 2971 }
 2972 
 2973 /*
 2974  * Frame reception handling. This is called if there's a frame
 2975  * on the receive return list.
 2976  *
 2977  * Note: we have to be able to handle two possibilities here:
 2978  * 1) the frame is from the jumbo recieve ring
 2979  * 2) the frame is from the standard receive ring
 2980  */
 2981 
 2982 static void
 2983 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int count)
 2984 {
 2985         struct ifnet *ifp;
 2986         int stdcnt = 0, jumbocnt = 0;
 2987 
 2988         ifp = &sc->arpcom.ac_if;
 2989 
 2990         while (sc->bge_rx_saved_considx != rx_prod && count != 0) {
 2991                 struct bge_rx_bd        *cur_rx;
 2992                 uint32_t                rxidx;
 2993                 struct mbuf             *m = NULL;
 2994                 uint16_t                vlan_tag = 0;
 2995                 int                     have_tag = 0;
 2996 
 2997                 --count;
 2998 
 2999                 cur_rx =
 3000             &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx];
 3001 
 3002                 rxidx = cur_rx->bge_idx;
 3003                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
 3004                 logif(rx_pkt);
 3005 
 3006                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
 3007                         have_tag = 1;
 3008                         vlan_tag = cur_rx->bge_vlan_tag;
 3009                 }
 3010 
 3011                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
 3012                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
 3013                         jumbocnt++;
 3014 
 3015                         if (rxidx != sc->bge_jumbo) {
 3016                                 IFNET_STAT_INC(ifp, ierrors, 1);
 3017                                 if_printf(ifp, "sw jumbo index(%d) "
 3018                                     "and hw jumbo index(%d) mismatch, drop!\n",
 3019                                     sc->bge_jumbo, rxidx);
 3020                                 bge_setup_rxdesc_jumbo(sc, rxidx);
 3021                                 continue;
 3022                         }
 3023 
 3024                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx].bge_mbuf;
 3025                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
 3026                                 IFNET_STAT_INC(ifp, ierrors, 1);
 3027                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
 3028                                 continue;
 3029                         }
 3030                         if (bge_newbuf_jumbo(sc, sc->bge_jumbo, 0)) {
 3031                                 IFNET_STAT_INC(ifp, ierrors, 1);
 3032                                 bge_setup_rxdesc_jumbo(sc, sc->bge_jumbo);
 3033                                 continue;
 3034                         }
 3035                 } else {
 3036                         int discard = 0;
 3037 
 3038                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
 3039                         stdcnt++;
 3040 
 3041                         if (rxidx != sc->bge_std) {
 3042                                 IFNET_STAT_INC(ifp, ierrors, 1);
 3043                                 if_printf(ifp, "sw std index(%d) "
 3044                                     "and hw std index(%d) mismatch, drop!\n",
 3045                                     sc->bge_std, rxidx);
 3046                                 bge_setup_rxdesc_std(sc, rxidx);
 3047                                 discard = 1;
 3048                                 goto refresh_rx;
 3049                         }
 3050 
 3051                         m = sc->bge_cdata.bge_rx_std_chain[rxidx].bge_mbuf;
 3052                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
 3053                                 IFNET_STAT_INC(ifp, ierrors, 1);
 3054                                 bge_setup_rxdesc_std(sc, sc->bge_std);
 3055                                 discard = 1;
 3056                                 goto refresh_rx;
 3057                         }
 3058                         if (bge_newbuf_std(sc, sc->bge_std, 0)) {
 3059                                 IFNET_STAT_INC(ifp, ierrors, 1);
 3060                                 bge_setup_rxdesc_std(sc, sc->bge_std);
 3061                                 discard = 1;
 3062                         }
 3063 refresh_rx:
 3064                         if (sc->bge_rx_wreg > 0 && stdcnt >= sc->bge_rx_wreg) {
 3065                                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO,
 3066                                     sc->bge_std);
 3067                                 stdcnt = 0;
 3068                         }
 3069                         if (discard)
 3070                                 continue;
 3071                 }
 3072 
 3073                 IFNET_STAT_INC(ifp, ipackets, 1);
 3074 #if !defined(__i386__) && !defined(__x86_64__)
 3075                 /*
 3076                  * The x86 allows unaligned accesses, but for other
 3077                  * platforms we must make sure the payload is aligned.
 3078                  */
 3079                 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
 3080                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
 3081                             cur_rx->bge_len);
 3082                         m->m_data += ETHER_ALIGN;
 3083                 }
 3084 #endif
 3085                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
 3086                 m->m_pkthdr.rcvif = ifp;
 3087 
 3088                 if (ifp->if_capenable & IFCAP_RXCSUM) {
 3089                         if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
 3090                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
 3091                                 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
 3092                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
 3093                         }
 3094                         if ((cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) &&
 3095                             m->m_pkthdr.len >= BGE_MIN_FRAMELEN) {
 3096                                 m->m_pkthdr.csum_data =
 3097                                         cur_rx->bge_tcp_udp_csum;
 3098                                 m->m_pkthdr.csum_flags |=
 3099                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
 3100                         }
 3101                 }
 3102 
 3103                 /*
 3104                  * If we received a packet with a vlan tag, pass it
 3105                  * to vlan_input() instead of ether_input().
 3106                  */
 3107                 if (have_tag) {
 3108                         m->m_flags |= M_VLANTAG;
 3109                         m->m_pkthdr.ether_vlantag = vlan_tag;
 3110                 }
 3111                 ifp->if_input(ifp, m);
 3112         }
 3113 
 3114         bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
 3115         if (stdcnt)
 3116                 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 3117         if (jumbocnt)
 3118                 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 3119 }
 3120 
 3121 static void
 3122 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
 3123 {
 3124         struct ifnet *ifp;
 3125 
 3126         ifp = &sc->arpcom.ac_if;
 3127 
 3128         /*
 3129          * Go through our tx ring and free mbufs for those
 3130          * frames that have been sent.
 3131          */
 3132         while (sc->bge_tx_saved_considx != tx_cons) {
 3133                 uint32_t idx = 0;
 3134 
 3135                 idx = sc->bge_tx_saved_considx;
 3136                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
 3137                         IFNET_STAT_INC(ifp, opackets, 1);
 3138                         bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
 3139                             sc->bge_cdata.bge_tx_dmamap[idx]);
 3140                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
 3141                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
 3142                 }
 3143                 sc->bge_txcnt--;
 3144                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
 3145                 logif(tx_pkt);
 3146         }
 3147 
 3148         if ((BGE_TX_RING_CNT - sc->bge_txcnt) >=
 3149             (sc->bge_txrsvd + sc->bge_txspare))
 3150                 ifq_clr_oactive(&ifp->if_snd);
 3151 
 3152         if (sc->bge_txcnt == 0)
 3153                 ifp->if_timer = 0;
 3154 
 3155         if (!ifq_is_empty(&ifp->if_snd))
 3156                 if_devstart(ifp);
 3157 }
 3158 
 3159 #ifdef IFPOLL_ENABLE
 3160 
 3161 static void
 3162 bge_npoll_compat(struct ifnet *ifp, void *arg __unused, int cycles)
 3163 {
 3164         struct bge_softc *sc = ifp->if_softc;
 3165         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
 3166         uint16_t rx_prod, tx_cons;
 3167 
 3168         ASSERT_SERIALIZED(ifp->if_serializer);
 3169 
 3170         if (sc->bge_npoll.ifpc_stcount-- == 0) {
 3171                 sc->bge_npoll.ifpc_stcount = sc->bge_npoll.ifpc_stfrac;
 3172                 /*
 3173                  * Process link state changes.
 3174                  */
 3175                 bge_link_poll(sc);
 3176         }
 3177 
 3178         if (sc->bge_flags & BGE_FLAG_STATUS_TAG) {
 3179                 sc->bge_status_tag = sblk->bge_status_tag;
 3180                 /*
 3181                  * Use a load fence to ensure that status_tag
 3182                  * is saved  before rx_prod and tx_cons.
 3183                  */
 3184                 cpu_lfence();
 3185         }
 3186 
 3187         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
 3188         if (sc->bge_rx_saved_considx != rx_prod)
 3189                 bge_rxeof(sc, rx_prod, cycles);
 3190 
 3191         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
 3192         if (sc->bge_tx_saved_considx != tx_cons)
 3193                 bge_txeof(sc, tx_cons);
 3194 
 3195         if (sc->bge_flags & BGE_FLAG_STATUS_TAG)
 3196                 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
 3197 
 3198         if (sc->bge_coal_chg)
 3199                 bge_coal_change(sc);
 3200 }
 3201 
 3202 static void
 3203 bge_npoll(struct ifnet *ifp, struct ifpoll_info *info)
 3204 {
 3205         struct bge_softc *sc = ifp->if_softc;
 3206 
 3207         ASSERT_SERIALIZED(ifp->if_serializer);
 3208 
 3209         if (info != NULL) {
 3210                 int cpuid = sc->bge_npoll.ifpc_cpuid;
 3211 
 3212                 info->ifpi_rx[cpuid].poll_func = bge_npoll_compat;
 3213                 info->ifpi_rx[cpuid].arg = NULL;
 3214                 info->ifpi_rx[cpuid].serializer = ifp->if_serializer;
 3215 
 3216                 if (ifp->if_flags & IFF_RUNNING)
 3217                         bge_disable_intr(sc);
 3218                 ifq_set_cpuid(&ifp->if_snd, cpuid);
 3219         } else {
 3220                 if (ifp->if_flags & IFF_RUNNING)
 3221                         bge_enable_intr(sc);
 3222                 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->bge_irq));
 3223         }
 3224 }
 3225 
 3226 #endif  /* IFPOLL_ENABLE */
 3227 
 3228 static void
 3229 bge_intr_crippled(void *xsc)
 3230 {
 3231         struct bge_softc *sc = xsc;
 3232         struct ifnet *ifp = &sc->arpcom.ac_if;
 3233 
 3234         logif(intr);
 3235 
 3236         /*
 3237          * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
 3238          * disable interrupts by writing nonzero like we used to, since with
 3239          * our current organization this just gives complications and
 3240          * pessimizations for re-enabling interrupts.  We used to have races
 3241          * instead of the necessary complications.  Disabling interrupts
 3242          * would just reduce the chance of a status update while we are
 3243          * running (by switching to the interrupt-mode coalescence
 3244          * parameters), but this chance is already very low so it is more
 3245          * efficient to get another interrupt than prevent it.
 3246          *
 3247          * We do the ack first to ensure another interrupt if there is a
 3248          * status update after the ack.  We don't check for the status
 3249          * changing later because it is more efficient to get another
 3250          * interrupt than prevent it, not quite as above (not checking is
 3251          * a smaller optimization than not toggling the interrupt enable,
 3252          * since checking doesn't involve PCI accesses and toggling require
 3253          * the status check).  So toggling would probably be a pessimization
 3254          * even with MSI.  It would only be needed for using a task queue.
 3255          */
 3256         bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
 3257 
 3258         /*
 3259          * Process link state changes.
 3260          */
 3261         bge_link_poll(sc);
 3262 
 3263         if (ifp->if_flags & IFF_RUNNING) {
 3264                 struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
 3265                 uint16_t rx_prod, tx_cons;
 3266 
 3267                 rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
 3268                 if (sc->bge_rx_saved_considx != rx_prod)
 3269                         bge_rxeof(sc, rx_prod, -1);
 3270 
 3271                 tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
 3272                 if (sc->bge_tx_saved_considx != tx_cons)
 3273                         bge_txeof(sc, tx_cons);
 3274         }
 3275 
 3276         if (sc->bge_coal_chg)
 3277                 bge_coal_change(sc);
 3278 }
 3279 
 3280 static void
 3281 bge_intr_legacy(void *xsc)
 3282 {
 3283         struct bge_softc *sc = xsc;
 3284         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
 3285 
 3286         if (sc->bge_status_tag == sblk->bge_status_tag) {
 3287                 uint32_t val;
 3288 
 3289                 val = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
 3290                 if (val & BGE_PCISTAT_INTR_NOTACT)
 3291                         return;
 3292         }
 3293 
 3294         /*
 3295          * NOTE:
 3296          * Interrupt will have to be disabled if tagged status
 3297          * is used, else interrupt will always be asserted on
 3298          * certain chips (at least on BCM5750 AX/BX).
 3299          */
 3300         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
 3301 
 3302         bge_intr(sc);
 3303 }
 3304 
 3305 static void
 3306 bge_msi(void *xsc)
 3307 {
 3308         struct bge_softc *sc = xsc;
 3309 
 3310         /* Disable interrupt first */
 3311         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
 3312         bge_intr(sc);
 3313 }
 3314 
 3315 static void
 3316 bge_msi_oneshot(void *xsc)
 3317 {
 3318         bge_intr(xsc);
 3319 }
 3320 
 3321 static void
 3322 bge_intr(struct bge_softc *sc)
 3323 {
 3324         struct ifnet *ifp = &sc->arpcom.ac_if;
 3325         struct bge_status_block *sblk = sc->bge_ldata.bge_status_block;
 3326         uint16_t rx_prod, tx_cons;
 3327         uint32_t status;
 3328 
 3329         sc->bge_status_tag = sblk->bge_status_tag;
 3330         /*
 3331          * Use a load fence to ensure that status_tag is saved 
 3332          * before rx_prod, tx_cons and status.
 3333          */
 3334         cpu_lfence();
 3335 
 3336         rx_prod = sblk->bge_idx[0].bge_rx_prod_idx;
 3337         tx_cons = sblk->bge_idx[0].bge_tx_cons_idx;
 3338         status = sblk->bge_status;
 3339 
 3340         if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) || sc->bge_link_evt)
 3341                 bge_link_poll(sc);
 3342 
 3343         if (ifp->if_flags & IFF_RUNNING) {
 3344                 if (sc->bge_rx_saved_considx != rx_prod)
 3345                         bge_rxeof(sc, rx_prod, -1);
 3346 
 3347                 if (sc->bge_tx_saved_considx != tx_cons)
 3348                         bge_txeof(sc, tx_cons);
 3349         }
 3350 
 3351         bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
 3352 
 3353         if (sc->bge_coal_chg)
 3354                 bge_coal_change(sc);
 3355 }
 3356 
 3357 static void
 3358 bge_tick(void *xsc)
 3359 {
 3360         struct bge_softc *sc = xsc;
 3361         struct ifnet *ifp = &sc->arpcom.ac_if;
 3362 
 3363         lwkt_serialize_enter(ifp->if_serializer);
 3364 
 3365         if (BGE_IS_5705_PLUS(sc))
 3366                 bge_stats_update_regs(sc);
 3367         else
 3368                 bge_stats_update(sc);
 3369 
 3370         if (sc->bge_flags & BGE_FLAG_TBI) {
 3371                 /*
 3372                  * Since in TBI mode auto-polling can't be used we should poll
 3373                  * link status manually. Here we register pending link event
 3374                  * and trigger interrupt.
 3375                  */
 3376                 sc->bge_link_evt++;
 3377                 if (BGE_IS_CRIPPLED(sc))
 3378                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
 3379                 else
 3380                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
 3381         } else if (!sc->bge_link) {
 3382                 mii_tick(device_get_softc(sc->bge_miibus));
 3383         }
 3384 
 3385         bge_asf_driver_up(sc);
 3386 
 3387         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
 3388 
 3389         lwkt_serialize_exit(ifp->if_serializer);
 3390 }
 3391 
 3392 static void
 3393 bge_stats_update_regs(struct bge_softc *sc)
 3394 {
 3395         struct ifnet *ifp = &sc->arpcom.ac_if;
 3396         struct bge_mac_stats_regs stats;
 3397         uint32_t *s;
 3398         int i;
 3399 
 3400         s = (uint32_t *)&stats;
 3401         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
 3402                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
 3403                 s++;
 3404         }
 3405 
 3406         IFNET_STAT_SET(ifp, collisions,
 3407            (stats.dot3StatsSingleCollisionFrames +
 3408            stats.dot3StatsMultipleCollisionFrames +
 3409            stats.dot3StatsExcessiveCollisions +
 3410            stats.dot3StatsLateCollisions));
 3411 }
 3412 
 3413 static void
 3414 bge_stats_update(struct bge_softc *sc)
 3415 {
 3416         struct ifnet *ifp = &sc->arpcom.ac_if;
 3417         bus_size_t stats;
 3418 
 3419         stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
 3420 
 3421 #define READ_STAT(sc, stats, stat)      \
 3422         CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
 3423 
 3424         IFNET_STAT_SET(ifp, collisions,
 3425            (READ_STAT(sc, stats,
 3426                 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
 3427             READ_STAT(sc, stats,
 3428                 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
 3429             READ_STAT(sc, stats,
 3430                 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
 3431             READ_STAT(sc, stats,
 3432                 txstats.dot3StatsLateCollisions.bge_addr_lo)));
 3433 
 3434 #undef READ_STAT
 3435 
 3436 #ifdef notdef
 3437         IFNET_STAT_SET(ifp, collisions,
 3438            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
 3439            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
 3440            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
 3441            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions));
 3442 #endif
 3443 }
 3444 
 3445 /*
 3446  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
 3447  * pointers to descriptors.
 3448  */
 3449 static int
 3450 bge_encap(struct bge_softc *sc, struct mbuf **m_head0, uint32_t *txidx,
 3451     int *segs_used)
 3452 {
 3453         struct bge_tx_bd *d = NULL, *last_d;
 3454         uint16_t csum_flags = 0, mss = 0;
 3455         bus_dma_segment_t segs[BGE_NSEG_NEW];
 3456         bus_dmamap_t map;
 3457         int error, maxsegs, nsegs, idx, i;
 3458         struct mbuf *m_head = *m_head0, *m_new;
 3459 
 3460         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
 3461                 error = bge_setup_tso(sc, m_head0, &mss, &csum_flags);
 3462                 if (error)
 3463                         return ENOBUFS;
 3464                 m_head = *m_head0;
 3465         } else if (m_head->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) {
 3466                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
 3467                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
 3468                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
 3469                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
 3470                 if (m_head->m_flags & M_LASTFRAG)
 3471                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
 3472                 else if (m_head->m_flags & M_FRAG)
 3473                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
 3474         }
 3475 
 3476         idx = *txidx;
 3477         map = sc->bge_cdata.bge_tx_dmamap[idx];
 3478 
 3479         maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - sc->bge_txrsvd;
 3480         KASSERT(maxsegs >= sc->bge_txspare,
 3481                 ("not enough segments %d", maxsegs));
 3482 
 3483         if (maxsegs > BGE_NSEG_NEW)
 3484                 maxsegs = BGE_NSEG_NEW;
 3485 
 3486         /*
 3487          * Pad outbound frame to BGE_MIN_FRAMELEN for an unusual reason.
 3488          * The bge hardware will pad out Tx runts to BGE_MIN_FRAMELEN,
 3489          * but when such padded frames employ the bge IP/TCP checksum
 3490          * offload, the hardware checksum assist gives incorrect results
 3491          * (possibly from incorporating its own padding into the UDP/TCP
 3492          * checksum; who knows).  If we pad such runts with zeros, the
 3493          * onboard checksum comes out correct.
 3494          */
 3495         if ((csum_flags & BGE_TXBDFLAG_TCP_UDP_CSUM) &&
 3496             m_head->m_pkthdr.len < BGE_MIN_FRAMELEN) {
 3497                 error = m_devpad(m_head, BGE_MIN_FRAMELEN);
 3498                 if (error)
 3499                         goto back;
 3500         }
 3501 
 3502         if ((sc->bge_flags & BGE_FLAG_SHORTDMA) && m_head->m_next != NULL) {
 3503                 m_new = bge_defrag_shortdma(m_head);
 3504                 if (m_new == NULL) {
 3505                         error = ENOBUFS;
 3506                         goto back;
 3507                 }
 3508                 *m_head0 = m_head = m_new;
 3509         }
 3510         if ((m_head->m_pkthdr.csum_flags & CSUM_TSO) == 0 &&
 3511             sc->bge_force_defrag && (sc->bge_flags & BGE_FLAG_PCIE) &&
 3512             m_head->m_next != NULL) {
 3513                 /*
 3514                  * Forcefully defragment mbuf chain to overcome hardware
 3515                  * limitation which only support a single outstanding
 3516                  * DMA read operation.  If it fails, keep moving on using
 3517                  * the original mbuf chain.
 3518                  */
 3519                 m_new = m_defrag(m_head, MB_DONTWAIT);
 3520                 if (m_new != NULL)
 3521                         *m_head0 = m_head = m_new;
 3522         }
 3523 
 3524         error = bus_dmamap_load_mbuf_defrag(sc->bge_cdata.bge_tx_mtag, map,
 3525                         m_head0, segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
 3526         if (error)
 3527                 goto back;
 3528         *segs_used += nsegs;
 3529 
 3530         m_head = *m_head0;
 3531         bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
 3532 
 3533         for (i = 0; ; i++) {
 3534                 d = &sc->bge_ldata.bge_tx_ring[idx];
 3535 
 3536                 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
 3537                 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
 3538                 d->bge_len = segs[i].ds_len;
 3539                 d->bge_flags = csum_flags;
 3540                 d->bge_mss = mss;
 3541 
 3542                 if (i == nsegs - 1)
 3543                         break;
 3544                 BGE_INC(idx, BGE_TX_RING_CNT);
 3545         }
 3546         last_d = d;
 3547 
 3548         /* Set vlan tag to the first segment of the packet. */
 3549         d = &sc->bge_ldata.bge_tx_ring[*txidx];
 3550         if (m_head->m_flags & M_VLANTAG) {
 3551                 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
 3552                 d->bge_vlan_tag = m_head->m_pkthdr.ether_vlantag;
 3553         } else {
 3554                 d->bge_vlan_tag = 0;
 3555         }
 3556 
 3557         /* Mark the last segment as end of packet... */
 3558         last_d->bge_flags |= BGE_TXBDFLAG_END;
 3559 
 3560         /*
 3561          * Insure that the map for this transmission is placed at
 3562          * the array index of the last descriptor in this chain.
 3563          */
 3564         sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
 3565         sc->bge_cdata.bge_tx_dmamap[idx] = map;
 3566         sc->bge_cdata.bge_tx_chain[idx] = m_head;
 3567         sc->bge_txcnt += nsegs;
 3568 
 3569         BGE_INC(idx, BGE_TX_RING_CNT);
 3570         *txidx = idx;
 3571 back:
 3572         if (error) {
 3573                 m_freem(*m_head0);
 3574                 *m_head0 = NULL;
 3575         }
 3576         return error;
 3577 }
 3578 
 3579 static void
 3580 bge_xmit(struct bge_softc *sc, uint32_t prodidx)
 3581 {
 3582         /* Transmit */
 3583         bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
 3584         /* 5700 b2 errata */
 3585         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 3586                 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
 3587 }
 3588 
 3589 /*
 3590  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
 3591  * to the mbuf data regions directly in the transmit descriptors.
 3592  */
 3593 static void
 3594 bge_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
 3595 {
 3596         struct bge_softc *sc = ifp->if_softc;
 3597         struct mbuf *m_head = NULL;
 3598         uint32_t prodidx;
 3599         int nsegs = 0;
 3600 
 3601         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
 3602 
 3603         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
 3604                 return;
 3605 
 3606         prodidx = sc->bge_tx_prodidx;
 3607 
 3608         while (sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
 3609                 m_head = ifq_dequeue(&ifp->if_snd);
 3610                 if (m_head == NULL)
 3611                         break;
 3612 
 3613                 /*
 3614                  * XXX
 3615                  * The code inside the if() block is never reached since we
 3616                  * must mark CSUM_IP_FRAGS in our if_hwassist to start getting
 3617                  * requests to checksum TCP/UDP in a fragmented packet.
 3618                  * 
 3619                  * XXX
 3620                  * safety overkill.  If this is a fragmented packet chain
 3621                  * with delayed TCP/UDP checksums, then only encapsulate
 3622                  * it if we have enough descriptors to handle the entire
 3623                  * chain at once.
 3624                  * (paranoia -- may not actually be needed)
 3625                  */
 3626                 if ((m_head->m_flags & M_FIRSTFRAG) &&
 3627                     (m_head->m_pkthdr.csum_flags & CSUM_DELAY_DATA)) {
 3628                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
 3629                             m_head->m_pkthdr.csum_data + sc->bge_txrsvd) {
 3630                                 ifq_set_oactive(&ifp->if_snd);
 3631                                 ifq_prepend(&ifp->if_snd, m_head);
 3632                                 break;
 3633                         }
 3634                 }
 3635 
 3636                 /*
 3637                  * Sanity check: avoid coming within bge_txrsvd
 3638                  * descriptors of the end of the ring.  Also make
 3639                  * sure there are bge_txspare descriptors for
 3640                  * jumbo buffers' defragmentation.
 3641                  */
 3642                 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
 3643                     (sc->bge_txrsvd + sc->bge_txspare)) {
 3644                         ifq_set_oactive(&ifp->if_snd);
 3645                         ifq_prepend(&ifp->if_snd, m_head);
 3646                         break;
 3647                 }
 3648 
 3649                 /*
 3650                  * Pack the data into the transmit ring. If we
 3651                  * don't have room, set the OACTIVE flag and wait
 3652                  * for the NIC to drain the ring.
 3653                  */
 3654                 if (bge_encap(sc, &m_head, &prodidx, &nsegs)) {
 3655                         ifq_set_oactive(&ifp->if_snd);
 3656                         IFNET_STAT_INC(ifp, oerrors, 1);
 3657                         break;
 3658                 }
 3659 
 3660                 if (nsegs >= sc->bge_tx_wreg) {
 3661                         bge_xmit(sc, prodidx);
 3662                         nsegs = 0;
 3663                 }
 3664 
 3665                 ETHER_BPF_MTAP(ifp, m_head);
 3666 
 3667                 /*
 3668                  * Set a timeout in case the chip goes out to lunch.
 3669                  */
 3670                 ifp->if_timer = 5;
 3671         }
 3672 
 3673         if (nsegs > 0)
 3674                 bge_xmit(sc, prodidx);
 3675         sc->bge_tx_prodidx = prodidx;
 3676 }
 3677 
 3678 static void
 3679 bge_init(void *xsc)
 3680 {
 3681         struct bge_softc *sc = xsc;
 3682         struct ifnet *ifp = &sc->arpcom.ac_if;
 3683         uint16_t *m;
 3684         uint32_t mode;
 3685 
 3686         ASSERT_SERIALIZED(ifp->if_serializer);
 3687 
 3688         /* Cancel pending I/O and flush buffers. */
 3689         bge_stop(sc);
 3690 
 3691         bge_stop_fw(sc);
 3692         bge_sig_pre_reset(sc, BGE_RESET_START);
 3693         bge_reset(sc);
 3694         bge_sig_legacy(sc, BGE_RESET_START);
 3695         bge_sig_post_reset(sc, BGE_RESET_START);
 3696 
 3697         bge_chipinit(sc);
 3698 
 3699         /*
 3700          * Init the various state machines, ring
 3701          * control blocks and firmware.
 3702          */
 3703         if (bge_blockinit(sc)) {
 3704                 if_printf(ifp, "initialization failure\n");
 3705                 bge_stop(sc);
 3706                 return;
 3707         }
 3708 
 3709         /* Specify MTU. */
 3710         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
 3711             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
 3712 
 3713         /* Load our MAC address. */
 3714         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
 3715         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
 3716         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
 3717 
 3718         /* Enable or disable promiscuous mode as needed. */
 3719         bge_setpromisc(sc);
 3720 
 3721         /* Program multicast filter. */
 3722         bge_setmulti(sc);
 3723 
 3724         /* Init RX ring. */
 3725         if (bge_init_rx_ring_std(sc)) {
 3726                 if_printf(ifp, "RX ring initialization failed\n");
 3727                 bge_stop(sc);
 3728                 return;
 3729         }
 3730 
 3731         /*
 3732          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
 3733          * memory to insure that the chip has in fact read the first
 3734          * entry of the ring.
 3735          */
 3736         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
 3737                 uint32_t                v, i;
 3738                 for (i = 0; i < 10; i++) {
 3739                         DELAY(20);
 3740                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
 3741                         if (v == (MCLBYTES - ETHER_ALIGN))
 3742                                 break;
 3743                 }
 3744                 if (i == 10)
 3745                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
 3746         }
 3747 
 3748         /* Init jumbo RX ring. */
 3749         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) {
 3750                 if (bge_init_rx_ring_jumbo(sc)) {
 3751                         if_printf(ifp, "Jumbo RX ring initialization failed\n");
 3752                         bge_stop(sc);
 3753                         return;
 3754                 }
 3755         }
 3756 
 3757         /* Init our RX return ring index */
 3758         sc->bge_rx_saved_considx = 0;
 3759 
 3760         /* Init TX ring. */
 3761         bge_init_tx_ring(sc);
 3762 
 3763         /* Enable TX MAC state machine lockup fix. */
 3764         mode = CSR_READ_4(sc, BGE_TX_MODE);
 3765         if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
 3766                 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
 3767         /* Turn on transmitter */
 3768         CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
 3769         DELAY(100);
 3770 
 3771         /* Turn on receiver */
 3772         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
 3773         DELAY(10);
 3774 
 3775         /*
 3776          * Set the number of good frames to receive after RX MBUF
 3777          * Low Watermark has been reached.  After the RX MAC receives
 3778          * this number of frames, it will drop subsequent incoming
 3779          * frames until the MBUF High Watermark is reached.
 3780          */
 3781         CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
 3782 
 3783         if (sc->bge_irq_type == PCI_INTR_TYPE_MSI) {
 3784                 if (bootverbose) {
 3785                         if_printf(ifp, "MSI_MODE: %#x\n",
 3786                             CSR_READ_4(sc, BGE_MSI_MODE));
 3787                 }
 3788 
 3789                 /*
 3790                  * XXX
 3791                  * Linux driver turns it on for all chips supporting MSI?!
 3792                  */
 3793                 if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
 3794                         /*
 3795                          * XXX
 3796                          * According to 5722-PG101-R,
 3797                          * BGE_PCIE_TRANSACT_ONESHOT_MSI applies only to
 3798                          * BCM5906.
 3799                          */
 3800                         BGE_SETBIT(sc, BGE_PCIE_TRANSACT,
 3801                             BGE_PCIE_TRANSACT_ONESHOT_MSI);
 3802                 }
 3803         }
 3804 
 3805         /* Tell firmware we're alive. */
 3806         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 3807 
 3808         /* Enable host interrupts if polling(4) is not enabled. */
 3809         PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA, 4);
 3810 #ifdef IFPOLL_ENABLE
 3811         if (ifp->if_flags & IFF_NPOLLING)
 3812                 bge_disable_intr(sc);
 3813         else
 3814 #endif
 3815         bge_enable_intr(sc);
 3816 
 3817         ifp->if_flags |= IFF_RUNNING;
 3818         ifq_clr_oactive(&ifp->if_snd);
 3819 
 3820         bge_ifmedia_upd(ifp);
 3821 
 3822         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
 3823 }
 3824 
 3825 /*
 3826  * Set media options.
 3827  */
 3828 static int
 3829 bge_ifmedia_upd(struct ifnet *ifp)
 3830 {
 3831         struct bge_softc *sc = ifp->if_softc;
 3832 
 3833         /* If this is a 1000baseX NIC, enable the TBI port. */
 3834         if (sc->bge_flags & BGE_FLAG_TBI) {
 3835                 struct ifmedia *ifm = &sc->bge_ifmedia;
 3836 
 3837                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 3838                         return(EINVAL);
 3839 
 3840                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
 3841                 case IFM_AUTO:
 3842                         /*
 3843                          * The BCM5704 ASIC appears to have a special
 3844                          * mechanism for programming the autoneg
 3845                          * advertisement registers in TBI mode.
 3846                          */
 3847                         if (!bge_fake_autoneg &&
 3848                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 3849                                 uint32_t sgdig;
 3850 
 3851                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
 3852                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
 3853                                 sgdig |= BGE_SGDIGCFG_AUTO |
 3854                                          BGE_SGDIGCFG_PAUSE_CAP |
 3855                                          BGE_SGDIGCFG_ASYM_PAUSE;
 3856                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
 3857                                             sgdig | BGE_SGDIGCFG_SEND);
 3858                                 DELAY(5);
 3859                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
 3860                         }
 3861                         break;
 3862                 case IFM_1000_SX:
 3863                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
 3864                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
 3865                                     BGE_MACMODE_HALF_DUPLEX);
 3866                         } else {
 3867                                 BGE_SETBIT(sc, BGE_MAC_MODE,
 3868                                     BGE_MACMODE_HALF_DUPLEX);
 3869                         }
 3870                         DELAY(40);
 3871                         break;
 3872                 default:
 3873                         return(EINVAL);
 3874                 }
 3875         } else {
 3876                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
 3877 
 3878                 sc->bge_link_evt++;
 3879                 sc->bge_link = 0;
 3880                 if (mii->mii_instance) {
 3881                         struct mii_softc *miisc;
 3882 
 3883                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 3884                                 mii_phy_reset(miisc);
 3885                 }
 3886                 mii_mediachg(mii);
 3887 
 3888                 /*
 3889                  * Force an interrupt so that we will call bge_link_upd
 3890                  * if needed and clear any pending link state attention.
 3891                  * Without this we are not getting any further interrupts
 3892                  * for link state changes and thus will not UP the link and
 3893                  * not be able to send in bge_start.  The only way to get
 3894                  * things working was to receive a packet and get an RX
 3895                  * intr.
 3896                  *
 3897                  * bge_tick should help for fiber cards and we might not
 3898                  * need to do this here if BGE_FLAG_TBI is set but as
 3899                  * we poll for fiber anyway it should not harm.
 3900                  */
 3901                 if (BGE_IS_CRIPPLED(sc))
 3902                         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
 3903                 else
 3904                         BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
 3905         }
 3906         return(0);
 3907 }
 3908 
 3909 /*
 3910  * Report current media status.
 3911  */
 3912 static void
 3913 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 3914 {
 3915         struct bge_softc *sc = ifp->if_softc;
 3916 
 3917         if ((ifp->if_flags & IFF_RUNNING) == 0)
 3918                 return;
 3919 
 3920         if (sc->bge_flags & BGE_FLAG_TBI) {
 3921                 ifmr->ifm_status = IFM_AVALID;
 3922                 ifmr->ifm_active = IFM_ETHER;
 3923                 if (CSR_READ_4(sc, BGE_MAC_STS) &
 3924                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
 3925                         ifmr->ifm_status |= IFM_ACTIVE;
 3926                 } else {
 3927                         ifmr->ifm_active |= IFM_NONE;
 3928                         return;
 3929                 }
 3930 
 3931                 ifmr->ifm_active |= IFM_1000_SX;
 3932                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
 3933                         ifmr->ifm_active |= IFM_HDX;    
 3934                 else
 3935                         ifmr->ifm_active |= IFM_FDX;
 3936         } else {
 3937                 struct mii_data *mii = device_get_softc(sc->bge_miibus);
 3938 
 3939                 mii_pollstat(mii);
 3940                 ifmr->ifm_active = mii->mii_media_active;
 3941                 ifmr->ifm_status = mii->mii_media_status;
 3942         }
 3943 }
 3944 
 3945 static int
 3946 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 3947 {
 3948         struct bge_softc *sc = ifp->if_softc;
 3949         struct ifreq *ifr = (struct ifreq *)data;
 3950         int mask, error = 0;
 3951 
 3952         ASSERT_SERIALIZED(ifp->if_serializer);
 3953 
 3954         switch (command) {
 3955         case SIOCSIFMTU:
 3956                 if ((!BGE_IS_JUMBO_CAPABLE(sc) && ifr->ifr_mtu > ETHERMTU) ||
 3957                     (BGE_IS_JUMBO_CAPABLE(sc) &&
 3958                      ifr->ifr_mtu > BGE_JUMBO_MTU)) {
 3959                         error = EINVAL;
 3960                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
 3961                         ifp->if_mtu = ifr->ifr_mtu;
 3962                         if (ifp->if_flags & IFF_RUNNING)
 3963                                 bge_init(sc);
 3964                 }
 3965                 break;
 3966         case SIOCSIFFLAGS:
 3967                 if (ifp->if_flags & IFF_UP) {
 3968                         if (ifp->if_flags & IFF_RUNNING) {
 3969                                 mask = ifp->if_flags ^ sc->bge_if_flags;
 3970 
 3971                                 /*
 3972                                  * If only the state of the PROMISC flag
 3973                                  * changed, then just use the 'set promisc
 3974                                  * mode' command instead of reinitializing
 3975                                  * the entire NIC. Doing a full re-init
 3976                                  * means reloading the firmware and waiting
 3977                                  * for it to start up, which may take a
 3978                                  * second or two.  Similarly for ALLMULTI.
 3979                                  */
 3980                                 if (mask & IFF_PROMISC)
 3981                                         bge_setpromisc(sc);
 3982                                 if (mask & IFF_ALLMULTI)
 3983                                         bge_setmulti(sc);
 3984                         } else {
 3985                                 bge_init(sc);
 3986                         }
 3987                 } else if (ifp->if_flags & IFF_RUNNING) {
 3988                         bge_stop(sc);
 3989                 }
 3990                 sc->bge_if_flags = ifp->if_flags;
 3991                 break;
 3992         case SIOCADDMULTI:
 3993         case SIOCDELMULTI:
 3994                 if (ifp->if_flags & IFF_RUNNING)
 3995                         bge_setmulti(sc);
 3996                 break;
 3997         case SIOCSIFMEDIA:
 3998         case SIOCGIFMEDIA:
 3999                 if (sc->bge_flags & BGE_FLAG_TBI) {
 4000                         error = ifmedia_ioctl(ifp, ifr,
 4001                             &sc->bge_ifmedia, command);
 4002                 } else {
 4003                         struct mii_data *mii;
 4004 
 4005                         mii = device_get_softc(sc->bge_miibus);
 4006                         error = ifmedia_ioctl(ifp, ifr,
 4007                                               &mii->mii_media, command);
 4008                 }
 4009                 break;
 4010         case SIOCSIFCAP:
 4011                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 4012                 if (mask & IFCAP_HWCSUM) {
 4013                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
 4014                         if (ifp->if_capenable & IFCAP_TXCSUM)
 4015                                 ifp->if_hwassist |= BGE_CSUM_FEATURES;
 4016                         else
 4017                                 ifp->if_hwassist &= ~BGE_CSUM_FEATURES;
 4018                 }
 4019                 if (mask & IFCAP_TSO) {
 4020                         ifp->if_capenable ^= IFCAP_TSO;
 4021                         if (ifp->if_capenable & IFCAP_TSO)
 4022                                 ifp->if_hwassist |= CSUM_TSO;
 4023                         else
 4024                                 ifp->if_hwassist &= ~CSUM_TSO;
 4025                 }
 4026                 break;
 4027         default:
 4028                 error = ether_ioctl(ifp, command, data);
 4029                 break;
 4030         }
 4031         return error;
 4032 }
 4033 
 4034 static void
 4035 bge_watchdog(struct ifnet *ifp)
 4036 {
 4037         struct bge_softc *sc = ifp->if_softc;
 4038 
 4039         if_printf(ifp, "watchdog timeout -- resetting\n");
 4040 
 4041         bge_init(sc);
 4042 
 4043         IFNET_STAT_INC(ifp, oerrors, 1);
 4044 
 4045         if (!ifq_is_empty(&ifp->if_snd))
 4046                 if_devstart(ifp);
 4047 }
 4048 
 4049 /*
 4050  * Stop the adapter and free any mbufs allocated to the
 4051  * RX and TX lists.
 4052  */
 4053 static void
 4054 bge_stop(struct bge_softc *sc)
 4055 {
 4056         struct ifnet *ifp = &sc->arpcom.ac_if;
 4057 
 4058         ASSERT_SERIALIZED(ifp->if_serializer);
 4059 
 4060         callout_stop(&sc->bge_stat_timer);
 4061 
 4062         /* Disable host interrupts. */
 4063         bge_disable_intr(sc);
 4064 
 4065         /*
 4066          * Tell firmware we're shutting down.
 4067          */
 4068         bge_stop_fw(sc);
 4069         bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
 4070 
 4071         /*
 4072          * Disable all of the receiver blocks
 4073          */
 4074         bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
 4075         bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
 4076         bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
 4077         if (BGE_IS_5700_FAMILY(sc))
 4078                 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
 4079         bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
 4080         bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
 4081         bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
 4082 
 4083         /*
 4084          * Disable all of the transmit blocks
 4085          */
 4086         bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
 4087         bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
 4088         bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
 4089         bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
 4090         bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
 4091         if (BGE_IS_5700_FAMILY(sc))
 4092                 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
 4093         bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
 4094 
 4095         /*
 4096          * Shut down all of the memory managers and related
 4097          * state machines.
 4098          */
 4099         bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
 4100         bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
 4101         if (BGE_IS_5700_FAMILY(sc))
 4102                 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
 4103         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
 4104         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
 4105         if (!BGE_IS_5705_PLUS(sc)) {
 4106                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
 4107                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
 4108         }
 4109 
 4110         bge_reset(sc);
 4111         bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
 4112         bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
 4113 
 4114         /*
 4115          * Keep the ASF firmware running if up.
 4116          */
 4117         if (sc->bge_asf_mode & ASF_STACKUP)
 4118                 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 4119         else
 4120                 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
 4121 
 4122         /* Free the RX lists. */
 4123         bge_free_rx_ring_std(sc);
 4124 
 4125         /* Free jumbo RX list. */
 4126         if (BGE_IS_JUMBO_CAPABLE(sc))
 4127                 bge_free_rx_ring_jumbo(sc);
 4128 
 4129         /* Free TX buffers. */
 4130         bge_free_tx_ring(sc);
 4131 
 4132         sc->bge_status_tag = 0;
 4133         sc->bge_link = 0;
 4134         sc->bge_coal_chg = 0;
 4135 
 4136         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
 4137 
 4138         ifp->if_flags &= ~IFF_RUNNING;
 4139         ifq_clr_oactive(&ifp->if_snd);
 4140         ifp->if_timer = 0;
 4141 }
 4142 
 4143 /*
 4144  * Stop all chip I/O so that the kernel's probe routines don't
 4145  * get confused by errant DMAs when rebooting.
 4146  */
 4147 static void
 4148 bge_shutdown(device_t dev)
 4149 {
 4150         struct bge_softc *sc = device_get_softc(dev);
 4151         struct ifnet *ifp = &sc->arpcom.ac_if;
 4152 
 4153         lwkt_serialize_enter(ifp->if_serializer);
 4154         bge_stop(sc);
 4155         lwkt_serialize_exit(ifp->if_serializer);
 4156 }
 4157 
 4158 static int
 4159 bge_suspend(device_t dev)
 4160 {
 4161         struct bge_softc *sc = device_get_softc(dev);
 4162         struct ifnet *ifp = &sc->arpcom.ac_if;
 4163 
 4164         lwkt_serialize_enter(ifp->if_serializer);
 4165         bge_stop(sc);
 4166         lwkt_serialize_exit(ifp->if_serializer);
 4167 
 4168         return 0;
 4169 }
 4170 
 4171 static int
 4172 bge_resume(device_t dev)
 4173 {
 4174         struct bge_softc *sc = device_get_softc(dev);
 4175         struct ifnet *ifp = &sc->arpcom.ac_if;
 4176 
 4177         lwkt_serialize_enter(ifp->if_serializer);
 4178 
 4179         if (ifp->if_flags & IFF_UP) {
 4180                 bge_init(sc);
 4181 
 4182                 if (!ifq_is_empty(&ifp->if_snd))
 4183                         if_devstart(ifp);
 4184         }
 4185 
 4186         lwkt_serialize_exit(ifp->if_serializer);
 4187 
 4188         return 0;
 4189 }
 4190 
 4191 static void
 4192 bge_setpromisc(struct bge_softc *sc)
 4193 {
 4194         struct ifnet *ifp = &sc->arpcom.ac_if;
 4195 
 4196         if (ifp->if_flags & IFF_PROMISC)
 4197                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
 4198         else
 4199                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
 4200 }
 4201 
 4202 static void
 4203 bge_dma_free(struct bge_softc *sc)
 4204 {
 4205         int i;
 4206 
 4207         /* Destroy RX mbuf DMA stuffs. */
 4208         if (sc->bge_cdata.bge_rx_mtag != NULL) {
 4209                 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 4210                         bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
 4211                             sc->bge_cdata.bge_rx_std_dmamap[i]);
 4212                 }
 4213                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
 4214                                    sc->bge_cdata.bge_rx_tmpmap);
 4215                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
 4216         }
 4217 
 4218         /* Destroy TX mbuf DMA stuffs. */
 4219         if (sc->bge_cdata.bge_tx_mtag != NULL) {
 4220                 for (i = 0; i < BGE_TX_RING_CNT; i++) {
 4221                         bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
 4222                             sc->bge_cdata.bge_tx_dmamap[i]);
 4223                 }
 4224                 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
 4225         }
 4226 
 4227         /* Destroy standard RX ring */
 4228         bge_dma_block_free(sc->bge_cdata.bge_rx_std_ring_tag,
 4229                            sc->bge_cdata.bge_rx_std_ring_map,
 4230                            sc->bge_ldata.bge_rx_std_ring);
 4231 
 4232         if (BGE_IS_JUMBO_CAPABLE(sc))
 4233                 bge_free_jumbo_mem(sc);
 4234 
 4235         /* Destroy RX return ring */
 4236         bge_dma_block_free(sc->bge_cdata.bge_rx_return_ring_tag,
 4237                            sc->bge_cdata.bge_rx_return_ring_map,
 4238                            sc->bge_ldata.bge_rx_return_ring);
 4239 
 4240         /* Destroy TX ring */
 4241         bge_dma_block_free(sc->bge_cdata.bge_tx_ring_tag,
 4242                            sc->bge_cdata.bge_tx_ring_map,
 4243                            sc->bge_ldata.bge_tx_ring);
 4244 
 4245         /* Destroy status block */
 4246         bge_dma_block_free(sc->bge_cdata.bge_status_tag,
 4247                            sc->bge_cdata.bge_status_map,
 4248                            sc->bge_ldata.bge_status_block);
 4249 
 4250         /* Destroy statistics block */
 4251         bge_dma_block_free(sc->bge_cdata.bge_stats_tag,
 4252                            sc->bge_cdata.bge_stats_map,
 4253                            sc->bge_ldata.bge_stats);
 4254 
 4255         /* Destroy the parent tag */
 4256         if (sc->bge_cdata.bge_parent_tag != NULL)
 4257                 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
 4258 }
 4259 
 4260 static int
 4261 bge_dma_alloc(struct bge_softc *sc)
 4262 {
 4263         struct ifnet *ifp = &sc->arpcom.ac_if;
 4264         int i, error;
 4265         bus_addr_t lowaddr;
 4266         bus_size_t txmaxsz;
 4267 
 4268         lowaddr = BUS_SPACE_MAXADDR;
 4269         if (sc->bge_flags & BGE_FLAG_MAXADDR_40BIT)
 4270                 lowaddr = BGE_DMA_MAXADDR_40BIT;
 4271 
 4272         /*
 4273          * Allocate the parent bus DMA tag appropriate for PCI.
 4274          *
 4275          * All of the NetExtreme/NetLink controllers have 4GB boundary
 4276          * DMA bug.
 4277          * Whenever an address crosses a multiple of the 4GB boundary
 4278          * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
 4279          * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
 4280          * state machine will lockup and cause the device to hang.
 4281          */
 4282         error = bus_dma_tag_create(NULL, 1, BGE_DMA_BOUNDARY_4G,
 4283                                    lowaddr, BUS_SPACE_MAXADDR,
 4284                                    NULL, NULL,
 4285                                    BUS_SPACE_MAXSIZE_32BIT, 0,
 4286                                    BUS_SPACE_MAXSIZE_32BIT,
 4287                                    0, &sc->bge_cdata.bge_parent_tag);
 4288         if (error) {
 4289                 if_printf(ifp, "could not allocate parent dma tag\n");
 4290                 return error;
 4291         }
 4292 
 4293         /*
 4294          * Create DMA tag and maps for RX mbufs.
 4295          */
 4296         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
 4297                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
 4298                                    NULL, NULL, MCLBYTES, 1, MCLBYTES,
 4299                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK,
 4300                                    &sc->bge_cdata.bge_rx_mtag);
 4301         if (error) {
 4302                 if_printf(ifp, "could not allocate RX mbuf dma tag\n");
 4303                 return error;
 4304         }
 4305 
 4306         error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
 4307                                   BUS_DMA_WAITOK, &sc->bge_cdata.bge_rx_tmpmap);
 4308         if (error) {
 4309                 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
 4310                 sc->bge_cdata.bge_rx_mtag = NULL;
 4311                 return error;
 4312         }
 4313 
 4314         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 4315                 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag,
 4316                                           BUS_DMA_WAITOK,
 4317                                           &sc->bge_cdata.bge_rx_std_dmamap[i]);
 4318                 if (error) {
 4319                         int j;
 4320 
 4321                         for (j = 0; j < i; ++j) {
 4322                                 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
 4323                                         sc->bge_cdata.bge_rx_std_dmamap[j]);
 4324                         }
 4325                         bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
 4326                         sc->bge_cdata.bge_rx_mtag = NULL;
 4327 
 4328                         if_printf(ifp, "could not create DMA map for RX\n");
 4329                         return error;
 4330                 }
 4331         }
 4332 
 4333         /*
 4334          * Create DMA tag and maps for TX mbufs.
 4335          */
 4336         if (sc->bge_flags & BGE_FLAG_TSO)
 4337                 txmaxsz = IP_MAXPACKET + sizeof(struct ether_vlan_header);
 4338         else
 4339                 txmaxsz = BGE_JUMBO_FRAMELEN;
 4340         error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0,
 4341                                    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
 4342                                    NULL, NULL,
 4343                                    txmaxsz, BGE_NSEG_NEW, PAGE_SIZE,
 4344                                    BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
 4345                                    BUS_DMA_ONEBPAGE,
 4346                                    &sc->bge_cdata.bge_tx_mtag);
 4347         if (error) {
 4348                 if_printf(ifp, "could not allocate TX mbuf dma tag\n");
 4349                 return error;
 4350         }
 4351 
 4352         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 4353                 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag,
 4354                                           BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
 4355                                           &sc->bge_cdata.bge_tx_dmamap[i]);
 4356                 if (error) {
 4357                         int j;
 4358 
 4359                         for (j = 0; j < i; ++j) {
 4360                                 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
 4361                                         sc->bge_cdata.bge_tx_dmamap[j]);
 4362                         }
 4363                         bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
 4364                         sc->bge_cdata.bge_tx_mtag = NULL;
 4365 
 4366                         if_printf(ifp, "could not create DMA map for TX\n");
 4367                         return error;
 4368                 }
 4369         }
 4370 
 4371         /*
 4372          * Create DMA stuffs for standard RX ring.
 4373          */
 4374         error = bge_dma_block_alloc(sc, BGE_STD_RX_RING_SZ,
 4375                                     &sc->bge_cdata.bge_rx_std_ring_tag,
 4376                                     &sc->bge_cdata.bge_rx_std_ring_map,
 4377                                     (void *)&sc->bge_ldata.bge_rx_std_ring,
 4378                                     &sc->bge_ldata.bge_rx_std_ring_paddr);
 4379         if (error) {
 4380                 if_printf(ifp, "could not create std RX ring\n");
 4381                 return error;
 4382         }
 4383 
 4384         /*
 4385          * Create jumbo buffer pool.
 4386          */
 4387         if (BGE_IS_JUMBO_CAPABLE(sc)) {
 4388                 error = bge_alloc_jumbo_mem(sc);
 4389                 if (error) {
 4390                         if_printf(ifp, "could not create jumbo buffer pool\n");
 4391                         return error;
 4392                 }
 4393         }
 4394 
 4395         /*
 4396          * Create DMA stuffs for RX return ring.
 4397          */
 4398         error = bge_dma_block_alloc(sc,
 4399             BGE_RX_RTN_RING_SZ(sc->bge_return_ring_cnt),
 4400             &sc->bge_cdata.bge_rx_return_ring_tag,
 4401             &sc->bge_cdata.bge_rx_return_ring_map,
 4402             (void *)&sc->bge_ldata.bge_rx_return_ring,
 4403             &sc->bge_ldata.bge_rx_return_ring_paddr);
 4404         if (error) {
 4405                 if_printf(ifp, "could not create RX ret ring\n");
 4406                 return error;
 4407         }
 4408 
 4409         /*
 4410          * Create DMA stuffs for TX ring.
 4411          */
 4412         error = bge_dma_block_alloc(sc, BGE_TX_RING_SZ,
 4413                                     &sc->bge_cdata.bge_tx_ring_tag,
 4414                                     &sc->bge_cdata.bge_tx_ring_map,
 4415                                     (void *)&sc->bge_ldata.bge_tx_ring,
 4416                                     &sc->bge_ldata.bge_tx_ring_paddr);
 4417         if (error) {
 4418                 if_printf(ifp, "could not create TX ring\n");
 4419                 return error;
 4420         }
 4421 
 4422         /*
 4423          * Create DMA stuffs for status block.
 4424          */
 4425         error = bge_dma_block_alloc(sc, BGE_STATUS_BLK_SZ,
 4426                                     &sc->bge_cdata.bge_status_tag,
 4427                                     &sc->bge_cdata.bge_status_map,
 4428                                     (void *)&sc->bge_ldata.bge_status_block,
 4429                                     &sc->bge_ldata.bge_status_block_paddr);
 4430         if (error) {
 4431                 if_printf(ifp, "could not create status block\n");
 4432                 return error;
 4433         }
 4434 
 4435         /*
 4436          * Create DMA stuffs for statistics block.
 4437          */
 4438         error = bge_dma_block_alloc(sc, BGE_STATS_SZ,
 4439                                     &sc->bge_cdata.bge_stats_tag,
 4440                                     &sc->bge_cdata.bge_stats_map,
 4441                                     (void *)&sc->bge_ldata.bge_stats,
 4442                                     &sc->bge_ldata.bge_stats_paddr);
 4443         if (error) {
 4444                 if_printf(ifp, "could not create stats block\n");
 4445                 return error;
 4446         }
 4447         return 0;
 4448 }
 4449 
 4450 static int
 4451 bge_dma_block_alloc(struct bge_softc *sc, bus_size_t size, bus_dma_tag_t *tag,
 4452                     bus_dmamap_t *map, void **addr, bus_addr_t *paddr)
 4453 {
 4454         bus_dmamem_t dmem;
 4455         int error;
 4456 
 4457         error = bus_dmamem_coherent(sc->bge_cdata.bge_parent_tag, PAGE_SIZE, 0,
 4458                                     BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
 4459                                     size, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
 4460         if (error)
 4461                 return error;
 4462 
 4463         *tag = dmem.dmem_tag;
 4464         *map = dmem.dmem_map;
 4465         *addr = dmem.dmem_addr;
 4466         *paddr = dmem.dmem_busaddr;
 4467 
 4468         return 0;
 4469 }
 4470 
 4471 static void
 4472 bge_dma_block_free(bus_dma_tag_t tag, bus_dmamap_t map, void *addr)
 4473 {
 4474         if (tag != NULL) {
 4475                 bus_dmamap_unload(tag, map);
 4476                 bus_dmamem_free(tag, addr, map);
 4477                 bus_dma_tag_destroy(tag);
 4478         }
 4479 }
 4480 
 4481 /*
 4482  * Grrr. The link status word in the status block does
 4483  * not work correctly on the BCM5700 rev AX and BX chips,
 4484  * according to all available information. Hence, we have
 4485  * to enable MII interrupts in order to properly obtain
 4486  * async link changes. Unfortunately, this also means that
 4487  * we have to read the MAC status register to detect link
 4488  * changes, thereby adding an additional register access to
 4489  * the interrupt handler.
 4490  *
 4491  * XXX: perhaps link state detection procedure used for
 4492  * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
 4493  */
 4494 static void
 4495 bge_bcm5700_link_upd(struct bge_softc *sc, uint32_t status __unused)
 4496 {
 4497         struct ifnet *ifp = &sc->arpcom.ac_if;
 4498         struct mii_data *mii = device_get_softc(sc->bge_miibus);
 4499 
 4500         mii_pollstat(mii);
 4501 
 4502         if (!sc->bge_link &&
 4503             (mii->mii_media_status & IFM_ACTIVE) &&
 4504             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 4505                 sc->bge_link++;
 4506                 if (bootverbose)
 4507                         if_printf(ifp, "link UP\n");
 4508         } else if (sc->bge_link &&
 4509             (!(mii->mii_media_status & IFM_ACTIVE) ||
 4510             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
 4511                 sc->bge_link = 0;
 4512                 if (bootverbose)
 4513                         if_printf(ifp, "link DOWN\n");
 4514         }
 4515 
 4516         /* Clear the interrupt. */
 4517         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_MI_INTERRUPT);
 4518         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
 4519         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, BRGPHY_INTRS);
 4520 }
 4521 
 4522 static void
 4523 bge_tbi_link_upd(struct bge_softc *sc, uint32_t status)
 4524 {
 4525         struct ifnet *ifp = &sc->arpcom.ac_if;
 4526 
 4527 #define PCS_ENCODE_ERR  (BGE_MACSTAT_PORT_DECODE_ERROR|BGE_MACSTAT_MI_COMPLETE)
 4528 
 4529         /*
 4530          * Sometimes PCS encoding errors are detected in
 4531          * TBI mode (on fiber NICs), and for some reason
 4532          * the chip will signal them as link changes.
 4533          * If we get a link change event, but the 'PCS
 4534          * encoding error' bit in the MAC status register
 4535          * is set, don't bother doing a link check.
 4536          * This avoids spurious "gigabit link up" messages
 4537          * that sometimes appear on fiber NICs during
 4538          * periods of heavy traffic.
 4539          */
 4540         if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
 4541                 if (!sc->bge_link) {
 4542                         sc->bge_link++;
 4543                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
 4544                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
 4545                                     BGE_MACMODE_TBI_SEND_CFGS);
 4546                                 DELAY(40);
 4547                         }
 4548                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
 4549 
 4550                         if (bootverbose)
 4551                                 if_printf(ifp, "link UP\n");
 4552 
 4553                         ifp->if_link_state = LINK_STATE_UP;
 4554                         if_link_state_change(ifp);
 4555                 }
 4556         } else if ((status & PCS_ENCODE_ERR) != PCS_ENCODE_ERR) {
 4557                 if (sc->bge_link) {
 4558                         sc->bge_link = 0;
 4559 
 4560                         if (bootverbose)
 4561                                 if_printf(ifp, "link DOWN\n");
 4562 
 4563                         ifp->if_link_state = LINK_STATE_DOWN;
 4564                         if_link_state_change(ifp);
 4565                 }
 4566         }
 4567 
 4568 #undef PCS_ENCODE_ERR
 4569 
 4570         /* Clear the attention. */
 4571         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
 4572             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
 4573             BGE_MACSTAT_LINK_CHANGED);
 4574 }
 4575 
 4576 static void
 4577 bge_copper_link_upd(struct bge_softc *sc, uint32_t status __unused)
 4578 {
 4579         struct ifnet *ifp = &sc->arpcom.ac_if;
 4580         struct mii_data *mii = device_get_softc(sc->bge_miibus);
 4581 
 4582         mii_pollstat(mii);
 4583         bge_miibus_statchg(sc->bge_dev);
 4584 
 4585         if (bootverbose) {
 4586                 if (sc->bge_link)
 4587                         if_printf(ifp, "link UP\n");
 4588                 else
 4589                         if_printf(ifp, "link DOWN\n");
 4590         }
 4591 
 4592         /* Clear the attention. */
 4593         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
 4594             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
 4595             BGE_MACSTAT_LINK_CHANGED);
 4596 }
 4597 
 4598 static void
 4599 bge_autopoll_link_upd(struct bge_softc *sc, uint32_t status __unused)
 4600 {
 4601         struct ifnet *ifp = &sc->arpcom.ac_if;
 4602         struct mii_data *mii = device_get_softc(sc->bge_miibus);
 4603 
 4604         mii_pollstat(mii);
 4605 
 4606         if (!sc->bge_link &&
 4607             (mii->mii_media_status & IFM_ACTIVE) &&
 4608             IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
 4609                 sc->bge_link++;
 4610                 if (bootverbose)
 4611                         if_printf(ifp, "link UP\n");
 4612         } else if (sc->bge_link &&
 4613             (!(mii->mii_media_status & IFM_ACTIVE) ||
 4614             IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
 4615                 sc->bge_link = 0;
 4616                 if (bootverbose)
 4617                         if_printf(ifp, "link DOWN\n");
 4618         }
 4619 
 4620         /* Clear the attention. */
 4621         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
 4622             BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
 4623             BGE_MACSTAT_LINK_CHANGED);
 4624 }
 4625 
 4626 static int
 4627 bge_sysctl_rx_coal_ticks(SYSCTL_HANDLER_ARGS)
 4628 {
 4629         struct bge_softc *sc = arg1;
 4630 
 4631         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
 4632             &sc->bge_rx_coal_ticks,
 4633             BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
 4634             BGE_RX_COAL_TICKS_CHG);
 4635 }
 4636 
 4637 static int
 4638 bge_sysctl_tx_coal_ticks(SYSCTL_HANDLER_ARGS)
 4639 {
 4640         struct bge_softc *sc = arg1;
 4641 
 4642         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
 4643             &sc->bge_tx_coal_ticks,
 4644             BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
 4645             BGE_TX_COAL_TICKS_CHG);
 4646 }
 4647 
 4648 static int
 4649 bge_sysctl_rx_coal_bds(SYSCTL_HANDLER_ARGS)
 4650 {
 4651         struct bge_softc *sc = arg1;
 4652 
 4653         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
 4654             &sc->bge_rx_coal_bds,
 4655             BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
 4656             BGE_RX_COAL_BDS_CHG);
 4657 }
 4658 
 4659 static int
 4660 bge_sysctl_tx_coal_bds(SYSCTL_HANDLER_ARGS)
 4661 {
 4662         struct bge_softc *sc = arg1;
 4663 
 4664         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
 4665             &sc->bge_tx_coal_bds,
 4666             BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
 4667             BGE_TX_COAL_BDS_CHG);
 4668 }
 4669 
 4670 static int
 4671 bge_sysctl_rx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
 4672 {
 4673         struct bge_softc *sc = arg1;
 4674 
 4675         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
 4676             &sc->bge_rx_coal_ticks_int,
 4677             BGE_RX_COAL_TICKS_MIN, BGE_RX_COAL_TICKS_MAX,
 4678             BGE_RX_COAL_TICKS_INT_CHG);
 4679 }
 4680 
 4681 static int
 4682 bge_sysctl_tx_coal_ticks_int(SYSCTL_HANDLER_ARGS)
 4683 {
 4684         struct bge_softc *sc = arg1;
 4685 
 4686         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
 4687             &sc->bge_tx_coal_ticks_int,
 4688             BGE_TX_COAL_TICKS_MIN, BGE_TX_COAL_TICKS_MAX,
 4689             BGE_TX_COAL_TICKS_INT_CHG);
 4690 }
 4691 
 4692 static int
 4693 bge_sysctl_rx_coal_bds_int(SYSCTL_HANDLER_ARGS)
 4694 {
 4695         struct bge_softc *sc = arg1;
 4696 
 4697         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
 4698             &sc->bge_rx_coal_bds_int,
 4699             BGE_RX_COAL_BDS_MIN, BGE_RX_COAL_BDS_MAX,
 4700             BGE_RX_COAL_BDS_INT_CHG);
 4701 }
 4702 
 4703 static int
 4704 bge_sysctl_tx_coal_bds_int(SYSCTL_HANDLER_ARGS)
 4705 {
 4706         struct bge_softc *sc = arg1;
 4707 
 4708         return bge_sysctl_coal_chg(oidp, arg1, arg2, req,
 4709             &sc->bge_tx_coal_bds_int,
 4710             BGE_TX_COAL_BDS_MIN, BGE_TX_COAL_BDS_MAX,
 4711             BGE_TX_COAL_BDS_INT_CHG);
 4712 }
 4713 
 4714 static int
 4715 bge_sysctl_coal_chg(SYSCTL_HANDLER_ARGS, uint32_t *coal,
 4716     int coal_min, int coal_max, uint32_t coal_chg_mask)
 4717 {
 4718         struct bge_softc *sc = arg1;
 4719         struct ifnet *ifp = &sc->arpcom.ac_if;
 4720         int error = 0, v;
 4721 
 4722         lwkt_serialize_enter(ifp->if_serializer);
 4723 
 4724         v = *coal;
 4725         error = sysctl_handle_int(oidp, &v, 0, req);
 4726         if (!error && req->newptr != NULL) {
 4727                 if (v < coal_min || v > coal_max) {
 4728                         error = EINVAL;
 4729                 } else {
 4730                         *coal = v;
 4731                         sc->bge_coal_chg |= coal_chg_mask;
 4732                 }
 4733         }
 4734 
 4735         lwkt_serialize_exit(ifp->if_serializer);
 4736         return error;
 4737 }
 4738 
 4739 static void
 4740 bge_coal_change(struct bge_softc *sc)
 4741 {
 4742         struct ifnet *ifp = &sc->arpcom.ac_if;
 4743 
 4744         ASSERT_SERIALIZED(ifp->if_serializer);
 4745 
 4746         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_CHG) {
 4747                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS,
 4748                             sc->bge_rx_coal_ticks);
 4749                 DELAY(10);
 4750                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS);
 4751 
 4752                 if (bootverbose) {
 4753                         if_printf(ifp, "rx_coal_ticks -> %u\n",
 4754                                   sc->bge_rx_coal_ticks);
 4755                 }
 4756         }
 4757 
 4758         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_CHG) {
 4759                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS,
 4760                             sc->bge_tx_coal_ticks);
 4761                 DELAY(10);
 4762                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS);
 4763 
 4764                 if (bootverbose) {
 4765                         if_printf(ifp, "tx_coal_ticks -> %u\n",
 4766                                   sc->bge_tx_coal_ticks);
 4767                 }
 4768         }
 4769 
 4770         if (sc->bge_coal_chg & BGE_RX_COAL_BDS_CHG) {
 4771                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS,
 4772                             sc->bge_rx_coal_bds);
 4773                 DELAY(10);
 4774                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS);
 4775 
 4776                 if (bootverbose) {
 4777                         if_printf(ifp, "rx_coal_bds -> %u\n",
 4778                                   sc->bge_rx_coal_bds);
 4779                 }
 4780         }
 4781 
 4782         if (sc->bge_coal_chg & BGE_TX_COAL_BDS_CHG) {
 4783                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS,
 4784                             sc->bge_tx_coal_bds);
 4785                 DELAY(10);
 4786                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS);
 4787 
 4788                 if (bootverbose) {
 4789                         if_printf(ifp, "tx_max_coal_bds -> %u\n",
 4790                                   sc->bge_tx_coal_bds);
 4791                 }
 4792         }
 4793 
 4794         if (sc->bge_coal_chg & BGE_RX_COAL_TICKS_INT_CHG) {
 4795                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT,
 4796                     sc->bge_rx_coal_ticks_int);
 4797                 DELAY(10);
 4798                 CSR_READ_4(sc, BGE_HCC_RX_COAL_TICKS_INT);
 4799 
 4800                 if (bootverbose) {
 4801                         if_printf(ifp, "rx_coal_ticks_int -> %u\n",
 4802                             sc->bge_rx_coal_ticks_int);
 4803                 }
 4804         }
 4805 
 4806         if (sc->bge_coal_chg & BGE_TX_COAL_TICKS_INT_CHG) {
 4807                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT,
 4808                     sc->bge_tx_coal_ticks_int);
 4809                 DELAY(10);
 4810                 CSR_READ_4(sc, BGE_HCC_TX_COAL_TICKS_INT);
 4811 
 4812                 if (bootverbose) {
 4813                         if_printf(ifp, "tx_coal_ticks_int -> %u\n",
 4814                             sc->bge_tx_coal_ticks_int);
 4815                 }
 4816         }
 4817 
 4818         if (sc->bge_coal_chg & BGE_RX_COAL_BDS_INT_CHG) {
 4819                 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT,
 4820                     sc->bge_rx_coal_bds_int);
 4821                 DELAY(10);
 4822                 CSR_READ_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT);
 4823 
 4824                 if (bootverbose) {
 4825                         if_printf(ifp, "rx_coal_bds_int -> %u\n",
 4826                             sc->bge_rx_coal_bds_int);
 4827                 }
 4828         }
 4829 
 4830         if (sc->bge_coal_chg & BGE_TX_COAL_BDS_INT_CHG) {
 4831                 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT,
 4832                     sc->bge_tx_coal_bds_int);
 4833                 DELAY(10);
 4834                 CSR_READ_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT);
 4835 
 4836                 if (bootverbose) {
 4837                         if_printf(ifp, "tx_coal_bds_int -> %u\n",
 4838                             sc->bge_tx_coal_bds_int);
 4839                 }
 4840         }
 4841 
 4842         sc->bge_coal_chg = 0;
 4843 }
 4844 
 4845 static void
 4846 bge_enable_intr(struct bge_softc *sc)
 4847 {
 4848         struct ifnet *ifp = &sc->arpcom.ac_if;
 4849 
 4850         lwkt_serialize_handler_enable(ifp->if_serializer);
 4851 
 4852         /*
 4853          * Enable interrupt.
 4854          */
 4855         bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
 4856         if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
 4857                 /* XXX Linux driver */
 4858                 bge_writembx(sc, BGE_MBX_IRQ0_LO, sc->bge_status_tag << 24);
 4859         }
 4860 
 4861         /*
 4862          * Unmask the interrupt when we stop polling.
 4863          */
 4864         PCI_CLRBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
 4865             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
 4866 
 4867         /*
 4868          * Trigger another interrupt, since above writing
 4869          * to interrupt mailbox0 may acknowledge pending
 4870          * interrupt.
 4871          */
 4872         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
 4873 }
 4874 
 4875 static void
 4876 bge_disable_intr(struct bge_softc *sc)
 4877 {
 4878         struct ifnet *ifp = &sc->arpcom.ac_if;
 4879 
 4880         /*
 4881          * Mask the interrupt when we start polling.
 4882          */
 4883         PCI_SETBIT(sc->bge_dev, BGE_PCI_MISC_CTL,
 4884             BGE_PCIMISCCTL_MASK_PCI_INTR, 4);
 4885 
 4886         /*
 4887          * Acknowledge possible asserted interrupt.
 4888          */
 4889         bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
 4890 
 4891         sc->bge_npoll.ifpc_stcount = 0;
 4892 
 4893         lwkt_serialize_handler_disable(ifp->if_serializer);
 4894 }
 4895 
 4896 static int
 4897 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
 4898 {
 4899         uint32_t mac_addr;
 4900         int ret = 1;
 4901 
 4902         mac_addr = bge_readmem_ind(sc, 0x0c14);
 4903         if ((mac_addr >> 16) == 0x484b) {
 4904                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
 4905                 ether_addr[1] = (uint8_t)mac_addr;
 4906                 mac_addr = bge_readmem_ind(sc, 0x0c18);
 4907                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
 4908                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
 4909                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
 4910                 ether_addr[5] = (uint8_t)mac_addr;
 4911                 ret = 0;
 4912         }
 4913         return ret;
 4914 }
 4915 
 4916 static int
 4917 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
 4918 {
 4919         int mac_offset = BGE_EE_MAC_OFFSET;
 4920 
 4921         if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
 4922                 mac_offset = BGE_EE_MAC_OFFSET_5906;
 4923 
 4924         return bge_read_nvram(sc, ether_addr, mac_offset + 2, ETHER_ADDR_LEN);
 4925 }
 4926 
 4927 static int
 4928 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
 4929 {
 4930         if (sc->bge_flags & BGE_FLAG_NO_EEPROM)
 4931                 return 1;
 4932 
 4933         return bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
 4934                                ETHER_ADDR_LEN);
 4935 }
 4936 
 4937 static int
 4938 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
 4939 {
 4940         static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
 4941                 /* NOTE: Order is critical */
 4942                 bge_get_eaddr_mem,
 4943                 bge_get_eaddr_nvram,
 4944                 bge_get_eaddr_eeprom,
 4945                 NULL
 4946         };
 4947         const bge_eaddr_fcn_t *func;
 4948 
 4949         for (func = bge_eaddr_funcs; *func != NULL; ++func) {
 4950                 if ((*func)(sc, eaddr) == 0)
 4951                         break;
 4952         }
 4953         return (*func == NULL ? ENXIO : 0);
 4954 }
 4955 
 4956 /*
 4957  * NOTE: 'm' is not freed upon failure
 4958  */
 4959 struct mbuf *
 4960 bge_defrag_shortdma(struct mbuf *m)
 4961 {
 4962         struct mbuf *n;
 4963         int found;
 4964 
 4965         /*
 4966          * If device receive two back-to-back send BDs with less than
 4967          * or equal to 8 total bytes then the device may hang.  The two
 4968          * back-to-back send BDs must in the same frame for this failure
 4969          * to occur.  Scan mbuf chains and see whether two back-to-back
 4970          * send BDs are there.  If this is the case, allocate new mbuf
 4971          * and copy the frame to workaround the silicon bug.
 4972          */
 4973         for (n = m, found = 0; n != NULL; n = n->m_next) {
 4974                 if (n->m_len < 8) {
 4975                         found++;
 4976                         if (found > 1)
 4977                                 break;
 4978                         continue;
 4979                 }
 4980                 found = 0;
 4981         }
 4982 
 4983         if (found > 1)
 4984                 n = m_defrag(m, MB_DONTWAIT);
 4985         else
 4986                 n = m;
 4987         return n;
 4988 }
 4989 
 4990 static void
 4991 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
 4992 {
 4993         int i;
 4994 
 4995         BGE_CLRBIT(sc, reg, bit);
 4996         for (i = 0; i < BGE_TIMEOUT; i++) {
 4997                 if ((CSR_READ_4(sc, reg) & bit) == 0)
 4998                         return;
 4999                 DELAY(100);
 5000         }
 5001 }
 5002 
 5003 static void
 5004 bge_link_poll(struct bge_softc *sc)
 5005 {
 5006         uint32_t status;
 5007 
 5008         status = CSR_READ_4(sc, BGE_MAC_STS);
 5009         if ((status & sc->bge_link_chg) || sc->bge_link_evt) {
 5010                 sc->bge_link_evt = 0;
 5011                 sc->bge_link_upd(sc, status);
 5012         }
 5013 }
 5014 
 5015 static void
 5016 bge_enable_msi(struct bge_softc *sc)
 5017 {
 5018         uint32_t msi_mode;
 5019 
 5020         msi_mode = CSR_READ_4(sc, BGE_MSI_MODE);
 5021         msi_mode |= BGE_MSIMODE_ENABLE;
 5022         if (sc->bge_flags & BGE_FLAG_ONESHOT_MSI) {
 5023                 /*
 5024                  * According to all of the datasheets that are publicly
 5025                  * available, bit 5 of the MSI_MODE is defined to be
 5026                  * "MSI FIFO Underrun Attn" for BCM5755+ and BCM5906, on
 5027                  * which "oneshot MSI" is enabled.  However, it is always
 5028                  * safe to clear it here.
 5029                  */
 5030                 msi_mode &= ~BGE_MSIMODE_ONESHOT_DISABLE;
 5031         }
 5032         CSR_WRITE_4(sc, BGE_MSI_MODE, msi_mode);
 5033 }
 5034 
 5035 static int
 5036 bge_setup_tso(struct bge_softc *sc, struct mbuf **mp,
 5037     uint16_t *mss0, uint16_t *flags0)
 5038 {
 5039         struct mbuf *m;
 5040         struct ip *ip;
 5041         struct tcphdr *th;
 5042         int thoff, iphlen, hoff, hlen;
 5043         uint16_t flags, mss;
 5044 
 5045         m = *mp;
 5046         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
 5047 
 5048         hoff = m->m_pkthdr.csum_lhlen;
 5049         iphlen = m->m_pkthdr.csum_iphlen;
 5050         thoff = m->m_pkthdr.csum_thlen;
 5051 
 5052         KASSERT(hoff > 0, ("invalid ether header len"));
 5053         KASSERT(iphlen > 0, ("invalid ip header len"));
 5054         KASSERT(thoff > 0, ("invalid tcp header len"));
 5055 
 5056         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
 5057                 m = m_pullup(m, hoff + iphlen + thoff);
 5058                 if (m == NULL) {
 5059                         *mp = NULL;
 5060                         return ENOBUFS;
 5061                 }
 5062                 *mp = m;
 5063         }
 5064         ip = mtodoff(m, struct ip *, hoff);
 5065         th = mtodoff(m, struct tcphdr *, hoff + iphlen);
 5066 
 5067         mss = m->m_pkthdr.tso_segsz;
 5068         flags = BGE_TXBDFLAG_CPU_PRE_DMA | BGE_TXBDFLAG_CPU_POST_DMA;
 5069 
 5070         ip->ip_len = htons(mss + iphlen + thoff);
 5071         th->th_sum = 0;
 5072 
 5073         hlen = (iphlen + thoff) >> 2;
 5074         mss |= (hlen << 11);
 5075 
 5076         *mss0 = mss;
 5077         *flags0 = flags;
 5078 
 5079         return 0;
 5080 }
 5081 
 5082 static void
 5083 bge_stop_fw(struct bge_softc *sc)
 5084 {
 5085         int i;
 5086 
 5087         if (sc->bge_asf_mode) {
 5088                 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
 5089                 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
 5090                     CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
 5091 
 5092                 for (i = 0; i < 100; i++ ) {
 5093                         if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
 5094                             BGE_RX_CPU_DRV_EVENT))
 5095                                 break;
 5096                         DELAY(10);
 5097                 }
 5098         }
 5099 }
 5100 
 5101 static void
 5102 bge_sig_pre_reset(struct bge_softc *sc, int type)
 5103 {
 5104         /*
 5105          * Some chips don't like this so only do this if ASF is enabled
 5106          */
 5107         if (sc->bge_asf_mode)
 5108                 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
 5109 
 5110         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
 5111                 switch (type) {
 5112                 case BGE_RESET_START:
 5113                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 5114                             BGE_FW_DRV_STATE_START);
 5115                         break;
 5116                 case BGE_RESET_SHUTDOWN:
 5117                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 5118                             BGE_FW_DRV_STATE_UNLOAD);
 5119                         break;
 5120                 case BGE_RESET_SUSPEND:
 5121                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 5122                             BGE_FW_DRV_STATE_SUSPEND);
 5123                         break;
 5124                 }
 5125         }
 5126 
 5127 #ifdef notyet
 5128         if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
 5129                 bge_ape_driver_state_change(sc, type);
 5130 #endif
 5131 }
 5132 
 5133 static void
 5134 bge_sig_legacy(struct bge_softc *sc, int type)
 5135 {
 5136         if (sc->bge_asf_mode) {
 5137                 switch (type) {
 5138                 case BGE_RESET_START:
 5139                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 5140                             BGE_FW_DRV_STATE_START);
 5141                         break;
 5142                 case BGE_RESET_SHUTDOWN:
 5143                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 5144                             BGE_FW_DRV_STATE_UNLOAD);
 5145                         break;
 5146                 }
 5147         }
 5148 }
 5149 
 5150 static void
 5151 bge_sig_post_reset(struct bge_softc *sc, int type)
 5152 {
 5153         if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
 5154                 switch (type) {
 5155                 case BGE_RESET_START:
 5156                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 5157                             BGE_FW_DRV_STATE_START_DONE);
 5158                         /* START DONE */
 5159                         break;
 5160                 case BGE_RESET_SHUTDOWN:
 5161                         bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
 5162                             BGE_FW_DRV_STATE_UNLOAD_DONE);
 5163                         break;
 5164                 }
 5165         }
 5166 #ifdef notyet
 5167         if (type == BGE_RESET_SHUTDOWN)
 5168                 bge_ape_driver_state_change(sc, type);
 5169 #endif
 5170 }
 5171 
 5172 static void
 5173 bge_asf_driver_up(struct bge_softc *sc)
 5174 {
 5175         if (sc->bge_asf_mode & ASF_STACKUP) {
 5176                 /* Send ASF heartbeat aprox. every 2s */
 5177                 if (sc->bge_asf_count)
 5178                         sc->bge_asf_count --;
 5179                 else {
 5180                         sc->bge_asf_count = 2;
 5181                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
 5182                             BGE_FW_CMD_DRV_ALIVE);
 5183                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
 5184                         bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
 5185                             BGE_FW_HB_TIMEOUT_SEC);
 5186                         CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
 5187                             CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
 5188                             BGE_RX_CPU_DRV_EVENT);
 5189                 }
 5190         }
 5191 }

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