Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/netif/dc/if_dc.c
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1 /* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: src/sys/pci/if_dc.c,v 1.9.2.45 2003/06/08 14:31:53 mux Exp $ 33 */ 34 35 /* 36 * DEC "tulip" clone ethernet driver. Supports the DEC/Intel 21143 37 * series chips and several workalikes including the following: 38 * 39 * Macronix 98713/98715/98725/98727/98732 PMAC (www.macronix.com) 40 * Macronix/Lite-On 82c115 PNIC II (www.macronix.com) 41 * Lite-On 82c168/82c169 PNIC (www.litecom.com) 42 * ASIX Electronics AX88140A (www.asix.com.tw) 43 * ASIX Electronics AX88141 (www.asix.com.tw) 44 * ADMtek AL981 (www.admtek.com.tw) 45 * ADMtek AN985 (www.admtek.com.tw) 46 * Netgear FA511 (www.netgear.com) Appears to be rebadged ADMTek AN985 47 * Davicom DM9100, DM9102, DM9102A (www.davicom8.com) 48 * Accton EN1217 (www.accton.com) 49 * Xircom X3201 (www.xircom.com) 50 * Abocom FE2500 51 * Conexant LANfinity (www.conexant.com) 52 * 53 * Datasheets for the 21143 are available at developer.intel.com. 54 * Datasheets for the clone parts can be found at their respective sites. 55 * (Except for the PNIC; see www.freebsd.org/~wpaul/PNIC/pnic.ps.gz.) 56 * The PNIC II is essentially a Macronix 98715A chip; the only difference 57 * worth noting is that its multicast hash table is only 128 bits wide 58 * instead of 512. 59 * 60 * Written by Bill Paul <wpaul@ee.columbia.edu> 61 * Electrical Engineering Department 62 * Columbia University, New York City 63 */ 64 65 /* 66 * The Intel 21143 is the successor to the DEC 21140. It is basically 67 * the same as the 21140 but with a few new features. The 21143 supports 68 * three kinds of media attachments: 69 * 70 * o MII port, for 10Mbps and 100Mbps support and NWAY 71 * autonegotiation provided by an external PHY. 72 * o SYM port, for symbol mode 100Mbps support. 73 * o 10baseT port. 74 * o AUI/BNC port. 75 * 76 * The 100Mbps SYM port and 10baseT port can be used together in 77 * combination with the internal NWAY support to create a 10/100 78 * autosensing configuration. 79 * 80 * Note that not all tulip workalikes are handled in this driver: we only 81 * deal with those which are relatively well behaved. The Winbond is 82 * handled separately due to its different register offsets and the 83 * special handling needed for its various bugs. The PNIC is handled 84 * here, but I'm not thrilled about it. 85 * 86 * All of the workalike chips use some form of MII transceiver support 87 * with the exception of the Macronix chips, which also have a SYM port. 88 * The ASIX AX88140A is also documented to have a SYM port, but all 89 * the cards I've seen use an MII transceiver, probably because the 90 * AX88140A doesn't support internal NWAY. 91 */ 92 93 #include "opt_ifpoll.h" 94 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/interrupt.h> 102 #include <sys/socket.h> 103 #include <sys/sysctl.h> 104 #include <sys/bus.h> 105 #include <sys/rman.h> 106 #include <sys/thread2.h> 107 108 #include <net/if.h> 109 #include <net/ifq_var.h> 110 #include <net/if_arp.h> 111 #include <net/ethernet.h> 112 #include <net/if_dl.h> 113 #include <net/if_media.h> 114 #include <net/if_poll.h> 115 #include <net/if_types.h> 116 #include <net/vlan/if_vlan_var.h> 117 118 #include <net/bpf.h> 119 120 #include <vm/vm.h> /* for vtophys */ 121 #include <vm/pmap.h> /* for vtophys */ 122 123 #include "../mii_layer/mii.h" 124 #include "../mii_layer/miivar.h" 125 126 #include <bus/pci/pcireg.h> 127 #include <bus/pci/pcivar.h> 128 129 #define DC_USEIOSPACE 130 131 #include "if_dcreg.h" 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 /* 137 * Various supported device vendors/types and their names. 138 */ 139 static const struct dc_type dc_devs[] = { 140 { DC_VENDORID_DEC, DC_DEVICEID_21143, 141 "Intel 21143 10/100BaseTX" }, 142 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9009, 143 "Davicom DM9009 10/100BaseTX" }, 144 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9100, 145 "Davicom DM9100 10/100BaseTX" }, 146 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 147 "Davicom DM9102 10/100BaseTX" }, 148 { DC_VENDORID_DAVICOM, DC_DEVICEID_DM9102, 149 "Davicom DM9102A 10/100BaseTX" }, 150 { DC_VENDORID_ADMTEK, DC_DEVICEID_AL981, 151 "ADMtek AL981 10/100BaseTX" }, 152 { DC_VENDORID_ADMTEK, DC_DEVICEID_AN985, 153 "ADMtek AN985 10/100BaseTX" }, 154 { DC_VENDORID_ADMTEK, DC_DEVICEID_FA511, 155 "Netgear FA511 10/100BaseTX" }, 156 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9511, 157 "ADMtek ADM9511 10/100BaseTX" }, 158 { DC_VENDORID_ADMTEK, DC_DEVICEID_ADM9513, 159 "ADMtek ADM9513 10/100BaseTX" }, 160 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 161 "ASIX AX88140A 10/100BaseTX" }, 162 { DC_VENDORID_ASIX, DC_DEVICEID_AX88140A, 163 "ASIX AX88141 10/100BaseTX" }, 164 { DC_VENDORID_MX, DC_DEVICEID_98713, 165 "Macronix 98713 10/100BaseTX" }, 166 { DC_VENDORID_MX, DC_DEVICEID_98713, 167 "Macronix 98713A 10/100BaseTX" }, 168 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 169 "Compex RL100-TX 10/100BaseTX" }, 170 { DC_VENDORID_CP, DC_DEVICEID_98713_CP, 171 "Compex RL100-TX 10/100BaseTX" }, 172 { DC_VENDORID_MX, DC_DEVICEID_987x5, 173 "Macronix 98715/98715A 10/100BaseTX" }, 174 { DC_VENDORID_MX, DC_DEVICEID_987x5, 175 "Macronix 98715AEC-C 10/100BaseTX" }, 176 { DC_VENDORID_MX, DC_DEVICEID_987x5, 177 "Macronix 98725 10/100BaseTX" }, 178 { DC_VENDORID_MX, DC_DEVICEID_98727, 179 "Macronix 98727/98732 10/100BaseTX" }, 180 { DC_VENDORID_LO, DC_DEVICEID_82C115, 181 "LC82C115 PNIC II 10/100BaseTX" }, 182 { DC_VENDORID_LO, DC_DEVICEID_82C168, 183 "82c168 PNIC 10/100BaseTX" }, 184 { DC_VENDORID_LO, DC_DEVICEID_82C168, 185 "82c169 PNIC 10/100BaseTX" }, 186 { DC_VENDORID_ACCTON, DC_DEVICEID_EN1217, 187 "Accton EN1217 10/100BaseTX" }, 188 { DC_VENDORID_ACCTON, DC_DEVICEID_EN2242, 189 "Accton EN2242 MiniPCI 10/100BaseTX" }, 190 { DC_VENDORID_XIRCOM, DC_DEVICEID_X3201, 191 "Xircom X3201 10/100BaseTX" }, 192 { DC_VENDORID_CONEXANT, DC_DEVICEID_RS7112, 193 "Conexant LANfinity MiniPCI 10/100BaseTX" }, 194 { DC_VENDORID_3COM, DC_DEVICEID_3CSOHOB, 195 "3Com OfficeConnect 10/100B" }, 196 { DC_VENDORID_ABOCOM, DC_DEVICEID_FE2500, 197 "Abocom FE2500 10/100BaseTX" }, 198 { 0, 0, NULL } 199 }; 200 201 static int dc_probe (device_t); 202 static int dc_attach (device_t); 203 static int dc_detach (device_t); 204 static int dc_suspend (device_t); 205 static int dc_resume (device_t); 206 static void dc_acpi (device_t); 207 static const struct dc_type *dc_devtype (device_t); 208 static int dc_newbuf (struct dc_softc *, int, struct mbuf *); 209 static int dc_encap (struct dc_softc *, struct mbuf *, 210 u_int32_t *); 211 static void dc_pnic_rx_bug_war (struct dc_softc *, int); 212 static int dc_rx_resync (struct dc_softc *); 213 static void dc_rxeof (struct dc_softc *); 214 static void dc_txeof (struct dc_softc *); 215 static void dc_tick (void *); 216 static void dc_tx_underrun (struct dc_softc *); 217 static void dc_intr (void *); 218 static void dc_start (struct ifnet *, struct ifaltq_subque *); 219 static int dc_ioctl (struct ifnet *, u_long, caddr_t, 220 struct ucred *); 221 #ifdef IFPOLL_ENABLE 222 static void dc_npoll (struct ifnet *, struct ifpoll_info *); 223 static void dc_npoll_compat (struct ifnet *, void *, int); 224 #endif 225 static void dc_init (void *); 226 static void dc_stop (struct dc_softc *); 227 static void dc_watchdog (struct ifnet *); 228 static void dc_shutdown (device_t); 229 static int dc_ifmedia_upd (struct ifnet *); 230 static void dc_ifmedia_sts (struct ifnet *, struct ifmediareq *); 231 232 static void dc_delay (struct dc_softc *); 233 static void dc_eeprom_idle (struct dc_softc *); 234 static void dc_eeprom_putbyte (struct dc_softc *, int); 235 static void dc_eeprom_getword (struct dc_softc *, int, u_int16_t *); 236 static void dc_eeprom_getword_pnic 237 (struct dc_softc *, int, u_int16_t *); 238 static void dc_eeprom_getword_xircom 239 (struct dc_softc *, int, u_int16_t *); 240 static void dc_eeprom_width (struct dc_softc *); 241 static void dc_read_eeprom (struct dc_softc *, caddr_t, int, 242 int, int); 243 244 static void dc_mii_writebit (struct dc_softc *, int); 245 static int dc_mii_readbit (struct dc_softc *); 246 static void dc_mii_sync (struct dc_softc *); 247 static void dc_mii_send (struct dc_softc *, u_int32_t, int); 248 static int dc_mii_readreg (struct dc_softc *, struct dc_mii_frame *); 249 static int dc_mii_writereg (struct dc_softc *, struct dc_mii_frame *); 250 static int dc_miibus_readreg (device_t, int, int); 251 static int dc_miibus_writereg (device_t, int, int, int); 252 static void dc_miibus_statchg (device_t); 253 static void dc_miibus_mediainit (device_t); 254 255 static u_int32_t dc_crc_mask (struct dc_softc *); 256 static void dc_setcfg (struct dc_softc *, int); 257 static void dc_setfilt_21143 (struct dc_softc *); 258 static void dc_setfilt_asix (struct dc_softc *); 259 static void dc_setfilt_admtek (struct dc_softc *); 260 static void dc_setfilt_xircom (struct dc_softc *); 261 262 static void dc_setfilt (struct dc_softc *); 263 264 static void dc_reset (struct dc_softc *); 265 static int dc_list_rx_init (struct dc_softc *); 266 static int dc_list_tx_init (struct dc_softc *); 267 268 static void dc_read_srom (struct dc_softc *, int); 269 static void dc_parse_21143_srom (struct dc_softc *); 270 static void dc_decode_leaf_sia (struct dc_softc *, 271 struct dc_eblock_sia *); 272 static void dc_decode_leaf_mii (struct dc_softc *, 273 struct dc_eblock_mii *); 274 static void dc_decode_leaf_sym (struct dc_softc *, 275 struct dc_eblock_sym *); 276 static void dc_apply_fixup (struct dc_softc *, int); 277 static uint32_t dc_mchash_xircom(struct dc_softc *, const uint8_t *); 278 279 #ifdef DC_USEIOSPACE 280 #define DC_RES SYS_RES_IOPORT 281 #define DC_RID DC_PCI_CFBIO 282 #else 283 #define DC_RES SYS_RES_MEMORY 284 #define DC_RID DC_PCI_CFBMA 285 #endif 286 287 static device_method_t dc_methods[] = { 288 /* Device interface */ 289 DEVMETHOD(device_probe, dc_probe), 290 DEVMETHOD(device_attach, dc_attach), 291 DEVMETHOD(device_detach, dc_detach), 292 DEVMETHOD(device_suspend, dc_suspend), 293 DEVMETHOD(device_resume, dc_resume), 294 DEVMETHOD(device_shutdown, dc_shutdown), 295 296 /* bus interface */ 297 DEVMETHOD(bus_print_child, bus_generic_print_child), 298 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 299 300 /* MII interface */ 301 DEVMETHOD(miibus_readreg, dc_miibus_readreg), 302 DEVMETHOD(miibus_writereg, dc_miibus_writereg), 303 DEVMETHOD(miibus_statchg, dc_miibus_statchg), 304 DEVMETHOD(miibus_mediainit, dc_miibus_mediainit), 305 306 DEVMETHOD_END 307 }; 308 309 static driver_t dc_driver = { 310 "dc", 311 dc_methods, 312 sizeof(struct dc_softc) 313 }; 314 315 static devclass_t dc_devclass; 316 317 #ifdef __i386__ 318 static int dc_quick=1; 319 SYSCTL_INT(_hw, OID_AUTO, dc_quick, CTLFLAG_RW, 320 &dc_quick,0,"do not mdevget in dc driver"); 321 #endif 322 323 DECLARE_DUMMY_MODULE(if_dc); 324 DRIVER_MODULE(if_dc, cardbus, dc_driver, dc_devclass, NULL, NULL); 325 DRIVER_MODULE(if_dc, pci, dc_driver, dc_devclass, NULL, NULL); 326 DRIVER_MODULE(miibus, dc, miibus_driver, miibus_devclass, NULL, NULL); 327 328 #define DC_SETBIT(sc, reg, x) \ 329 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 330 331 #define DC_CLRBIT(sc, reg, x) \ 332 CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 333 334 #define SIO_SET(x) DC_SETBIT(sc, DC_SIO, (x)) 335 #define SIO_CLR(x) DC_CLRBIT(sc, DC_SIO, (x)) 336 337 static void 338 dc_delay(struct dc_softc *sc) 339 { 340 int idx; 341 342 for (idx = (300 / 33) + 1; idx > 0; idx--) 343 CSR_READ_4(sc, DC_BUSCTL); 344 } 345 346 static void 347 dc_eeprom_width(struct dc_softc *sc) 348 { 349 int i; 350 351 /* Force EEPROM to idle state. */ 352 dc_eeprom_idle(sc); 353 354 /* Enter EEPROM access mode. */ 355 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 356 dc_delay(sc); 357 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 358 dc_delay(sc); 359 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 360 dc_delay(sc); 361 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 362 dc_delay(sc); 363 364 for (i = 3; i--;) { 365 if (6 & (1 << i)) 366 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 367 else 368 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 369 dc_delay(sc); 370 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 371 dc_delay(sc); 372 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 373 dc_delay(sc); 374 } 375 376 for (i = 1; i <= 12; i++) { 377 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 378 dc_delay(sc); 379 if (!(CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT)) { 380 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 381 dc_delay(sc); 382 break; 383 } 384 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 385 dc_delay(sc); 386 } 387 388 /* Turn off EEPROM access mode. */ 389 dc_eeprom_idle(sc); 390 391 if (i < 4 || i > 12) 392 sc->dc_romwidth = 6; 393 else 394 sc->dc_romwidth = i; 395 396 /* Enter EEPROM access mode. */ 397 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 398 dc_delay(sc); 399 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 400 dc_delay(sc); 401 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 402 dc_delay(sc); 403 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 404 dc_delay(sc); 405 406 /* Turn off EEPROM access mode. */ 407 dc_eeprom_idle(sc); 408 } 409 410 static void 411 dc_eeprom_idle(struct dc_softc *sc) 412 { 413 int i; 414 415 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 416 dc_delay(sc); 417 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 418 dc_delay(sc); 419 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 420 dc_delay(sc); 421 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 422 dc_delay(sc); 423 424 for (i = 0; i < 25; i++) { 425 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 426 dc_delay(sc); 427 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 428 dc_delay(sc); 429 } 430 431 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 432 dc_delay(sc); 433 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CS); 434 dc_delay(sc); 435 CSR_WRITE_4(sc, DC_SIO, 0x00000000); 436 437 return; 438 } 439 440 /* 441 * Send a read command and address to the EEPROM, check for ACK. 442 */ 443 static void 444 dc_eeprom_putbyte(struct dc_softc *sc, int addr) 445 { 446 int d, i; 447 448 d = DC_EECMD_READ >> 6; 449 for (i = 3; i--; ) { 450 if (d & (1 << i)) 451 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 452 else 453 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_DATAIN); 454 dc_delay(sc); 455 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CLK); 456 dc_delay(sc); 457 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 458 dc_delay(sc); 459 } 460 461 /* 462 * Feed in each bit and strobe the clock. 463 */ 464 for (i = sc->dc_romwidth; i--;) { 465 if (addr & (1 << i)) { 466 SIO_SET(DC_SIO_EE_DATAIN); 467 } else { 468 SIO_CLR(DC_SIO_EE_DATAIN); 469 } 470 dc_delay(sc); 471 SIO_SET(DC_SIO_EE_CLK); 472 dc_delay(sc); 473 SIO_CLR(DC_SIO_EE_CLK); 474 dc_delay(sc); 475 } 476 477 return; 478 } 479 480 /* 481 * Read a word of data stored in the EEPROM at address 'addr.' 482 * The PNIC 82c168/82c169 has its own non-standard way to read 483 * the EEPROM. 484 */ 485 static void 486 dc_eeprom_getword_pnic(struct dc_softc *sc, int addr, u_int16_t *dest) 487 { 488 int i; 489 u_int32_t r; 490 491 CSR_WRITE_4(sc, DC_PN_SIOCTL, DC_PN_EEOPCODE_READ|addr); 492 493 for (i = 0; i < DC_TIMEOUT; i++) { 494 DELAY(1); 495 r = CSR_READ_4(sc, DC_SIO); 496 if (!(r & DC_PN_SIOCTL_BUSY)) { 497 *dest = (u_int16_t)(r & 0xFFFF); 498 return; 499 } 500 } 501 502 return; 503 } 504 505 /* 506 * Read a word of data stored in the EEPROM at address 'addr.' 507 * The Xircom X3201 has its own non-standard way to read 508 * the EEPROM, too. 509 */ 510 static void 511 dc_eeprom_getword_xircom(struct dc_softc *sc, int addr, u_int16_t *dest) 512 { 513 SIO_SET(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 514 515 addr *= 2; 516 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 517 *dest = (u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff; 518 addr += 1; 519 CSR_WRITE_4(sc, DC_ROM, addr | 0x160); 520 *dest |= ((u_int16_t)CSR_READ_4(sc, DC_SIO)&0xff) << 8; 521 522 SIO_CLR(DC_SIO_ROMSEL | DC_SIO_ROMCTL_READ); 523 } 524 525 /* 526 * Read a word of data stored in the EEPROM at address 'addr.' 527 */ 528 static void 529 dc_eeprom_getword(struct dc_softc *sc, int addr, u_int16_t *dest) 530 { 531 int i; 532 u_int16_t word = 0; 533 534 /* Force EEPROM to idle state. */ 535 dc_eeprom_idle(sc); 536 537 /* Enter EEPROM access mode. */ 538 CSR_WRITE_4(sc, DC_SIO, DC_SIO_EESEL); 539 dc_delay(sc); 540 DC_SETBIT(sc, DC_SIO, DC_SIO_ROMCTL_READ); 541 dc_delay(sc); 542 DC_CLRBIT(sc, DC_SIO, DC_SIO_EE_CLK); 543 dc_delay(sc); 544 DC_SETBIT(sc, DC_SIO, DC_SIO_EE_CS); 545 dc_delay(sc); 546 547 /* 548 * Send address of word we want to read. 549 */ 550 dc_eeprom_putbyte(sc, addr); 551 552 /* 553 * Start reading bits from EEPROM. 554 */ 555 for (i = 0x8000; i; i >>= 1) { 556 SIO_SET(DC_SIO_EE_CLK); 557 dc_delay(sc); 558 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_EE_DATAOUT) 559 word |= i; 560 dc_delay(sc); 561 SIO_CLR(DC_SIO_EE_CLK); 562 dc_delay(sc); 563 } 564 565 /* Turn off EEPROM access mode. */ 566 dc_eeprom_idle(sc); 567 568 *dest = word; 569 570 return; 571 } 572 573 /* 574 * Read a sequence of words from the EEPROM. 575 */ 576 static void 577 dc_read_eeprom(struct dc_softc *sc, caddr_t dest, int off, int cnt, int swap) 578 { 579 int i; 580 u_int16_t word = 0, *ptr; 581 582 for (i = 0; i < cnt; i++) { 583 if (DC_IS_PNIC(sc)) 584 dc_eeprom_getword_pnic(sc, off + i, &word); 585 else if (DC_IS_XIRCOM(sc)) 586 dc_eeprom_getword_xircom(sc, off + i, &word); 587 else 588 dc_eeprom_getword(sc, off + i, &word); 589 ptr = (u_int16_t *)(dest + (i * 2)); 590 if (swap) 591 *ptr = ntohs(word); 592 else 593 *ptr = word; 594 } 595 596 return; 597 } 598 599 /* 600 * The following two routines are taken from the Macronix 98713 601 * Application Notes pp.19-21. 602 */ 603 /* 604 * Write a bit to the MII bus. 605 */ 606 static void 607 dc_mii_writebit(struct dc_softc *sc, int bit) 608 { 609 if (bit) 610 CSR_WRITE_4(sc, DC_SIO, 611 DC_SIO_ROMCTL_WRITE|DC_SIO_MII_DATAOUT); 612 else 613 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 614 615 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 616 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 617 618 return; 619 } 620 621 /* 622 * Read a bit from the MII bus. 623 */ 624 static int 625 dc_mii_readbit(struct dc_softc *sc) 626 { 627 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_READ|DC_SIO_MII_DIR); 628 CSR_READ_4(sc, DC_SIO); 629 DC_SETBIT(sc, DC_SIO, DC_SIO_MII_CLK); 630 DC_CLRBIT(sc, DC_SIO, DC_SIO_MII_CLK); 631 if (CSR_READ_4(sc, DC_SIO) & DC_SIO_MII_DATAIN) 632 return(1); 633 634 return(0); 635 } 636 637 /* 638 * Sync the PHYs by setting data bit and strobing the clock 32 times. 639 */ 640 static void 641 dc_mii_sync(struct dc_softc *sc) 642 { 643 int i; 644 645 CSR_WRITE_4(sc, DC_SIO, DC_SIO_ROMCTL_WRITE); 646 647 for (i = 0; i < 32; i++) 648 dc_mii_writebit(sc, 1); 649 650 return; 651 } 652 653 /* 654 * Clock a series of bits through the MII. 655 */ 656 static void 657 dc_mii_send(struct dc_softc *sc, u_int32_t bits, int cnt) 658 { 659 int i; 660 661 for (i = (0x1 << (cnt - 1)); i; i >>= 1) 662 dc_mii_writebit(sc, bits & i); 663 } 664 665 /* 666 * Read an PHY register through the MII. 667 */ 668 static int 669 dc_mii_readreg(struct dc_softc *sc, struct dc_mii_frame *frame) 670 { 671 int ack, i; 672 673 /* 674 * Set up frame for RX. 675 */ 676 frame->mii_stdelim = DC_MII_STARTDELIM; 677 frame->mii_opcode = DC_MII_READOP; 678 frame->mii_turnaround = 0; 679 frame->mii_data = 0; 680 681 /* 682 * Sync the PHYs. 683 */ 684 dc_mii_sync(sc); 685 686 /* 687 * Send command/address info. 688 */ 689 dc_mii_send(sc, frame->mii_stdelim, 2); 690 dc_mii_send(sc, frame->mii_opcode, 2); 691 dc_mii_send(sc, frame->mii_phyaddr, 5); 692 dc_mii_send(sc, frame->mii_regaddr, 5); 693 694 #ifdef notdef 695 /* Idle bit */ 696 dc_mii_writebit(sc, 1); 697 dc_mii_writebit(sc, 0); 698 #endif 699 700 /* Check for ack */ 701 ack = dc_mii_readbit(sc); 702 703 /* 704 * Now try reading data bits. If the ack failed, we still 705 * need to clock through 16 cycles to keep the PHY(s) in sync. 706 */ 707 if (ack) { 708 for(i = 0; i < 16; i++) { 709 dc_mii_readbit(sc); 710 } 711 goto fail; 712 } 713 714 for (i = 0x8000; i; i >>= 1) { 715 if (!ack) { 716 if (dc_mii_readbit(sc)) 717 frame->mii_data |= i; 718 } 719 } 720 721 fail: 722 723 dc_mii_writebit(sc, 0); 724 dc_mii_writebit(sc, 0); 725 726 if (ack) 727 return(1); 728 return(0); 729 } 730 731 /* 732 * Write to a PHY register through the MII. 733 */ 734 static int 735 dc_mii_writereg(struct dc_softc *sc, struct dc_mii_frame *frame) 736 { 737 /* 738 * Set up frame for TX. 739 */ 740 741 frame->mii_stdelim = DC_MII_STARTDELIM; 742 frame->mii_opcode = DC_MII_WRITEOP; 743 frame->mii_turnaround = DC_MII_TURNAROUND; 744 745 /* 746 * Sync the PHYs. 747 */ 748 dc_mii_sync(sc); 749 750 dc_mii_send(sc, frame->mii_stdelim, 2); 751 dc_mii_send(sc, frame->mii_opcode, 2); 752 dc_mii_send(sc, frame->mii_phyaddr, 5); 753 dc_mii_send(sc, frame->mii_regaddr, 5); 754 dc_mii_send(sc, frame->mii_turnaround, 2); 755 dc_mii_send(sc, frame->mii_data, 16); 756 757 /* Idle bit. */ 758 dc_mii_writebit(sc, 0); 759 dc_mii_writebit(sc, 0); 760 761 return(0); 762 } 763 764 static int 765 dc_miibus_readreg(device_t dev, int phy, int reg) 766 { 767 struct dc_mii_frame frame; 768 struct dc_softc *sc; 769 int i, rval, phy_reg = 0; 770 771 sc = device_get_softc(dev); 772 bzero((char *)&frame, sizeof(frame)); 773 774 /* 775 * Note: both the AL981 and AN985 have internal PHYs, 776 * however the AL981 provides direct access to the PHY 777 * registers while the AN985 uses a serial MII interface. 778 * The AN985's MII interface is also buggy in that you 779 * can read from any MII address (0 to 31), but only address 1 780 * behaves normally. To deal with both cases, we pretend 781 * that the PHY is at MII address 1. 782 */ 783 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 784 return(0); 785 786 /* 787 * Note: the ukphy probes of the RS7112 report a PHY at 788 * MII address 0 (possibly HomePNA?) and 1 (ethernet) 789 * so we only respond to correct one. 790 */ 791 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 792 return(0); 793 794 if (sc->dc_pmode != DC_PMODE_MII) { 795 if (phy == (MII_NPHY - 1)) { 796 switch(reg) { 797 case MII_BMSR: 798 /* 799 * Fake something to make the probe 800 * code think there's a PHY here. 801 */ 802 return(BMSR_MEDIAMASK); 803 break; 804 case MII_PHYIDR1: 805 if (DC_IS_PNIC(sc)) 806 return(DC_VENDORID_LO); 807 return(DC_VENDORID_DEC); 808 break; 809 case MII_PHYIDR2: 810 if (DC_IS_PNIC(sc)) 811 return(DC_DEVICEID_82C168); 812 return(DC_DEVICEID_21143); 813 break; 814 default: 815 return(0); 816 break; 817 } 818 } else 819 return(0); 820 } 821 822 if (DC_IS_PNIC(sc)) { 823 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_READ | 824 (phy << 23) | (reg << 18)); 825 for (i = 0; i < DC_TIMEOUT; i++) { 826 DELAY(1); 827 rval = CSR_READ_4(sc, DC_PN_MII); 828 if (!(rval & DC_PN_MII_BUSY)) { 829 rval &= 0xFFFF; 830 return(rval == 0xFFFF ? 0 : rval); 831 } 832 } 833 return(0); 834 } 835 836 if (DC_IS_COMET(sc)) { 837 switch(reg) { 838 case MII_BMCR: 839 phy_reg = DC_AL_BMCR; 840 break; 841 case MII_BMSR: 842 phy_reg = DC_AL_BMSR; 843 break; 844 case MII_PHYIDR1: 845 phy_reg = DC_AL_VENID; 846 break; 847 case MII_PHYIDR2: 848 phy_reg = DC_AL_DEVID; 849 break; 850 case MII_ANAR: 851 phy_reg = DC_AL_ANAR; 852 break; 853 case MII_ANLPAR: 854 phy_reg = DC_AL_LPAR; 855 break; 856 case MII_ANER: 857 phy_reg = DC_AL_ANER; 858 break; 859 default: 860 if_printf(&sc->arpcom.ac_if, 861 "phy_read: bad phy register %x\n", reg); 862 return(0); 863 break; 864 } 865 866 rval = CSR_READ_4(sc, phy_reg) & 0x0000FFFF; 867 868 if (rval == 0xFFFF) 869 return(0); 870 return(rval); 871 } 872 873 frame.mii_phyaddr = phy; 874 frame.mii_regaddr = reg; 875 if (sc->dc_type == DC_TYPE_98713) { 876 phy_reg = CSR_READ_4(sc, DC_NETCFG); 877 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 878 } 879 dc_mii_readreg(sc, &frame); 880 if (sc->dc_type == DC_TYPE_98713) 881 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 882 883 return(frame.mii_data); 884 } 885 886 static int 887 dc_miibus_writereg(device_t dev, int phy, int reg, int data) 888 { 889 struct dc_softc *sc; 890 struct dc_mii_frame frame; 891 int i, phy_reg = 0; 892 893 sc = device_get_softc(dev); 894 bzero((char *)&frame, sizeof(frame)); 895 896 if (DC_IS_ADMTEK(sc) && phy != DC_ADMTEK_PHYADDR) 897 return(0); 898 899 if (DC_IS_CONEXANT(sc) && phy != DC_CONEXANT_PHYADDR) 900 return(0); 901 902 if (DC_IS_PNIC(sc)) { 903 CSR_WRITE_4(sc, DC_PN_MII, DC_PN_MIIOPCODE_WRITE | 904 (phy << 23) | (reg << 10) | data); 905 for (i = 0; i < DC_TIMEOUT; i++) { 906 if (!(CSR_READ_4(sc, DC_PN_MII) & DC_PN_MII_BUSY)) 907 break; 908 } 909 return(0); 910 } 911 912 if (DC_IS_COMET(sc)) { 913 switch(reg) { 914 case MII_BMCR: 915 phy_reg = DC_AL_BMCR; 916 break; 917 case MII_BMSR: 918 phy_reg = DC_AL_BMSR; 919 break; 920 case MII_PHYIDR1: 921 phy_reg = DC_AL_VENID; 922 break; 923 case MII_PHYIDR2: 924 phy_reg = DC_AL_DEVID; 925 break; 926 case MII_ANAR: 927 phy_reg = DC_AL_ANAR; 928 break; 929 case MII_ANLPAR: 930 phy_reg = DC_AL_LPAR; 931 break; 932 case MII_ANER: 933 phy_reg = DC_AL_ANER; 934 break; 935 default: 936 if_printf(&sc->arpcom.ac_if, 937 "phy_write: bad phy register %x\n", reg); 938 return(0); 939 break; 940 } 941 942 CSR_WRITE_4(sc, phy_reg, data); 943 return(0); 944 } 945 946 frame.mii_phyaddr = phy; 947 frame.mii_regaddr = reg; 948 frame.mii_data = data; 949 950 if (sc->dc_type == DC_TYPE_98713) { 951 phy_reg = CSR_READ_4(sc, DC_NETCFG); 952 CSR_WRITE_4(sc, DC_NETCFG, phy_reg & ~DC_NETCFG_PORTSEL); 953 } 954 dc_mii_writereg(sc, &frame); 955 if (sc->dc_type == DC_TYPE_98713) 956 CSR_WRITE_4(sc, DC_NETCFG, phy_reg); 957 958 return(0); 959 } 960 961 static void 962 dc_miibus_statchg(device_t dev) 963 { 964 struct dc_softc *sc; 965 struct mii_data *mii; 966 struct ifmedia *ifm; 967 968 sc = device_get_softc(dev); 969 if (DC_IS_ADMTEK(sc)) 970 return; 971 972 mii = device_get_softc(sc->dc_miibus); 973 ifm = &mii->mii_media; 974 if (DC_IS_DAVICOM(sc) && 975 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 976 dc_setcfg(sc, ifm->ifm_media); 977 sc->dc_if_media = ifm->ifm_media; 978 } else { 979 dc_setcfg(sc, mii->mii_media_active); 980 sc->dc_if_media = mii->mii_media_active; 981 } 982 983 return; 984 } 985 986 /* 987 * Special support for DM9102A cards with HomePNA PHYs. Note: 988 * with the Davicom DM9102A/DM9801 eval board that I have, it seems 989 * to be impossible to talk to the management interface of the DM9801 990 * PHY (its MDIO pin is not connected to anything). Consequently, 991 * the driver has to just 'know' about the additional mode and deal 992 * with it itself. *sigh* 993 */ 994 static void 995 dc_miibus_mediainit(device_t dev) 996 { 997 struct dc_softc *sc; 998 struct mii_data *mii; 999 struct ifmedia *ifm; 1000 int rev; 1001 1002 rev = pci_get_revid(dev); 1003 1004 sc = device_get_softc(dev); 1005 mii = device_get_softc(sc->dc_miibus); 1006 ifm = &mii->mii_media; 1007 1008 if (DC_IS_DAVICOM(sc) && rev >= DC_REVISION_DM9102A) 1009 ifmedia_add(ifm, IFM_ETHER | IFM_HPNA_1, 0, NULL); 1010 1011 return; 1012 } 1013 1014 #define DC_BITS_512 9 1015 #define DC_BITS_128 7 1016 #define DC_BITS_64 6 1017 1018 static u_int32_t 1019 dc_crc_mask(struct dc_softc *sc) 1020 { 1021 /* 1022 * The hash table on the PNIC II and the MX98715AEC-C/D/E 1023 * chips is only 128 bits wide. 1024 */ 1025 if (sc->dc_flags & DC_128BIT_HASH) 1026 return ((1 << DC_BITS_128) - 1); 1027 1028 /* The hash table on the MX98715BEC is only 64 bits wide. */ 1029 if (sc->dc_flags & DC_64BIT_HASH) 1030 return ((1 << DC_BITS_64) - 1); 1031 1032 return ((1 << DC_BITS_512) - 1); 1033 } 1034 1035 /* 1036 * 21143-style RX filter setup routine. Filter programming is done by 1037 * downloading a special setup frame into the TX engine. 21143, Macronix, 1038 * PNIC, PNIC II and Davicom chips are programmed this way. 1039 * 1040 * We always program the chip using 'hash perfect' mode, i.e. one perfect 1041 * address (our node address) and a 512-bit hash filter for multicast 1042 * frames. We also sneak the broadcast address into the hash filter since 1043 * we need that too. 1044 */ 1045 void 1046 dc_setfilt_21143(struct dc_softc *sc) 1047 { 1048 struct dc_desc *sframe; 1049 u_int32_t h, crc_mask, *sp; 1050 struct ifmultiaddr *ifma; 1051 struct ifnet *ifp; 1052 int i; 1053 1054 ifp = &sc->arpcom.ac_if; 1055 1056 i = sc->dc_cdata.dc_tx_prod; 1057 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1058 sc->dc_cdata.dc_tx_cnt++; 1059 sframe = &sc->dc_ldata->dc_tx_list[i]; 1060 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1061 bzero((char *)sp, DC_SFRAME_LEN); 1062 1063 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1064 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1065 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1066 1067 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1068 1069 /* If we want promiscuous mode, set the allframes bit. */ 1070 if (ifp->if_flags & IFF_PROMISC) 1071 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1072 else 1073 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1074 1075 if (ifp->if_flags & IFF_ALLMULTI) 1076 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1077 else 1078 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1079 1080 crc_mask = dc_crc_mask(sc); 1081 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1082 if (ifma->ifma_addr->sa_family != AF_LINK) 1083 continue; 1084 h = ether_crc32_le( 1085 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1086 ETHER_ADDR_LEN) & crc_mask; 1087 sp[h >> 4] |= 1 << (h & 0xF); 1088 } 1089 1090 if (ifp->if_flags & IFF_BROADCAST) { 1091 h = ether_crc32_le(ifp->if_broadcastaddr, 1092 ETHER_ADDR_LEN) & crc_mask; 1093 sp[h >> 4] |= 1 << (h & 0xF); 1094 } 1095 1096 /* Set our MAC address */ 1097 sp[39] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1098 sp[40] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1099 sp[41] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1100 1101 sframe->dc_status = DC_TXSTAT_OWN; 1102 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1103 1104 /* 1105 * The PNIC takes an exceedingly long time to process its 1106 * setup frame; wait 10ms after posting the setup frame 1107 * before proceeding, just so it has time to swallow its 1108 * medicine. 1109 */ 1110 DELAY(10000); 1111 1112 ifp->if_timer = 5; 1113 1114 return; 1115 } 1116 1117 void 1118 dc_setfilt_admtek(struct dc_softc *sc) 1119 { 1120 struct ifnet *ifp; 1121 int h = 0; 1122 u_int32_t crc_mask; 1123 u_int32_t hashes[2] = { 0, 0 }; 1124 struct ifmultiaddr *ifma; 1125 1126 ifp = &sc->arpcom.ac_if; 1127 1128 /* Init our MAC address */ 1129 CSR_WRITE_4(sc, DC_AL_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1130 CSR_WRITE_4(sc, DC_AL_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1131 1132 /* If we want promiscuous mode, set the allframes bit. */ 1133 if (ifp->if_flags & IFF_PROMISC) 1134 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1135 else 1136 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1137 1138 if (ifp->if_flags & IFF_ALLMULTI) 1139 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1140 else 1141 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1142 1143 /* first, zot all the existing hash bits */ 1144 CSR_WRITE_4(sc, DC_AL_MAR0, 0); 1145 CSR_WRITE_4(sc, DC_AL_MAR1, 0); 1146 1147 /* 1148 * If we're already in promisc or allmulti mode, we 1149 * don't have to bother programming the multicast filter. 1150 */ 1151 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1152 return; 1153 1154 /* now program new ones */ 1155 if (DC_IS_CENTAUR(sc)) 1156 crc_mask = dc_crc_mask(sc); 1157 else 1158 crc_mask = 0x3f; 1159 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1160 if (ifma->ifma_addr->sa_family != AF_LINK) 1161 continue; 1162 if (DC_IS_CENTAUR(sc)) { 1163 h = ether_crc32_le( 1164 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1165 ETHER_ADDR_LEN) & crc_mask; 1166 } else { 1167 h = ether_crc32_be( 1168 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1169 ETHER_ADDR_LEN); 1170 h = (h >> 26) & crc_mask; 1171 } 1172 if (h < 32) 1173 hashes[0] |= (1 << h); 1174 else 1175 hashes[1] |= (1 << (h - 32)); 1176 } 1177 1178 CSR_WRITE_4(sc, DC_AL_MAR0, hashes[0]); 1179 CSR_WRITE_4(sc, DC_AL_MAR1, hashes[1]); 1180 1181 return; 1182 } 1183 1184 void 1185 dc_setfilt_asix(struct dc_softc *sc) 1186 { 1187 struct ifnet *ifp; 1188 int h = 0; 1189 u_int32_t hashes[2] = { 0, 0 }; 1190 struct ifmultiaddr *ifma; 1191 1192 ifp = &sc->arpcom.ac_if; 1193 1194 /* Init our MAC address */ 1195 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR0); 1196 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1197 *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1198 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_PAR1); 1199 CSR_WRITE_4(sc, DC_AX_FILTDATA, 1200 *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1201 1202 /* If we want promiscuous mode, set the allframes bit. */ 1203 if (ifp->if_flags & IFF_PROMISC) 1204 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1205 else 1206 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1207 1208 if (ifp->if_flags & IFF_ALLMULTI) 1209 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1210 else 1211 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1212 1213 /* 1214 * The ASIX chip has a special bit to enable reception 1215 * of broadcast frames. 1216 */ 1217 if (ifp->if_flags & IFF_BROADCAST) 1218 DC_SETBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1219 else 1220 DC_CLRBIT(sc, DC_NETCFG, DC_AX_NETCFG_RX_BROAD); 1221 1222 /* first, zot all the existing hash bits */ 1223 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1224 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1225 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1226 CSR_WRITE_4(sc, DC_AX_FILTDATA, 0); 1227 1228 /* 1229 * If we're already in promisc or allmulti mode, we 1230 * don't have to bother programming the multicast filter. 1231 */ 1232 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) 1233 return; 1234 1235 /* now program new ones */ 1236 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1237 if (ifma->ifma_addr->sa_family != AF_LINK) 1238 continue; 1239 h = ether_crc32_be( 1240 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1241 ETHER_ADDR_LEN); 1242 h = (h >> 26) & 0x3f; 1243 if (h < 32) 1244 hashes[0] |= (1 << h); 1245 else 1246 hashes[1] |= (1 << (h - 32)); 1247 } 1248 1249 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR0); 1250 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[0]); 1251 CSR_WRITE_4(sc, DC_AX_FILTIDX, DC_AX_FILTIDX_MAR1); 1252 CSR_WRITE_4(sc, DC_AX_FILTDATA, hashes[1]); 1253 1254 return; 1255 } 1256 1257 void 1258 dc_setfilt_xircom(struct dc_softc *sc) 1259 { 1260 struct dc_desc *sframe; 1261 u_int32_t h, *sp; 1262 struct ifmultiaddr *ifma; 1263 struct ifnet *ifp; 1264 int i; 1265 1266 ifp = &sc->arpcom.ac_if; 1267 KASSERT(ifp->if_flags & IFF_RUNNING, 1268 ("%s is not running yet", ifp->if_xname)); 1269 1270 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1271 1272 i = sc->dc_cdata.dc_tx_prod; 1273 DC_INC(sc->dc_cdata.dc_tx_prod, DC_TX_LIST_CNT); 1274 sc->dc_cdata.dc_tx_cnt++; 1275 sframe = &sc->dc_ldata->dc_tx_list[i]; 1276 sp = (u_int32_t *)&sc->dc_cdata.dc_sbuf; 1277 bzero(sp, DC_SFRAME_LEN); 1278 1279 sframe->dc_data = vtophys(&sc->dc_cdata.dc_sbuf); 1280 sframe->dc_ctl = DC_SFRAME_LEN | DC_TXCTL_SETUP | DC_TXCTL_TLINK | 1281 DC_FILTER_HASHPERF | DC_TXCTL_FINT; 1282 1283 sc->dc_cdata.dc_tx_chain[i] = (struct mbuf *)&sc->dc_cdata.dc_sbuf; 1284 1285 /* If we want promiscuous mode, set the allframes bit. */ 1286 if (ifp->if_flags & IFF_PROMISC) 1287 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1288 else 1289 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_PROMISC); 1290 1291 if (ifp->if_flags & IFF_ALLMULTI) 1292 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1293 else 1294 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_RX_ALLMULTI); 1295 1296 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1297 if (ifma->ifma_addr->sa_family != AF_LINK) 1298 continue; 1299 h = dc_mchash_xircom(sc, 1300 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1301 sp[h >> 4] |= 1 << (h & 0xF); 1302 } 1303 1304 if (ifp->if_flags & IFF_BROADCAST) { 1305 h = dc_mchash_xircom(sc, (caddr_t)ðerbroadcastaddr); 1306 sp[h >> 4] |= 1 << (h & 0xF); 1307 } 1308 1309 /* Set our MAC address */ 1310 sp[0] = ((u_int16_t *)sc->arpcom.ac_enaddr)[0]; 1311 sp[1] = ((u_int16_t *)sc->arpcom.ac_enaddr)[1]; 1312 sp[2] = ((u_int16_t *)sc->arpcom.ac_enaddr)[2]; 1313 1314 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 1315 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 1316 sframe->dc_status = DC_TXSTAT_OWN; 1317 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 1318 1319 /* 1320 * wait some time... 1321 */ 1322 DELAY(1000); 1323 1324 ifp->if_timer = 5; 1325 } 1326 1327 static void 1328 dc_setfilt(struct dc_softc *sc) 1329 { 1330 if (DC_IS_INTEL(sc) || DC_IS_MACRONIX(sc) || DC_IS_PNIC(sc) || 1331 DC_IS_PNICII(sc) || DC_IS_DAVICOM(sc) || DC_IS_CONEXANT(sc)) 1332 dc_setfilt_21143(sc); 1333 1334 if (DC_IS_ASIX(sc)) 1335 dc_setfilt_asix(sc); 1336 1337 if (DC_IS_ADMTEK(sc)) 1338 dc_setfilt_admtek(sc); 1339 1340 if (DC_IS_XIRCOM(sc)) 1341 dc_setfilt_xircom(sc); 1342 } 1343 1344 /* 1345 * In order to fiddle with the 1346 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 1347 * first have to put the transmit and/or receive logic in the idle state. 1348 */ 1349 static void 1350 dc_setcfg(struct dc_softc *sc, int media) 1351 { 1352 int i, restart = 0; 1353 u_int32_t isr; 1354 1355 if (IFM_SUBTYPE(media) == IFM_NONE) 1356 return; 1357 1358 if (CSR_READ_4(sc, DC_NETCFG) & (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)) { 1359 restart = 1; 1360 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_TX_ON|DC_NETCFG_RX_ON)); 1361 1362 for (i = 0; i < DC_TIMEOUT; i++) { 1363 isr = CSR_READ_4(sc, DC_ISR); 1364 if ((isr & DC_ISR_TX_IDLE) && 1365 ((isr & DC_ISR_RX_STATE) == DC_RXSTATE_STOPPED || 1366 (isr & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT)) 1367 break; 1368 DELAY(10); 1369 } 1370 1371 if (i == DC_TIMEOUT) { 1372 if_printf(&sc->arpcom.ac_if, 1373 "failed to force tx and rx to idle state\n"); 1374 } 1375 } 1376 1377 if (IFM_SUBTYPE(media) == IFM_100_TX) { 1378 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1379 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1380 if (sc->dc_pmode == DC_PMODE_MII) { 1381 int watchdogreg; 1382 1383 if (DC_IS_INTEL(sc)) { 1384 /* there's a write enable bit here that reads as 1 */ 1385 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1386 watchdogreg &= ~DC_WDOG_CTLWREN; 1387 watchdogreg |= DC_WDOG_JABBERDIS; 1388 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1389 } else { 1390 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1391 } 1392 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1393 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1394 if (sc->dc_type == DC_TYPE_98713) 1395 DC_SETBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1396 DC_NETCFG_SCRAMBLER)); 1397 if (!DC_IS_DAVICOM(sc)) 1398 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1399 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1400 if (DC_IS_INTEL(sc)) 1401 dc_apply_fixup(sc, IFM_AUTO); 1402 } else { 1403 if (DC_IS_PNIC(sc)) { 1404 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_SPEEDSEL); 1405 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1406 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1407 } 1408 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1409 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1410 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1411 if (DC_IS_INTEL(sc)) 1412 dc_apply_fixup(sc, 1413 (media & IFM_GMASK) == IFM_FDX ? 1414 IFM_100_TX|IFM_FDX : IFM_100_TX); 1415 } 1416 } 1417 1418 if (IFM_SUBTYPE(media) == IFM_10_T) { 1419 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_SPEEDSEL); 1420 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_HEARTBEAT); 1421 if (sc->dc_pmode == DC_PMODE_MII) { 1422 int watchdogreg; 1423 1424 /* there's a write enable bit here that reads as 1 */ 1425 if (DC_IS_INTEL(sc)) { 1426 watchdogreg = CSR_READ_4(sc, DC_WATCHDOG); 1427 watchdogreg &= ~DC_WDOG_CTLWREN; 1428 watchdogreg |= DC_WDOG_JABBERDIS; 1429 CSR_WRITE_4(sc, DC_WATCHDOG, watchdogreg); 1430 } else { 1431 DC_SETBIT(sc, DC_WATCHDOG, DC_WDOG_JABBERDIS); 1432 } 1433 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_PCS| 1434 DC_NETCFG_PORTSEL|DC_NETCFG_SCRAMBLER)); 1435 if (sc->dc_type == DC_TYPE_98713) 1436 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1437 if (!DC_IS_DAVICOM(sc)) 1438 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1439 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1440 if (DC_IS_INTEL(sc)) 1441 dc_apply_fixup(sc, IFM_AUTO); 1442 } else { 1443 if (DC_IS_PNIC(sc)) { 1444 DC_PN_GPIO_CLRBIT(sc, DC_PN_GPIO_SPEEDSEL); 1445 DC_PN_GPIO_SETBIT(sc, DC_PN_GPIO_100TX_LOOP); 1446 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_SPEEDSEL); 1447 } 1448 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1449 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PCS); 1450 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_SCRAMBLER); 1451 if (DC_IS_INTEL(sc)) { 1452 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 1453 DC_CLRBIT(sc, DC_10BTCTRL, 0xFFFF); 1454 if ((media & IFM_GMASK) == IFM_FDX) 1455 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3D); 1456 else 1457 DC_SETBIT(sc, DC_10BTCTRL, 0x7F3F); 1458 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1459 DC_CLRBIT(sc, DC_10BTCTRL, 1460 DC_TCTL_AUTONEGENBL); 1461 dc_apply_fixup(sc, 1462 (media & IFM_GMASK) == IFM_FDX ? 1463 IFM_10_T|IFM_FDX : IFM_10_T); 1464 DELAY(20000); 1465 } 1466 } 1467 } 1468 1469 /* 1470 * If this is a Davicom DM9102A card with a DM9801 HomePNA 1471 * PHY and we want HomePNA mode, set the portsel bit to turn 1472 * on the external MII port. 1473 */ 1474 if (DC_IS_DAVICOM(sc)) { 1475 if (IFM_SUBTYPE(media) == IFM_HPNA_1) { 1476 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1477 sc->dc_link = 1; 1478 } else { 1479 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 1480 } 1481 } 1482 1483 if ((media & IFM_GMASK) == IFM_FDX) { 1484 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1485 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1486 DC_SETBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1487 } else { 1488 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 1489 if (sc->dc_pmode == DC_PMODE_SYM && DC_IS_PNIC(sc)) 1490 DC_CLRBIT(sc, DC_PN_NWAY, DC_PN_NWAY_DUPLEX); 1491 } 1492 1493 if (restart) 1494 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON|DC_NETCFG_RX_ON); 1495 1496 return; 1497 } 1498 1499 static void 1500 dc_reset(struct dc_softc *sc) 1501 { 1502 int i; 1503 1504 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1505 1506 for (i = 0; i < DC_TIMEOUT; i++) { 1507 DELAY(10); 1508 if (!(CSR_READ_4(sc, DC_BUSCTL) & DC_BUSCTL_RESET)) 1509 break; 1510 } 1511 1512 if (DC_IS_ASIX(sc) || DC_IS_ADMTEK(sc) || DC_IS_XIRCOM(sc) || 1513 DC_IS_CONEXANT(sc)) { 1514 DELAY(10000); 1515 DC_CLRBIT(sc, DC_BUSCTL, DC_BUSCTL_RESET); 1516 i = 0; 1517 } 1518 1519 if (i == DC_TIMEOUT) 1520 if_printf(&sc->arpcom.ac_if, "reset never completed!\n"); 1521 1522 /* Wait a little while for the chip to get its brains in order. */ 1523 DELAY(1000); 1524 1525 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 1526 CSR_WRITE_4(sc, DC_BUSCTL, 0x00000000); 1527 CSR_WRITE_4(sc, DC_NETCFG, 0x00000000); 1528 1529 /* 1530 * Bring the SIA out of reset. In some cases, it looks 1531 * like failing to unreset the SIA soon enough gets it 1532 * into a state where it will never come out of reset 1533 * until we reset the whole chip again. 1534 */ 1535 if (DC_IS_INTEL(sc)) { 1536 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 1537 CSR_WRITE_4(sc, DC_10BTCTRL, 0); 1538 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 1539 } 1540 1541 return; 1542 } 1543 1544 static const struct dc_type * 1545 dc_devtype(device_t dev) 1546 { 1547 const struct dc_type *t; 1548 u_int32_t rev; 1549 1550 t = dc_devs; 1551 1552 while(t->dc_name != NULL) { 1553 if ((pci_get_vendor(dev) == t->dc_vid) && 1554 (pci_get_device(dev) == t->dc_did)) { 1555 /* Check the PCI revision */ 1556 rev = pci_get_revid(dev); 1557 if (t->dc_did == DC_DEVICEID_98713 && 1558 rev >= DC_REVISION_98713A) 1559 t++; 1560 if (t->dc_did == DC_DEVICEID_98713_CP && 1561 rev >= DC_REVISION_98713A) 1562 t++; 1563 if (t->dc_did == DC_DEVICEID_987x5 && 1564 rev >= DC_REVISION_98715AEC_C) 1565 t++; 1566 if (t->dc_did == DC_DEVICEID_987x5 && 1567 rev >= DC_REVISION_98725) 1568 t++; 1569 if (t->dc_did == DC_DEVICEID_AX88140A && 1570 rev >= DC_REVISION_88141) 1571 t++; 1572 if (t->dc_did == DC_DEVICEID_82C168 && 1573 rev >= DC_REVISION_82C169) 1574 t++; 1575 if (t->dc_did == DC_DEVICEID_DM9102 && 1576 rev >= DC_REVISION_DM9102A) 1577 t++; 1578 return(t); 1579 } 1580 t++; 1581 } 1582 1583 return(NULL); 1584 } 1585 1586 /* 1587 * Probe for a 21143 or clone chip. Check the PCI vendor and device 1588 * IDs against our list and return a device name if we find a match. 1589 * We do a little bit of extra work to identify the exact type of 1590 * chip. The MX98713 and MX98713A have the same PCI vendor/device ID, 1591 * but different revision IDs. The same is true for 98715/98715A 1592 * chips and the 98725, as well as the ASIX and ADMtek chips. In some 1593 * cases, the exact chip revision affects driver behavior. 1594 */ 1595 static int 1596 dc_probe(device_t dev) 1597 { 1598 const struct dc_type *t; 1599 1600 t = dc_devtype(dev); 1601 if (t != NULL) { 1602 struct dc_softc *sc = device_get_softc(dev); 1603 1604 /* Need this info to decide on a chip type. */ 1605 sc->dc_info = t; 1606 device_set_desc(dev, t->dc_name); 1607 return(0); 1608 } 1609 1610 return(ENXIO); 1611 } 1612 1613 static void 1614 dc_acpi(device_t dev) 1615 { 1616 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 1617 uint32_t iobase, membase, irq; 1618 struct dc_softc *sc; 1619 1620 /* Save important PCI config data. */ 1621 iobase = pci_read_config(dev, DC_PCI_CFBIO, 4); 1622 membase = pci_read_config(dev, DC_PCI_CFBMA, 4); 1623 irq = pci_read_config(dev, DC_PCI_CFIT, 4); 1624 1625 sc = device_get_softc(dev); 1626 /* Reset the power state. */ 1627 if_printf(&sc->arpcom.ac_if, 1628 "chip is in D%d power mode " 1629 "-- setting to D0\n", pci_get_powerstate(dev)); 1630 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 1631 1632 /* Restore PCI config data. */ 1633 pci_write_config(dev, DC_PCI_CFBIO, iobase, 4); 1634 pci_write_config(dev, DC_PCI_CFBMA, membase, 4); 1635 pci_write_config(dev, DC_PCI_CFIT, irq, 4); 1636 } 1637 } 1638 1639 static void 1640 dc_apply_fixup(struct dc_softc *sc, int media) 1641 { 1642 struct dc_mediainfo *m; 1643 u_int8_t *p; 1644 int i; 1645 u_int32_t reg; 1646 1647 m = sc->dc_mi; 1648 1649 while (m != NULL) { 1650 if (m->dc_media == media) 1651 break; 1652 m = m->dc_next; 1653 } 1654 1655 if (m == NULL) 1656 return; 1657 1658 for (i = 0, p = m->dc_reset_ptr; i < m->dc_reset_len; i++, p += 2) { 1659 reg = (p[0] | (p[1] << 8)) << 16; 1660 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1661 } 1662 1663 for (i = 0, p = m->dc_gp_ptr; i < m->dc_gp_len; i++, p += 2) { 1664 reg = (p[0] | (p[1] << 8)) << 16; 1665 CSR_WRITE_4(sc, DC_WATCHDOG, reg); 1666 } 1667 1668 return; 1669 } 1670 1671 static void 1672 dc_decode_leaf_sia(struct dc_softc *sc, struct dc_eblock_sia *l) 1673 { 1674 struct dc_mediainfo *m; 1675 1676 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1677 switch (l->dc_sia_code & ~DC_SIA_CODE_EXT){ 1678 case DC_SIA_CODE_10BT: 1679 m->dc_media = IFM_10_T; 1680 break; 1681 1682 case DC_SIA_CODE_10BT_FDX: 1683 m->dc_media = IFM_10_T|IFM_FDX; 1684 break; 1685 1686 case DC_SIA_CODE_10B2: 1687 m->dc_media = IFM_10_2; 1688 break; 1689 1690 case DC_SIA_CODE_10B5: 1691 m->dc_media = IFM_10_5; 1692 break; 1693 } 1694 if (l->dc_sia_code & DC_SIA_CODE_EXT){ 1695 m->dc_gp_len = 2; 1696 m->dc_gp_ptr = 1697 (u_int8_t *)&l->dc_un.dc_sia_ext.dc_sia_gpio_ctl; 1698 } else { 1699 m->dc_gp_len = 2; 1700 m->dc_gp_ptr = 1701 (u_int8_t *)&l->dc_un.dc_sia_noext.dc_sia_gpio_ctl; 1702 } 1703 1704 m->dc_next = sc->dc_mi; 1705 sc->dc_mi = m; 1706 1707 sc->dc_pmode = DC_PMODE_SIA; 1708 1709 return; 1710 } 1711 1712 static void 1713 dc_decode_leaf_sym(struct dc_softc *sc, struct dc_eblock_sym *l) 1714 { 1715 struct dc_mediainfo *m; 1716 1717 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1718 if (l->dc_sym_code == DC_SYM_CODE_100BT) 1719 m->dc_media = IFM_100_TX; 1720 1721 if (l->dc_sym_code == DC_SYM_CODE_100BT_FDX) 1722 m->dc_media = IFM_100_TX|IFM_FDX; 1723 1724 m->dc_gp_len = 2; 1725 m->dc_gp_ptr = (u_int8_t *)&l->dc_sym_gpio_ctl; 1726 1727 m->dc_next = sc->dc_mi; 1728 sc->dc_mi = m; 1729 1730 sc->dc_pmode = DC_PMODE_SYM; 1731 1732 return; 1733 } 1734 1735 static void 1736 dc_decode_leaf_mii(struct dc_softc *sc, struct dc_eblock_mii *l) 1737 { 1738 u_int8_t *p; 1739 struct dc_mediainfo *m; 1740 1741 m = kmalloc(sizeof(struct dc_mediainfo), M_DEVBUF, M_INTWAIT | M_ZERO); 1742 /* We abuse IFM_AUTO to represent MII. */ 1743 m->dc_media = IFM_AUTO; 1744 m->dc_gp_len = l->dc_gpr_len; 1745 1746 p = (u_int8_t *)l; 1747 p += sizeof(struct dc_eblock_mii); 1748 m->dc_gp_ptr = p; 1749 p += 2 * l->dc_gpr_len; 1750 m->dc_reset_len = *p; 1751 p++; 1752 m->dc_reset_ptr = p; 1753 1754 m->dc_next = sc->dc_mi; 1755 sc->dc_mi = m; 1756 1757 return; 1758 } 1759 1760 static void 1761 dc_read_srom(struct dc_softc *sc, int bits) 1762 { 1763 int size; 1764 1765 size = 2 << bits; 1766 sc->dc_srom = kmalloc(size, M_DEVBUF, M_INTWAIT); 1767 dc_read_eeprom(sc, (caddr_t)sc->dc_srom, 0, (size / 2), 0); 1768 } 1769 1770 static void 1771 dc_parse_21143_srom(struct dc_softc *sc) 1772 { 1773 struct dc_leaf_hdr *lhdr; 1774 struct dc_eblock_hdr *hdr; 1775 int i, loff; 1776 char *ptr; 1777 int have_mii; 1778 1779 have_mii = 0; 1780 loff = sc->dc_srom[27]; 1781 lhdr = (struct dc_leaf_hdr *)&(sc->dc_srom[loff]); 1782 1783 ptr = (char *)lhdr; 1784 ptr += sizeof(struct dc_leaf_hdr) - 1; 1785 /* 1786 * Look if we got a MII media block. 1787 */ 1788 for (i = 0; i < lhdr->dc_mcnt; i++) { 1789 hdr = (struct dc_eblock_hdr *)ptr; 1790 if (hdr->dc_type == DC_EBLOCK_MII) 1791 have_mii++; 1792 1793 ptr += (hdr->dc_len & 0x7F); 1794 ptr++; 1795 } 1796 1797 /* 1798 * Do the same thing again. Only use SIA and SYM media 1799 * blocks if no MII media block is available. 1800 */ 1801 ptr = (char *)lhdr; 1802 ptr += sizeof(struct dc_leaf_hdr) - 1; 1803 for (i = 0; i < lhdr->dc_mcnt; i++) { 1804 hdr = (struct dc_eblock_hdr *)ptr; 1805 switch(hdr->dc_type) { 1806 case DC_EBLOCK_MII: 1807 dc_decode_leaf_mii(sc, (struct dc_eblock_mii *)hdr); 1808 break; 1809 case DC_EBLOCK_SIA: 1810 if (! have_mii) 1811 dc_decode_leaf_sia(sc, 1812 (struct dc_eblock_sia *)hdr); 1813 break; 1814 case DC_EBLOCK_SYM: 1815 if (! have_mii) 1816 dc_decode_leaf_sym(sc, 1817 (struct dc_eblock_sym *)hdr); 1818 break; 1819 default: 1820 /* Don't care. Yet. */ 1821 break; 1822 } 1823 ptr += (hdr->dc_len & 0x7F); 1824 ptr++; 1825 } 1826 1827 return; 1828 } 1829 1830 /* 1831 * Attach the interface. Allocate softc structures, do ifmedia 1832 * setup and ethernet/BPF attach. 1833 */ 1834 static int 1835 dc_attach(device_t dev) 1836 { 1837 int tmp = 0; 1838 u_char eaddr[ETHER_ADDR_LEN]; 1839 u_int32_t command; 1840 struct dc_softc *sc; 1841 struct ifnet *ifp; 1842 u_int32_t revision; 1843 int error = 0, rid, mac_offset; 1844 uint8_t *mac; 1845 1846 sc = device_get_softc(dev); 1847 callout_init(&sc->dc_stat_timer); 1848 1849 ifp = &sc->arpcom.ac_if; 1850 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1851 1852 /* 1853 * Handle power management nonsense. 1854 */ 1855 dc_acpi(dev); 1856 1857 /* 1858 * Map control/status registers. 1859 */ 1860 pci_enable_busmaster(dev); 1861 1862 rid = DC_RID; 1863 sc->dc_res = bus_alloc_resource_any(dev, DC_RES, &rid, RF_ACTIVE); 1864 1865 if (sc->dc_res == NULL) { 1866 device_printf(dev, "couldn't map ports/memory\n"); 1867 error = ENXIO; 1868 goto fail; 1869 } 1870 1871 sc->dc_btag = rman_get_bustag(sc->dc_res); 1872 sc->dc_bhandle = rman_get_bushandle(sc->dc_res); 1873 1874 /* Allocate interrupt */ 1875 rid = 0; 1876 sc->dc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1877 RF_SHAREABLE | RF_ACTIVE); 1878 1879 if (sc->dc_irq == NULL) { 1880 device_printf(dev, "couldn't map interrupt\n"); 1881 error = ENXIO; 1882 goto fail; 1883 } 1884 1885 revision = pci_get_revid(dev); 1886 1887 /* Get the eeprom width, but PNIC and XIRCOM have diff eeprom */ 1888 if (sc->dc_info->dc_did != DC_DEVICEID_82C168 && 1889 sc->dc_info->dc_did != DC_DEVICEID_X3201) 1890 dc_eeprom_width(sc); 1891 1892 switch(sc->dc_info->dc_did) { 1893 case DC_DEVICEID_21143: 1894 sc->dc_type = DC_TYPE_21143; 1895 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1896 sc->dc_flags |= DC_REDUCED_MII_POLL; 1897 /* Save EEPROM contents so we can parse them later. */ 1898 dc_read_srom(sc, sc->dc_romwidth); 1899 break; 1900 case DC_DEVICEID_DM9009: 1901 case DC_DEVICEID_DM9100: 1902 case DC_DEVICEID_DM9102: 1903 sc->dc_type = DC_TYPE_DM9102; 1904 sc->dc_flags |= DC_TX_COALESCE|DC_TX_INTR_ALWAYS; 1905 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; 1906 sc->dc_flags |= DC_TX_ALIGN; 1907 sc->dc_pmode = DC_PMODE_MII; 1908 /* Increase the latency timer value. */ 1909 command = pci_read_config(dev, DC_PCI_CFLT, 4); 1910 command &= 0xFFFF00FF; 1911 command |= 0x00008000; 1912 pci_write_config(dev, DC_PCI_CFLT, command, 4); 1913 break; 1914 case DC_DEVICEID_AL981: 1915 sc->dc_type = DC_TYPE_AL981; 1916 sc->dc_flags |= DC_TX_USE_TX_INTR; 1917 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1918 sc->dc_pmode = DC_PMODE_MII; 1919 dc_read_srom(sc, sc->dc_romwidth); 1920 break; 1921 case DC_DEVICEID_AN985: 1922 case DC_DEVICEID_FE2500: 1923 case DC_DEVICEID_ADM9511: 1924 case DC_DEVICEID_ADM9513: 1925 case DC_DEVICEID_FA511: 1926 case DC_DEVICEID_EN2242: 1927 case DC_DEVICEID_3CSOHOB: 1928 sc->dc_type = DC_TYPE_AN985; 1929 sc->dc_flags |= DC_64BIT_HASH; 1930 sc->dc_flags |= DC_TX_USE_TX_INTR; 1931 sc->dc_flags |= DC_TX_ADMTEK_WAR; 1932 sc->dc_pmode = DC_PMODE_MII; 1933 break; 1934 case DC_DEVICEID_98713: 1935 case DC_DEVICEID_98713_CP: 1936 if (revision < DC_REVISION_98713A) { 1937 sc->dc_type = DC_TYPE_98713; 1938 } 1939 if (revision >= DC_REVISION_98713A) { 1940 sc->dc_type = DC_TYPE_98713A; 1941 sc->dc_flags |= DC_21143_NWAY; 1942 } 1943 sc->dc_flags |= DC_REDUCED_MII_POLL; 1944 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1945 break; 1946 case DC_DEVICEID_987x5: 1947 case DC_DEVICEID_EN1217: 1948 /* 1949 * Macronix MX98715AEC-C/D/E parts have only a 1950 * 128-bit hash table. We need to deal with these 1951 * in the same manner as the PNIC II so that we 1952 * get the right number of bits out of the 1953 * CRC routine. 1954 */ 1955 if (revision >= DC_REVISION_98715AEC_C && 1956 revision < DC_REVISION_98725) 1957 sc->dc_flags |= DC_128BIT_HASH; 1958 sc->dc_type = DC_TYPE_987x5; 1959 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1960 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1961 break; 1962 case DC_DEVICEID_98727: 1963 sc->dc_type = DC_TYPE_987x5; 1964 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR; 1965 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1966 break; 1967 case DC_DEVICEID_82C115: 1968 sc->dc_type = DC_TYPE_PNICII; 1969 sc->dc_flags |= DC_TX_POLL|DC_TX_USE_TX_INTR|DC_128BIT_HASH; 1970 sc->dc_flags |= DC_REDUCED_MII_POLL|DC_21143_NWAY; 1971 break; 1972 case DC_DEVICEID_82C168: 1973 sc->dc_type = DC_TYPE_PNIC; 1974 sc->dc_flags |= DC_TX_STORENFWD|DC_TX_INTR_ALWAYS; 1975 sc->dc_flags |= DC_PNIC_RX_BUG_WAR; 1976 sc->dc_pnic_rx_buf = kmalloc(DC_RXLEN * 5, M_DEVBUF, M_WAITOK); 1977 if (revision < DC_REVISION_82C169) 1978 sc->dc_pmode = DC_PMODE_SYM; 1979 break; 1980 case DC_DEVICEID_AX88140A: 1981 sc->dc_type = DC_TYPE_ASIX; 1982 sc->dc_flags |= DC_TX_USE_TX_INTR|DC_TX_INTR_FIRSTFRAG; 1983 sc->dc_flags |= DC_REDUCED_MII_POLL; 1984 sc->dc_pmode = DC_PMODE_MII; 1985 break; 1986 case DC_DEVICEID_RS7112: 1987 sc->dc_type = DC_TYPE_CONEXANT; 1988 sc->dc_flags |= DC_TX_INTR_ALWAYS; 1989 sc->dc_flags |= DC_REDUCED_MII_POLL; 1990 sc->dc_pmode = DC_PMODE_MII; 1991 dc_read_srom(sc, sc->dc_romwidth); 1992 break; 1993 case DC_DEVICEID_X3201: 1994 sc->dc_type = DC_TYPE_XIRCOM; 1995 sc->dc_flags |= (DC_TX_INTR_ALWAYS | DC_TX_COALESCE | 1996 DC_TX_ALIGN); 1997 /* 1998 * We don't actually need to coalesce, but we're doing 1999 * it to obtain a double word aligned buffer. 2000 * The DC_TX_COALESCE flag is required. 2001 */ 2002 sc->dc_pmode = DC_PMODE_MII; 2003 break; 2004 default: 2005 device_printf(dev, "unknown device: %x\n", sc->dc_info->dc_did); 2006 break; 2007 } 2008 2009 /* Save the cache line size. */ 2010 if (DC_IS_DAVICOM(sc)) 2011 sc->dc_cachesize = 0; 2012 else 2013 sc->dc_cachesize = pci_read_config(dev, 2014 DC_PCI_CFLT, 4) & 0xFF; 2015 2016 /* Reset the adapter. */ 2017 dc_reset(sc); 2018 2019 /* Take 21143 out of snooze mode */ 2020 if (DC_IS_INTEL(sc) || DC_IS_XIRCOM(sc)) { 2021 command = pci_read_config(dev, DC_PCI_CFDD, 4); 2022 command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); 2023 pci_write_config(dev, DC_PCI_CFDD, command, 4); 2024 } 2025 2026 /* 2027 * Try to learn something about the supported media. 2028 * We know that ASIX and ADMtek and Davicom devices 2029 * will *always* be using MII media, so that's a no-brainer. 2030 * The tricky ones are the Macronix/PNIC II and the 2031 * Intel 21143. 2032 */ 2033 if (DC_IS_INTEL(sc)) 2034 dc_parse_21143_srom(sc); 2035 else if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 2036 if (sc->dc_type == DC_TYPE_98713) 2037 sc->dc_pmode = DC_PMODE_MII; 2038 else 2039 sc->dc_pmode = DC_PMODE_SYM; 2040 } else if (!sc->dc_pmode) 2041 sc->dc_pmode = DC_PMODE_MII; 2042 2043 /* 2044 * Get station address from the EEPROM. 2045 */ 2046 switch(sc->dc_type) { 2047 case DC_TYPE_98713: 2048 case DC_TYPE_98713A: 2049 case DC_TYPE_987x5: 2050 case DC_TYPE_PNICII: 2051 dc_read_eeprom(sc, (caddr_t)&mac_offset, 2052 (DC_EE_NODEADDR_OFFSET / 2), 1, 0); 2053 dc_read_eeprom(sc, (caddr_t)&eaddr, (mac_offset / 2), 3, 0); 2054 break; 2055 case DC_TYPE_PNIC: 2056 dc_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 1); 2057 break; 2058 case DC_TYPE_DM9102: 2059 case DC_TYPE_21143: 2060 case DC_TYPE_ASIX: 2061 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2062 break; 2063 case DC_TYPE_AL981: 2064 case DC_TYPE_AN985: 2065 *(u_int32_t *)(&eaddr[0]) = CSR_READ_4(sc,DC_AL_PAR0); 2066 *(u_int16_t *)(&eaddr[4]) = CSR_READ_4(sc,DC_AL_PAR1); 2067 break; 2068 case DC_TYPE_CONEXANT: 2069 bcopy(sc->dc_srom + DC_CONEXANT_EE_NODEADDR, &eaddr, 6); 2070 break; 2071 case DC_TYPE_XIRCOM: 2072 /* The MAC comes from the CIS */ 2073 mac = pci_get_ether(dev); 2074 if (!mac) { 2075 device_printf(dev, "No station address in CIS!\n"); 2076 error = ENXIO; 2077 goto fail; 2078 } 2079 bcopy(mac, eaddr, ETHER_ADDR_LEN); 2080 break; 2081 default: 2082 dc_read_eeprom(sc, (caddr_t)&eaddr, DC_EE_NODEADDR, 3, 0); 2083 break; 2084 } 2085 2086 sc->dc_ldata = contigmalloc(sizeof(struct dc_list_data), M_DEVBUF, 2087 M_WAITOK | M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0); 2088 2089 if (sc->dc_ldata == NULL) { 2090 device_printf(dev, "no memory for list buffers!\n"); 2091 error = ENXIO; 2092 goto fail; 2093 } 2094 2095 ifp->if_softc = sc; 2096 ifp->if_mtu = ETHERMTU; 2097 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2098 ifp->if_ioctl = dc_ioctl; 2099 ifp->if_start = dc_start; 2100 #ifdef IFPOLL_ENABLE 2101 ifp->if_npoll = dc_npoll; 2102 #endif 2103 ifp->if_watchdog = dc_watchdog; 2104 ifp->if_init = dc_init; 2105 ifp->if_baudrate = 10000000; 2106 ifq_set_maxlen(&ifp->if_snd, DC_TX_LIST_CNT - 1); 2107 ifq_set_ready(&ifp->if_snd); 2108 2109 /* 2110 * Do MII setup. If this is a 21143, check for a PHY on the 2111 * MII bus after applying any necessary fixups to twiddle the 2112 * GPIO bits. If we don't end up finding a PHY, restore the 2113 * old selection (SIA only or SIA/SYM) and attach the dcphy 2114 * driver instead. 2115 */ 2116 if (DC_IS_INTEL(sc)) { 2117 dc_apply_fixup(sc, IFM_AUTO); 2118 tmp = sc->dc_pmode; 2119 sc->dc_pmode = DC_PMODE_MII; 2120 } 2121 2122 /* 2123 * Setup General Purpose port mode and data so the tulip can talk 2124 * to the MII. This needs to be done before mii_phy_probe so that 2125 * we can actually see them. 2126 */ 2127 if (DC_IS_XIRCOM(sc)) { 2128 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 2129 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2130 DELAY(10); 2131 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 2132 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 2133 DELAY(10); 2134 } 2135 2136 error = mii_phy_probe(dev, &sc->dc_miibus, 2137 dc_ifmedia_upd, dc_ifmedia_sts); 2138 2139 if (error && DC_IS_INTEL(sc)) { 2140 sc->dc_pmode = tmp; 2141 if (sc->dc_pmode != DC_PMODE_SIA) 2142 sc->dc_pmode = DC_PMODE_SYM; 2143 sc->dc_flags |= DC_21143_NWAY; 2144 mii_phy_probe(dev, &sc->dc_miibus, 2145 dc_ifmedia_upd, dc_ifmedia_sts); 2146 /* 2147 * For non-MII cards, we need to have the 21143 2148 * drive the LEDs. Except there are some systems 2149 * like the NEC VersaPro NoteBook PC which have no 2150 * LEDs, and twiddling these bits has adverse effects 2151 * on them. (I.e. you suddenly can't get a link.) 2152 */ 2153 if (pci_read_config(dev, DC_PCI_CSID, 4) != 0x80281033) 2154 sc->dc_flags |= DC_TULIP_LEDS; 2155 error = 0; 2156 } 2157 2158 if (error) { 2159 device_printf(dev, "MII without any PHY!\n"); 2160 error = ENXIO; 2161 goto fail; 2162 } 2163 2164 /* 2165 * Call MI attach routine. 2166 */ 2167 ether_ifattach(ifp, eaddr, NULL); 2168 2169 #ifdef IFPOLL_ENABLE 2170 ifpoll_compat_setup(&sc->dc_npoll, NULL, NULL, device_get_unit(dev), 2171 ifp->if_serializer); 2172 #endif 2173 2174 if (DC_IS_ADMTEK(sc)) { 2175 /* 2176 * Set automatic TX underrun recovery for the ADMtek chips 2177 */ 2178 DC_SETBIT(sc, DC_AL_CR, DC_AL_CR_ATUR); 2179 } 2180 2181 /* 2182 * Tell the upper layer(s) we support long frames. 2183 */ 2184 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2185 2186 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->dc_irq)); 2187 2188 error = bus_setup_intr(dev, sc->dc_irq, INTR_MPSAFE, 2189 dc_intr, sc, &sc->dc_intrhand, 2190 ifp->if_serializer); 2191 if (error) { 2192 ether_ifdetach(ifp); 2193 device_printf(dev, "couldn't set up irq\n"); 2194 goto fail; 2195 } 2196 2197 return(0); 2198 2199 fail: 2200 dc_detach(dev); 2201 return(error); 2202 } 2203 2204 static int 2205 dc_detach(device_t dev) 2206 { 2207 struct dc_softc *sc = device_get_softc(dev); 2208 struct ifnet *ifp = &sc->arpcom.ac_if; 2209 struct dc_mediainfo *m; 2210 2211 if (device_is_attached(dev)) { 2212 lwkt_serialize_enter(ifp->if_serializer); 2213 dc_stop(sc); 2214 bus_teardown_intr(dev, sc->dc_irq, sc->dc_intrhand); 2215 lwkt_serialize_exit(ifp->if_serializer); 2216 2217 ether_ifdetach(ifp); 2218 } 2219 2220 if (sc->dc_miibus) 2221 device_delete_child(dev, sc->dc_miibus); 2222 bus_generic_detach(dev); 2223 2224 if (sc->dc_irq) 2225 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->dc_irq); 2226 if (sc->dc_res) 2227 bus_release_resource(dev, DC_RES, DC_RID, sc->dc_res); 2228 2229 if (sc->dc_ldata) 2230 contigfree(sc->dc_ldata, sizeof(struct dc_list_data), M_DEVBUF); 2231 if (sc->dc_pnic_rx_buf != NULL) 2232 kfree(sc->dc_pnic_rx_buf, M_DEVBUF); 2233 2234 while (sc->dc_mi != NULL) { 2235 m = sc->dc_mi->dc_next; 2236 kfree(sc->dc_mi, M_DEVBUF); 2237 sc->dc_mi = m; 2238 } 2239 2240 if (sc->dc_srom) 2241 kfree(sc->dc_srom, M_DEVBUF); 2242 2243 return(0); 2244 } 2245 2246 /* 2247 * Initialize the transmit descriptors. 2248 */ 2249 static int 2250 dc_list_tx_init(struct dc_softc *sc) 2251 { 2252 struct dc_chain_data *cd; 2253 struct dc_list_data *ld; 2254 int i; 2255 2256 cd = &sc->dc_cdata; 2257 ld = sc->dc_ldata; 2258 for (i = 0; i < DC_TX_LIST_CNT; i++) { 2259 if (i == (DC_TX_LIST_CNT - 1)) { 2260 ld->dc_tx_list[i].dc_next = 2261 vtophys(&ld->dc_tx_list[0]); 2262 } else { 2263 ld->dc_tx_list[i].dc_next = 2264 vtophys(&ld->dc_tx_list[i + 1]); 2265 } 2266 cd->dc_tx_chain[i] = NULL; 2267 ld->dc_tx_list[i].dc_data = 0; 2268 ld->dc_tx_list[i].dc_ctl = 0; 2269 } 2270 2271 cd->dc_tx_prod = cd->dc_tx_cons = cd->dc_tx_cnt = 0; 2272 2273 return(0); 2274 } 2275 2276 2277 /* 2278 * Initialize the RX descriptors and allocate mbufs for them. Note that 2279 * we arrange the descriptors in a closed ring, so that the last descriptor 2280 * points back to the first. 2281 */ 2282 static int 2283 dc_list_rx_init(struct dc_softc *sc) 2284 { 2285 struct dc_chain_data *cd; 2286 struct dc_list_data *ld; 2287 int i; 2288 2289 cd = &sc->dc_cdata; 2290 ld = sc->dc_ldata; 2291 2292 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2293 if (dc_newbuf(sc, i, NULL) == ENOBUFS) 2294 return(ENOBUFS); 2295 if (i == (DC_RX_LIST_CNT - 1)) { 2296 ld->dc_rx_list[i].dc_next = 2297 vtophys(&ld->dc_rx_list[0]); 2298 } else { 2299 ld->dc_rx_list[i].dc_next = 2300 vtophys(&ld->dc_rx_list[i + 1]); 2301 } 2302 } 2303 2304 cd->dc_rx_prod = 0; 2305 2306 return(0); 2307 } 2308 2309 /* 2310 * Initialize an RX descriptor and attach an MBUF cluster. 2311 */ 2312 static int 2313 dc_newbuf(struct dc_softc *sc, int i, struct mbuf *m) 2314 { 2315 struct mbuf *m_new = NULL; 2316 struct dc_desc *c; 2317 2318 c = &sc->dc_ldata->dc_rx_list[i]; 2319 2320 if (m == NULL) { 2321 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR); 2322 if (m_new == NULL) 2323 return (ENOBUFS); 2324 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2325 } else { 2326 m_new = m; 2327 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 2328 m_new->m_data = m_new->m_ext.ext_buf; 2329 } 2330 2331 m_adj(m_new, sizeof(u_int64_t)); 2332 2333 /* 2334 * If this is a PNIC chip, zero the buffer. This is part 2335 * of the workaround for the receive bug in the 82c168 and 2336 * 82c169 chips. 2337 */ 2338 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) 2339 bzero((char *)mtod(m_new, char *), m_new->m_len); 2340 2341 sc->dc_cdata.dc_rx_chain[i] = m_new; 2342 c->dc_data = vtophys(mtod(m_new, caddr_t)); 2343 c->dc_ctl = DC_RXCTL_RLINK | DC_RXLEN; 2344 c->dc_status = DC_RXSTAT_OWN; 2345 2346 return(0); 2347 } 2348 2349 /* 2350 * Grrrrr. 2351 * The PNIC chip has a terrible bug in it that manifests itself during 2352 * periods of heavy activity. The exact mode of failure if difficult to 2353 * pinpoint: sometimes it only happens in promiscuous mode, sometimes it 2354 * will happen on slow machines. The bug is that sometimes instead of 2355 * uploading one complete frame during reception, it uploads what looks 2356 * like the entire contents of its FIFO memory. The frame we want is at 2357 * the end of the whole mess, but we never know exactly how much data has 2358 * been uploaded, so salvaging the frame is hard. 2359 * 2360 * There is only one way to do it reliably, and it's disgusting. 2361 * Here's what we know: 2362 * 2363 * - We know there will always be somewhere between one and three extra 2364 * descriptors uploaded. 2365 * 2366 * - We know the desired received frame will always be at the end of the 2367 * total data upload. 2368 * 2369 * - We know the size of the desired received frame because it will be 2370 * provided in the length field of the status word in the last descriptor. 2371 * 2372 * Here's what we do: 2373 * 2374 * - When we allocate buffers for the receive ring, we bzero() them. 2375 * This means that we know that the buffer contents should be all 2376 * zeros, except for data uploaded by the chip. 2377 * 2378 * - We also force the PNIC chip to upload frames that include the 2379 * ethernet CRC at the end. 2380 * 2381 * - We gather all of the bogus frame data into a single buffer. 2382 * 2383 * - We then position a pointer at the end of this buffer and scan 2384 * backwards until we encounter the first non-zero byte of data. 2385 * This is the end of the received frame. We know we will encounter 2386 * some data at the end of the frame because the CRC will always be 2387 * there, so even if the sender transmits a packet of all zeros, 2388 * we won't be fooled. 2389 * 2390 * - We know the size of the actual received frame, so we subtract 2391 * that value from the current pointer location. This brings us 2392 * to the start of the actual received packet. 2393 * 2394 * - We copy this into an mbuf and pass it on, along with the actual 2395 * frame length. 2396 * 2397 * The performance hit is tremendous, but it beats dropping frames all 2398 * the time. 2399 */ 2400 2401 #define DC_WHOLEFRAME (DC_RXSTAT_FIRSTFRAG|DC_RXSTAT_LASTFRAG) 2402 static void 2403 dc_pnic_rx_bug_war(struct dc_softc *sc, int idx) 2404 { 2405 struct dc_desc *cur_rx; 2406 struct dc_desc *c = NULL; 2407 struct mbuf *m = NULL; 2408 unsigned char *ptr; 2409 int i, total_len; 2410 u_int32_t rxstat = 0; 2411 2412 i = sc->dc_pnic_rx_bug_save; 2413 cur_rx = &sc->dc_ldata->dc_rx_list[idx]; 2414 ptr = sc->dc_pnic_rx_buf; 2415 bzero(ptr, DC_RXLEN * 5); 2416 2417 /* Copy all the bytes from the bogus buffers. */ 2418 while (1) { 2419 c = &sc->dc_ldata->dc_rx_list[i]; 2420 rxstat = c->dc_status; 2421 m = sc->dc_cdata.dc_rx_chain[i]; 2422 bcopy(mtod(m, char *), ptr, DC_RXLEN); 2423 ptr += DC_RXLEN; 2424 /* If this is the last buffer, break out. */ 2425 if (i == idx || rxstat & DC_RXSTAT_LASTFRAG) 2426 break; 2427 dc_newbuf(sc, i, m); 2428 DC_INC(i, DC_RX_LIST_CNT); 2429 } 2430 2431 /* Find the length of the actual receive frame. */ 2432 total_len = DC_RXBYTES(rxstat); 2433 2434 /* Scan backwards until we hit a non-zero byte. */ 2435 while(*ptr == 0x00) 2436 ptr--; 2437 2438 /* Round off. */ 2439 if ((uintptr_t)(ptr) & 0x3) 2440 ptr -= 1; 2441 2442 /* Now find the start of the frame. */ 2443 ptr -= total_len; 2444 if (ptr < sc->dc_pnic_rx_buf) 2445 ptr = sc->dc_pnic_rx_buf; 2446 2447 /* 2448 * Now copy the salvaged frame to the last mbuf and fake up 2449 * the status word to make it look like a successful 2450 * frame reception. 2451 */ 2452 dc_newbuf(sc, i, m); 2453 bcopy(ptr, mtod(m, char *), total_len); 2454 cur_rx->dc_status = rxstat | DC_RXSTAT_FIRSTFRAG; 2455 2456 return; 2457 } 2458 2459 /* 2460 * This routine searches the RX ring for dirty descriptors in the 2461 * event that the rxeof routine falls out of sync with the chip's 2462 * current descriptor pointer. This may happen sometimes as a result 2463 * of a "no RX buffer available" condition that happens when the chip 2464 * consumes all of the RX buffers before the driver has a chance to 2465 * process the RX ring. This routine may need to be called more than 2466 * once to bring the driver back in sync with the chip, however we 2467 * should still be getting RX DONE interrupts to drive the search 2468 * for new packets in the RX ring, so we should catch up eventually. 2469 */ 2470 static int 2471 dc_rx_resync(struct dc_softc *sc) 2472 { 2473 int i, pos; 2474 struct dc_desc *cur_rx; 2475 2476 pos = sc->dc_cdata.dc_rx_prod; 2477 2478 for (i = 0; i < DC_RX_LIST_CNT; i++) { 2479 cur_rx = &sc->dc_ldata->dc_rx_list[pos]; 2480 if (!(cur_rx->dc_status & DC_RXSTAT_OWN)) 2481 break; 2482 DC_INC(pos, DC_RX_LIST_CNT); 2483 } 2484 2485 /* If the ring really is empty, then just return. */ 2486 if (i == DC_RX_LIST_CNT) 2487 return(0); 2488 2489 /* We've fallen behing the chip: catch it. */ 2490 sc->dc_cdata.dc_rx_prod = pos; 2491 2492 return(EAGAIN); 2493 } 2494 2495 /* 2496 * A frame has been uploaded: pass the resulting mbuf chain up to 2497 * the higher level protocols. 2498 */ 2499 static void 2500 dc_rxeof(struct dc_softc *sc) 2501 { 2502 struct mbuf *m; 2503 struct ifnet *ifp; 2504 struct dc_desc *cur_rx; 2505 int i, total_len = 0; 2506 u_int32_t rxstat; 2507 2508 ifp = &sc->arpcom.ac_if; 2509 i = sc->dc_cdata.dc_rx_prod; 2510 2511 while(!(sc->dc_ldata->dc_rx_list[i].dc_status & DC_RXSTAT_OWN)) { 2512 2513 #ifdef IFPOLL_ENABLE 2514 if (ifp->if_flags & IFF_NPOLLING) { 2515 if (sc->rxcycles <= 0) 2516 break; 2517 sc->rxcycles--; 2518 } 2519 #endif /* IFPOLL_ENABLE */ 2520 cur_rx = &sc->dc_ldata->dc_rx_list[i]; 2521 rxstat = cur_rx->dc_status; 2522 m = sc->dc_cdata.dc_rx_chain[i]; 2523 total_len = DC_RXBYTES(rxstat); 2524 2525 if (sc->dc_flags & DC_PNIC_RX_BUG_WAR) { 2526 if ((rxstat & DC_WHOLEFRAME) != DC_WHOLEFRAME) { 2527 if (rxstat & DC_RXSTAT_FIRSTFRAG) 2528 sc->dc_pnic_rx_bug_save = i; 2529 if ((rxstat & DC_RXSTAT_LASTFRAG) == 0) { 2530 DC_INC(i, DC_RX_LIST_CNT); 2531 continue; 2532 } 2533 dc_pnic_rx_bug_war(sc, i); 2534 rxstat = cur_rx->dc_status; 2535 total_len = DC_RXBYTES(rxstat); 2536 } 2537 } 2538 2539 sc->dc_cdata.dc_rx_chain[i] = NULL; 2540 2541 /* 2542 * If an error occurs, update stats, clear the 2543 * status word and leave the mbuf cluster in place: 2544 * it should simply get re-used next time this descriptor 2545 * comes up in the ring. However, don't report long 2546 * frames as errors since they could be vlans 2547 */ 2548 if ((rxstat & DC_RXSTAT_RXERR)){ 2549 if (!(rxstat & DC_RXSTAT_GIANT) || 2550 (rxstat & (DC_RXSTAT_CRCERR | DC_RXSTAT_DRIBBLE | 2551 DC_RXSTAT_MIIERE | DC_RXSTAT_COLLSEEN | 2552 DC_RXSTAT_RUNT | DC_RXSTAT_DE))) { 2553 IFNET_STAT_INC(ifp, ierrors, 1); 2554 if (rxstat & DC_RXSTAT_COLLSEEN) 2555 IFNET_STAT_INC(ifp, collisions, 1); 2556 dc_newbuf(sc, i, m); 2557 if (rxstat & DC_RXSTAT_CRCERR) { 2558 DC_INC(i, DC_RX_LIST_CNT); 2559 continue; 2560 } else { 2561 dc_init(sc); 2562 return; 2563 } 2564 } 2565 } 2566 2567 /* No errors; receive the packet. */ 2568 total_len -= ETHER_CRC_LEN; 2569 2570 #ifdef __i386__ 2571 /* 2572 * On the x86 we do not have alignment problems, so try to 2573 * allocate a new buffer for the receive ring, and pass up 2574 * the one where the packet is already, saving the expensive 2575 * copy done in m_devget(). 2576 * If we are on an architecture with alignment problems, or 2577 * if the allocation fails, then use m_devget and leave the 2578 * existing buffer in the receive ring. 2579 */ 2580 if (dc_quick && dc_newbuf(sc, i, NULL) == 0) { 2581 m->m_pkthdr.rcvif = ifp; 2582 m->m_pkthdr.len = m->m_len = total_len; 2583 DC_INC(i, DC_RX_LIST_CNT); 2584 } else 2585 #endif 2586 { 2587 struct mbuf *m0; 2588 2589 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 2590 total_len + ETHER_ALIGN, 0, ifp, NULL); 2591 dc_newbuf(sc, i, m); 2592 DC_INC(i, DC_RX_LIST_CNT); 2593 if (m0 == NULL) { 2594 IFNET_STAT_INC(ifp, ierrors, 1); 2595 continue; 2596 } 2597 m_adj(m0, ETHER_ALIGN); 2598 m = m0; 2599 } 2600 2601 IFNET_STAT_INC(ifp, ipackets, 1); 2602 ifp->if_input(ifp, m); 2603 } 2604 2605 sc->dc_cdata.dc_rx_prod = i; 2606 } 2607 2608 /* 2609 * A frame was downloaded to the chip. It's safe for us to clean up 2610 * the list buffers. 2611 */ 2612 2613 static void 2614 dc_txeof(struct dc_softc *sc) 2615 { 2616 struct dc_desc *cur_tx = NULL; 2617 struct ifnet *ifp; 2618 int idx; 2619 2620 ifp = &sc->arpcom.ac_if; 2621 2622 /* 2623 * Go through our tx list and free mbufs for those 2624 * frames that have been transmitted. 2625 */ 2626 idx = sc->dc_cdata.dc_tx_cons; 2627 while(idx != sc->dc_cdata.dc_tx_prod) { 2628 u_int32_t txstat; 2629 2630 cur_tx = &sc->dc_ldata->dc_tx_list[idx]; 2631 txstat = cur_tx->dc_status; 2632 2633 if (txstat & DC_TXSTAT_OWN) 2634 break; 2635 2636 if (!(cur_tx->dc_ctl & DC_TXCTL_LASTFRAG) || 2637 cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2638 if (cur_tx->dc_ctl & DC_TXCTL_SETUP) { 2639 /* 2640 * Yes, the PNIC is so brain damaged 2641 * that it will sometimes generate a TX 2642 * underrun error while DMAing the RX 2643 * filter setup frame. If we detect this, 2644 * we have to send the setup frame again, 2645 * or else the filter won't be programmed 2646 * correctly. 2647 */ 2648 if (DC_IS_PNIC(sc)) { 2649 if (txstat & DC_TXSTAT_ERRSUM) 2650 dc_setfilt(sc); 2651 } 2652 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2653 } 2654 sc->dc_cdata.dc_tx_cnt--; 2655 DC_INC(idx, DC_TX_LIST_CNT); 2656 continue; 2657 } 2658 2659 if (DC_IS_XIRCOM(sc) || DC_IS_CONEXANT(sc)) { 2660 /* 2661 * XXX: Why does my Xircom taunt me so? 2662 * For some reason Conexant chips like 2663 * setting the CARRLOST flag even when 2664 * the carrier is there. In CURRENT we 2665 * have the same problem for Xircom 2666 * cards ! 2667 */ 2668 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2669 sc->dc_pmode == DC_PMODE_MII && 2670 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2671 DC_TXSTAT_NOCARRIER))) 2672 txstat &= ~DC_TXSTAT_ERRSUM; 2673 } else { 2674 if (/*sc->dc_type == DC_TYPE_21143 &&*/ 2675 sc->dc_pmode == DC_PMODE_MII && 2676 ((txstat & 0xFFFF) & ~(DC_TXSTAT_ERRSUM| 2677 DC_TXSTAT_NOCARRIER|DC_TXSTAT_CARRLOST))) 2678 txstat &= ~DC_TXSTAT_ERRSUM; 2679 } 2680 2681 if (txstat & DC_TXSTAT_ERRSUM) { 2682 IFNET_STAT_INC(ifp, oerrors, 1); 2683 if (txstat & DC_TXSTAT_EXCESSCOLL) 2684 IFNET_STAT_INC(ifp, collisions, 1); 2685 if (txstat & DC_TXSTAT_LATECOLL) 2686 IFNET_STAT_INC(ifp, collisions, 1); 2687 if (!(txstat & DC_TXSTAT_UNDERRUN)) { 2688 dc_init(sc); 2689 return; 2690 } 2691 } 2692 2693 IFNET_STAT_INC(ifp, collisions, 2694 (txstat & DC_TXSTAT_COLLCNT) >> 3); 2695 2696 IFNET_STAT_INC(ifp, opackets, 1); 2697 if (sc->dc_cdata.dc_tx_chain[idx] != NULL) { 2698 m_freem(sc->dc_cdata.dc_tx_chain[idx]); 2699 sc->dc_cdata.dc_tx_chain[idx] = NULL; 2700 } 2701 2702 sc->dc_cdata.dc_tx_cnt--; 2703 DC_INC(idx, DC_TX_LIST_CNT); 2704 } 2705 2706 if (idx != sc->dc_cdata.dc_tx_cons) { 2707 /* some buffers have been freed */ 2708 sc->dc_cdata.dc_tx_cons = idx; 2709 ifq_clr_oactive(&ifp->if_snd); 2710 } 2711 ifp->if_timer = (sc->dc_cdata.dc_tx_cnt == 0) ? 0 : 5; 2712 2713 return; 2714 } 2715 2716 static void 2717 dc_tick(void *xsc) 2718 { 2719 struct dc_softc *sc = xsc; 2720 struct ifnet *ifp = &sc->arpcom.ac_if; 2721 struct mii_data *mii; 2722 u_int32_t r; 2723 2724 lwkt_serialize_enter(ifp->if_serializer); 2725 2726 mii = device_get_softc(sc->dc_miibus); 2727 2728 if (sc->dc_flags & DC_REDUCED_MII_POLL) { 2729 if (sc->dc_flags & DC_21143_NWAY) { 2730 r = CSR_READ_4(sc, DC_10BTSTAT); 2731 if (IFM_SUBTYPE(mii->mii_media_active) == 2732 IFM_100_TX && (r & DC_TSTAT_LS100)) { 2733 sc->dc_link = 0; 2734 mii_mediachg(mii); 2735 } 2736 if (IFM_SUBTYPE(mii->mii_media_active) == 2737 IFM_10_T && (r & DC_TSTAT_LS10)) { 2738 sc->dc_link = 0; 2739 mii_mediachg(mii); 2740 } 2741 if (sc->dc_link == 0) 2742 mii_tick(mii); 2743 } else { 2744 r = CSR_READ_4(sc, DC_ISR); 2745 if ((r & DC_ISR_RX_STATE) == DC_RXSTATE_WAIT && 2746 sc->dc_cdata.dc_tx_cnt == 0) { 2747 mii_tick(mii); 2748 if (!(mii->mii_media_status & IFM_ACTIVE)) 2749 sc->dc_link = 0; 2750 } 2751 } 2752 } else { 2753 mii_tick(mii); 2754 } 2755 2756 /* 2757 * When the init routine completes, we expect to be able to send 2758 * packets right away, and in fact the network code will send a 2759 * gratuitous ARP the moment the init routine marks the interface 2760 * as running. However, even though the MAC may have been initialized, 2761 * there may be a delay of a few seconds before the PHY completes 2762 * autonegotiation and the link is brought up. Any transmissions 2763 * made during that delay will be lost. Dealing with this is tricky: 2764 * we can't just pause in the init routine while waiting for the 2765 * PHY to come ready since that would bring the whole system to 2766 * a screeching halt for several seconds. 2767 * 2768 * What we do here is prevent the TX start routine from sending 2769 * any packets until a link has been established. After the 2770 * interface has been initialized, the tick routine will poll 2771 * the state of the PHY until the IFM_ACTIVE flag is set. Until 2772 * that time, packets will stay in the send queue, and once the 2773 * link comes up, they will be flushed out to the wire. 2774 */ 2775 if (!sc->dc_link) { 2776 mii_pollstat(mii); 2777 if (mii->mii_media_status & IFM_ACTIVE && 2778 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2779 sc->dc_link++; 2780 if (!ifq_is_empty(&ifp->if_snd)) 2781 if_devstart(ifp); 2782 } 2783 } 2784 2785 if (sc->dc_flags & DC_21143_NWAY && !sc->dc_link) 2786 callout_reset(&sc->dc_stat_timer, hz / 10, dc_tick, sc); 2787 else 2788 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 2789 2790 lwkt_serialize_exit(ifp->if_serializer); 2791 } 2792 2793 /* 2794 * A transmit underrun has occurred. Back off the transmit threshold, 2795 * or switch to store and forward mode if we have to. 2796 */ 2797 static void 2798 dc_tx_underrun(struct dc_softc *sc) 2799 { 2800 u_int32_t isr; 2801 int i; 2802 2803 if (DC_IS_DAVICOM(sc)) 2804 dc_init(sc); 2805 2806 if (DC_IS_INTEL(sc)) { 2807 /* 2808 * The real 21143 requires that the transmitter be idle 2809 * in order to change the transmit threshold or store 2810 * and forward state. 2811 */ 2812 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2813 2814 for (i = 0; i < DC_TIMEOUT; i++) { 2815 isr = CSR_READ_4(sc, DC_ISR); 2816 if (isr & DC_ISR_TX_IDLE) 2817 break; 2818 DELAY(10); 2819 } 2820 if (i == DC_TIMEOUT) { 2821 if_printf(&sc->arpcom.ac_if, 2822 "failed to force tx to idle state\n"); 2823 dc_init(sc); 2824 } 2825 } 2826 2827 if_printf(&sc->arpcom.ac_if, "TX underrun -- "); 2828 sc->dc_txthresh += DC_TXTHRESH_INC; 2829 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 2830 kprintf("using store and forward mode\n"); 2831 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 2832 } else { 2833 kprintf("increasing TX threshold\n"); 2834 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 2835 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 2836 } 2837 2838 if (DC_IS_INTEL(sc)) 2839 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2840 2841 return; 2842 } 2843 2844 #ifdef IFPOLL_ENABLE 2845 2846 static void 2847 dc_npoll_compat(struct ifnet *ifp, void *arg __unused, int count) 2848 { 2849 struct dc_softc *sc = ifp->if_softc; 2850 2851 ASSERT_SERIALIZED(ifp->if_serializer); 2852 2853 sc->rxcycles = count; 2854 dc_rxeof(sc); 2855 dc_txeof(sc); 2856 if (!ifq_is_empty(&ifp->if_snd)) 2857 if_devstart(ifp); 2858 2859 if (sc->dc_npoll.ifpc_stcount-- == 0) { 2860 uint32_t status; 2861 2862 sc->dc_npoll.ifpc_stcount = sc->dc_npoll.ifpc_stfrac; 2863 2864 status = CSR_READ_4(sc, DC_ISR); 2865 status &= (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF| 2866 DC_ISR_TX_NOBUF|DC_ISR_TX_IDLE|DC_ISR_TX_UNDERRUN| 2867 DC_ISR_BUS_ERR); 2868 if (!status) 2869 return; 2870 /* ack what we have */ 2871 CSR_WRITE_4(sc, DC_ISR, status); 2872 2873 if (status & (DC_ISR_RX_WATDOGTIMEO|DC_ISR_RX_NOBUF) ) { 2874 u_int32_t r = CSR_READ_4(sc, DC_FRAMESDISCARDED); 2875 IFNET_STAT_INC(ifp, ierrors, 2876 (r & 0xffff) + ((r >> 17) & 0x7ff)); 2877 2878 if (dc_rx_resync(sc)) 2879 dc_rxeof(sc); 2880 } 2881 /* restart transmit unit if necessary */ 2882 if (status & DC_ISR_TX_IDLE && sc->dc_cdata.dc_tx_cnt) 2883 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2884 2885 if (status & DC_ISR_TX_UNDERRUN) 2886 dc_tx_underrun(sc); 2887 2888 if (status & DC_ISR_BUS_ERR) { 2889 if_printf(ifp, "dc_poll: bus error\n"); 2890 dc_reset(sc); 2891 dc_init(sc); 2892 } 2893 } 2894 } 2895 2896 static void 2897 dc_npoll(struct ifnet *ifp, struct ifpoll_info *info) 2898 { 2899 struct dc_softc *sc = ifp->if_softc; 2900 2901 ASSERT_SERIALIZED(ifp->if_serializer); 2902 2903 if (info != NULL) { 2904 int cpuid = sc->dc_npoll.ifpc_cpuid; 2905 2906 info->ifpi_rx[cpuid].poll_func = dc_npoll_compat; 2907 info->ifpi_rx[cpuid].arg = NULL; 2908 info->ifpi_rx[cpuid].serializer = ifp->if_serializer; 2909 2910 if (ifp->if_flags & IFF_RUNNING) { 2911 /* Disable interrupts */ 2912 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2913 sc->dc_npoll.ifpc_stcount = 0; 2914 } 2915 ifq_set_cpuid(&ifp->if_snd, cpuid); 2916 } else { 2917 if (ifp->if_flags & IFF_RUNNING) { 2918 /* Re-enable interrupts. */ 2919 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 2920 } 2921 ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->dc_irq)); 2922 } 2923 } 2924 2925 #endif /* IFPOLL_ENABLE */ 2926 2927 static void 2928 dc_intr(void *arg) 2929 { 2930 struct dc_softc *sc; 2931 struct ifnet *ifp; 2932 u_int32_t status; 2933 2934 sc = arg; 2935 2936 if (sc->suspended) { 2937 return; 2938 } 2939 2940 ifp = &sc->arpcom.ac_if; 2941 2942 if ( (CSR_READ_4(sc, DC_ISR) & DC_INTRS) == 0) 2943 return ; 2944 2945 /* Suppress unwanted interrupts */ 2946 if ((ifp->if_flags & IFF_RUNNING) == 0) { 2947 if (CSR_READ_4(sc, DC_ISR) & DC_INTRS) 2948 dc_stop(sc); 2949 return; 2950 } 2951 2952 /* Disable interrupts. */ 2953 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 2954 2955 while(((status = CSR_READ_4(sc, DC_ISR)) & DC_INTRS) && 2956 status != 0xFFFFFFFF) { 2957 2958 CSR_WRITE_4(sc, DC_ISR, status); 2959 2960 if (status & DC_ISR_RX_OK) { 2961 u_long curpkts, ncurpkts; 2962 2963 IFNET_STAT_GET(ifp, ipackets, curpkts); 2964 dc_rxeof(sc); 2965 IFNET_STAT_GET(ifp, ipackets, ncurpkts); 2966 2967 if (curpkts == ncurpkts) { 2968 while(dc_rx_resync(sc)) 2969 dc_rxeof(sc); 2970 } 2971 } 2972 2973 if (status & (DC_ISR_TX_OK|DC_ISR_TX_NOBUF)) 2974 dc_txeof(sc); 2975 2976 if (status & DC_ISR_TX_IDLE) { 2977 dc_txeof(sc); 2978 if (sc->dc_cdata.dc_tx_cnt) { 2979 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 2980 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 2981 } 2982 } 2983 2984 if (status & DC_ISR_TX_UNDERRUN) 2985 dc_tx_underrun(sc); 2986 2987 if ((status & DC_ISR_RX_WATDOGTIMEO) 2988 || (status & DC_ISR_RX_NOBUF)) { 2989 u_long curpkts, ncurpkts; 2990 2991 IFNET_STAT_GET(ifp, ipackets, curpkts); 2992 dc_rxeof(sc); 2993 IFNET_STAT_GET(ifp, ipackets, ncurpkts); 2994 2995 if (curpkts == ncurpkts) { 2996 while(dc_rx_resync(sc)) 2997 dc_rxeof(sc); 2998 } 2999 } 3000 3001 if (status & DC_ISR_BUS_ERR) { 3002 dc_reset(sc); 3003 dc_init(sc); 3004 } 3005 } 3006 3007 /* Re-enable interrupts. */ 3008 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3009 3010 if (!ifq_is_empty(&ifp->if_snd)) 3011 if_devstart(ifp); 3012 } 3013 3014 /* 3015 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 3016 * pointers to the fragment pointers. 3017 */ 3018 static int 3019 dc_encap(struct dc_softc *sc, struct mbuf *m_head, u_int32_t *txidx) 3020 { 3021 struct dc_desc *f = NULL; 3022 struct mbuf *m; 3023 int frag, cur, cnt = 0; 3024 3025 /* 3026 * Start packing the mbufs in this chain into 3027 * the fragment pointers. Stop when we run out 3028 * of fragments or hit the end of the mbuf chain. 3029 */ 3030 m = m_head; 3031 cur = frag = *txidx; 3032 3033 for (m = m_head; m != NULL; m = m->m_next) { 3034 if (m->m_len != 0) { 3035 if (sc->dc_flags & DC_TX_ADMTEK_WAR) { 3036 if (*txidx != sc->dc_cdata.dc_tx_prod && 3037 frag == (DC_TX_LIST_CNT - 1)) 3038 return(ENOBUFS); 3039 } 3040 if ((DC_TX_LIST_CNT - 3041 (sc->dc_cdata.dc_tx_cnt + cnt)) < 5) 3042 return(ENOBUFS); 3043 3044 f = &sc->dc_ldata->dc_tx_list[frag]; 3045 f->dc_ctl = DC_TXCTL_TLINK | m->m_len; 3046 if (cnt == 0) { 3047 f->dc_status = 0; 3048 f->dc_ctl |= DC_TXCTL_FIRSTFRAG; 3049 } else 3050 f->dc_status = DC_TXSTAT_OWN; 3051 f->dc_data = vtophys(mtod(m, vm_offset_t)); 3052 cur = frag; 3053 DC_INC(frag, DC_TX_LIST_CNT); 3054 cnt++; 3055 } 3056 } 3057 3058 if (m != NULL) 3059 return(ENOBUFS); 3060 3061 sc->dc_cdata.dc_tx_cnt += cnt; 3062 sc->dc_cdata.dc_tx_chain[cur] = m_head; 3063 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_LASTFRAG; 3064 if (sc->dc_flags & DC_TX_INTR_FIRSTFRAG) 3065 sc->dc_ldata->dc_tx_list[*txidx].dc_ctl |= DC_TXCTL_FINT; 3066 if (sc->dc_flags & DC_TX_INTR_ALWAYS) 3067 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3068 if (sc->dc_flags & DC_TX_USE_TX_INTR && sc->dc_cdata.dc_tx_cnt > 64) 3069 sc->dc_ldata->dc_tx_list[cur].dc_ctl |= DC_TXCTL_FINT; 3070 sc->dc_ldata->dc_tx_list[*txidx].dc_status = DC_TXSTAT_OWN; 3071 *txidx = frag; 3072 3073 return(0); 3074 } 3075 3076 /* 3077 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3078 * to the mbuf data regions directly in the transmit lists. We also save a 3079 * copy of the pointers since the transmit list fragment pointers are 3080 * physical addresses. 3081 */ 3082 3083 static void 3084 dc_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 3085 { 3086 struct dc_softc *sc; 3087 struct mbuf *m_head, *m_defragged; 3088 int idx, need_trans; 3089 3090 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 3091 sc = ifp->if_softc; 3092 3093 if (!sc->dc_link) { 3094 ifq_purge(&ifp->if_snd); 3095 return; 3096 } 3097 3098 if (ifq_is_oactive(&ifp->if_snd)) 3099 return; 3100 3101 idx = sc->dc_cdata.dc_tx_prod; 3102 3103 need_trans = 0; 3104 while(sc->dc_cdata.dc_tx_chain[idx] == NULL) { 3105 m_defragged = NULL; 3106 m_head = ifq_dequeue(&ifp->if_snd); 3107 if (m_head == NULL) 3108 break; 3109 3110 if ((sc->dc_flags & DC_TX_COALESCE) && 3111 (m_head->m_next != NULL || (sc->dc_flags & DC_TX_ALIGN))) { 3112 /* 3113 * Check first if coalescing allows us to queue 3114 * the packet. We don't want to loose it if 3115 * the TX queue is full. 3116 */ 3117 if ((sc->dc_flags & DC_TX_ADMTEK_WAR) && 3118 idx != sc->dc_cdata.dc_tx_prod && 3119 idx == (DC_TX_LIST_CNT - 1)) { 3120 ifq_set_oactive(&ifp->if_snd); 3121 ifq_prepend(&ifp->if_snd, m_head); 3122 break; 3123 } 3124 if ((DC_TX_LIST_CNT - sc->dc_cdata.dc_tx_cnt) < 5) { 3125 ifq_set_oactive(&ifp->if_snd); 3126 ifq_prepend(&ifp->if_snd, m_head); 3127 break; 3128 } 3129 3130 /* only coalesce if have >1 mbufs */ 3131 m_defragged = m_defrag(m_head, MB_DONTWAIT); 3132 if (m_defragged == NULL) { 3133 ifq_set_oactive(&ifp->if_snd); 3134 ifq_prepend(&ifp->if_snd, m_head); 3135 break; 3136 } 3137 m_head = m_defragged; 3138 } 3139 3140 if (dc_encap(sc, m_head, &idx)) { 3141 if (m_defragged) { 3142 /* 3143 * Throw away the original packet if the 3144 * defragged packet could not be encapsulated, 3145 * as well as the defragged packet. 3146 */ 3147 m_freem(m_head); 3148 } else { 3149 ifq_prepend(&ifp->if_snd, m_head); 3150 } 3151 ifq_set_oactive(&ifp->if_snd); 3152 break; 3153 } 3154 3155 need_trans = 1; 3156 3157 /* 3158 * If there's a BPF listener, bounce a copy of this frame 3159 * to him. 3160 */ 3161 BPF_MTAP(ifp, m_head); 3162 3163 if (sc->dc_flags & DC_TX_ONE) { 3164 ifq_set_oactive(&ifp->if_snd); 3165 break; 3166 } 3167 } 3168 3169 if (!need_trans) 3170 return; 3171 3172 /* Transmit */ 3173 sc->dc_cdata.dc_tx_prod = idx; 3174 if (!(sc->dc_flags & DC_TX_POLL)) 3175 CSR_WRITE_4(sc, DC_TXSTART, 0xFFFFFFFF); 3176 3177 /* 3178 * Set a timeout in case the chip goes out to lunch. 3179 */ 3180 ifp->if_timer = 5; 3181 } 3182 3183 static void 3184 dc_init(void *xsc) 3185 { 3186 struct dc_softc *sc = xsc; 3187 struct ifnet *ifp = &sc->arpcom.ac_if; 3188 struct mii_data *mii; 3189 3190 mii = device_get_softc(sc->dc_miibus); 3191 3192 /* 3193 * Cancel pending I/O and free all RX/TX buffers. 3194 */ 3195 dc_stop(sc); 3196 dc_reset(sc); 3197 3198 /* 3199 * Set cache alignment and burst length. 3200 */ 3201 if (DC_IS_ASIX(sc) || DC_IS_DAVICOM(sc)) 3202 CSR_WRITE_4(sc, DC_BUSCTL, 0); 3203 else 3204 CSR_WRITE_4(sc, DC_BUSCTL, DC_BUSCTL_MRME|DC_BUSCTL_MRLE); 3205 /* 3206 * Evenly share the bus between receive and transmit process. 3207 */ 3208 if (DC_IS_INTEL(sc)) 3209 DC_SETBIT(sc, DC_BUSCTL, DC_BUSCTL_ARBITRATION); 3210 if (DC_IS_DAVICOM(sc) || DC_IS_INTEL(sc)) { 3211 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_USECA); 3212 } else { 3213 DC_SETBIT(sc, DC_BUSCTL, DC_BURSTLEN_16LONG); 3214 } 3215 if (sc->dc_flags & DC_TX_POLL) 3216 DC_SETBIT(sc, DC_BUSCTL, DC_TXPOLL_1); 3217 switch(sc->dc_cachesize) { 3218 case 32: 3219 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_32LONG); 3220 break; 3221 case 16: 3222 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_16LONG); 3223 break; 3224 case 8: 3225 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_8LONG); 3226 break; 3227 case 0: 3228 default: 3229 DC_SETBIT(sc, DC_BUSCTL, DC_CACHEALIGN_NONE); 3230 break; 3231 } 3232 3233 if (sc->dc_flags & DC_TX_STORENFWD) 3234 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3235 else { 3236 if (sc->dc_txthresh > DC_TXTHRESH_MAX) { 3237 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3238 } else { 3239 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_STORENFWD); 3240 DC_SETBIT(sc, DC_NETCFG, sc->dc_txthresh); 3241 } 3242 } 3243 3244 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_NO_RXCRC); 3245 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_BACKOFF); 3246 3247 if (DC_IS_MACRONIX(sc) || DC_IS_PNICII(sc)) { 3248 /* 3249 * The app notes for the 98713 and 98715A say that 3250 * in order to have the chips operate properly, a magic 3251 * number must be written to CSR16. Macronix does not 3252 * document the meaning of these bits so there's no way 3253 * to know exactly what they do. The 98713 has a magic 3254 * number all its own; the rest all use a different one. 3255 */ 3256 DC_CLRBIT(sc, DC_MX_MAGICPACKET, 0xFFFF0000); 3257 if (sc->dc_type == DC_TYPE_98713) 3258 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98713); 3259 else 3260 DC_SETBIT(sc, DC_MX_MAGICPACKET, DC_MX_MAGIC_98715); 3261 } 3262 3263 if (DC_IS_XIRCOM(sc)) { 3264 /* 3265 * Setup General Purpose Port mode and data so the tulip 3266 * can talk to the MII. 3267 */ 3268 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_WRITE_EN | DC_SIAGP_INT1_EN | 3269 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3270 DELAY(10); 3271 CSR_WRITE_4(sc, DC_SIAGP, DC_SIAGP_INT1_EN | 3272 DC_SIAGP_MD_GP2_OUTPUT | DC_SIAGP_MD_GP0_OUTPUT); 3273 DELAY(10); 3274 } 3275 3276 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_TX_THRESH); 3277 DC_SETBIT(sc, DC_NETCFG, DC_TXTHRESH_MIN); 3278 3279 /* Init circular RX list. */ 3280 if (dc_list_rx_init(sc) == ENOBUFS) { 3281 if_printf(ifp, "initialization failed: no " 3282 "memory for rx buffers\n"); 3283 dc_stop(sc); 3284 return; 3285 } 3286 3287 /* 3288 * Init tx descriptors. 3289 */ 3290 dc_list_tx_init(sc); 3291 3292 /* 3293 * Load the address of the RX list. 3294 */ 3295 CSR_WRITE_4(sc, DC_RXADDR, vtophys(&sc->dc_ldata->dc_rx_list[0])); 3296 CSR_WRITE_4(sc, DC_TXADDR, vtophys(&sc->dc_ldata->dc_tx_list[0])); 3297 3298 /* 3299 * Enable interrupts. 3300 */ 3301 #ifdef IFPOLL_ENABLE 3302 /* 3303 * ... but only if we are not polling, and make sure they are off in 3304 * the case of polling. Some cards (e.g. fxp) turn interrupts on 3305 * after a reset. 3306 */ 3307 if (ifp->if_flags & IFF_NPOLLING) { 3308 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3309 sc->dc_npoll.ifpc_stcount = 0; 3310 } else 3311 #endif 3312 CSR_WRITE_4(sc, DC_IMR, DC_INTRS); 3313 CSR_WRITE_4(sc, DC_ISR, 0xFFFFFFFF); 3314 3315 /* Enable transmitter. */ 3316 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_TX_ON); 3317 3318 /* 3319 * If this is an Intel 21143 and we're not using the 3320 * MII port, program the LED control pins so we get 3321 * link and activity indications. 3322 */ 3323 if (sc->dc_flags & DC_TULIP_LEDS) { 3324 CSR_WRITE_4(sc, DC_WATCHDOG, 3325 DC_WDOG_CTLWREN|DC_WDOG_LINK|DC_WDOG_ACTIVITY); 3326 CSR_WRITE_4(sc, DC_WATCHDOG, 0); 3327 } 3328 3329 /* 3330 * Set IFF_RUNNING here to keep the assertion in dc_setfilt() 3331 * working. 3332 */ 3333 ifp->if_flags |= IFF_RUNNING; 3334 ifq_clr_oactive(&ifp->if_snd); 3335 3336 /* 3337 * Load the RX/multicast filter. We do this sort of late 3338 * because the filter programming scheme on the 21143 and 3339 * some clones requires DMAing a setup frame via the TX 3340 * engine, and we need the transmitter enabled for that. 3341 */ 3342 dc_setfilt(sc); 3343 3344 /* Enable receiver. */ 3345 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_RX_ON); 3346 CSR_WRITE_4(sc, DC_RXSTART, 0xFFFFFFFF); 3347 3348 mii_mediachg(mii); 3349 dc_setcfg(sc, sc->dc_if_media); 3350 3351 /* Don't start the ticker if this is a homePNA link. */ 3352 if (IFM_SUBTYPE(mii->mii_media.ifm_media) == IFM_HPNA_1) 3353 sc->dc_link = 1; 3354 else { 3355 if (sc->dc_flags & DC_21143_NWAY) 3356 callout_reset(&sc->dc_stat_timer, hz/10, dc_tick, sc); 3357 else 3358 callout_reset(&sc->dc_stat_timer, hz, dc_tick, sc); 3359 } 3360 } 3361 3362 /* 3363 * Set media options. 3364 */ 3365 static int 3366 dc_ifmedia_upd(struct ifnet *ifp) 3367 { 3368 struct dc_softc *sc; 3369 struct mii_data *mii; 3370 struct ifmedia *ifm; 3371 3372 sc = ifp->if_softc; 3373 mii = device_get_softc(sc->dc_miibus); 3374 mii_mediachg(mii); 3375 ifm = &mii->mii_media; 3376 3377 if (DC_IS_DAVICOM(sc) && 3378 IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) 3379 dc_setcfg(sc, ifm->ifm_media); 3380 else 3381 sc->dc_link = 0; 3382 3383 return(0); 3384 } 3385 3386 /* 3387 * Report current media status. 3388 */ 3389 static void 3390 dc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3391 { 3392 struct dc_softc *sc; 3393 struct mii_data *mii; 3394 struct ifmedia *ifm; 3395 3396 sc = ifp->if_softc; 3397 mii = device_get_softc(sc->dc_miibus); 3398 mii_pollstat(mii); 3399 ifm = &mii->mii_media; 3400 if (DC_IS_DAVICOM(sc)) { 3401 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_HPNA_1) { 3402 ifmr->ifm_active = ifm->ifm_media; 3403 ifmr->ifm_status = 0; 3404 return; 3405 } 3406 } 3407 ifmr->ifm_active = mii->mii_media_active; 3408 ifmr->ifm_status = mii->mii_media_status; 3409 3410 return; 3411 } 3412 3413 static int 3414 dc_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 3415 { 3416 struct dc_softc *sc = ifp->if_softc; 3417 struct ifreq *ifr = (struct ifreq *) data; 3418 struct mii_data *mii; 3419 int error = 0; 3420 3421 switch(command) { 3422 case SIOCSIFFLAGS: 3423 if (ifp->if_flags & IFF_UP) { 3424 int need_setfilt = (ifp->if_flags ^ sc->dc_if_flags) & 3425 (IFF_PROMISC | IFF_ALLMULTI); 3426 if (ifp->if_flags & IFF_RUNNING) { 3427 if (need_setfilt) 3428 dc_setfilt(sc); 3429 } else { 3430 sc->dc_txthresh = 0; 3431 dc_init(sc); 3432 } 3433 } else { 3434 if (ifp->if_flags & IFF_RUNNING) 3435 dc_stop(sc); 3436 } 3437 sc->dc_if_flags = ifp->if_flags; 3438 break; 3439 case SIOCADDMULTI: 3440 case SIOCDELMULTI: 3441 if (ifp->if_flags & IFF_RUNNING) 3442 dc_setfilt(sc); 3443 break; 3444 case SIOCGIFMEDIA: 3445 case SIOCSIFMEDIA: 3446 mii = device_get_softc(sc->dc_miibus); 3447 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3448 break; 3449 default: 3450 error = ether_ioctl(ifp, command, data); 3451 break; 3452 } 3453 3454 return(error); 3455 } 3456 3457 static void 3458 dc_watchdog(struct ifnet *ifp) 3459 { 3460 struct dc_softc *sc; 3461 3462 sc = ifp->if_softc; 3463 3464 IFNET_STAT_INC(ifp, oerrors, 1); 3465 if_printf(ifp, "watchdog timeout\n"); 3466 3467 dc_stop(sc); 3468 dc_reset(sc); 3469 dc_init(sc); 3470 3471 if (!ifq_is_empty(&ifp->if_snd)) 3472 if_devstart(ifp); 3473 } 3474 3475 /* 3476 * Stop the adapter and free any mbufs allocated to the 3477 * RX and TX lists. 3478 */ 3479 static void 3480 dc_stop(struct dc_softc *sc) 3481 { 3482 int i; 3483 struct ifnet *ifp; 3484 3485 ifp = &sc->arpcom.ac_if; 3486 ifp->if_timer = 0; 3487 3488 callout_stop(&sc->dc_stat_timer); 3489 3490 ifp->if_flags &= ~IFF_RUNNING; 3491 ifq_clr_oactive(&ifp->if_snd); 3492 3493 DC_CLRBIT(sc, DC_NETCFG, (DC_NETCFG_RX_ON|DC_NETCFG_TX_ON)); 3494 CSR_WRITE_4(sc, DC_IMR, 0x00000000); 3495 CSR_WRITE_4(sc, DC_TXADDR, 0x00000000); 3496 CSR_WRITE_4(sc, DC_RXADDR, 0x00000000); 3497 sc->dc_link = 0; 3498 3499 /* 3500 * Free data in the RX lists. 3501 */ 3502 for (i = 0; i < DC_RX_LIST_CNT; i++) { 3503 if (sc->dc_cdata.dc_rx_chain[i] != NULL) { 3504 m_freem(sc->dc_cdata.dc_rx_chain[i]); 3505 sc->dc_cdata.dc_rx_chain[i] = NULL; 3506 } 3507 } 3508 bzero((char *)&sc->dc_ldata->dc_rx_list, 3509 sizeof(sc->dc_ldata->dc_rx_list)); 3510 3511 /* 3512 * Free the TX list buffers. 3513 */ 3514 for (i = 0; i < DC_TX_LIST_CNT; i++) { 3515 if (sc->dc_cdata.dc_tx_chain[i] != NULL) { 3516 if ((sc->dc_ldata->dc_tx_list[i].dc_ctl & 3517 DC_TXCTL_SETUP) || 3518 !(sc->dc_ldata->dc_tx_list[i].dc_ctl & 3519 DC_TXCTL_LASTFRAG)) { 3520 sc->dc_cdata.dc_tx_chain[i] = NULL; 3521 continue; 3522 } 3523 m_freem(sc->dc_cdata.dc_tx_chain[i]); 3524 sc->dc_cdata.dc_tx_chain[i] = NULL; 3525 } 3526 } 3527 bzero((char *)&sc->dc_ldata->dc_tx_list, 3528 sizeof(sc->dc_ldata->dc_tx_list)); 3529 } 3530 3531 /* 3532 * Stop all chip I/O so that the kernel's probe routines don't 3533 * get confused by errant DMAs when rebooting. 3534 */ 3535 static void 3536 dc_shutdown(device_t dev) 3537 { 3538 struct dc_softc *sc; 3539 struct ifnet *ifp; 3540 3541 sc = device_get_softc(dev); 3542 ifp = &sc->arpcom.ac_if; 3543 lwkt_serialize_enter(ifp->if_serializer); 3544 3545 dc_stop(sc); 3546 3547 lwkt_serialize_exit(ifp->if_serializer); 3548 } 3549 3550 /* 3551 * Device suspend routine. Stop the interface and save some PCI 3552 * settings in case the BIOS doesn't restore them properly on 3553 * resume. 3554 */ 3555 static int 3556 dc_suspend(device_t dev) 3557 { 3558 struct dc_softc *sc = device_get_softc(dev); 3559 struct ifnet *ifp = &sc->arpcom.ac_if; 3560 int i; 3561 lwkt_serialize_enter(ifp->if_serializer); 3562 3563 dc_stop(sc); 3564 for (i = 0; i < 5; i++) 3565 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4); 3566 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4); 3567 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1); 3568 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1); 3569 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1); 3570 3571 sc->suspended = 1; 3572 3573 lwkt_serialize_exit(ifp->if_serializer); 3574 return (0); 3575 } 3576 3577 /* 3578 * Device resume routine. Restore some PCI settings in case the BIOS 3579 * doesn't, re-enable busmastering, and restart the interface if 3580 * appropriate. 3581 */ 3582 static int 3583 dc_resume(device_t dev) 3584 { 3585 struct dc_softc *sc = device_get_softc(dev); 3586 struct ifnet *ifp = &sc->arpcom.ac_if; 3587 int i; 3588 3589 lwkt_serialize_enter(ifp->if_serializer); 3590 dc_acpi(dev); 3591 3592 /* better way to do this? */ 3593 for (i = 0; i < 5; i++) 3594 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4); 3595 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4); 3596 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1); 3597 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1); 3598 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1); 3599 3600 /* reenable busmastering */ 3601 pci_enable_busmaster(dev); 3602 pci_enable_io(dev, DC_RES); 3603 3604 /* reinitialize interface if necessary */ 3605 if (ifp->if_flags & IFF_UP) 3606 dc_init(sc); 3607 3608 sc->suspended = 0; 3609 lwkt_serialize_exit(ifp->if_serializer); 3610 3611 return (0); 3612 } 3613 3614 static uint32_t 3615 dc_mchash_xircom(struct dc_softc *sc, const uint8_t *addr) 3616 { 3617 uint32_t crc; 3618 3619 /* Compute CRC for the address value. */ 3620 crc = ether_crc32_le(addr, ETHER_ADDR_LEN); 3621 3622 if ((crc & 0x180) == 0x180) 3623 return ((crc & 0x0F) + (crc & 0x70) * 3 + (14 << 4)); 3624 else 3625 return ((crc & 0x1F) + ((crc >> 1) & 0xF0) * 3 + (12 << 4)); 3626 }
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