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sys/dev/netif/ed/if_ed.c
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1 /* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.224 2003/12/08 07:54:12 obrien Exp $ 28 */ 29 30 /* 31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 32 * adapters. By David Greenman, 29-April-1993 33 * 34 * Currently supports the Western Digital/SMC 8003 and 8013 series, 35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 36 * and a variety of similar clones. 37 * 38 */ 39 40 #include "opt_ed.h" 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/sockio.h> 45 #include <sys/mbuf.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/syslog.h> 49 #include <sys/module.h> 50 #include <sys/bus.h> 51 #include <sys/rman.h> 52 #include <sys/thread2.h> 53 #include <sys/machintr.h> 54 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/ifq_var.h> 58 #include <net/if_arp.h> 59 #include <net/if_dl.h> 60 #include <net/if_mib.h> 61 #include <net/if_media.h> 62 63 #ifndef ED_NO_MIIBUS 64 #include <dev/netif/mii_layer/mii.h> 65 #include <dev/netif/mii_layer/miivar.h> 66 #endif 67 68 #include <net/bpf.h> 69 70 #include <machine/md_var.h> 71 72 #include "if_edreg.h" 73 #include "if_edvar.h" 74 75 devclass_t ed_devclass; 76 77 static void ed_init (void *); 78 static int ed_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *); 79 static void ed_start (struct ifnet *, struct ifaltq_subque *); 80 static void ed_reset (struct ifnet *); 81 static void ed_watchdog (struct ifnet *); 82 #ifndef ED_NO_MIIBUS 83 static void ed_tick (void *); 84 #endif 85 86 static void ds_getmcaf (struct ed_softc *, u_int32_t *); 87 88 static void ed_get_packet (struct ed_softc *, char *, u_short); 89 90 static __inline void ed_rint (struct ed_softc *); 91 static __inline void ed_xmit (struct ed_softc *); 92 static __inline char * ed_ring_copy (struct ed_softc *, char *, char *, 93 u_short); 94 static void ed_hpp_set_physical_link (struct ed_softc *); 95 static void ed_hpp_readmem (struct ed_softc *, u_short, u_char *, u_short); 96 static void ed_hpp_writemem (struct ed_softc *, u_char *, u_short, u_short); 97 static u_short ed_hpp_write_mbufs (struct ed_softc *, struct mbuf *, int); 98 99 static u_short ed_pio_write_mbufs (struct ed_softc *, struct mbuf *, int); 100 101 static void ed_setrcr (struct ed_softc *); 102 103 static uint32_t ds_mchash (const uint8_t *); 104 105 DECLARE_DUMMY_MODULE(if_ed); 106 107 /* 108 * Interrupt conversion table for WD/SMC ASIC/83C584 109 */ 110 static u_short ed_intr_val[] = { 111 9, 112 3, 113 5, 114 7, 115 10, 116 11, 117 15, 118 4 119 }; 120 121 /* 122 * Interrupt conversion table for 83C790 123 */ 124 static u_short ed_790_intr_val[] = { 125 0, 126 9, 127 3, 128 5, 129 7, 130 10, 131 11, 132 15 133 }; 134 135 /* 136 * Interrupt conversion table for the HP PC LAN+ 137 */ 138 139 static u_short ed_hpp_intr_val[] = { 140 0, /* 0 */ 141 0, /* 1 */ 142 0, /* 2 */ 143 3, /* 3 */ 144 4, /* 4 */ 145 5, /* 5 */ 146 6, /* 6 */ 147 7, /* 7 */ 148 0, /* 8 */ 149 9, /* 9 */ 150 10, /* 10 */ 151 11, /* 11 */ 152 12, /* 12 */ 153 0, /* 13 */ 154 0, /* 14 */ 155 15 /* 15 */ 156 }; 157 158 /* 159 * Generic probe routine for testing for the existance of a DS8390. 160 * Must be called after the NIC has just been reset. This routine 161 * works by looking at certain register values that are guaranteed 162 * to be initialized a certain way after power-up or reset. Seems 163 * not to currently work on the 83C690. 164 * 165 * Specifically: 166 * 167 * Register reset bits set bits 168 * Command Register (CR) TXP, STA RD2, STP 169 * Interrupt Status (ISR) RST 170 * Interrupt Mask (IMR) All bits 171 * Data Control (DCR) LAS 172 * Transmit Config. (TCR) LB1, LB0 173 * 174 * We only look at the CR and ISR registers, however, because looking at 175 * the others would require changing register pages (which would be 176 * intrusive if this isn't an 8390). 177 * 178 * Return 1 if 8390 was found, 0 if not. 179 */ 180 181 int 182 ed_probe_generic8390(struct ed_softc *sc) 183 { 184 if ((ed_nic_inb(sc, ED_P0_CR) & 185 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 186 (ED_CR_RD2 | ED_CR_STP)) 187 return (0); 188 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 189 return (0); 190 191 return (1); 192 } 193 194 /* 195 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 196 */ 197 int 198 ed_probe_WD80x3_generic(device_t dev, int flags, u_short *intr_vals[]) 199 { 200 struct ed_softc *sc = device_get_softc(dev); 201 int error; 202 int i; 203 u_int memsize, maddr; 204 u_char iptr, isa16bit, sum, totalsum; 205 u_long conf_maddr, conf_msize, irq, junk; 206 207 sc->chip_type = ED_CHIP_TYPE_DP8390; 208 209 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) { 210 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER; 211 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW); 212 DELAY(10000); 213 } 214 else 215 totalsum = ED_WD_ROM_CHECKSUM_TOTAL; 216 217 /* 218 * Attempt to do a checksum over the station address PROM. If it 219 * fails, it's probably not a SMC/WD board. There is a problem with 220 * this, though: some clone WD boards don't pass the checksum test. 221 * Danpex boards for one. 222 */ 223 for (sum = 0, i = 0; i < 8; ++i) 224 sum += ed_asic_inb(sc, ED_WD_PROM + i); 225 226 if (sum != totalsum) { 227 228 /* 229 * Checksum is invalid. This often happens with cheap WD8003E 230 * clones. In this case, the checksum byte (the eighth byte) 231 * seems to always be zero. 232 */ 233 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E || 234 ed_asic_inb(sc, ED_WD_PROM + 7) != 0) 235 return (ENXIO); 236 } 237 /* reset card to force it into a known state. */ 238 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) 239 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 240 else 241 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST); 242 243 DELAY(100); 244 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST); 245 /* wait in the case this card is reading its EEROM */ 246 DELAY(5000); 247 248 sc->vendor = ED_VENDOR_WD_SMC; 249 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID); 250 251 /* 252 * Set initial values for width/size. 253 */ 254 memsize = 8192; 255 isa16bit = 0; 256 switch (sc->type) { 257 case ED_TYPE_WD8003S: 258 sc->type_str = "WD8003S"; 259 break; 260 case ED_TYPE_WD8003E: 261 sc->type_str = "WD8003E"; 262 break; 263 case ED_TYPE_WD8003EB: 264 sc->type_str = "WD8003EB"; 265 break; 266 case ED_TYPE_WD8003W: 267 sc->type_str = "WD8003W"; 268 break; 269 case ED_TYPE_WD8013EBT: 270 sc->type_str = "WD8013EBT"; 271 memsize = 16384; 272 isa16bit = 1; 273 break; 274 case ED_TYPE_WD8013W: 275 sc->type_str = "WD8013W"; 276 memsize = 16384; 277 isa16bit = 1; 278 break; 279 case ED_TYPE_WD8013EP: /* also WD8003EP */ 280 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) { 281 isa16bit = 1; 282 memsize = 16384; 283 sc->type_str = "WD8013EP"; 284 } else { 285 sc->type_str = "WD8003EP"; 286 } 287 break; 288 case ED_TYPE_WD8013WC: 289 sc->type_str = "WD8013WC"; 290 memsize = 16384; 291 isa16bit = 1; 292 break; 293 case ED_TYPE_WD8013EBP: 294 sc->type_str = "WD8013EBP"; 295 memsize = 16384; 296 isa16bit = 1; 297 break; 298 case ED_TYPE_WD8013EPC: 299 sc->type_str = "WD8013EPC"; 300 memsize = 16384; 301 isa16bit = 1; 302 break; 303 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 304 case ED_TYPE_SMC8216T: 305 if (sc->type == ED_TYPE_SMC8216C) { 306 sc->type_str = "SMC8216/SMC8216C"; 307 } else { 308 sc->type_str = "SMC8216T"; 309 } 310 311 ed_asic_outb(sc, ED_WD790_HWR, 312 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH); 313 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 314 case ED_WD790_RAR_SZ64: 315 memsize = 65536; 316 break; 317 case ED_WD790_RAR_SZ32: 318 memsize = 32768; 319 break; 320 case ED_WD790_RAR_SZ16: 321 memsize = 16384; 322 break; 323 case ED_WD790_RAR_SZ8: 324 /* 8216 has 16K shared mem -- 8416 has 8K */ 325 if (sc->type == ED_TYPE_SMC8216C) { 326 sc->type_str = "SMC8416C/SMC8416BT"; 327 } else { 328 sc->type_str = "SMC8416T"; 329 } 330 memsize = 8192; 331 break; 332 } 333 ed_asic_outb(sc, ED_WD790_HWR, 334 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 335 336 isa16bit = 1; 337 sc->chip_type = ED_CHIP_TYPE_WD790; 338 break; 339 case ED_TYPE_TOSHIBA1: 340 sc->type_str = "Toshiba1"; 341 memsize = 32768; 342 isa16bit = 1; 343 break; 344 case ED_TYPE_TOSHIBA4: 345 sc->type_str = "Toshiba4"; 346 memsize = 32768; 347 isa16bit = 1; 348 break; 349 default: 350 sc->type_str = ""; 351 break; 352 } 353 354 /* 355 * Make some adjustments to initial values depending on what is found 356 * in the ICR. 357 */ 358 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 359 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 360 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 361 isa16bit = 0; 362 memsize = 8192; 363 } 364 365 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 366 &conf_maddr, &conf_msize); 367 if (error) 368 return (error); 369 370 #ifdef ED_DEBUG 371 kprintf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 372 sc->type, sc->type_str, isa16bit, memsize, conf_msize); 373 for (i = 0; i < 8; i++) 374 kprintf("%x -> %x\n", i, ed_asic_inb(sc, i)); 375 #endif 376 377 /* 378 * Allow the user to override the autoconfiguration 379 */ 380 if (conf_msize > 1) 381 memsize = conf_msize; 382 383 maddr = conf_maddr; 384 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) { 385 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n", 386 maddr, maddr + memsize); 387 return (ENXIO); 388 } 389 390 /* 391 * (note that if the user specifies both of the following flags that 392 * '8bit' mode intentionally has precedence) 393 */ 394 if (flags & ED_FLAGS_FORCE_16BIT_MODE) 395 isa16bit = 1; 396 if (flags & ED_FLAGS_FORCE_8BIT_MODE) 397 isa16bit = 0; 398 399 /* 400 * If possible, get the assigned interrupt number from the card and 401 * use it. 402 */ 403 if ((sc->type & ED_WD_SOFTCONFIG) && 404 (sc->chip_type != ED_CHIP_TYPE_WD790)) { 405 406 /* 407 * Assemble together the encoded interrupt number. 408 */ 409 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) | 410 ((ed_asic_inb(sc, ED_WD_IRR) & 411 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 412 413 /* 414 * If no interrupt specified (or "?"), use what the board tells us. 415 */ 416 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 417 &irq, &junk); 418 if (error && intr_vals[0] != NULL) { 419 int intr_val = intr_vals[0][iptr]; 420 421 error = bus_set_resource(dev, SYS_RES_IRQ, 0, 422 intr_val, 1, machintr_legacy_intr_cpuid(intr_val)); 423 } 424 if (error) 425 return (error); 426 427 /* 428 * Enable the interrupt. 429 */ 430 ed_asic_outb(sc, ED_WD_IRR, 431 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN); 432 } 433 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 434 ed_asic_outb(sc, ED_WD790_HWR, 435 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH); 436 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 437 (ed_asic_inb(sc, ED_WD790_GCR) & 438 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 439 ed_asic_outb(sc, ED_WD790_HWR, 440 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 441 442 /* 443 * If no interrupt specified (or "?"), use what the board tells us. 444 */ 445 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 446 &irq, &junk); 447 if (error && intr_vals[1] != NULL) { 448 int intr_val = intr_vals[1][iptr]; 449 450 error = bus_set_resource(dev, SYS_RES_IRQ, 0, 451 intr_val, 1, machintr_legacy_intr_cpuid(intr_val)); 452 } 453 if (error) 454 return (error); 455 456 /* 457 * Enable interrupts. 458 */ 459 ed_asic_outb(sc, ED_WD790_ICR, 460 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL); 461 } 462 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 463 &irq, &junk); 464 if (error) { 465 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n", 466 sc->type_str); 467 return (ENXIO); 468 } 469 sc->isa16bit = isa16bit; 470 sc->mem_shared = 1; 471 472 error = ed_alloc_memory(dev, 0, memsize); 473 if (error) { 474 kprintf("*** ed_alloc_memory() failed! (%d)\n", error); 475 return (error); 476 } 477 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 478 479 /* 480 * allocate one xmit buffer if < 16k, two buffers otherwise 481 */ 482 if ((memsize < 16384) || 483 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 484 sc->txb_cnt = 1; 485 } else { 486 sc->txb_cnt = 2; 487 } 488 sc->tx_page_start = ED_WD_PAGE_OFFSET; 489 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 490 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 491 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 492 sc->mem_size = memsize; 493 sc->mem_end = sc->mem_start + memsize; 494 495 /* 496 * Get station address from on-board ROM 497 */ 498 for (i = 0; i < ETHER_ADDR_LEN; ++i) 499 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i); 500 501 /* 502 * Set upper address bits and 8/16 bit access to shared memory. 503 */ 504 if (isa16bit) { 505 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 506 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR); 507 } else { 508 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 509 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 510 } 511 /* 512 * Enable 16bit access 513 */ 514 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto | 515 ED_WD_LAAR_M16EN); 516 } else { 517 if (((sc->type & ED_WD_SOFTCONFIG) || 518 (sc->type == ED_TYPE_TOSHIBA1) || 519 (sc->type == ED_TYPE_TOSHIBA4) || 520 (sc->type == ED_TYPE_WD8013EBT)) && 521 (sc->chip_type != ED_CHIP_TYPE_WD790)) { 522 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 523 ED_WD_LAAR_ADDRHI; 524 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto); 525 } 526 } 527 528 /* 529 * Set address and enable interface shared memory. 530 */ 531 if (sc->chip_type != ED_CHIP_TYPE_WD790) { 532 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) { 533 ed_asic_outb(sc, ED_WD_MSR + 1, 534 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 535 ed_asic_outb(sc, ED_WD_MSR + 2, 536 ((kvtop(sc->mem_start) >> 16) & 0x0f)); 537 ed_asic_outb(sc, ED_WD_MSR, 538 ED_WD_MSR_MENB | ED_WD_MSR_POW); 539 } else { 540 ed_asic_outb(sc, ED_WD_MSR, 541 ((kvtop(sc->mem_start) >> 13) & 542 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 543 } 544 sc->cr_proto = ED_CR_RD2; 545 } else { 546 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 547 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH)); 548 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 549 ((kvtop(sc->mem_start) >> 11) & 0x40) | 550 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0)); 551 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 552 sc->cr_proto = 0; 553 } 554 555 #if 0 556 kprintf("starting memory performance test at 0x%x, size %d...\n", 557 sc->mem_start, memsize*16384); 558 for (i = 0; i < 16384; i++) 559 bzero(sc->mem_start, memsize); 560 kprintf("***DONE***\n"); 561 #endif 562 563 /* 564 * Now zero memory and verify that it is clear 565 */ 566 bzero(sc->mem_start, memsize); 567 568 for (i = 0; i < memsize; ++i) { 569 if (sc->mem_start[i]) { 570 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n", 571 (long long)kvtop(sc->mem_start + i)); 572 573 /* 574 * Disable 16 bit access to shared memory 575 */ 576 if (isa16bit) { 577 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 578 ed_asic_outb(sc, ED_WD_MSR, 0x00); 579 } 580 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto & 581 ~ED_WD_LAAR_M16EN); 582 } 583 return (ENXIO); 584 } 585 } 586 587 /* 588 * Disable 16bit access to shared memory - we leave it 589 * disabled so that 1) machines reboot properly when the board 590 * is set 16 bit mode and there are conflicting 8bit 591 * devices/ROMS in the same 128k address space as this boards 592 * shared memory. and 2) so that other 8 bit devices with 593 * shared memory can be used in this 128k region, too. 594 */ 595 if (isa16bit) { 596 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 597 ed_asic_outb(sc, ED_WD_MSR, 0x00); 598 } 599 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto & 600 ~ED_WD_LAAR_M16EN); 601 } 602 return (0); 603 } 604 605 int 606 ed_probe_WD80x3(device_t dev, int port_rid, int flags) 607 { 608 struct ed_softc *sc = device_get_softc(dev); 609 int error; 610 static u_short *intr_vals[] = {ed_intr_val, ed_790_intr_val}; 611 612 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS); 613 if (error) 614 return (error); 615 616 sc->asic_offset = ED_WD_ASIC_OFFSET; 617 sc->nic_offset = ED_WD_NIC_OFFSET; 618 619 return ed_probe_WD80x3_generic(dev, flags, intr_vals); 620 } 621 622 /* 623 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 624 */ 625 int 626 ed_probe_3Com(device_t dev, int port_rid, int flags) 627 { 628 struct ed_softc *sc = device_get_softc(dev); 629 int error; 630 int i; 631 u_int memsize; 632 u_char isa16bit; 633 u_long conf_maddr, conf_msize, irq, junk; 634 635 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS); 636 if (error) 637 return (error); 638 639 sc->asic_offset = ED_3COM_ASIC_OFFSET; 640 sc->nic_offset = ED_3COM_NIC_OFFSET; 641 642 /* 643 * Verify that the kernel configured I/O address matches the board 644 * configured address 645 */ 646 switch (ed_asic_inb(sc, ED_3COM_BCFR)) { 647 case ED_3COM_BCFR_300: 648 if (rman_get_start(sc->port_res) != 0x300) 649 return (ENXIO); 650 break; 651 case ED_3COM_BCFR_310: 652 if (rman_get_start(sc->port_res) != 0x310) 653 return (ENXIO); 654 break; 655 case ED_3COM_BCFR_330: 656 if (rman_get_start(sc->port_res) != 0x330) 657 return (ENXIO); 658 break; 659 case ED_3COM_BCFR_350: 660 if (rman_get_start(sc->port_res) != 0x350) 661 return (ENXIO); 662 break; 663 case ED_3COM_BCFR_250: 664 if (rman_get_start(sc->port_res) != 0x250) 665 return (ENXIO); 666 break; 667 case ED_3COM_BCFR_280: 668 if (rman_get_start(sc->port_res) != 0x280) 669 return (ENXIO); 670 break; 671 case ED_3COM_BCFR_2A0: 672 if (rman_get_start(sc->port_res) != 0x2a0) 673 return (ENXIO); 674 break; 675 case ED_3COM_BCFR_2E0: 676 if (rman_get_start(sc->port_res) != 0x2e0) 677 return (ENXIO); 678 break; 679 default: 680 return (ENXIO); 681 } 682 683 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 684 &conf_maddr, &conf_msize); 685 if (error) 686 return (error); 687 688 /* 689 * Verify that the kernel shared memory address matches the board 690 * configured address. 691 */ 692 switch (ed_asic_inb(sc, ED_3COM_PCFR)) { 693 case ED_3COM_PCFR_DC000: 694 if (conf_maddr != 0xdc000) 695 return (ENXIO); 696 break; 697 case ED_3COM_PCFR_D8000: 698 if (conf_maddr != 0xd8000) 699 return (ENXIO); 700 break; 701 case ED_3COM_PCFR_CC000: 702 if (conf_maddr != 0xcc000) 703 return (ENXIO); 704 break; 705 case ED_3COM_PCFR_C8000: 706 if (conf_maddr != 0xc8000) 707 return (ENXIO); 708 break; 709 default: 710 return (ENXIO); 711 } 712 713 714 /* 715 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 716 * sequence because it'll lock up if the cable isn't connected if we 717 * don't. 718 */ 719 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 720 721 /* 722 * Wait for a while, then un-reset it 723 */ 724 DELAY(50); 725 726 /* 727 * The 3Com ASIC defaults to rather strange settings for the CR after 728 * a reset - it's important to set it again after the following outb 729 * (this is done when we map the PROM below). 730 */ 731 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 732 733 /* 734 * Wait a bit for the NIC to recover from the reset 735 */ 736 DELAY(5000); 737 738 sc->vendor = ED_VENDOR_3COM; 739 sc->type_str = "3c503"; 740 sc->mem_shared = 1; 741 sc->cr_proto = ED_CR_RD2; 742 743 /* 744 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 745 * to it. 746 */ 747 memsize = 8192; 748 749 /* 750 * Get station address from on-board ROM 751 */ 752 753 /* 754 * First, map ethernet address PROM over the top of where the NIC 755 * registers normally appear. 756 */ 757 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 758 759 for (i = 0; i < ETHER_ADDR_LEN; ++i) 760 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i); 761 762 /* 763 * Unmap PROM - select NIC registers. The proper setting of the 764 * tranceiver is set in ed_init so that the attach code is given a 765 * chance to set the default based on a compile-time config option 766 */ 767 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 768 769 /* 770 * Determine if this is an 8bit or 16bit board 771 */ 772 773 /* 774 * select page 0 registers 775 */ 776 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 777 778 /* 779 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 780 * board. 781 */ 782 ed_nic_outb(sc, ED_P0_DCR, 0); 783 784 /* 785 * select page 2 registers 786 */ 787 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 788 789 /* 790 * The 3c503 forces the WTS bit to a one if this is a 16bit board 791 */ 792 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS) 793 isa16bit = 1; 794 else 795 isa16bit = 0; 796 797 /* 798 * select page 0 registers 799 */ 800 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 801 802 error = ed_alloc_memory(dev, 0, memsize); 803 if (error) 804 return (error); 805 806 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 807 sc->mem_size = memsize; 808 sc->mem_end = sc->mem_start + memsize; 809 810 /* 811 * We have an entire 8k window to put the transmit buffers on the 812 * 16bit boards. But since the 16bit 3c503's shared memory is only 813 * fast enough to overlap the loading of one full-size packet, trying 814 * to load more than 2 buffers can actually leave the transmitter idle 815 * during the load. So 2 seems the best value. (Although a mix of 816 * variable-sized packets might change this assumption. Nonetheless, 817 * we optimize for linear transfers of same-size packets.) 818 */ 819 if (isa16bit) { 820 if (flags & ED_FLAGS_NO_MULTI_BUFFERING) 821 sc->txb_cnt = 1; 822 else 823 sc->txb_cnt = 2; 824 825 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 826 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 827 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 828 ED_3COM_RX_PAGE_OFFSET_16BIT; 829 sc->mem_ring = sc->mem_start; 830 } else { 831 sc->txb_cnt = 1; 832 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 833 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 834 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 835 ED_3COM_TX_PAGE_OFFSET_8BIT; 836 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 837 } 838 839 sc->isa16bit = isa16bit; 840 841 /* 842 * Initialize GA page start/stop registers. Probably only needed if 843 * doing DMA, but what the hell. 844 */ 845 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start); 846 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop); 847 848 /* 849 * Set IRQ. 3c503 only allows a choice of irq 2-5. 850 */ 851 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk); 852 if (error) 853 return (error); 854 855 switch (irq) { 856 case 2: 857 case 9: 858 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 859 break; 860 case 3: 861 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 862 break; 863 case 4: 864 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 865 break; 866 case 5: 867 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 868 break; 869 default: 870 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n", 871 irq); 872 return (ENXIO); 873 } 874 875 /* 876 * Initialize GA configuration register. Set bank and enable shared 877 * mem. 878 */ 879 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 880 ED_3COM_GACFR_MBS0); 881 882 /* 883 * Initialize "Vector Pointer" registers. These gawd-awful things are 884 * compared to 20 bits of the address on ISA, and if they match, the 885 * shared memory is disabled. We set them to 0xffff0...allegedly the 886 * reset vector. 887 */ 888 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff); 889 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff); 890 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00); 891 892 /* 893 * Zero memory and verify that it is clear 894 */ 895 bzero(sc->mem_start, memsize); 896 897 for (i = 0; i < memsize; ++i) 898 if (sc->mem_start[i]) { 899 device_printf(dev, "failed to clear shared memory " 900 "at %llx - check configuration\n", 901 (unsigned long long)kvtop(sc->mem_start + i)); 902 return (ENXIO); 903 } 904 return (0); 905 } 906 907 /* 908 * Probe and vendor-specific initialization routine for SIC boards 909 */ 910 int 911 ed_probe_SIC(device_t dev, int port_rid, int flags) 912 { 913 struct ed_softc *sc = device_get_softc(dev); 914 int error; 915 int i; 916 u_int memsize; 917 u_long conf_maddr, conf_msize; 918 u_char sum; 919 #ifdef ED_DEBUG 920 char ethstr[ETHER_ADDRSTRLEN + 1]; 921 #endif 922 923 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS); 924 if (error) 925 return (error); 926 927 sc->asic_offset = ED_SIC_ASIC_OFFSET; 928 sc->nic_offset = ED_SIC_NIC_OFFSET; 929 930 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 931 &conf_maddr, &conf_msize); 932 if (error) 933 return (error); 934 935 memsize = 16384; 936 if (conf_msize > 1) 937 memsize = conf_msize; 938 939 error = ed_alloc_memory(dev, 0, memsize); 940 if (error) 941 return (error); 942 943 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res); 944 sc->mem_size = memsize; 945 946 /* Reset card to force it into a known state. */ 947 ed_asic_outb(sc, 0, 0x00); 948 DELAY(100); 949 950 /* 951 * Here we check the card ROM, if the checksum passes, and the 952 * type code and ethernet address check out, then we know we have 953 * an SIC card. 954 */ 955 ed_asic_outb(sc, 0, 0x81); 956 DELAY(100); 957 958 sum = sc->mem_start[6]; 959 for (i = 0; i < ETHER_ADDR_LEN; i++) { 960 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]); 961 } 962 #ifdef ED_DEBUG 963 device_printf(dev, "ed_probe_sic: got address %s\n", 964 kether_ntoa(sc->arpcom.ac_enaddr, ethstr)); 965 #endif 966 if (sum != 0) { 967 return (ENXIO); 968 } 969 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] | 970 sc->arpcom.ac_enaddr[2]) == 0) { 971 return (ENXIO); 972 } 973 974 sc->vendor = ED_VENDOR_SIC; 975 sc->type_str = "SIC"; 976 sc->isa16bit = 0; 977 sc->cr_proto = 0; 978 979 /* 980 * SIC RAM page 0x0000-0x3fff(or 0x7fff) 981 */ 982 ed_asic_outb(sc, 0, 0x80); 983 DELAY(100); 984 985 /* 986 * Now zero memory and verify that it is clear 987 */ 988 bzero(sc->mem_start, sc->mem_size); 989 990 for (i = 0; i < sc->mem_size; i++) { 991 if (sc->mem_start[i]) { 992 device_printf(dev, "failed to clear shared memory " 993 "at %llx - check configuration\n", 994 (long long)kvtop(sc->mem_start + i)); 995 996 return (ENXIO); 997 } 998 } 999 1000 sc->mem_shared = 1; 1001 sc->mem_end = sc->mem_start + sc->mem_size; 1002 1003 /* 1004 * allocate one xmit buffer if < 16k, two buffers otherwise 1005 */ 1006 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 1007 sc->txb_cnt = 1; 1008 } else { 1009 sc->txb_cnt = 2; 1010 } 1011 sc->tx_page_start = 0; 1012 1013 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt; 1014 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE; 1015 1016 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1017 1018 return (0); 1019 } 1020 1021 /* 1022 * Probe and vendor-specific initialization routine for NE1000/2000 boards 1023 */ 1024 int 1025 ed_probe_Novell_generic(device_t dev, int flags) 1026 { 1027 struct ed_softc *sc = device_get_softc(dev); 1028 u_int memsize, n; 1029 u_char romdata[16], tmp; 1030 static char test_pattern[32] = "THIS is A memory TEST pattern"; 1031 char test_buffer[32]; 1032 1033 /* XXX - do Novell-specific probe here */ 1034 1035 /* Reset the board */ 1036 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) { 1037 ed_asic_outb(sc, ED_NOVELL_RESET, 0); 1038 DELAY(200); 1039 } 1040 tmp = ed_asic_inb(sc, ED_NOVELL_RESET); 1041 1042 /* 1043 * I don't know if this is necessary; probably cruft leftover from 1044 * Clarkson packet driver code. Doesn't do a thing on the boards I've 1045 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is 1046 * non-invasive...but some boards don't seem to reset and I don't have 1047 * complete documentation on what the 'right' thing to do is...so we 1048 * do the invasive thing for now. Yuck.] 1049 */ 1050 ed_asic_outb(sc, ED_NOVELL_RESET, tmp); 1051 DELAY(5000); 1052 1053 /* 1054 * This is needed because some NE clones apparently don't reset the 1055 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 1056 * - this makes the probe invasive! ...Done against my better 1057 * judgement. -DLG 1058 */ 1059 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 1060 1061 DELAY(5000); 1062 1063 /* Make sure that we really have an 8390 based board */ 1064 if (!ed_probe_generic8390(sc)) 1065 return (ENXIO); 1066 1067 sc->vendor = ED_VENDOR_NOVELL; 1068 sc->mem_shared = 0; 1069 sc->cr_proto = ED_CR_RD2; 1070 1071 /* 1072 * Test the ability to read and write to the NIC memory. This has the 1073 * side affect of determining if this is an NE1000 or an NE2000. 1074 */ 1075 1076 /* 1077 * This prevents packets from being stored in the NIC memory when the 1078 * readmem routine turns on the start bit in the CR. 1079 */ 1080 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 1081 1082 /* Temporarily initialize DCR for byte operations */ 1083 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1084 1085 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1086 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1087 1088 sc->isa16bit = 0; 1089 1090 /* 1091 * Write a test pattern in byte mode. If this fails, then there 1092 * probably isn't any memory at 8k - which likely means that the board 1093 * is an NE2000. 1094 */ 1095 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1096 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1097 1098 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { 1099 sc->type = ED_TYPE_NE1000; 1100 sc->type_str = "NE1000"; 1101 } else { 1102 1103 /* neither an NE1000 nor a Linksys - try NE2000 */ 1104 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1105 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1106 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1107 1108 sc->isa16bit = 1; 1109 1110 /* 1111 * Write a test pattern in word mode. If this also fails, then 1112 * we don't know what this board is. 1113 */ 1114 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1115 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1116 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) { 1117 sc->type = ED_TYPE_NE2000; 1118 sc->type_str = "NE2000"; 1119 } else { 1120 return (ENXIO); 1121 } 1122 } 1123 1124 1125 /* 8k of memory plus an additional 8k if 16bit */ 1126 memsize = 8192 + sc->isa16bit * 8192; 1127 1128 #if 0 /* probably not useful - NE boards only come two ways */ 1129 /* allow kernel config file overrides */ 1130 if (isa_dev->id_msize) 1131 memsize = isa_dev->id_msize; 1132 #endif 1133 1134 sc->mem_size = memsize; 1135 1136 /* NIC memory doesn't start at zero on an NE board */ 1137 /* The start address is tied to the bus width */ 1138 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1139 sc->mem_end = sc->mem_start + memsize; 1140 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1141 1142 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) { 1143 int x, i, mstart = 0, msize = 0; 1144 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1145 1146 for (i = 0; i < ED_PAGE_SIZE; i++) 1147 pbuf0[i] = 0; 1148 1149 /* Clear all the memory. */ 1150 for (x = 1; x < 256; x++) 1151 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1152 1153 /* Search for the start of RAM. */ 1154 for (x = 1; x < 256; x++) { 1155 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1156 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1157 for (i = 0; i < ED_PAGE_SIZE; i++) 1158 pbuf[i] = 255 - x; 1159 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1160 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1161 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1162 mstart = x * ED_PAGE_SIZE; 1163 msize = ED_PAGE_SIZE; 1164 break; 1165 } 1166 } 1167 } 1168 1169 if (mstart == 0) { 1170 device_printf(dev, "Cannot find start of RAM.\n"); 1171 return (ENXIO); 1172 } 1173 /* Search for the start of RAM. */ 1174 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1175 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1176 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1177 for (i = 0; i < ED_PAGE_SIZE; i++) 1178 pbuf[i] = 255 - x; 1179 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1180 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1181 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1182 msize += ED_PAGE_SIZE; 1183 else { 1184 break; 1185 } 1186 } else { 1187 break; 1188 } 1189 } 1190 1191 if (msize == 0) { 1192 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x); 1193 return (ENXIO); 1194 } 1195 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize); 1196 1197 sc->mem_size = msize; 1198 sc->mem_start = (caddr_t) mstart; 1199 sc->mem_end = (caddr_t) (msize + mstart); 1200 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1201 } 1202 1203 /* 1204 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1205 * otherwise). 1206 */ 1207 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1208 sc->txb_cnt = 1; 1209 else 1210 sc->txb_cnt = 2; 1211 1212 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1213 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1214 1215 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1216 1217 ed_pio_readmem(sc, 0, romdata, 16); 1218 for (n = 0; n < ETHER_ADDR_LEN; n++) 1219 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1220 1221 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) && 1222 (sc->arpcom.ac_enaddr[2] == 0x86)) { 1223 sc->type_str = "Gateway AT"; 1224 } 1225 1226 /* clear any pending interrupts that might have occurred above */ 1227 ed_nic_outb(sc, ED_P0_ISR, 0xff); 1228 1229 return (0); 1230 } 1231 1232 int 1233 ed_probe_Novell(device_t dev, int port_rid, int flags) 1234 { 1235 struct ed_softc *sc = device_get_softc(dev); 1236 int error; 1237 1238 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS); 1239 if (error) 1240 return (error); 1241 1242 sc->asic_offset = ED_NOVELL_ASIC_OFFSET; 1243 sc->nic_offset = ED_NOVELL_NIC_OFFSET; 1244 1245 return ed_probe_Novell_generic(dev, flags); 1246 } 1247 1248 #define ED_HPP_TEST_SIZE 16 1249 1250 /* 1251 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1252 * (HP Part nos: 27247B and 27252A). 1253 * 1254 * The card has an asic wrapper around a DS8390 core. The asic handles 1255 * host accesses and offers both standard register IO and memory mapped 1256 * IO. Memory mapped I/O allows better performance at the expense of greater 1257 * chance of an incompatibility with existing ISA cards. 1258 * 1259 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1260 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1261 * don't allow 32 bit accesses; these are indicated by a bit in the software 1262 * ID register (see if_edreg.h). 1263 * 1264 * Other caveats are: we should read the MAC address only when the card 1265 * is inactive. 1266 * 1267 * For more information; please consult the CRYNWR packet driver. 1268 * 1269 * The AUI port is turned on using the "link2" option on the ifconfig 1270 * command line. 1271 */ 1272 int 1273 ed_probe_HP_pclanp(device_t dev, int port_rid, int flags) 1274 { 1275 struct ed_softc *sc = device_get_softc(dev); 1276 int error; 1277 int n; /* temp var */ 1278 int memsize; /* mem on board */ 1279 u_char checksum; /* checksum of board address */ 1280 u_char irq; /* board configured IRQ */ 1281 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1282 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1283 u_long conf_maddr, conf_msize, conf_irq, junk; 1284 1285 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS); 1286 if (error) 1287 return (error); 1288 1289 /* Fill in basic information */ 1290 sc->asic_offset = ED_HPP_ASIC_OFFSET; 1291 sc->nic_offset = ED_HPP_NIC_OFFSET; 1292 1293 sc->chip_type = ED_CHIP_TYPE_DP8390; 1294 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1295 1296 /* 1297 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1298 */ 1299 1300 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) || 1301 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) || 1302 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) || 1303 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53)) 1304 return ENXIO; 1305 1306 /* 1307 * Read the MAC address and verify checksum on the address. 1308 */ 1309 1310 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1311 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1312 checksum += (sc->arpcom.ac_enaddr[n] = 1313 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n)); 1314 1315 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1316 1317 if (checksum != 0xFF) 1318 return ENXIO; 1319 1320 /* 1321 * Verify that the software model number is 0. 1322 */ 1323 1324 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID); 1325 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) & 1326 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1327 return ENXIO; 1328 1329 /* 1330 * Read in and save the current options configured on card. 1331 */ 1332 1333 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION); 1334 1335 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1336 ED_HPP_OPTION_CHIP_RESET | 1337 ED_HPP_OPTION_ENABLE_IRQ); 1338 1339 /* 1340 * Reset the chip. This requires writing to the option register 1341 * so take care to preserve the other bits. 1342 */ 1343 1344 ed_asic_outw(sc, ED_HPP_OPTION, 1345 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1346 ED_HPP_OPTION_CHIP_RESET))); 1347 1348 DELAY(5000); /* wait for chip reset to complete */ 1349 1350 ed_asic_outw(sc, ED_HPP_OPTION, 1351 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1352 ED_HPP_OPTION_CHIP_RESET | 1353 ED_HPP_OPTION_ENABLE_IRQ))); 1354 1355 DELAY(5000); 1356 1357 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST)) 1358 return ENXIO; /* reset did not complete */ 1359 1360 /* 1361 * Read out configuration information. 1362 */ 1363 1364 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); 1365 1366 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ); 1367 1368 /* 1369 * Check for impossible IRQ. 1370 */ 1371 1372 if (irq >= NELEM(ed_hpp_intr_val)) 1373 return ENXIO; 1374 1375 /* 1376 * If the kernel IRQ was specified with a '?' use the cards idea 1377 * of the IRQ. If the kernel IRQ was explicitly specified, it 1378 * should match that of the hardware. 1379 */ 1380 error = bus_get_resource(dev, SYS_RES_IRQ, 0, 1381 &conf_irq, &junk); 1382 if (error) { 1383 int intr_val = ed_hpp_intr_val[irq]; 1384 1385 bus_set_resource(dev, SYS_RES_IRQ, 0, intr_val, 1, 1386 machintr_legacy_intr_cpuid(intr_val)); 1387 } else { 1388 if (conf_irq != ed_hpp_intr_val[irq]) 1389 return (ENXIO); 1390 } 1391 1392 /* 1393 * Fill in softconfig info. 1394 */ 1395 1396 sc->vendor = ED_VENDOR_HP; 1397 sc->type = ED_TYPE_HP_PCLANPLUS; 1398 sc->type_str = "HP-PCLAN+"; 1399 1400 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1401 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1402 1403 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1404 1405 /* 1406 * The board has 32KB of memory. Is there a way to determine 1407 * this programmatically? 1408 */ 1409 1410 memsize = 32768; 1411 1412 /* 1413 * Check if memory mapping of the I/O registers possible. 1414 */ 1415 1416 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1417 { 1418 u_long mem_addr; 1419 1420 /* 1421 * determine the memory address from the board. 1422 */ 1423 1424 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); 1425 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8); 1426 1427 /* 1428 * Check that the kernel specified start of memory and 1429 * hardware's idea of it match. 1430 */ 1431 error = bus_get_resource(dev, SYS_RES_MEMORY, 0, 1432 &conf_maddr, &conf_msize); 1433 if (error) 1434 return (error); 1435 1436 if (mem_addr != conf_maddr) 1437 return ENXIO; 1438 1439 error = ed_alloc_memory(dev, 0, memsize); 1440 if (error) 1441 return (error); 1442 1443 sc->hpp_mem_start = rman_get_virtual(sc->mem_res); 1444 } 1445 1446 /* 1447 * Fill in the rest of the soft config structure. 1448 */ 1449 1450 /* 1451 * The transmit page index. 1452 */ 1453 1454 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1455 1456 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING) 1457 sc->txb_cnt = 1; 1458 else 1459 sc->txb_cnt = 2; 1460 1461 /* 1462 * Memory description 1463 */ 1464 1465 sc->mem_size = memsize; 1466 sc->mem_ring = sc->mem_start + 1467 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1468 sc->mem_end = sc->mem_start + sc->mem_size; 1469 1470 /* 1471 * Receive area starts after the transmit area and 1472 * continues till the end of memory. 1473 */ 1474 1475 sc->rec_page_start = sc->tx_page_start + 1476 (sc->txb_cnt * ED_TXBUF_SIZE); 1477 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1478 1479 1480 sc->cr_proto = 0; /* value works */ 1481 1482 /* 1483 * Set the wrap registers for string I/O reads. 1484 */ 1485 1486 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW); 1487 ed_asic_outw(sc, ED_HPP_HW_WRAP, 1488 ((sc->rec_page_start / ED_PAGE_SIZE) | 1489 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1490 1491 /* 1492 * Reset the register page to normal operation. 1493 */ 1494 1495 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1496 1497 /* 1498 * Verify that we can read/write from adapter memory. 1499 * Create test pattern. 1500 */ 1501 1502 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1503 { 1504 test_pattern[n] = (n*n) ^ ~n; 1505 } 1506 1507 #undef ED_HPP_TEST_SIZE 1508 1509 /* 1510 * Check that the memory is accessible thru the I/O ports. 1511 * Write out the contents of "test_pattern", read back 1512 * into "test_buffer" and compare the two for any 1513 * mismatch. 1514 */ 1515 1516 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1517 1518 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1519 sizeof(test_pattern)); 1520 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE), 1521 test_buffer, sizeof(test_pattern)); 1522 1523 if (bcmp(test_pattern, test_buffer, 1524 sizeof(test_pattern))) 1525 return ENXIO; 1526 } 1527 1528 return (0); 1529 1530 } 1531 1532 /* 1533 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1534 */ 1535 1536 static void 1537 ed_hpp_set_physical_link(struct ed_softc *sc) 1538 { 1539 struct ifnet *ifp = &sc->arpcom.ac_if; 1540 int lan_page; 1541 1542 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1543 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0); 1544 1545 if (ifp->if_flags & IFF_ALTPHYS) { 1546 1547 /* 1548 * Use the AUI port. 1549 */ 1550 1551 lan_page |= ED_HPP_LAN_AUI; 1552 1553 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1554 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page); 1555 1556 1557 } else { 1558 1559 /* 1560 * Use the ThinLan interface 1561 */ 1562 1563 lan_page &= ~ED_HPP_LAN_AUI; 1564 1565 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1566 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page); 1567 1568 } 1569 1570 /* 1571 * Wait for the lan card to re-initialize itself 1572 */ 1573 1574 DELAY(150000); /* wait 150 ms */ 1575 1576 /* 1577 * Restore normal pages. 1578 */ 1579 1580 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1581 1582 } 1583 1584 /* 1585 * Allocate a port resource with the given resource id. 1586 */ 1587 int 1588 ed_alloc_port(device_t dev, int rid, int size) 1589 { 1590 struct ed_softc *sc = device_get_softc(dev); 1591 struct resource *res; 1592 1593 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 1594 0ul, ~0ul, size, RF_ACTIVE); 1595 if (res) { 1596 sc->port_rid = rid; 1597 sc->port_res = res; 1598 sc->port_used = size; 1599 return (0); 1600 } else { 1601 return (ENOENT); 1602 } 1603 } 1604 1605 /* 1606 * Allocate a memory resource with the given resource id. 1607 */ 1608 int 1609 ed_alloc_memory(device_t dev, int rid, int size) 1610 { 1611 struct ed_softc *sc = device_get_softc(dev); 1612 struct resource *res; 1613 1614 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1615 0ul, ~0ul, size, RF_ACTIVE); 1616 if (res) { 1617 sc->mem_rid = rid; 1618 sc->mem_res = res; 1619 sc->mem_used = size; 1620 return (0); 1621 } else { 1622 return (ENOENT); 1623 } 1624 } 1625 1626 /* 1627 * Allocate an irq resource with the given resource id. 1628 */ 1629 int 1630 ed_alloc_irq(device_t dev, int rid, int flags) 1631 { 1632 struct ed_softc *sc = device_get_softc(dev); 1633 struct resource *res; 1634 1635 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1636 (RF_ACTIVE | flags)); 1637 if (res) { 1638 sc->irq_rid = rid; 1639 sc->irq_res = res; 1640 return (0); 1641 } else { 1642 return (ENOENT); 1643 } 1644 } 1645 1646 /* 1647 * Release all resources 1648 */ 1649 void 1650 ed_release_resources(device_t dev) 1651 { 1652 struct ed_softc *sc = device_get_softc(dev); 1653 1654 if (sc->port_res) { 1655 bus_deactivate_resource(dev, SYS_RES_IOPORT, 1656 sc->port_rid, sc->port_res); 1657 bus_release_resource(dev, SYS_RES_IOPORT, 1658 sc->port_rid, sc->port_res); 1659 sc->port_res = 0; 1660 } 1661 if (sc->mem_res) { 1662 bus_deactivate_resource(dev, SYS_RES_MEMORY, 1663 sc->mem_rid, sc->mem_res); 1664 bus_release_resource(dev, SYS_RES_MEMORY, 1665 sc->mem_rid, sc->mem_res); 1666 sc->mem_res = 0; 1667 } 1668 if (sc->irq_res) { 1669 bus_deactivate_resource(dev, SYS_RES_IRQ, 1670 sc->irq_rid, sc->irq_res); 1671 bus_release_resource(dev, SYS_RES_IRQ, 1672 sc->irq_rid, sc->irq_res); 1673 sc->irq_res = 0; 1674 } 1675 } 1676 1677 /* 1678 * Install interface into kernel networking data structures 1679 */ 1680 int 1681 ed_attach(device_t dev) 1682 { 1683 struct ed_softc *sc = device_get_softc(dev); 1684 struct ifnet *ifp = &sc->arpcom.ac_if; 1685 1686 callout_init(&sc->ed_timer); 1687 /* 1688 * Set interface to stopped condition (reset) 1689 */ 1690 ed_stop(sc); 1691 1692 /* 1693 * Initialize ifnet structure 1694 */ 1695 ifp->if_softc = sc; 1696 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1697 ifp->if_mtu = ETHERMTU; 1698 ifp->if_start = ed_start; 1699 ifp->if_ioctl = ed_ioctl; 1700 ifp->if_watchdog = ed_watchdog; 1701 ifp->if_init = ed_init; 1702 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN); 1703 ifq_set_ready(&ifp->if_snd); 1704 ifp->if_linkmib = &sc->mibdata; 1705 ifp->if_linkmiblen = sizeof sc->mibdata; 1706 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1707 /* 1708 * XXX - should do a better job. 1709 */ 1710 if (sc->chip_type == ED_CHIP_TYPE_WD790) 1711 sc->mibdata.dot3StatsEtherChipSet = 1712 DOT3CHIPSET(dot3VendorWesternDigital, 1713 dot3ChipSetWesternDigital83C790); 1714 else 1715 sc->mibdata.dot3StatsEtherChipSet = 1716 DOT3CHIPSET(dot3VendorNational, 1717 dot3ChipSetNational8390); 1718 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1719 1720 /* 1721 * Set default state for ALTPHYS flag (used to disable the 1722 * tranceiver for AUI operation), based on compile-time 1723 * config option. 1724 */ 1725 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER) 1726 ifp->if_flags |= IFF_ALTPHYS; 1727 1728 /* 1729 * Attach the interface 1730 */ 1731 ether_ifattach(ifp, sc->arpcom.ac_enaddr, NULL); 1732 1733 /* device attach does transition from UNCONFIGURED to IDLE state */ 1734 1735 if (sc->type_str && (*sc->type_str != 0)) 1736 kprintf("type %s ", sc->type_str); 1737 else 1738 kprintf("type unknown (0x%x) ", sc->type); 1739 1740 if (sc->vendor == ED_VENDOR_HP) 1741 kprintf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1742 "16-bit" : "32-bit", 1743 sc->hpp_mem_start ? "memory mapped" : "regular"); 1744 else 1745 kprintf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1746 1747 kprintf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1748 (sc->vendor == ED_VENDOR_HP)) && 1749 (ifp->if_flags & IFF_ALTPHYS)) ? " transceiver disabled" : ""); 1750 1751 return (0); 1752 } 1753 1754 /* 1755 * Reset interface. 1756 */ 1757 static void 1758 ed_reset(struct ifnet *ifp) 1759 { 1760 struct ed_softc *sc = ifp->if_softc; 1761 1762 crit_enter(); 1763 1764 if (sc->gone) { 1765 crit_exit(); 1766 return; 1767 } 1768 1769 /* 1770 * Stop interface and re-initialize. 1771 */ 1772 ed_stop(sc); 1773 ed_init(sc); 1774 1775 crit_exit(); 1776 } 1777 1778 /* 1779 * Take interface offline. 1780 */ 1781 void 1782 ed_stop(struct ed_softc *sc) 1783 { 1784 int n = 5000; 1785 1786 #ifndef ED_NO_MIIBUS 1787 callout_stop(&sc->ed_timer); 1788 #endif 1789 if (sc->gone) 1790 return; 1791 /* 1792 * Stop everything on the interface, and select page 0 registers. 1793 */ 1794 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1795 1796 /* 1797 * Wait for interface to enter stopped state, but limit # of checks to 1798 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1799 * just in case it's an old one. 1800 */ 1801 if (sc->chip_type != ED_CHIP_TYPE_AX88190) 1802 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1803 } 1804 1805 /* 1806 * Device timeout/watchdog routine. Entered if the device neglects to 1807 * generate an interrupt after a transmit has been started on it. 1808 */ 1809 static void 1810 ed_watchdog(struct ifnet *ifp) 1811 { 1812 struct ed_softc *sc = ifp->if_softc; 1813 1814 if (sc->gone) 1815 return; 1816 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname); 1817 IFNET_STAT_INC(ifp, oerrors, 1); 1818 1819 ed_reset(ifp); 1820 } 1821 1822 #ifndef ED_NO_MIIBUS 1823 static void 1824 ed_tick(void *arg) 1825 { 1826 struct ed_softc *sc = arg; 1827 struct mii_data *mii; 1828 struct ifnet *ifp; 1829 1830 ifp = &sc->arpcom.ac_if; 1831 lwkt_serialize_enter(ifp->if_serializer); 1832 1833 if (sc->gone) { 1834 lwkt_serialize_exit(ifp->if_serializer); 1835 return; 1836 } 1837 1838 if (sc->miibus != NULL) { 1839 mii = device_get_softc(sc->miibus); 1840 mii_tick(mii); 1841 } 1842 1843 callout_reset(&sc->ed_timer, hz, ed_tick, sc); 1844 lwkt_serialize_exit(ifp->if_serializer); 1845 } 1846 #endif 1847 1848 /* 1849 * Initialize device. 1850 */ 1851 static void 1852 ed_init(void *xsc) 1853 { 1854 struct ed_softc *sc = xsc; 1855 struct ifnet *ifp = &sc->arpcom.ac_if; 1856 int i; 1857 1858 crit_enter(); 1859 1860 if (sc->gone) { 1861 crit_exit(); 1862 return; 1863 } 1864 1865 /* 1866 * Initialize the NIC in the exact order outlined in the NS manual. 1867 * This init procedure is "mandatory"...don't change what or when 1868 * things happen. 1869 */ 1870 1871 /* reset transmitter flags */ 1872 sc->xmit_busy = 0; 1873 ifp->if_timer = 0; 1874 1875 sc->txb_inuse = 0; 1876 sc->txb_new = 0; 1877 sc->txb_next_tx = 0; 1878 1879 /* This variable is used below - don't move this assignment */ 1880 sc->next_packet = sc->rec_page_start + 1; 1881 1882 /* 1883 * Set interface for page 0, Remote DMA complete, Stopped 1884 */ 1885 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 1886 1887 if (sc->isa16bit) { 1888 1889 /* 1890 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1891 * order=80x86, word-wide DMA xfers, 1892 */ 1893 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1894 } else { 1895 1896 /* 1897 * Same as above, but byte-wide DMA xfers 1898 */ 1899 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1900 } 1901 1902 /* 1903 * Clear Remote Byte Count Registers 1904 */ 1905 ed_nic_outb(sc, ED_P0_RBCR0, 0); 1906 ed_nic_outb(sc, ED_P0_RBCR1, 0); 1907 1908 /* 1909 * For the moment, don't store incoming packets in memory. 1910 */ 1911 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON); 1912 1913 /* 1914 * Place NIC in internal loopback mode 1915 */ 1916 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0); 1917 1918 /* 1919 * Initialize transmit/receive (ring-buffer) Page Start 1920 */ 1921 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start); 1922 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start); 1923 /* Set lower bits of byte addressable framing to 0 */ 1924 if (sc->chip_type == ED_CHIP_TYPE_WD790) 1925 ed_nic_outb(sc, 0x09, 0); 1926 1927 /* 1928 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1929 */ 1930 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop); 1931 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start); 1932 1933 /* 1934 * Clear all interrupts. A '1' in each bit position clears the 1935 * corresponding flag. 1936 */ 1937 ed_nic_outb(sc, ED_P0_ISR, 0xff); 1938 1939 /* 1940 * Enable the following interrupts: receive/transmit complete, 1941 * receive/transmit error, and Receiver OverWrite. 1942 * 1943 * Counter overflow and Remote DMA complete are *not* enabled. 1944 */ 1945 ed_nic_outb(sc, ED_P0_IMR, 1946 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1947 1948 /* 1949 * Program Command Register for page 1 1950 */ 1951 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1952 1953 /* 1954 * Copy out our station address 1955 */ 1956 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1957 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 1958 1959 /* 1960 * Set Current Page pointer to next_packet (initialized above) 1961 */ 1962 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet); 1963 1964 /* 1965 * Program Receiver Configuration Register and multicast filter. CR is 1966 * set to page 0 on return. 1967 */ 1968 ed_setrcr(sc); 1969 1970 /* 1971 * Take interface out of loopback 1972 */ 1973 ed_nic_outb(sc, ED_P0_TCR, 0); 1974 1975 /* 1976 * If this is a 3Com board, the tranceiver must be software enabled 1977 * (there is no settable hardware default). 1978 */ 1979 if (sc->vendor == ED_VENDOR_3COM) { 1980 if (ifp->if_flags & IFF_ALTPHYS) { 1981 ed_asic_outb(sc, ED_3COM_CR, 0); 1982 } else { 1983 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 1984 } 1985 } 1986 1987 #ifndef ED_NO_MIIBUS 1988 if (sc->miibus != NULL) { 1989 struct mii_data *mii; 1990 mii = device_get_softc(sc->miibus); 1991 mii_mediachg(mii); 1992 } 1993 #endif 1994 /* 1995 * Set 'running' flag, and clear output active flag. 1996 */ 1997 ifp->if_flags |= IFF_RUNNING; 1998 ifq_clr_oactive(&ifp->if_snd); 1999 2000 /* 2001 * ...and attempt to start output 2002 */ 2003 if_devstart(ifp); 2004 2005 #ifndef ED_NO_MIIBUS 2006 callout_reset(&sc->ed_timer, hz, ed_tick, sc); 2007 #endif 2008 2009 crit_exit(); 2010 } 2011 2012 /* 2013 * This routine actually starts the transmission on the interface 2014 */ 2015 static __inline void 2016 ed_xmit(struct ed_softc *sc) 2017 { 2018 struct ifnet *ifp = (struct ifnet *)sc; 2019 u_short len; 2020 2021 if (sc->gone) 2022 return; 2023 len = sc->txb_len[sc->txb_next_tx]; 2024 2025 /* 2026 * Set NIC for page 0 register access 2027 */ 2028 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2029 2030 /* 2031 * Set TX buffer start page 2032 */ 2033 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start + 2034 sc->txb_next_tx * ED_TXBUF_SIZE); 2035 2036 /* 2037 * Set TX length 2038 */ 2039 ed_nic_outb(sc, ED_P0_TBCR0, len); 2040 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8); 2041 2042 /* 2043 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 2044 */ 2045 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 2046 sc->xmit_busy = 1; 2047 2048 /* 2049 * Point to next transmit buffer slot and wrap if necessary. 2050 */ 2051 sc->txb_next_tx++; 2052 if (sc->txb_next_tx == sc->txb_cnt) 2053 sc->txb_next_tx = 0; 2054 2055 /* 2056 * Set a timer just in case we never hear from the board again 2057 */ 2058 ifp->if_timer = 2; 2059 } 2060 2061 /* 2062 * Start output on interface. 2063 * We make two assumptions here: 2064 * 1) that the current priority is set to splimp _before_ this code 2065 * is called *and* is returned to the appropriate priority after 2066 * return 2067 * 2) that the OACTIVE flag is checked before this code is called 2068 * (i.e. that the output part of the interface is idle) 2069 */ 2070 static void 2071 ed_start(struct ifnet *ifp, struct ifaltq_subque *ifsq) 2072 { 2073 struct ed_softc *sc = ifp->if_softc; 2074 struct mbuf *m0, *m; 2075 caddr_t buffer; 2076 int len; 2077 2078 ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq); 2079 2080 if (sc->gone) { 2081 kprintf("ed_start(%p) GONE\n",ifp); 2082 ifq_purge(&ifp->if_snd); 2083 return; 2084 } 2085 outloop: 2086 2087 /* 2088 * First, see if there are buffered packets and an idle transmitter - 2089 * should never happen at this point. 2090 */ 2091 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 2092 kprintf("ed: packets buffered, but transmitter idle\n"); 2093 ed_xmit(sc); 2094 } 2095 2096 /* 2097 * See if there is room to put another packet in the buffer. 2098 */ 2099 if (sc->txb_inuse == sc->txb_cnt) { 2100 2101 /* 2102 * No room. Indicate this to the outside world and exit. 2103 */ 2104 ifq_set_oactive(&ifp->if_snd); 2105 return; 2106 } 2107 m = ifq_dequeue(&ifp->if_snd); 2108 if (m == NULL) { 2109 2110 /* 2111 * We are using the !OACTIVE flag to indicate to the outside 2112 * world that we can accept an additional packet rather than 2113 * that the transmitter is _actually_ active. Indeed, the 2114 * transmitter may be active, but if we haven't filled all the 2115 * buffers with data then we still want to accept more. 2116 */ 2117 ifq_clr_oactive(&ifp->if_snd); 2118 return; 2119 } 2120 2121 /* 2122 * Copy the mbuf chain into the transmit buffer 2123 */ 2124 2125 m0 = m; 2126 2127 /* txb_new points to next open buffer slot */ 2128 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2129 2130 if (sc->mem_shared) { 2131 2132 /* 2133 * Special case setup for 16 bit boards... 2134 */ 2135 if (sc->isa16bit) { 2136 switch (sc->vendor) { 2137 2138 /* 2139 * For 16bit 3Com boards (which have 16k of 2140 * memory), we have the xmit buffers in a 2141 * different page of memory ('page 0') - so 2142 * change pages. 2143 */ 2144 case ED_VENDOR_3COM: 2145 ed_asic_outb(sc, ED_3COM_GACFR, 2146 ED_3COM_GACFR_RSEL); 2147 break; 2148 2149 /* 2150 * Enable 16bit access to shared memory on 2151 * WD/SMC boards. 2152 */ 2153 case ED_VENDOR_WD_SMC: 2154 ed_asic_outb(sc, ED_WD_LAAR, 2155 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2156 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2157 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB); 2158 } 2159 break; 2160 } 2161 } 2162 for (len = 0; m != NULL; m = m->m_next) { 2163 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2164 buffer += m->m_len; 2165 len += m->m_len; 2166 } 2167 2168 /* 2169 * Restore previous shared memory access 2170 */ 2171 if (sc->isa16bit) { 2172 switch (sc->vendor) { 2173 case ED_VENDOR_3COM: 2174 ed_asic_outb(sc, ED_3COM_GACFR, 2175 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2176 break; 2177 case ED_VENDOR_WD_SMC: 2178 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2179 ed_asic_outb(sc, ED_WD_MSR, 0x00); 2180 } 2181 ed_asic_outb(sc, ED_WD_LAAR, 2182 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2183 break; 2184 } 2185 } 2186 } else { 2187 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2188 if (len == 0) { 2189 m_freem(m0); 2190 goto outloop; 2191 } 2192 } 2193 2194 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2195 2196 sc->txb_inuse++; 2197 2198 /* 2199 * Point to next buffer slot and wrap if necessary. 2200 */ 2201 sc->txb_new++; 2202 if (sc->txb_new == sc->txb_cnt) 2203 sc->txb_new = 0; 2204 2205 if (sc->xmit_busy == 0) 2206 ed_xmit(sc); 2207 2208 BPF_MTAP(ifp, m0); 2209 2210 m_freem(m0); 2211 2212 /* 2213 * Loop back to the top to possibly buffer more packets 2214 */ 2215 goto outloop; 2216 } 2217 2218 /* 2219 * Ethernet interface receiver interrupt. 2220 */ 2221 static __inline void 2222 ed_rint(struct ed_softc *sc) 2223 { 2224 struct ifnet *ifp = &sc->arpcom.ac_if; 2225 u_char boundry; 2226 u_short len; 2227 struct ed_ring packet_hdr; 2228 char *packet_ptr; 2229 2230 if (sc->gone) 2231 return; 2232 2233 /* 2234 * Set NIC to page 1 registers to get 'current' pointer 2235 */ 2236 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2237 2238 /* 2239 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2240 * i.e. it points to where new data has been buffered. The 'CURR' 2241 * (current) register points to the logical end of the ring-buffer - 2242 * i.e. it points to where additional new data will be added. We loop 2243 * here until the logical beginning equals the logical end (or in 2244 * other words, until the ring-buffer is empty). 2245 */ 2246 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) { 2247 2248 /* get pointer to this buffer's header structure */ 2249 packet_ptr = sc->mem_ring + 2250 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2251 2252 /* 2253 * The byte count includes a 4 byte header that was added by 2254 * the NIC. 2255 */ 2256 if (sc->mem_shared) 2257 packet_hdr = *(struct ed_ring *) packet_ptr; 2258 else 2259 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2260 sizeof(packet_hdr)); 2261 len = packet_hdr.count; 2262 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2263 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2264 /* 2265 * Length is a wild value. There's a good chance that 2266 * this was caused by the NIC being old and buggy. 2267 * The bug is that the length low byte is duplicated in 2268 * the high byte. Try to recalculate the length based on 2269 * the pointer to the next packet. 2270 */ 2271 /* 2272 * NOTE: sc->next_packet is pointing at the current packet. 2273 */ 2274 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2275 if (packet_hdr.next_packet >= sc->next_packet) { 2276 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2277 } else { 2278 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2279 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2280 } 2281 /* 2282 * because buffers are aligned on 256-byte boundary, 2283 * the length computed above is off by 256 in almost 2284 * all cases. Fix it... 2285 */ 2286 if (len & 0xff) 2287 len -= 256 ; 2288 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2289 + sizeof(struct ed_ring))) 2290 sc->mibdata.dot3StatsFrameTooLongs++; 2291 } 2292 /* 2293 * Be fairly liberal about what we allow as a "reasonable" length 2294 * so that a [crufty] packet will make it to BPF (and can thus 2295 * be analyzed). Note that all that is really important is that 2296 * we have a length that will fit into one mbuf cluster or less; 2297 * the upper layer protocols can then figure out the length from 2298 * their own length field(s). 2299 * But make sure that we have at least a full ethernet header 2300 * or we would be unable to call ether_input() later. 2301 */ 2302 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) && 2303 (len <= MCLBYTES) && 2304 (packet_hdr.next_packet >= sc->rec_page_start) && 2305 (packet_hdr.next_packet < sc->rec_page_stop)) { 2306 /* 2307 * Go get packet. 2308 */ 2309 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2310 len - sizeof(struct ed_ring)); 2311 IFNET_STAT_INC(ifp, ipackets, 1); 2312 } else { 2313 /* 2314 * Really BAD. The ring pointers are corrupted. 2315 */ 2316 log(LOG_ERR, 2317 "%s: NIC memory corrupt - invalid packet length %d\n", 2318 ifp->if_xname, len); 2319 IFNET_STAT_INC(ifp, ierrors, 1); 2320 ed_reset(ifp); 2321 return; 2322 } 2323 2324 /* 2325 * Update next packet pointer 2326 */ 2327 sc->next_packet = packet_hdr.next_packet; 2328 2329 /* 2330 * Update NIC boundry pointer - being careful to keep it one 2331 * buffer behind. (as recommended by NS databook) 2332 */ 2333 boundry = sc->next_packet - 1; 2334 if (boundry < sc->rec_page_start) 2335 boundry = sc->rec_page_stop - 1; 2336 2337 /* 2338 * Set NIC to page 0 registers to update boundry register 2339 */ 2340 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2341 2342 ed_nic_outb(sc, ED_P0_BNRY, boundry); 2343 2344 /* 2345 * Set NIC to page 1 registers before looping to top (prepare 2346 * to get 'CURR' current pointer) 2347 */ 2348 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2349 } 2350 } 2351 2352 /* 2353 * Ethernet interface interrupt processor 2354 */ 2355 void 2356 edintr(void *arg) 2357 { 2358 struct ed_softc *sc = (struct ed_softc*) arg; 2359 struct ifnet *ifp = (struct ifnet *)sc; 2360 u_char isr; 2361 int count; 2362 2363 if (sc->gone) 2364 return; 2365 /* 2366 * Set NIC to page 0 registers 2367 */ 2368 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2369 2370 /* 2371 * loop until there are no more new interrupts. When the card 2372 * goes away, the hardware will read back 0xff. Looking at 2373 * the interrupts, it would appear that 0xff is impossible, 2374 * or at least extremely unlikely. 2375 */ 2376 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) { 2377 2378 /* 2379 * reset all the bits that we are 'acknowledging' by writing a 2380 * '1' to each bit position that was set (writing a '1' 2381 * *clears* the bit) 2382 */ 2383 ed_nic_outb(sc, ED_P0_ISR, isr); 2384 2385 /* 2386 * XXX workaround for AX88190 2387 * We limit this to 5000 iterations. At 1us per inb/outb, 2388 * this translates to about 15ms, which should be plenty 2389 * of time, and also gives protection in the card eject 2390 * case. 2391 */ 2392 if (sc->chip_type == ED_CHIP_TYPE_AX88190) { 2393 count = 5000; /* 15ms */ 2394 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) { 2395 ed_nic_outb(sc, ED_P0_ISR,0); 2396 ed_nic_outb(sc, ED_P0_ISR,isr); 2397 } 2398 if (count == 0) 2399 break; 2400 } 2401 2402 /* 2403 * Handle transmitter interrupts. Handle these first because 2404 * the receiver will reset the board under some conditions. 2405 */ 2406 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2407 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f; 2408 2409 /* 2410 * Check for transmit error. If a TX completed with an 2411 * error, we end up throwing the packet away. Really 2412 * the only error that is possible is excessive 2413 * collisions, and in this case it is best to allow 2414 * the automatic mechanisms of TCP to backoff the 2415 * flow. Of course, with UDP we're screwed, but this 2416 * is expected when a network is heavily loaded. 2417 */ 2418 ed_nic_inb(sc, ED_P0_TSR); 2419 if (isr & ED_ISR_TXE) { 2420 u_char tsr; 2421 2422 /* 2423 * Excessive collisions (16) 2424 */ 2425 tsr = ed_nic_inb(sc, ED_P0_TSR); 2426 if ((tsr & ED_TSR_ABT) 2427 && (collisions == 0)) { 2428 2429 /* 2430 * When collisions total 16, the 2431 * P0_NCR will indicate 0, and the 2432 * TSR_ABT is set. 2433 */ 2434 collisions = 16; 2435 sc->mibdata.dot3StatsExcessiveCollisions++; 2436 sc->mibdata.dot3StatsCollFrequencies[15]++; 2437 } 2438 if (tsr & ED_TSR_OWC) 2439 sc->mibdata.dot3StatsLateCollisions++; 2440 if (tsr & ED_TSR_CDH) 2441 sc->mibdata.dot3StatsSQETestErrors++; 2442 if (tsr & ED_TSR_CRS) 2443 sc->mibdata.dot3StatsCarrierSenseErrors++; 2444 if (tsr & ED_TSR_FU) 2445 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2446 2447 /* 2448 * update output errors counter 2449 */ 2450 IFNET_STAT_INC(ifp, oerrors, 1); 2451 } else { 2452 2453 /* 2454 * Update total number of successfully 2455 * transmitted packets. 2456 */ 2457 IFNET_STAT_INC(ifp, opackets, 1); 2458 } 2459 2460 /* 2461 * reset tx busy and output active flags 2462 */ 2463 sc->xmit_busy = 0; 2464 ifq_clr_oactive(&ifp->if_snd); 2465 2466 /* 2467 * clear watchdog timer 2468 */ 2469 ifp->if_timer = 0; 2470 2471 /* 2472 * Add in total number of collisions on last 2473 * transmission. 2474 */ 2475 IFNET_STAT_INC(ifp, collisions, collisions); 2476 switch(collisions) { 2477 case 0: 2478 case 16: 2479 break; 2480 case 1: 2481 sc->mibdata.dot3StatsSingleCollisionFrames++; 2482 sc->mibdata.dot3StatsCollFrequencies[0]++; 2483 break; 2484 default: 2485 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2486 sc->mibdata. 2487 dot3StatsCollFrequencies[collisions-1] 2488 ++; 2489 break; 2490 } 2491 2492 /* 2493 * Decrement buffer in-use count if not zero (can only 2494 * be zero if a transmitter interrupt occured while 2495 * not actually transmitting). If data is ready to 2496 * transmit, start it transmitting, otherwise defer 2497 * until after handling receiver 2498 */ 2499 if (sc->txb_inuse && --sc->txb_inuse) 2500 ed_xmit(sc); 2501 } 2502 2503 /* 2504 * Handle receiver interrupts 2505 */ 2506 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2507 2508 /* 2509 * Overwrite warning. In order to make sure that a 2510 * lockup of the local DMA hasn't occurred, we reset 2511 * and re-init the NIC. The NSC manual suggests only a 2512 * partial reset/re-init is necessary - but some chips 2513 * seem to want more. The DMA lockup has been seen 2514 * only with early rev chips - Methinks this bug was 2515 * fixed in later revs. -DG 2516 */ 2517 if (isr & ED_ISR_OVW) { 2518 IFNET_STAT_INC(ifp, ierrors, 1); 2519 #ifdef DIAGNOSTIC 2520 log(LOG_WARNING, 2521 "%s: warning - receiver ring buffer overrun\n", 2522 ifp->if_xname); 2523 #endif 2524 2525 /* 2526 * Stop/reset/re-init NIC 2527 */ 2528 ed_reset(ifp); 2529 } else { 2530 2531 /* 2532 * Receiver Error. One or more of: CRC error, 2533 * frame alignment error FIFO overrun, or 2534 * missed packet. 2535 */ 2536 if (isr & ED_ISR_RXE) { 2537 u_char rsr; 2538 rsr = ed_nic_inb(sc, ED_P0_RSR); 2539 if (rsr & ED_RSR_CRC) 2540 sc->mibdata.dot3StatsFCSErrors++; 2541 if (rsr & ED_RSR_FAE) 2542 sc->mibdata.dot3StatsAlignmentErrors++; 2543 if (rsr & ED_RSR_FO) 2544 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2545 IFNET_STAT_INC(ifp, ierrors, 1); 2546 #ifdef ED_DEBUG 2547 if_printf("receive error %x\n", 2548 ed_nic_inb(sc, ED_P0_RSR)); 2549 #endif 2550 } 2551 2552 /* 2553 * Go get the packet(s) XXX - Doing this on an 2554 * error is dubious because there shouldn't be 2555 * any data to get (we've configured the 2556 * interface to not accept packets with 2557 * errors). 2558 */ 2559 2560 /* 2561 * Enable 16bit access to shared memory first 2562 * on WD/SMC boards. 2563 */ 2564 if (sc->isa16bit && 2565 (sc->vendor == ED_VENDOR_WD_SMC)) { 2566 2567 ed_asic_outb(sc, ED_WD_LAAR, 2568 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2569 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2570 ed_asic_outb(sc, ED_WD_MSR, 2571 ED_WD_MSR_MENB); 2572 } 2573 } 2574 ed_rint(sc); 2575 2576 /* disable 16bit access */ 2577 if (sc->isa16bit && 2578 (sc->vendor == ED_VENDOR_WD_SMC)) { 2579 2580 if (sc->chip_type == ED_CHIP_TYPE_WD790) { 2581 ed_asic_outb(sc, ED_WD_MSR, 0x00); 2582 } 2583 ed_asic_outb(sc, ED_WD_LAAR, 2584 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2585 } 2586 } 2587 } 2588 2589 /* 2590 * If it looks like the transmitter can take more data, 2591 * attempt to start output on the interface. This is done 2592 * after handling the receiver to give the receiver priority. 2593 */ 2594 if (!ifq_is_oactive(&ifp->if_snd)) 2595 if_devstart(ifp); 2596 2597 /* 2598 * return NIC CR to standard state: page 0, remote DMA 2599 * complete, start (toggling the TXP bit off, even if was just 2600 * set in the transmit routine, is *okay* - it is 'edge' 2601 * triggered from low to high) 2602 */ 2603 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 2604 2605 /* 2606 * If the Network Talley Counters overflow, read them to reset 2607 * them. It appears that old 8390's won't clear the ISR flag 2608 * otherwise - resulting in an infinite loop. 2609 */ 2610 if (isr & ED_ISR_CNT) { 2611 ed_nic_inb(sc, ED_P0_CNTR0); 2612 ed_nic_inb(sc, ED_P0_CNTR1); 2613 ed_nic_inb(sc, ED_P0_CNTR2); 2614 } 2615 } 2616 } 2617 2618 /* 2619 * Process an ioctl request. This code needs some work - it looks 2620 * pretty ugly. 2621 */ 2622 static int 2623 ed_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr) 2624 { 2625 struct ed_softc *sc = ifp->if_softc; 2626 #ifndef ED_NO_MIIBUS 2627 struct ifreq *ifr = (struct ifreq *)data; 2628 struct mii_data *mii; 2629 #endif 2630 int error = 0; 2631 2632 crit_enter(); 2633 2634 if (sc == NULL || sc->gone) { 2635 ifp->if_flags &= ~IFF_RUNNING; 2636 crit_exit(); 2637 return ENXIO; 2638 } 2639 2640 switch (command) { 2641 case SIOCSIFFLAGS: 2642 2643 /* 2644 * If the interface is marked up and stopped, then start it. 2645 * If it is marked down and running, then stop it. 2646 */ 2647 if (ifp->if_flags & IFF_UP) { 2648 if ((ifp->if_flags & IFF_RUNNING) == 0) 2649 ed_init(sc); 2650 } else { 2651 if (ifp->if_flags & IFF_RUNNING) { 2652 ed_stop(sc); 2653 ifp->if_flags &= ~IFF_RUNNING; 2654 } 2655 } 2656 2657 /* 2658 * Promiscuous flag may have changed, so reprogram the RCR. 2659 */ 2660 ed_setrcr(sc); 2661 2662 /* 2663 * An unfortunate hack to provide the (required) software 2664 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2665 * disables the tranceiver if set. 2666 */ 2667 if (sc->vendor == ED_VENDOR_3COM) { 2668 if (ifp->if_flags & IFF_ALTPHYS) { 2669 ed_asic_outb(sc, ED_3COM_CR, 0); 2670 } else { 2671 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL); 2672 } 2673 } else if (sc->vendor == ED_VENDOR_HP) 2674 ed_hpp_set_physical_link(sc); 2675 break; 2676 2677 case SIOCADDMULTI: 2678 case SIOCDELMULTI: 2679 /* 2680 * Multicast list has changed; set the hardware filter 2681 * accordingly. 2682 */ 2683 ed_setrcr(sc); 2684 error = 0; 2685 break; 2686 2687 #ifndef ED_NO_MIIBUS 2688 case SIOCGIFMEDIA: 2689 case SIOCSIFMEDIA: 2690 if (sc->miibus == NULL) { 2691 error = EINVAL; 2692 break; 2693 } 2694 mii = device_get_softc(sc->miibus); 2695 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2696 break; 2697 #endif 2698 2699 default: 2700 error = ether_ioctl(ifp, command, data); 2701 break; 2702 } 2703 2704 crit_exit(); 2705 2706 return (error); 2707 } 2708 2709 /* 2710 * Given a source and destination address, copy 'amount' of a packet from 2711 * the ring buffer into a linear destination buffer. Takes into account 2712 * ring-wrap. 2713 */ 2714 static __inline char * 2715 ed_ring_copy(struct ed_softc *sc, char *src, char *dst, u_short amount) 2716 { 2717 u_short tmp_amount; 2718 2719 /* does copy wrap to lower addr in ring buffer? */ 2720 if (src + amount > sc->mem_end) { 2721 tmp_amount = sc->mem_end - src; 2722 2723 /* copy amount up to end of NIC memory */ 2724 if (sc->mem_shared) 2725 bcopy(src, dst, tmp_amount); 2726 else 2727 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2728 2729 amount -= tmp_amount; 2730 src = sc->mem_ring; 2731 dst += tmp_amount; 2732 } 2733 if (sc->mem_shared) 2734 bcopy(src, dst, amount); 2735 else 2736 ed_pio_readmem(sc, (int)src, dst, amount); 2737 2738 return (src + amount); 2739 } 2740 2741 /* 2742 * Retreive packet from shared memory and send to the next level up via 2743 * ether_input(). 2744 */ 2745 static void 2746 ed_get_packet(struct ed_softc *sc, char *buf, u_short len) 2747 { 2748 struct ifnet *ifp = &sc->arpcom.ac_if; 2749 struct ether_header *eh; 2750 struct mbuf *m; 2751 2752 /* 2753 * Allocate a header mbuf. 2754 * We always put the received packet in a single buffer - 2755 * either with just an mbuf header or in a cluster attached 2756 * to the header. The +2 is to compensate for the alignment 2757 * fixup below. 2758 */ 2759 m = m_getl(len + 2, MB_DONTWAIT, MT_DATA, M_PKTHDR, NULL); 2760 if (m == NULL) 2761 return; 2762 m->m_pkthdr.rcvif = ifp; 2763 m->m_pkthdr.len = m->m_len = len; 2764 2765 /* 2766 * The +2 is to longword align the start of the real packet. 2767 * This is important for NFS. 2768 */ 2769 m->m_data += 2; 2770 eh = mtod(m, struct ether_header *); 2771 2772 /* 2773 * Get packet, including link layer address, from interface. 2774 */ 2775 ed_ring_copy(sc, buf, (char *)eh, len); 2776 2777 m->m_pkthdr.len = m->m_len = len; 2778 2779 ifp->if_input(ifp, m); 2780 } 2781 2782 /* 2783 * Supporting routines 2784 */ 2785 2786 /* 2787 * Given a NIC memory source address and a host memory destination 2788 * address, copy 'amount' from NIC to host using Programmed I/O. 2789 * The 'amount' is rounded up to a word - okay as long as mbufs 2790 * are word sized. 2791 * This routine is currently Novell-specific. 2792 */ 2793 void 2794 ed_pio_readmem(struct ed_softc *sc, int src, u_char *dst, u_short amount) 2795 { 2796 /* HP PC Lan+ cards need special handling */ 2797 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2798 ed_hpp_readmem(sc, src, dst, amount); 2799 return; 2800 } 2801 2802 /* Regular Novell cards */ 2803 /* select page 0 registers */ 2804 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2805 2806 /* round up to a word */ 2807 if (amount & 1) 2808 ++amount; 2809 2810 /* set up DMA byte count */ 2811 ed_nic_outb(sc, ED_P0_RBCR0, amount); 2812 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8); 2813 2814 /* set up source address in NIC mem */ 2815 ed_nic_outb(sc, ED_P0_RSAR0, src); 2816 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8); 2817 2818 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2819 2820 if (sc->isa16bit) { 2821 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2); 2822 } else { 2823 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount); 2824 } 2825 } 2826 2827 /* 2828 * Stripped down routine for writing a linear buffer to NIC memory. 2829 * Only used in the probe routine to test the memory. 'len' must 2830 * be even. 2831 */ 2832 void 2833 ed_pio_writemem(struct ed_softc *sc, char *src, u_short dst, u_short len) 2834 { 2835 int maxwait = 200; /* about 240us */ 2836 2837 /* select page 0 registers */ 2838 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2839 2840 /* reset remote DMA complete flag */ 2841 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 2842 2843 /* set up DMA byte count */ 2844 ed_nic_outb(sc, ED_P0_RBCR0, len); 2845 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8); 2846 2847 /* set up destination address in NIC mem */ 2848 ed_nic_outb(sc, ED_P0_RSAR0, dst); 2849 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 2850 2851 /* set remote DMA write */ 2852 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2853 2854 if (sc->isa16bit) { 2855 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2); 2856 } else { 2857 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len); 2858 } 2859 2860 /* 2861 * Wait for remote DMA complete. This is necessary because on the 2862 * transmit side, data is handled internally by the NIC in bursts and 2863 * we can't start another remote DMA until this one completes. Not 2864 * waiting causes really bad things to happen - like the NIC 2865 * irrecoverably jamming the ISA bus. 2866 */ 2867 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2868 } 2869 2870 /* 2871 * Write an mbuf chain to the destination NIC memory address using 2872 * programmed I/O. 2873 */ 2874 static u_short 2875 ed_pio_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 2876 { 2877 struct ifnet *ifp = (struct ifnet *)sc; 2878 u_short total_len, dma_len; 2879 struct mbuf *mp; 2880 int maxwait = 200; /* about 240us */ 2881 2882 /* HP PC Lan+ cards need special handling */ 2883 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2884 return ed_hpp_write_mbufs(sc, m, dst); 2885 } 2886 2887 /* Regular Novell cards */ 2888 /* First, count up the total number of bytes to copy */ 2889 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2890 total_len += mp->m_len; 2891 2892 dma_len = total_len; 2893 if (sc->isa16bit && (dma_len & 1)) 2894 dma_len++; 2895 2896 /* select page 0 registers */ 2897 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2898 2899 /* reset remote DMA complete flag */ 2900 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 2901 2902 /* set up DMA byte count */ 2903 ed_nic_outb(sc, ED_P0_RBCR0, dma_len); 2904 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8); 2905 2906 /* set up destination address in NIC mem */ 2907 ed_nic_outb(sc, ED_P0_RSAR0, dst); 2908 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8); 2909 2910 /* set remote DMA write */ 2911 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2912 2913 /* 2914 * Transfer the mbuf chain to the NIC memory. 2915 * 16-bit cards require that data be transferred as words, and only words. 2916 * So that case requires some extra code to patch over odd-length mbufs. 2917 */ 2918 2919 if (!sc->isa16bit) { 2920 /* NE1000s are easy */ 2921 while (m) { 2922 if (m->m_len) { 2923 ed_asic_outsb(sc, ED_NOVELL_DATA, 2924 m->m_data, m->m_len); 2925 } 2926 m = m->m_next; 2927 } 2928 } else { 2929 /* NE2000s are a pain */ 2930 u_char *data; 2931 int len, wantbyte; 2932 u_char savebyte[2]; 2933 2934 wantbyte = 0; 2935 2936 while (m) { 2937 len = m->m_len; 2938 if (len) { 2939 data = mtod(m, caddr_t); 2940 /* finish the last word */ 2941 if (wantbyte) { 2942 savebyte[1] = *data; 2943 ed_asic_outw(sc, ED_NOVELL_DATA, 2944 *(u_short *)savebyte); 2945 data++; 2946 len--; 2947 wantbyte = 0; 2948 } 2949 /* output contiguous words */ 2950 if (len > 1) { 2951 ed_asic_outsw(sc, ED_NOVELL_DATA, 2952 data, len >> 1); 2953 data += len & ~1; 2954 len &= 1; 2955 } 2956 /* save last byte, if necessary */ 2957 if (len == 1) { 2958 savebyte[0] = *data; 2959 wantbyte = 1; 2960 } 2961 } 2962 m = m->m_next; 2963 } 2964 /* spit last byte */ 2965 if (wantbyte) { 2966 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte); 2967 } 2968 } 2969 2970 /* 2971 * Wait for remote DMA complete. This is necessary because on the 2972 * transmit side, data is handled internally by the NIC in bursts and 2973 * we can't start another remote DMA until this one completes. Not 2974 * waiting causes really bad things to happen - like the NIC 2975 * irrecoverably jamming the ISA bus. 2976 */ 2977 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2978 2979 if (!maxwait) { 2980 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n", 2981 ifp->if_xname); 2982 ed_reset(ifp); 2983 return(0); 2984 } 2985 return (total_len); 2986 } 2987 2988 /* 2989 * Support routines to handle the HP PC Lan+ card. 2990 */ 2991 2992 /* 2993 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 2994 * IO. 2995 */ 2996 2997 static void 2998 ed_hpp_readmem(struct ed_softc *sc, u_short src, u_char *dst, u_short amount) 2999 { 3000 3001 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3002 3003 3004 /* Program the source address in RAM */ 3005 ed_asic_outw(sc, ED_HPP_PAGE_2, src); 3006 3007 /* 3008 * The HP PC Lan+ card supports word reads as well as 3009 * a memory mapped i/o port that is aliased to every 3010 * even address on the board. 3011 */ 3012 3013 if (sc->hpp_mem_start) { 3014 3015 /* Enable memory mapped access. */ 3016 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options & 3017 ~(ED_HPP_OPTION_MEM_DISABLE | 3018 ED_HPP_OPTION_BOOT_ROM_ENB)); 3019 3020 if (use_32bit_access && (amount > 3)) { 3021 u_int32_t *dl = (u_int32_t *) dst; 3022 volatile u_int32_t *const sl = 3023 (u_int32_t *) sc->hpp_mem_start; 3024 u_int32_t *const fence = dl + (amount >> 2); 3025 3026 /* Copy out NIC data. We could probably write this 3027 as a `movsl'. The currently generated code is lousy. 3028 */ 3029 3030 while (dl < fence) 3031 *dl++ = *sl; 3032 3033 dst += (amount & ~3); 3034 amount &= 3; 3035 3036 } 3037 3038 /* Finish off any words left, as a series of short reads */ 3039 if (amount > 1) { 3040 u_short *d = (u_short *) dst; 3041 volatile u_short *const s = 3042 (u_short *) sc->hpp_mem_start; 3043 u_short *const fence = d + (amount >> 1); 3044 3045 /* Copy out NIC data. */ 3046 3047 while (d < fence) 3048 *d++ = *s; 3049 3050 dst += (amount & ~1); 3051 amount &= 1; 3052 } 3053 3054 /* 3055 * read in a byte; however we need to always read 16 bits 3056 * at a time or the hardware gets into a funny state 3057 */ 3058 3059 if (amount == 1) { 3060 /* need to read in a short and copy LSB */ 3061 volatile u_short *const s = 3062 (volatile u_short *) sc->hpp_mem_start; 3063 3064 *dst = (*s) & 0xFF; 3065 } 3066 3067 /* Restore Boot ROM access. */ 3068 3069 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options); 3070 3071 3072 } else { 3073 /* Read in data using the I/O port */ 3074 if (use_32bit_access && (amount > 3)) { 3075 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2); 3076 dst += (amount & ~3); 3077 amount &= 3; 3078 } 3079 if (amount > 1) { 3080 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1); 3081 dst += (amount & ~1); 3082 amount &= 1; 3083 } 3084 if (amount == 1) { /* read in a short and keep the LSB */ 3085 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF; 3086 } 3087 } 3088 } 3089 3090 /* 3091 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped 3092 * IO. 3093 * Only used in the probe routine to test the memory. 'len' must 3094 * be even. 3095 */ 3096 static void 3097 ed_hpp_writemem(struct ed_softc *sc, u_char *src, u_short dst, u_short len) 3098 { 3099 /* reset remote DMA complete flag */ 3100 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 3101 3102 /* program the write address in RAM */ 3103 ed_asic_outw(sc, ED_HPP_PAGE_0, dst); 3104 3105 if (sc->hpp_mem_start) { 3106 u_short *s = (u_short *) src; 3107 volatile u_short *d = (u_short *) sc->hpp_mem_start; 3108 u_short *const fence = s + (len >> 1); 3109 3110 /* 3111 * Enable memory mapped access. 3112 */ 3113 3114 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options & 3115 ~(ED_HPP_OPTION_MEM_DISABLE | 3116 ED_HPP_OPTION_BOOT_ROM_ENB)); 3117 3118 /* 3119 * Copy to NIC memory. 3120 */ 3121 3122 while (s < fence) 3123 *d = *s++; 3124 3125 /* 3126 * Restore Boot ROM access. 3127 */ 3128 3129 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options); 3130 3131 } else { 3132 /* write data using I/O writes */ 3133 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2); 3134 } 3135 } 3136 3137 /* 3138 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3139 * outsw() or via the memory mapped interface to the same register. 3140 * Writes have to be in word units; byte accesses won't work and may cause 3141 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC 3142 * allows it. 3143 */ 3144 3145 static u_short 3146 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3147 { 3148 int len, wantbyte; 3149 u_short total_len; 3150 u_char savebyte[2]; 3151 volatile u_short * const d = 3152 (volatile u_short *) sc->hpp_mem_start; 3153 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3154 3155 /* select page 0 registers */ 3156 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 3157 3158 /* reset remote DMA complete flag */ 3159 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC); 3160 3161 /* program the write address in RAM */ 3162 ed_asic_outw(sc, ED_HPP_PAGE_0, dst); 3163 3164 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3165 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options & 3166 ~(ED_HPP_OPTION_MEM_DISABLE | 3167 ED_HPP_OPTION_BOOT_ROM_ENB)); 3168 3169 wantbyte = 0; 3170 total_len = 0; 3171 3172 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3173 while (m) { 3174 total_len += (len = m->m_len); 3175 if (len) { 3176 caddr_t data = mtod(m, caddr_t); 3177 /* finish the last word of the previous mbuf */ 3178 if (wantbyte) { 3179 savebyte[1] = *data; 3180 *d = *((u_short *) savebyte); 3181 data++; len--; wantbyte = 0; 3182 } 3183 /* output contiguous words */ 3184 if ((len > 3) && (use_32bit_accesses)) { 3185 volatile u_int32_t *const dl = 3186 (volatile u_int32_t *) d; 3187 u_int32_t *sl = (u_int32_t *) data; 3188 u_int32_t *fence = sl + (len >> 2); 3189 3190 while (sl < fence) 3191 *dl = *sl++; 3192 3193 data += (len & ~3); 3194 len &= 3; 3195 } 3196 /* finish off remain 16 bit writes */ 3197 if (len > 1) { 3198 u_short *s = (u_short *) data; 3199 u_short *fence = s + (len >> 1); 3200 3201 while (s < fence) 3202 *d = *s++; 3203 3204 data += (len & ~1); 3205 len &= 1; 3206 } 3207 /* save last byte if needed */ 3208 if ((wantbyte = (len == 1)) != 0) 3209 savebyte[0] = *data; 3210 } 3211 m = m->m_next; /* to next mbuf */ 3212 } 3213 if (wantbyte) /* write last byte */ 3214 *d = *((u_short *) savebyte); 3215 } else { 3216 /* use programmed I/O */ 3217 while (m) { 3218 total_len += (len = m->m_len); 3219 if (len) { 3220 caddr_t data = mtod(m, caddr_t); 3221 /* finish the last word of the previous mbuf */ 3222 if (wantbyte) { 3223 savebyte[1] = *data; 3224 ed_asic_outw(sc, ED_HPP_PAGE_4, 3225 *((u_short *)savebyte)); 3226 data++; 3227 len--; 3228 wantbyte = 0; 3229 } 3230 /* output contiguous words */ 3231 if ((len > 3) && use_32bit_accesses) { 3232 ed_asic_outsl(sc, ED_HPP_PAGE_4, 3233 data, len >> 2); 3234 data += (len & ~3); 3235 len &= 3; 3236 } 3237 /* finish off remaining 16 bit accesses */ 3238 if (len > 1) { 3239 ed_asic_outsw(sc, ED_HPP_PAGE_4, 3240 data, len >> 1); 3241 data += (len & ~1); 3242 len &= 1; 3243 } 3244 if ((wantbyte = (len == 1)) != 0) 3245 savebyte[0] = *data; 3246 3247 } /* if len != 0 */ 3248 m = m->m_next; 3249 } 3250 if (wantbyte) /* spit last byte */ 3251 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte); 3252 3253 } 3254 3255 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3256 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options); 3257 3258 return (total_len); 3259 } 3260 3261 #ifndef ED_NO_MIIBUS 3262 /* 3263 * MII bus support routines. 3264 */ 3265 int 3266 ed_miibus_readreg(device_t dev, int phy, int reg) 3267 { 3268 struct ed_softc *sc = device_get_softc(dev); 3269 int failed, val; 3270 3271 crit_enter(); 3272 3273 if (sc->gone) { 3274 crit_exit(); 3275 return (0); 3276 } 3277 3278 (*sc->mii_writebits)(sc, 0xffffffff, 32); 3279 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS); 3280 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS); 3281 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); 3282 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); 3283 3284 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS); 3285 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS); 3286 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS); 3287 3288 crit_exit(); 3289 3290 return (failed ? 0 : val); 3291 } 3292 3293 void 3294 ed_miibus_writereg(device_t dev, int phy, int reg, int data) 3295 { 3296 struct ed_softc *sc = device_get_softc(dev); 3297 3298 crit_enter(); 3299 3300 if (sc->gone) { 3301 crit_exit(); 3302 return; 3303 } 3304 3305 (*sc->mii_writebits)(sc, 0xffffffff, 32); 3306 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS); 3307 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS); 3308 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS); 3309 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS); 3310 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS); 3311 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS); 3312 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS); 3313 3314 crit_exit(); 3315 } 3316 3317 int 3318 ed_ifmedia_upd(struct ifnet *ifp) 3319 { 3320 struct ed_softc *sc; 3321 struct mii_data *mii; 3322 3323 sc = ifp->if_softc; 3324 if (sc->gone || sc->miibus == NULL) 3325 return (ENXIO); 3326 3327 mii = device_get_softc(sc->miibus); 3328 return mii_mediachg(mii); 3329 } 3330 3331 void 3332 ed_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3333 { 3334 struct ed_softc *sc; 3335 struct mii_data *mii; 3336 3337 sc = ifp->if_softc; 3338 if (sc->gone || sc->miibus == NULL) 3339 return; 3340 3341 mii = device_get_softc(sc->miibus); 3342 mii_pollstat(mii); 3343 ifmr->ifm_active = mii->mii_media_active; 3344 ifmr->ifm_status = mii->mii_media_status; 3345 } 3346 3347 void 3348 ed_child_detached(device_t dev, device_t child) 3349 { 3350 struct ed_softc *sc; 3351 3352 sc = device_get_softc(dev); 3353 if (child == sc->miibus) 3354 sc->miibus = NULL; 3355 } 3356 #endif 3357 3358 static void 3359 ed_setrcr(struct ed_softc *sc) 3360 { 3361 struct ifnet *ifp = (struct ifnet *)sc; 3362 int i; 3363 u_char reg1; 3364 3365 /* Bit 6 in AX88190 RCR register must be set. */ 3366 if (sc->chip_type == ED_CHIP_TYPE_AX88190) 3367 reg1 = ED_RCR_INTT; 3368 else 3369 reg1 = 0x00; 3370 3371 /* set page 1 registers */ 3372 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3373 3374 if (ifp->if_flags & IFF_PROMISC) { 3375 3376 /* 3377 * Reconfigure the multicast filter. 3378 */ 3379 for (i = 0; i < 8; i++) 3380 ed_nic_outb(sc, ED_P1_MAR(i), 0xff); 3381 3382 /* 3383 * And turn on promiscuous mode. Also enable reception of 3384 * runts and packets with CRC & alignment errors. 3385 */ 3386 /* Set page 0 registers */ 3387 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 3388 3389 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3390 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1); 3391 } else { 3392 /* set up multicast addresses and filter modes */ 3393 if (ifp->if_flags & IFF_MULTICAST) { 3394 u_int32_t mcaf[2]; 3395 3396 if (ifp->if_flags & IFF_ALLMULTI) { 3397 mcaf[0] = 0xffffffff; 3398 mcaf[1] = 0xffffffff; 3399 } else 3400 ds_getmcaf(sc, mcaf); 3401 3402 /* 3403 * Set multicast filter on chip. 3404 */ 3405 for (i = 0; i < 8; i++) 3406 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]); 3407 3408 /* Set page 0 registers */ 3409 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 3410 3411 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1); 3412 } else { 3413 3414 /* 3415 * Initialize multicast address hashing registers to 3416 * not accept multicasts. 3417 */ 3418 for (i = 0; i < 8; ++i) 3419 ed_nic_outb(sc, ED_P1_MAR(i), 0x00); 3420 3421 /* Set page 0 registers */ 3422 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP); 3423 3424 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1); 3425 } 3426 } 3427 3428 /* 3429 * Start interface. 3430 */ 3431 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA); 3432 } 3433 3434 /* 3435 * Compute crc for ethernet address 3436 */ 3437 static uint32_t 3438 ds_mchash(const uint8_t *addr) 3439 { 3440 #define ED_POLYNOMIAL 0x04c11db6 3441 uint32_t crc = 0xffffffff; 3442 int carry, idx, bit; 3443 uint8_t data; 3444 3445 for (idx = 6; --idx >= 0;) { 3446 for (data = *addr++, bit = 8; --bit >= 0; data >>=1 ) { 3447 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 3448 crc <<= 1; 3449 if (carry) 3450 crc = (crc ^ ED_POLYNOMIAL) | carry; 3451 } 3452 } 3453 return crc; 3454 #undef POLYNOMIAL 3455 } 3456 3457 /* 3458 * Compute the multicast address filter from the 3459 * list of multicast addresses we need to listen to. 3460 */ 3461 static void 3462 ds_getmcaf(struct ed_softc *sc, u_int32_t *mcaf) 3463 { 3464 u_int32_t index; 3465 u_char *af = (u_char *) mcaf; 3466 struct ifmultiaddr *ifma; 3467 3468 mcaf[0] = 0; 3469 mcaf[1] = 0; 3470 3471 TAILQ_FOREACH(ifma, &sc->arpcom.ac_if.if_multiaddrs, ifma_link) { 3472 if (ifma->ifma_addr->sa_family != AF_LINK) 3473 continue; 3474 index = ds_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3475 >> 26; 3476 af[index >> 3] |= 1 << (index & 7); 3477 } 3478 }
Cache object: 6385189f39d62275df4782261117d019
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