The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/netif/ex/if_exreg.h

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    1 /*
    2  * Copyright (c) 1996, Javier Martín Rueda (jmrueda@diatel.upm.es)
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD: src/sys/dev/ex/if_exreg.h,v 1.1.10.2 2001/03/05 05:33:20 imp Exp $
   28  * $DragonFly: src/sys/dev/netif/ex/if_exreg.h,v 1.2 2003/06/17 04:28:25 dillon Exp $
   29  */
   30 
   31 /*
   32  * Intel EtherExpress Pro/10 Ethernet driver
   33  */
   34 
   35 /*
   36  * Several constants.
   37  */
   38 
   39 #define CARD_TYPE_EX_10         1
   40 #define CARD_TYPE_EX_10_PLUS    2
   41 
   42 /* Length of an ethernet address. */
   43 #define ETHER_ADDR_LEN 6
   44 /* Default RAM size in board. */
   45 #define CARD_RAM_SIZE 0x8000
   46 /* Number of I/O ports used. */
   47 #define EX_IOSIZE 16
   48 
   49 /*
   50  * Intel EtherExpress Pro (i82595 based) registers
   51  */
   52 
   53 /* Common registers to all banks. */
   54 
   55 #define CMD_REG 0
   56 #define REG1 1
   57 #define REG2 2
   58 #define REG3 3
   59 #define REG4 4
   60 #define REG5 5
   61 #define REG6 6
   62 #define REG7 7
   63 #define REG8 8
   64 #define REG9 9
   65 #define REG10 10
   66 #define REG11 11
   67 #define REG12 12
   68 #define REG13 13
   69 #define REG14 14
   70 #define REG15 15
   71 
   72 /* Definitions for command register (CMD_REG). */
   73 
   74 #define Switch_Bank_CMD 0
   75 #define MC_Setup_CMD 3
   76 #define Transmit_CMD 4
   77 #define Diagnose_CMD 7
   78 #define Rcv_Enable_CMD 8
   79 #define Rcv_Stop 11
   80 #define Reset_CMD 14
   81 #define Resume_XMT_List_CMD 28
   82 #define Sel_Reset_CMD 30
   83 #define Abort 0x20
   84 #define Bank0_Sel 0x00
   85 #define Bank1_Sel 0x40
   86 #define Bank2_Sel 0x80
   87 
   88 /* Bank 0 specific registers. */
   89 
   90 #define STATUS_REG 1
   91 #define ID_REG 2
   92 #define Id_Mask 0x2c
   93 #define Id_Sig 0x24
   94 #define Counter_bits 0xc0
   95 #define MASK_REG 3
   96 #define Exec_Int 0x08
   97 #define Tx_Int 0x04
   98 #define Rx_Int 0x02
   99 #define Rx_Stp_Int 0x01
  100 #define All_Int 0x0f
  101 #define RCV_BAR 4
  102 #define RCV_BAR_Lo 4
  103 #define RCV_BAR_Hi 5
  104 #define RCV_STOP_REG 6
  105 #define XMT_BAR 10
  106 #define HOST_ADDR_REG 12        /* 16-bit register */
  107 #define IO_PORT_REG 14  /* 16-bit register */
  108 
  109 /* Bank 1 specific registers. */
  110 
  111 #define TriST_INT 0x80
  112 #define INT_NO_REG 2
  113 #define RCV_LOWER_LIMIT_REG 8
  114 #define RCV_UPPER_LIMIT_REG 9
  115 #define XMT_LOWER_LIMIT_REG 10
  116 #define XMT_UPPER_LIMIT_REG 11
  117 
  118 /* Bank 2 specific registers. */
  119 
  120 #define Disc_Bad_Fr 0x80
  121 #define Tx_Chn_ErStp 0x40
  122 #define Tx_Chn_Int_Md 0x20
  123 #define No_SA_Ins 0x10
  124 #define RX_CRC_InMem 0x04
  125 #define BNC_bit 0x20
  126 #define TPE_bit 0x04
  127 #define I_ADDR_REG0 4
  128 #define EEPROM_REG 10
  129 #define Trnoff_Enable 0x10
  130 
  131 /* EEPROM memory positions (16-bit wide). */
  132 
  133 #define EE_W0                   0x00
  134 # define EE_W0_PNP              0x0001
  135 # define EE_W0_BUS16            0x0004
  136 # define EE_W0_FLASH_ADDR_MASK  0x0038
  137 # define EE_W0_FLASH_ADDR_SHIFT 3
  138 # define EE_W0_AUTO_IO          0x0040
  139 # define EE_W0_FLASH            0x0100
  140 # define EE_W0_AUTO_NEG         0x0200
  141 # define EE_W0_IO_MASK          0xFC00
  142 # define EE_W0_IO_SHIFT         10
  143 
  144 #define EE_IRQ_No 1
  145 #define IRQ_No_Mask 0x07
  146 
  147 #define EE_W1                   0x01
  148 # define EE_W1_INT_SEL          0x0007
  149 # define EE_W1_NO_LINK_INT      0x0008  /* Link Integrity Off           */
  150 # define EE_W1_NO_POLARITY      0x0010  /* Polarity Correction Off      */
  151 # define EE_W1_TPE_AUI          0x0020  /* 1 = TPE, 0 = AUI             */
  152 # define EE_W1_NO_JABBER_PREV   0x0040  /* Jabber prevention Off        */
  153 # define EE_W1_NO_AUTO_SELECT   0x0080  /* Auto Port Selection Off      */
  154 # define EE_W1_SMOUT            0x0100  /* SMout Pin Control 0= Input   */
  155 # define EE_W1_PROM             0x0200  /* Flash = 0, PROM = 1          */
  156 # define EE_W1_ALT_READY        0x2000  /* Alternate Ready, 0=normal    */
  157 # define EE_W1_FULL_DUPLEX      0x8000
  158 
  159 #define EE_W2                   0x02
  160 #define EE_W3                   0x03
  161 #define EE_W4                   0x04
  162 
  163 #define EE_Eth_Addr_Lo 2
  164 #define EE_Eth_Addr_Mid 3
  165 #define EE_Eth_Addr_Hi 4
  166 
  167 #define EE_W5                   0x05
  168 # define EE_W5_BNC_TPE          0x0001  /* 0 = TPE, 1 = BNC             */
  169 # define EE_W5_BOOT_IPX         0x0002
  170 # define EE_W5_BOOT_ODI         0x0004
  171 # define EE_W5_BOOT_NDIS        (EE_W5_BOOT_IPX|EE_W5_BOOT_ODI)
  172 # define EE_W5_NUM_CONN         0x0008  /* 0 = 2, 1 = 3                 */
  173 # define EE_W5_NOFLASH          0x0010  /* No flash socket present      */
  174 # define EE_W5_PORT_TPE         0x0020  /* TPE present                  */
  175 # define EE_W5_PORT_BNC         0x0040  /* BNC present                  */
  176 # define EE_W5_PORT_AUI         0x0080  /* AUI present                  */
  177 # define EE_W5_PWR_MGT          0x0100  /* Power Management             */
  178 # define EE_W5_CP               0x0200  /* COncurrent Processing        */
  179 
  180 #define EE_W6                   0x05
  181 # define EE_W6_STEP_MASK        0x000F
  182 # define EE_W6_BOARD_MASK       0xFFF0
  183 # define EE_W6_BOARD_SHIFT      4
  184 
  185 /* EEPROM serial interface. */
  186 
  187 #define EESK 0x01
  188 #define EECS 0x02
  189 #define EEDI 0x04
  190 #define EEDO 0x08
  191 #define EE_READ_CMD (6 << 6)
  192 
  193 /* Frame chain constants. */
  194 
  195 /* Transmit header length (in board's ring buffer). */
  196 #define XMT_HEADER_LEN 8
  197 #define XMT_Chain_Point 4
  198 #define XMT_Byte_Count 6
  199 #define Done_bit 0x0080
  200 #define Ch_bit 0x8000
  201 /* Transmit result bits. */
  202 #define No_Collisions_bits 0x000f
  203 #define TX_OK_bit 0x2000
  204 /* Receive result bits. */
  205 #define RCV_Done 8
  206 #define RCV_OK_bit 0x2000

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