Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/netif/fxp/if_fxpreg.h
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1 /* 2 * Copyright (c) 1995, David Greenman 3 * Copyright (c) 2001 Jonathan Lemon <jlemon@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice unmodified, this list of conditions, and the following 11 * disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD: src/sys/dev/fxp/if_fxpreg.h,v 1.23.2.5 2001/11/02 16:50:41 jlemon Exp $ 29 * $DragonFly: src/sys/dev/netif/fxp/if_fxpreg.h,v 1.2 2003/06/17 04:28:26 dillon Exp $ 30 */ 31 32 #define FXP_VENDORID_INTEL 0x8086 33 34 #define FXP_PCI_MMBA 0x10 35 #define FXP_PCI_IOBA 0x14 36 37 /* 38 * Control/status registers. 39 */ 40 #define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 41 #define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 42 #define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 43 #define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 44 #define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 45 #define FXP_CSR_PORT 8 /* port (4 bytes) */ 46 #define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 47 #define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 48 #define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 49 #define FXP_CSR_FLOWCONTROL 0x19 /* flow control (2 bytes) */ 50 #define FXP_CSR_GENCONTROL 0x1C /* general control (1 byte) */ 51 52 /* 53 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 54 * 55 * volatile u_int8_t :2, 56 * scb_rus:4, 57 * scb_cus:2; 58 */ 59 60 #define FXP_PORT_SOFTWARE_RESET 0 61 #define FXP_PORT_SELFTEST 1 62 #define FXP_PORT_SELECTIVE_RESET 2 63 #define FXP_PORT_DUMP 3 64 65 #define FXP_SCB_RUS_IDLE 0 66 #define FXP_SCB_RUS_SUSPENDED 1 67 #define FXP_SCB_RUS_NORESOURCES 2 68 #define FXP_SCB_RUS_READY 4 69 #define FXP_SCB_RUS_SUSP_NORBDS 9 70 #define FXP_SCB_RUS_NORES_NORBDS 10 71 #define FXP_SCB_RUS_READY_NORBDS 12 72 73 #define FXP_SCB_CUS_IDLE 0 74 #define FXP_SCB_CUS_SUSPENDED 1 75 #define FXP_SCB_CUS_ACTIVE 2 76 77 #define FXP_SCB_INTR_DISABLE 0x01 /* Disable all interrupts */ 78 #define FXP_SCB_INTR_SWI 0x02 /* Generate SWI */ 79 #define FXP_SCB_INTMASK_FCP 0x04 80 #define FXP_SCB_INTMASK_ER 0x08 81 #define FXP_SCB_INTMASK_RNR 0x10 82 #define FXP_SCB_INTMASK_CNA 0x20 83 #define FXP_SCB_INTMASK_FR 0x40 84 #define FXP_SCB_INTMASK_CXTNO 0x80 85 86 #define FXP_SCB_STATACK_FCP 0x01 /* Flow Control Pause */ 87 #define FXP_SCB_STATACK_ER 0x02 /* Early Receive */ 88 #define FXP_SCB_STATACK_SWI 0x04 89 #define FXP_SCB_STATACK_MDI 0x08 90 #define FXP_SCB_STATACK_RNR 0x10 91 #define FXP_SCB_STATACK_CNA 0x20 92 #define FXP_SCB_STATACK_FR 0x40 93 #define FXP_SCB_STATACK_CXTNO 0x80 94 95 #define FXP_SCB_COMMAND_CU_NOP 0x00 96 #define FXP_SCB_COMMAND_CU_START 0x10 97 #define FXP_SCB_COMMAND_CU_RESUME 0x20 98 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 99 #define FXP_SCB_COMMAND_CU_DUMP 0x50 100 #define FXP_SCB_COMMAND_CU_BASE 0x60 101 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 102 103 #define FXP_SCB_COMMAND_RU_NOP 0 104 #define FXP_SCB_COMMAND_RU_START 1 105 #define FXP_SCB_COMMAND_RU_RESUME 2 106 #define FXP_SCB_COMMAND_RU_ABORT 4 107 #define FXP_SCB_COMMAND_RU_LOADHDS 5 108 #define FXP_SCB_COMMAND_RU_BASE 6 109 #define FXP_SCB_COMMAND_RU_RBDRESUME 7 110 111 /* 112 * Command block definitions 113 */ 114 struct fxp_cb_nop { 115 void *fill[2]; 116 volatile u_int16_t cb_status; 117 volatile u_int16_t cb_command; 118 volatile u_int32_t link_addr; 119 }; 120 struct fxp_cb_ias { 121 void *fill[2]; 122 volatile u_int16_t cb_status; 123 volatile u_int16_t cb_command; 124 volatile u_int32_t link_addr; 125 volatile u_int8_t macaddr[6]; 126 }; 127 /* I hate bit-fields :-( */ 128 struct fxp_cb_config { 129 void *fill[2]; 130 volatile u_int16_t cb_status; 131 volatile u_int16_t cb_command; 132 volatile u_int32_t link_addr; 133 volatile u_int byte_count:6, 134 :2; 135 volatile u_int rx_fifo_limit:4, 136 tx_fifo_limit:3, 137 :1; 138 volatile u_int8_t adaptive_ifs; 139 volatile u_int mwi_enable:1, /* 8,9 */ 140 type_enable:1, /* 8,9 */ 141 read_align_en:1, /* 8,9 */ 142 end_wr_on_cl:1, /* 8,9 */ 143 :4; 144 volatile u_int rx_dma_bytecount:7, 145 :1; 146 volatile u_int tx_dma_bytecount:7, 147 dma_mbce:1; 148 volatile u_int late_scb:1, /* 7 */ 149 direct_dma_dis:1, /* 8,9 */ 150 tno_int_or_tco_en:1, /* 7,9 */ 151 ci_int:1, 152 ext_txcb_dis:1, /* 8,9 */ 153 ext_stats_dis:1, /* 8,9 */ 154 keep_overrun_rx:1, 155 save_bf:1; 156 volatile u_int disc_short_rx:1, 157 underrun_retry:2, 158 :3, 159 two_frames:1, /* 8,9 */ 160 dyn_tbd:1; /* 8,9 */ 161 volatile u_int mediatype:1, /* 7 */ 162 :6, 163 csma_dis:1; /* 8,9 */ 164 volatile u_int tcp_udp_cksum:1, /* 9 */ 165 :3, 166 vlan_tco:1, /* 8,9 */ 167 link_wake_en:1, /* 8,9 */ 168 arp_wake_en:1, /* 8 */ 169 mc_wake_en:1; /* 8 */ 170 volatile u_int :3, 171 nsai:1, 172 preamble_length:2, 173 loopback:2; 174 volatile u_int linear_priority:3, /* 7 */ 175 :5; 176 volatile u_int linear_pri_mode:1, /* 7 */ 177 :3, 178 interfrm_spacing:4; 179 volatile u_int :8; 180 volatile u_int :8; 181 volatile u_int promiscuous:1, 182 bcast_disable:1, 183 wait_after_win:1, /* 8,9 */ 184 :1, 185 ignore_ul:1, /* 8,9 */ 186 crc16_en:1, /* 9 */ 187 :1, 188 crscdt:1; 189 volatile u_int fc_delay_lsb:8; /* 8,9 */ 190 volatile u_int fc_delay_msb:8; /* 8,9 */ 191 volatile u_int stripping:1, 192 padding:1, 193 rcv_crc_xfer:1, 194 long_rx_en:1, /* 8,9 */ 195 pri_fc_thresh:3, /* 8,9 */ 196 :1; 197 volatile u_int ia_wake_en:1, /* 8 */ 198 magic_pkt_dis:1, /* 8,9,!9ER */ 199 tx_fc_dis:1, /* 8,9 */ 200 rx_fc_restop:1, /* 8,9 */ 201 rx_fc_restart:1, /* 8,9 */ 202 fc_filter:1, /* 8,9 */ 203 force_fdx:1, 204 fdx_pin_en:1; 205 volatile u_int :5, 206 pri_fc_loc:1, /* 8,9 */ 207 multi_ia:1, 208 :1; 209 volatile u_int :3, 210 mc_all:1, 211 :4; 212 }; 213 214 #define MAXMCADDR 80 215 struct fxp_cb_mcs { 216 struct fxp_cb_tx *next; 217 struct mbuf *mb_head; 218 volatile u_int16_t cb_status; 219 volatile u_int16_t cb_command; 220 volatile u_int32_t link_addr; 221 volatile u_int16_t mc_cnt; 222 volatile u_int8_t mc_addr[MAXMCADDR][6]; 223 }; 224 225 #define MAXUCODESIZE 192 226 struct fxp_cb_ucode { 227 void *fill[2]; 228 u_int16_t cb_status; 229 u_int16_t cb_command; 230 u_int32_t link_addr; 231 u_int32_t ucode[MAXUCODESIZE]; 232 }; 233 234 /* 235 * Number of DMA segments in a TxCB. Note that this is carefully 236 * chosen to make the total struct size an even power of two. It's 237 * critical that no TxCB be split across a page boundry since 238 * no attempt is made to allocate physically contiguous memory. 239 */ 240 #define FXP_TXCB_FIXED 16 /* cb_status .. tbd_number */ 241 #define FXP_NTXSEG ((256 - (sizeof(void *) * 2) - FXP_TXCB_FIXED) / 8) 242 243 struct fxp_tbd { 244 volatile u_int32_t tb_addr; 245 volatile u_int32_t tb_size; 246 }; 247 struct fxp_cb_tx { 248 struct fxp_cb_tx *next; 249 struct mbuf *mb_head; 250 volatile u_int16_t cb_status; 251 volatile u_int16_t cb_command; 252 volatile u_int32_t link_addr; 253 volatile u_int32_t tbd_array_addr; 254 volatile u_int16_t byte_count; 255 volatile u_int8_t tx_threshold; 256 volatile u_int8_t tbd_number; 257 /* 258 * The following structure isn't actually part of the TxCB, 259 * unless the extended TxCB feature is being used. In this 260 * case, the first two elements of the structure below are 261 * fetched along with the TxCB. 262 */ 263 volatile struct fxp_tbd tbd[FXP_NTXSEG]; 264 }; 265 266 /* 267 * Control Block (CB) definitions 268 */ 269 270 /* status */ 271 #define FXP_CB_STATUS_OK 0x2000 272 #define FXP_CB_STATUS_C 0x8000 273 /* commands */ 274 #define FXP_CB_COMMAND_NOP 0x0 275 #define FXP_CB_COMMAND_IAS 0x1 276 #define FXP_CB_COMMAND_CONFIG 0x2 277 #define FXP_CB_COMMAND_MCAS 0x3 278 #define FXP_CB_COMMAND_XMIT 0x4 279 #define FXP_CB_COMMAND_UCODE 0x5 280 #define FXP_CB_COMMAND_DUMP 0x6 281 #define FXP_CB_COMMAND_DIAG 0x7 282 /* command flags */ 283 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 284 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 285 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 286 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 287 288 /* 289 * RFA definitions 290 */ 291 292 struct fxp_rfa { 293 volatile u_int16_t rfa_status; 294 volatile u_int16_t rfa_control; 295 volatile u_int8_t link_addr[4]; 296 volatile u_int8_t rbd_addr[4]; 297 volatile u_int16_t actual_size; 298 volatile u_int16_t size; 299 }; 300 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 301 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 302 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 303 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 304 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 305 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 306 #define FXP_RFA_STATUS_RNR 0x0200 /* no resources */ 307 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 308 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 309 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 310 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 311 #define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 312 #define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 313 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 314 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 315 316 /* 317 * Statistics dump area definitions 318 */ 319 struct fxp_stats { 320 volatile u_int32_t tx_good; 321 volatile u_int32_t tx_maxcols; 322 volatile u_int32_t tx_latecols; 323 volatile u_int32_t tx_underruns; 324 volatile u_int32_t tx_lostcrs; 325 volatile u_int32_t tx_deffered; 326 volatile u_int32_t tx_single_collisions; 327 volatile u_int32_t tx_multiple_collisions; 328 volatile u_int32_t tx_total_collisions; 329 volatile u_int32_t rx_good; 330 volatile u_int32_t rx_crc_errors; 331 volatile u_int32_t rx_alignment_errors; 332 volatile u_int32_t rx_rnr_errors; 333 volatile u_int32_t rx_overrun_errors; 334 volatile u_int32_t rx_cdt_errors; 335 volatile u_int32_t rx_shortframes; 336 volatile u_int32_t completion_status; 337 }; 338 #define FXP_STATS_DUMP_COMPLETE 0xa005 339 #define FXP_STATS_DR_COMPLETE 0xa007 340 341 /* 342 * Serial EEPROM control register bits 343 */ 344 #define FXP_EEPROM_EESK 0x01 /* shift clock */ 345 #define FXP_EEPROM_EECS 0x02 /* chip select */ 346 #define FXP_EEPROM_EEDI 0x04 /* data in */ 347 #define FXP_EEPROM_EEDO 0x08 /* data out */ 348 349 /* 350 * Serial EEPROM opcodes, including start bit 351 */ 352 #define FXP_EEPROM_OPC_ERASE 0x4 353 #define FXP_EEPROM_OPC_WRITE 0x5 354 #define FXP_EEPROM_OPC_READ 0x6 355 356 /* 357 * Management Data Interface opcodes 358 */ 359 #define FXP_MDI_WRITE 0x1 360 #define FXP_MDI_READ 0x2 361 362 /* 363 * PHY device types 364 */ 365 #define FXP_PHY_DEVICE_MASK 0x3f00 366 #define FXP_PHY_SERIAL_ONLY 0x8000 367 #define FXP_PHY_NONE 0 368 #define FXP_PHY_82553A 1 369 #define FXP_PHY_82553C 2 370 #define FXP_PHY_82503 3 371 #define FXP_PHY_DP83840 4 372 #define FXP_PHY_80C240 5 373 #define FXP_PHY_80C24 6 374 #define FXP_PHY_82555 7 375 #define FXP_PHY_DP83840A 10 376 #define FXP_PHY_82555B 11 377 378 /* 379 * Chip revision values. 380 */ 381 #define FXP_REV_82557 1 /* catchall 82557 chip type */ 382 #define FXP_REV_82558_A4 4 /* 82558 A4 stepping */ 383 #define FXP_REV_82558_B0 5 /* 82558 B0 stepping */ 384 #define FXP_REV_82559_A0 8 /* 82559 A0 stepping */ 385 #define FXP_REV_82559S_A 9 /* 82559S A stepping */ 386 #define FXP_REV_82550 12 387 #define FXP_REV_82550_C 13 /* 82550 C stepping */
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