Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/netif/ig_hal/e1000_80003es2lan.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /****************************************************************************** 2 3 Copyright (c) 2001-2012, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 ******************************************************************************/ 33 /*$FreeBSD:$*/ 34 35 /* 80003ES2LAN Gigabit Ethernet Controller (Copper) 36 * 80003ES2LAN Gigabit Ethernet Controller (Serdes) 37 */ 38 39 #include "e1000_api.h" 40 41 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw); 42 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw); 43 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw); 44 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw); 45 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 46 u32 offset, 47 u16 *data); 48 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 49 u32 offset, 50 u16 data); 51 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 52 u16 words, u16 *data); 53 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw); 54 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw); 55 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw); 56 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 57 u16 *duplex); 58 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw); 59 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw); 60 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw); 61 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw); 62 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 63 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex); 64 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw); 65 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw); 66 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 67 u16 *data); 68 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 69 u16 data); 70 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw); 71 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask); 72 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw); 73 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw); 74 75 /* A table for the GG82563 cable length where the range is defined 76 * with a lower bound at "index" and the upper bound at 77 * "index + 5". 78 */ 79 static const u16 e1000_gg82563_cable_length_table[] = { 80 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF }; 81 #define GG82563_CABLE_LENGTH_TABLE_SIZE \ 82 (sizeof(e1000_gg82563_cable_length_table) / \ 83 sizeof(e1000_gg82563_cable_length_table[0])) 84 85 /** 86 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs. 87 * @hw: pointer to the HW structure 88 **/ 89 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw) 90 { 91 struct e1000_phy_info *phy = &hw->phy; 92 s32 ret_val; 93 94 DEBUGFUNC("e1000_init_phy_params_80003es2lan"); 95 96 if (hw->phy.media_type != e1000_media_type_copper) { 97 phy->type = e1000_phy_none; 98 return E1000_SUCCESS; 99 } else { 100 phy->ops.power_up = e1000_power_up_phy_copper; 101 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; 102 } 103 104 phy->addr = 1; 105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 106 phy->reset_delay_us = 100; 107 phy->type = e1000_phy_gg82563; 108 109 phy->ops.acquire = e1000_acquire_phy_80003es2lan; 110 phy->ops.check_polarity = e1000_check_polarity_m88; 111 phy->ops.check_reset_block = e1000_check_reset_block_generic; 112 phy->ops.commit = e1000_phy_sw_reset_generic; 113 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan; 114 phy->ops.get_info = e1000_get_phy_info_m88; 115 phy->ops.release = e1000_release_phy_80003es2lan; 116 phy->ops.reset = e1000_phy_hw_reset_generic; 117 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; 118 119 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan; 120 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan; 121 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan; 122 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan; 123 124 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan; 125 126 /* This can only be done after all function pointers are setup. */ 127 ret_val = e1000_get_phy_id(hw); 128 129 /* Verify phy id */ 130 if (phy->id != GG82563_E_PHY_ID) 131 return -E1000_ERR_PHY; 132 133 return ret_val; 134 } 135 136 /** 137 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs. 138 * @hw: pointer to the HW structure 139 **/ 140 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw) 141 { 142 struct e1000_nvm_info *nvm = &hw->nvm; 143 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 144 u16 size; 145 146 DEBUGFUNC("e1000_init_nvm_params_80003es2lan"); 147 148 nvm->opcode_bits = 8; 149 nvm->delay_usec = 1; 150 switch (nvm->override) { 151 case e1000_nvm_override_spi_large: 152 nvm->page_size = 32; 153 nvm->address_bits = 16; 154 break; 155 case e1000_nvm_override_spi_small: 156 nvm->page_size = 8; 157 nvm->address_bits = 8; 158 break; 159 default: 160 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 161 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 162 break; 163 } 164 165 nvm->type = e1000_nvm_eeprom_spi; 166 167 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 168 E1000_EECD_SIZE_EX_SHIFT); 169 170 /* Added to a constant, "size" becomes the left-shift value 171 * for setting word_size. 172 */ 173 size += NVM_WORD_SIZE_BASE_SHIFT; 174 175 /* EEPROM access above 16k is unsupported */ 176 if (size > 14) 177 size = 14; 178 nvm->word_size = 1 << size; 179 180 /* Function Pointers */ 181 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan; 182 nvm->ops.read = e1000_read_nvm_eerd; 183 nvm->ops.release = e1000_release_nvm_80003es2lan; 184 nvm->ops.update = e1000_update_nvm_checksum_generic; 185 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 186 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 187 nvm->ops.write = e1000_write_nvm_80003es2lan; 188 189 return E1000_SUCCESS; 190 } 191 192 /** 193 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs. 194 * @hw: pointer to the HW structure 195 **/ 196 static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw) 197 { 198 struct e1000_mac_info *mac = &hw->mac; 199 200 DEBUGFUNC("e1000_init_mac_params_80003es2lan"); 201 202 /* Set media type and media-dependent function pointers */ 203 switch (hw->device_id) { 204 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT: 205 hw->phy.media_type = e1000_media_type_internal_serdes; 206 mac->ops.check_for_link = e1000_check_for_serdes_link_generic; 207 mac->ops.setup_physical_interface = 208 e1000_setup_fiber_serdes_link_generic; 209 break; 210 default: 211 hw->phy.media_type = e1000_media_type_copper; 212 mac->ops.check_for_link = e1000_check_for_copper_link_generic; 213 mac->ops.setup_physical_interface = 214 e1000_setup_copper_link_80003es2lan; 215 break; 216 } 217 218 /* Set mta register count */ 219 mac->mta_reg_count = 128; 220 /* Set rar entry count */ 221 mac->rar_entry_count = E1000_RAR_ENTRIES; 222 /* Set if part includes ASF firmware */ 223 mac->asf_firmware_present = TRUE; 224 /* FWSM register */ 225 mac->has_fwsm = TRUE; 226 /* ARC supported; valid only if manageability features are enabled. */ 227 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) & 228 E1000_FWSM_MODE_MASK); 229 /* Adaptive IFS not supported */ 230 mac->adaptive_ifs = FALSE; 231 232 /* Function pointers */ 233 234 /* bus type/speed/width */ 235 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic; 236 /* reset */ 237 mac->ops.reset_hw = e1000_reset_hw_80003es2lan; 238 /* hw initialization */ 239 mac->ops.init_hw = e1000_init_hw_80003es2lan; 240 /* link setup */ 241 mac->ops.setup_link = e1000_setup_link_generic; 242 /* check management mode */ 243 mac->ops.check_mng_mode = e1000_check_mng_mode_generic; 244 /* multicast address update */ 245 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 246 /* writing VFTA */ 247 mac->ops.write_vfta = e1000_write_vfta_generic; 248 /* clearing VFTA */ 249 mac->ops.clear_vfta = e1000_clear_vfta_generic; 250 /* read mac address */ 251 mac->ops.read_mac_addr = e1000_read_mac_addr_80003es2lan; 252 /* ID LED init */ 253 mac->ops.id_led_init = e1000_id_led_init_generic; 254 /* blink LED */ 255 mac->ops.blink_led = e1000_blink_led_generic; 256 /* setup LED */ 257 mac->ops.setup_led = e1000_setup_led_generic; 258 /* cleanup LED */ 259 mac->ops.cleanup_led = e1000_cleanup_led_generic; 260 /* turn on/off LED */ 261 mac->ops.led_on = e1000_led_on_generic; 262 mac->ops.led_off = e1000_led_off_generic; 263 /* clear hardware counters */ 264 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan; 265 /* link info */ 266 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan; 267 268 /* set lan id for port to determine which phy lock to use */ 269 hw->mac.ops.set_lan_id(hw); 270 271 return E1000_SUCCESS; 272 } 273 274 /** 275 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs. 276 * @hw: pointer to the HW structure 277 * 278 * Called to initialize all function pointers and parameters. 279 **/ 280 void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw) 281 { 282 DEBUGFUNC("e1000_init_function_pointers_80003es2lan"); 283 284 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan; 285 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan; 286 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan; 287 } 288 289 /** 290 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY 291 * @hw: pointer to the HW structure 292 * 293 * A wrapper to acquire access rights to the correct PHY. 294 **/ 295 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) 296 { 297 u16 mask; 298 299 DEBUGFUNC("e1000_acquire_phy_80003es2lan"); 300 301 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 302 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 303 } 304 305 /** 306 * e1000_release_phy_80003es2lan - Release rights to access PHY 307 * @hw: pointer to the HW structure 308 * 309 * A wrapper to release access rights to the correct PHY. 310 **/ 311 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) 312 { 313 u16 mask; 314 315 DEBUGFUNC("e1000_release_phy_80003es2lan"); 316 317 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; 318 e1000_release_swfw_sync_80003es2lan(hw, mask); 319 } 320 321 /** 322 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register 323 * @hw: pointer to the HW structure 324 * 325 * Acquire the semaphore to access the Kumeran interface. 326 * 327 **/ 328 static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw) 329 { 330 u16 mask; 331 332 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan"); 333 334 mask = E1000_SWFW_CSR_SM; 335 336 return e1000_acquire_swfw_sync_80003es2lan(hw, mask); 337 } 338 339 /** 340 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register 341 * @hw: pointer to the HW structure 342 * 343 * Release the semaphore used to access the Kumeran interface 344 **/ 345 static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw) 346 { 347 u16 mask; 348 349 DEBUGFUNC("e1000_release_mac_csr_80003es2lan"); 350 351 mask = E1000_SWFW_CSR_SM; 352 353 e1000_release_swfw_sync_80003es2lan(hw, mask); 354 } 355 356 /** 357 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM 358 * @hw: pointer to the HW structure 359 * 360 * Acquire the semaphore to access the EEPROM. 361 **/ 362 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw) 363 { 364 s32 ret_val; 365 366 DEBUGFUNC("e1000_acquire_nvm_80003es2lan"); 367 368 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 369 if (ret_val) 370 return ret_val; 371 372 ret_val = e1000_acquire_nvm_generic(hw); 373 374 if (ret_val) 375 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 376 377 return ret_val; 378 } 379 380 /** 381 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM 382 * @hw: pointer to the HW structure 383 * 384 * Release the semaphore used to access the EEPROM. 385 **/ 386 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw) 387 { 388 DEBUGFUNC("e1000_release_nvm_80003es2lan"); 389 390 e1000_release_nvm_generic(hw); 391 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM); 392 } 393 394 /** 395 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore 396 * @hw: pointer to the HW structure 397 * @mask: specifies which semaphore to acquire 398 * 399 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 400 * will also specify which port we're acquiring the lock for. 401 **/ 402 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 403 { 404 u32 swfw_sync; 405 u32 swmask = mask; 406 u32 fwmask = mask << 16; 407 s32 i = 0; 408 s32 timeout = 50; 409 410 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan"); 411 412 while (i < timeout) { 413 if (e1000_get_hw_semaphore_generic(hw)) 414 return -E1000_ERR_SWFW_SYNC; 415 416 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 417 if (!(swfw_sync & (fwmask | swmask))) 418 break; 419 420 /* Firmware currently using resource (fwmask) 421 * or other software thread using resource (swmask) 422 */ 423 e1000_put_hw_semaphore_generic(hw); 424 msec_delay_irq(5); 425 i++; 426 } 427 428 if (i == timeout) { 429 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 430 return -E1000_ERR_SWFW_SYNC; 431 } 432 433 swfw_sync |= swmask; 434 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 435 436 e1000_put_hw_semaphore_generic(hw); 437 438 return E1000_SUCCESS; 439 } 440 441 /** 442 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore 443 * @hw: pointer to the HW structure 444 * @mask: specifies which semaphore to acquire 445 * 446 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 447 * will also specify which port we're releasing the lock for. 448 **/ 449 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask) 450 { 451 u32 swfw_sync; 452 453 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan"); 454 455 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS) 456 ; /* Empty */ 457 458 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC); 459 swfw_sync &= ~mask; 460 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync); 461 462 e1000_put_hw_semaphore_generic(hw); 463 } 464 465 /** 466 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register 467 * @hw: pointer to the HW structure 468 * @offset: offset of the register to read 469 * @data: pointer to the data returned from the operation 470 * 471 * Read the GG82563 PHY register. 472 **/ 473 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 474 u32 offset, u16 *data) 475 { 476 s32 ret_val; 477 u32 page_select; 478 u16 temp; 479 480 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan"); 481 482 ret_val = e1000_acquire_phy_80003es2lan(hw); 483 if (ret_val) 484 return ret_val; 485 486 /* Select Configuration Page */ 487 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 488 page_select = GG82563_PHY_PAGE_SELECT; 489 } else { 490 /* Use Alternative Page Select register to access 491 * registers 30 and 31 492 */ 493 page_select = GG82563_PHY_PAGE_SELECT_ALT; 494 } 495 496 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 497 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 498 if (ret_val) { 499 e1000_release_phy_80003es2lan(hw); 500 return ret_val; 501 } 502 503 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 504 /* The "ready" bit in the MDIC register may be incorrectly set 505 * before the device has completed the "Page Select" MDI 506 * transaction. So we wait 200us after each MDI command... 507 */ 508 usec_delay(200); 509 510 /* ...and verify the command was successful. */ 511 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 512 513 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 514 e1000_release_phy_80003es2lan(hw); 515 return -E1000_ERR_PHY; 516 } 517 518 usec_delay(200); 519 520 ret_val = e1000_read_phy_reg_mdic(hw, 521 MAX_PHY_REG_ADDRESS & offset, 522 data); 523 524 usec_delay(200); 525 } else { 526 ret_val = e1000_read_phy_reg_mdic(hw, 527 MAX_PHY_REG_ADDRESS & offset, 528 data); 529 } 530 531 e1000_release_phy_80003es2lan(hw); 532 533 return ret_val; 534 } 535 536 /** 537 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register 538 * @hw: pointer to the HW structure 539 * @offset: offset of the register to read 540 * @data: value to write to the register 541 * 542 * Write to the GG82563 PHY register. 543 **/ 544 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, 545 u32 offset, u16 data) 546 { 547 s32 ret_val; 548 u32 page_select; 549 u16 temp; 550 551 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan"); 552 553 ret_val = e1000_acquire_phy_80003es2lan(hw); 554 if (ret_val) 555 return ret_val; 556 557 /* Select Configuration Page */ 558 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { 559 page_select = GG82563_PHY_PAGE_SELECT; 560 } else { 561 /* Use Alternative Page Select register to access 562 * registers 30 and 31 563 */ 564 page_select = GG82563_PHY_PAGE_SELECT_ALT; 565 } 566 567 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); 568 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp); 569 if (ret_val) { 570 e1000_release_phy_80003es2lan(hw); 571 return ret_val; 572 } 573 574 if (hw->dev_spec._80003es2lan.mdic_wa_enable) { 575 /* The "ready" bit in the MDIC register may be incorrectly set 576 * before the device has completed the "Page Select" MDI 577 * transaction. So we wait 200us after each MDI command... 578 */ 579 usec_delay(200); 580 581 /* ...and verify the command was successful. */ 582 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp); 583 584 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { 585 e1000_release_phy_80003es2lan(hw); 586 return -E1000_ERR_PHY; 587 } 588 589 usec_delay(200); 590 591 ret_val = e1000_write_phy_reg_mdic(hw, 592 MAX_PHY_REG_ADDRESS & offset, 593 data); 594 595 usec_delay(200); 596 } else { 597 ret_val = e1000_write_phy_reg_mdic(hw, 598 MAX_PHY_REG_ADDRESS & offset, 599 data); 600 } 601 602 e1000_release_phy_80003es2lan(hw); 603 604 return ret_val; 605 } 606 607 /** 608 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM 609 * @hw: pointer to the HW structure 610 * @offset: offset of the register to read 611 * @words: number of words to write 612 * @data: buffer of data to write to the NVM 613 * 614 * Write "words" of data to the ESB2 NVM. 615 **/ 616 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset, 617 u16 words, u16 *data) 618 { 619 DEBUGFUNC("e1000_write_nvm_80003es2lan"); 620 621 return e1000_write_nvm_spi(hw, offset, words, data); 622 } 623 624 /** 625 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete 626 * @hw: pointer to the HW structure 627 * 628 * Wait a specific amount of time for manageability processes to complete. 629 * This is a function pointer entry point called by the phy module. 630 **/ 631 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw) 632 { 633 s32 timeout = PHY_CFG_TIMEOUT; 634 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 635 636 DEBUGFUNC("e1000_get_cfg_done_80003es2lan"); 637 638 if (hw->bus.func == 1) 639 mask = E1000_NVM_CFG_DONE_PORT_1; 640 641 while (timeout) { 642 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask) 643 break; 644 msec_delay(1); 645 timeout--; 646 } 647 if (!timeout) { 648 DEBUGOUT("MNG configuration cycle has not completed.\n"); 649 return -E1000_ERR_RESET; 650 } 651 652 return E1000_SUCCESS; 653 } 654 655 /** 656 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex 657 * @hw: pointer to the HW structure 658 * 659 * Force the speed and duplex settings onto the PHY. This is a 660 * function pointer entry point called by the phy module. 661 **/ 662 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw) 663 { 664 s32 ret_val; 665 u16 phy_data; 666 bool link; 667 668 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan"); 669 670 if (!(hw->phy.ops.read_reg)) 671 return E1000_SUCCESS; 672 673 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI 674 * forced whenever speed and duplex are forced. 675 */ 676 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 677 if (ret_val) 678 return ret_val; 679 680 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO; 681 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data); 682 if (ret_val) 683 return ret_val; 684 685 DEBUGOUT1("GG82563 PSCR: %X\n", phy_data); 686 687 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_data); 688 if (ret_val) 689 return ret_val; 690 691 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 692 693 /* Reset the phy to commit changes. */ 694 phy_data |= MII_CR_RESET; 695 696 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data); 697 if (ret_val) 698 return ret_val; 699 700 usec_delay(1); 701 702 if (hw->phy.autoneg_wait_to_complete) { 703 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n"); 704 705 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 706 100000, &link); 707 if (ret_val) 708 return ret_val; 709 710 if (!link) { 711 /* We didn't get link. 712 * Reset the DSP and cross our fingers. 713 */ 714 ret_val = e1000_phy_reset_dsp_generic(hw); 715 if (ret_val) 716 return ret_val; 717 } 718 719 /* Try once more */ 720 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 721 100000, &link); 722 if (ret_val) 723 return ret_val; 724 } 725 726 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 727 &phy_data); 728 if (ret_val) 729 return ret_val; 730 731 /* Resetting the phy means we need to verify the TX_CLK corresponds 732 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz. 733 */ 734 phy_data &= ~GG82563_MSCR_TX_CLK_MASK; 735 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED) 736 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5; 737 else 738 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25; 739 740 /* In addition, we must re-enable CRS on Tx for both half and full 741 * duplex. 742 */ 743 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 744 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, 745 phy_data); 746 747 return ret_val; 748 } 749 750 /** 751 * e1000_get_cable_length_80003es2lan - Set approximate cable length 752 * @hw: pointer to the HW structure 753 * 754 * Find the approximate cable length as measured by the GG82563 PHY. 755 * This is a function pointer entry point called by the phy module. 756 **/ 757 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw) 758 { 759 struct e1000_phy_info *phy = &hw->phy; 760 s32 ret_val; 761 u16 phy_data, index; 762 763 DEBUGFUNC("e1000_get_cable_length_80003es2lan"); 764 765 if (!(hw->phy.ops.read_reg)) 766 return E1000_SUCCESS; 767 768 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data); 769 if (ret_val) 770 return ret_val; 771 772 index = phy_data & GG82563_DSPD_CABLE_LENGTH; 773 774 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) 775 return -E1000_ERR_PHY; 776 777 phy->min_cable_length = e1000_gg82563_cable_length_table[index]; 778 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5]; 779 780 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 781 782 return E1000_SUCCESS; 783 } 784 785 /** 786 * e1000_get_link_up_info_80003es2lan - Report speed and duplex 787 * @hw: pointer to the HW structure 788 * @speed: pointer to speed buffer 789 * @duplex: pointer to duplex buffer 790 * 791 * Retrieve the current speed and duplex configuration. 792 **/ 793 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, 794 u16 *duplex) 795 { 796 s32 ret_val; 797 798 DEBUGFUNC("e1000_get_link_up_info_80003es2lan"); 799 800 if (hw->phy.media_type == e1000_media_type_copper) { 801 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, 802 duplex); 803 hw->phy.ops.cfg_on_link_up(hw); 804 } else { 805 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw, 806 speed, 807 duplex); 808 } 809 810 return ret_val; 811 } 812 813 /** 814 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller 815 * @hw: pointer to the HW structure 816 * 817 * Perform a global reset to the ESB2 controller. 818 **/ 819 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw) 820 { 821 u32 ctrl; 822 s32 ret_val; 823 u16 kum_reg_data; 824 825 DEBUGFUNC("e1000_reset_hw_80003es2lan"); 826 827 /* Prevent the PCI-E bus from sticking if there is no TLP connection 828 * on the last TLP read/write transaction when MAC is reset. 829 */ 830 ret_val = e1000_disable_pcie_master_generic(hw); 831 if (ret_val) 832 DEBUGOUT("PCI-E Master disable polling has failed.\n"); 833 834 DEBUGOUT("Masking off all interrupts\n"); 835 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 836 837 E1000_WRITE_REG(hw, E1000_RCTL, 0); 838 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 839 E1000_WRITE_FLUSH(hw); 840 841 msec_delay(10); 842 843 ctrl = E1000_READ_REG(hw, E1000_CTRL); 844 845 ret_val = e1000_acquire_phy_80003es2lan(hw); 846 if (ret_val) 847 return ret_val; 848 849 DEBUGOUT("Issuing a global reset to MAC\n"); 850 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 851 e1000_release_phy_80003es2lan(hw); 852 853 /* Disable IBIST slave mode (far-end loopback) */ 854 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 855 &kum_reg_data); 856 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 857 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 858 kum_reg_data); 859 860 ret_val = e1000_get_auto_rd_done_generic(hw); 861 if (ret_val) 862 /* We don't want to continue accessing MAC registers. */ 863 return ret_val; 864 865 /* Clear any pending interrupt events. */ 866 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 867 E1000_READ_REG(hw, E1000_ICR); 868 869 return e1000_check_alt_mac_addr_generic(hw); 870 } 871 872 /** 873 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller 874 * @hw: pointer to the HW structure 875 * 876 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters. 877 **/ 878 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw) 879 { 880 struct e1000_mac_info *mac = &hw->mac; 881 u32 reg_data; 882 s32 ret_val; 883 u16 kum_reg_data; 884 u16 i; 885 886 DEBUGFUNC("e1000_init_hw_80003es2lan"); 887 888 e1000_initialize_hw_bits_80003es2lan(hw); 889 890 /* Initialize identification LED */ 891 ret_val = mac->ops.id_led_init(hw); 892 /* An error is not fatal and we should not stop init due to this */ 893 if (ret_val) 894 DEBUGOUT("Error initializing identification LED\n"); 895 896 /* Disabling VLAN filtering */ 897 DEBUGOUT("Initializing the IEEE VLAN\n"); 898 mac->ops.clear_vfta(hw); 899 900 /* Setup the receive address. */ 901 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 902 903 /* Zero out the Multicast HASH table */ 904 DEBUGOUT("Zeroing the MTA\n"); 905 for (i = 0; i < mac->mta_reg_count; i++) 906 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 907 908 /* Setup link and flow control */ 909 ret_val = mac->ops.setup_link(hw); 910 if (ret_val) 911 return ret_val; 912 913 /* Disable IBIST slave mode (far-end loopback) */ 914 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 915 &kum_reg_data); 916 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE; 917 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, 918 kum_reg_data); 919 920 /* Set the transmit descriptor write-back policy */ 921 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0)); 922 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 923 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 924 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data); 925 926 /* ...for both queues. */ 927 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1)); 928 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) | 929 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC; 930 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data); 931 932 /* Enable retransmit on late collisions */ 933 reg_data = E1000_READ_REG(hw, E1000_TCTL); 934 reg_data |= E1000_TCTL_RTLC; 935 E1000_WRITE_REG(hw, E1000_TCTL, reg_data); 936 937 /* Configure Gigabit Carry Extend Padding */ 938 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT); 939 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK; 940 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN; 941 E1000_WRITE_REG(hw, E1000_TCTL_EXT, reg_data); 942 943 /* Configure Transmit Inter-Packet Gap */ 944 reg_data = E1000_READ_REG(hw, E1000_TIPG); 945 reg_data &= ~E1000_TIPG_IPGT_MASK; 946 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 947 E1000_WRITE_REG(hw, E1000_TIPG, reg_data); 948 949 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001); 950 reg_data &= ~0x00100000; 951 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data); 952 953 /* default to TRUE to enable the MDIC W/A */ 954 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE; 955 956 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 957 E1000_KMRNCTRLSTA_OFFSET >> 958 E1000_KMRNCTRLSTA_OFFSET_SHIFT, 959 &i); 960 if (!ret_val) { 961 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) == 962 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO) 963 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE; 964 } 965 966 /* Clear all of the statistics registers (clear on read). It is 967 * important that we do this after we have tried to establish link 968 * because the symbol error count will increment wildly if there 969 * is no link. 970 */ 971 e1000_clear_hw_cntrs_80003es2lan(hw); 972 973 return ret_val; 974 } 975 976 /** 977 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2 978 * @hw: pointer to the HW structure 979 * 980 * Initializes required hardware-dependent bits needed for normal operation. 981 **/ 982 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw) 983 { 984 u32 reg; 985 986 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan"); 987 988 /* Transmit Descriptor Control 0 */ 989 reg = E1000_READ_REG(hw, E1000_TXDCTL(0)); 990 reg |= (1 << 22); 991 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg); 992 993 /* Transmit Descriptor Control 1 */ 994 reg = E1000_READ_REG(hw, E1000_TXDCTL(1)); 995 reg |= (1 << 22); 996 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg); 997 998 /* Transmit Arbitration Control 0 */ 999 reg = E1000_READ_REG(hw, E1000_TARC(0)); 1000 reg &= ~(0xF << 27); /* 30:27 */ 1001 if (hw->phy.media_type != e1000_media_type_copper) 1002 reg &= ~(1 << 20); 1003 E1000_WRITE_REG(hw, E1000_TARC(0), reg); 1004 1005 /* Transmit Arbitration Control 1 */ 1006 reg = E1000_READ_REG(hw, E1000_TARC(1)); 1007 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR) 1008 reg &= ~(1 << 28); 1009 else 1010 reg |= (1 << 28); 1011 E1000_WRITE_REG(hw, E1000_TARC(1), reg); 1012 1013 /* Disable IPv6 extension header parsing because some malformed 1014 * IPv6 headers can hang the Rx. 1015 */ 1016 reg = E1000_READ_REG(hw, E1000_RFCTL); 1017 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); 1018 E1000_WRITE_REG(hw, E1000_RFCTL, reg); 1019 1020 return; 1021 } 1022 1023 /** 1024 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link 1025 * @hw: pointer to the HW structure 1026 * 1027 * Setup some GG82563 PHY registers for obtaining link 1028 **/ 1029 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) 1030 { 1031 struct e1000_phy_info *phy = &hw->phy; 1032 s32 ret_val; 1033 u32 ctrl_ext; 1034 u16 data; 1035 1036 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan"); 1037 1038 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); 1039 if (ret_val) 1040 return ret_val; 1041 1042 data |= GG82563_MSCR_ASSERT_CRS_ON_TX; 1043 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ 1044 data |= GG82563_MSCR_TX_CLK_1000MBPS_25; 1045 1046 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data); 1047 if (ret_val) 1048 return ret_val; 1049 1050 /* Options: 1051 * MDI/MDI-X = 0 (default) 1052 * 0 - Auto for all speeds 1053 * 1 - MDI mode 1054 * 2 - MDI-X mode 1055 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1056 */ 1057 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL, &data); 1058 if (ret_val) 1059 return ret_val; 1060 1061 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK; 1062 1063 switch (phy->mdix) { 1064 case 1: 1065 data |= GG82563_PSCR_CROSSOVER_MODE_MDI; 1066 break; 1067 case 2: 1068 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX; 1069 break; 1070 case 0: 1071 default: 1072 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO; 1073 break; 1074 } 1075 1076 /* Options: 1077 * disable_polarity_correction = 0 (default) 1078 * Automatic Correction for Reversed Cable Polarity 1079 * 0 - Disabled 1080 * 1 - Enabled 1081 */ 1082 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1083 if (phy->disable_polarity_correction) 1084 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE; 1085 1086 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL, data); 1087 if (ret_val) 1088 return ret_val; 1089 1090 /* SW Reset the PHY so all changes take effect */ 1091 ret_val = hw->phy.ops.commit(hw); 1092 if (ret_val) { 1093 DEBUGOUT("Error Resetting the PHY\n"); 1094 return ret_val; 1095 } 1096 1097 /* Bypass Rx and Tx FIFO's */ 1098 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1099 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL, 1100 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS | 1101 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS); 1102 if (ret_val) 1103 return ret_val; 1104 1105 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 1106 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, &data); 1107 if (ret_val) 1108 return ret_val; 1109 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; 1110 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1111 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, data); 1112 if (ret_val) 1113 return ret_val; 1114 1115 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data); 1116 if (ret_val) 1117 return ret_val; 1118 1119 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG; 1120 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_SPEC_CTRL_2, data); 1121 if (ret_val) 1122 return ret_val; 1123 1124 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); 1125 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK); 1126 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext); 1127 1128 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data); 1129 if (ret_val) 1130 return ret_val; 1131 1132 /* Do not init these registers when the HW is in IAMT mode, since the 1133 * firmware will have already initialized them. We only initialize 1134 * them if the HW is not in IAMT mode. 1135 */ 1136 if (!hw->mac.ops.check_mng_mode(hw)) { 1137 /* Enable Electrical Idle on the PHY */ 1138 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE; 1139 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, 1140 data); 1141 if (ret_val) 1142 return ret_val; 1143 1144 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1145 &data); 1146 if (ret_val) 1147 return ret_val; 1148 1149 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1150 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1151 data); 1152 if (ret_val) 1153 return ret_val; 1154 } 1155 1156 /* Workaround: Disable padding in Kumeran interface in the MAC 1157 * and in the PHY to avoid CRC errors. 1158 */ 1159 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_INBAND_CTRL, &data); 1160 if (ret_val) 1161 return ret_val; 1162 1163 data |= GG82563_ICR_DIS_PADDING; 1164 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_INBAND_CTRL, data); 1165 if (ret_val) 1166 return ret_val; 1167 1168 return E1000_SUCCESS; 1169 } 1170 1171 /** 1172 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2 1173 * @hw: pointer to the HW structure 1174 * 1175 * Essentially a wrapper for setting up all things "copper" related. 1176 * This is a function pointer entry point called by the mac module. 1177 **/ 1178 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw) 1179 { 1180 u32 ctrl; 1181 s32 ret_val; 1182 u16 reg_data; 1183 1184 DEBUGFUNC("e1000_setup_copper_link_80003es2lan"); 1185 1186 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1187 ctrl |= E1000_CTRL_SLU; 1188 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1189 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1190 1191 /* Set the mac to wait the maximum time between each 1192 * iteration and increase the max iterations when 1193 * polling the phy; this fixes erroneous timeouts at 10Mbps. 1194 */ 1195 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4), 1196 0xFFFF); 1197 if (ret_val) 1198 return ret_val; 1199 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1200 ®_data); 1201 if (ret_val) 1202 return ret_val; 1203 reg_data |= 0x3F; 1204 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9), 1205 reg_data); 1206 if (ret_val) 1207 return ret_val; 1208 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, 1209 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, ®_data); 1210 if (ret_val) 1211 return ret_val; 1212 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING; 1213 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1214 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data); 1215 if (ret_val) 1216 return ret_val; 1217 1218 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw); 1219 if (ret_val) 1220 return ret_val; 1221 1222 return e1000_setup_copper_link_generic(hw); 1223 } 1224 1225 /** 1226 * e1000_cfg_on_link_up_80003es2lan - es2 link configuration after link-up 1227 * @hw: pointer to the HW structure 1228 * @duplex: current duplex setting 1229 * 1230 * Configure the KMRN interface by applying last minute quirks for 1231 * 10/100 operation. 1232 **/ 1233 static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw) 1234 { 1235 s32 ret_val = E1000_SUCCESS; 1236 u16 speed; 1237 u16 duplex; 1238 1239 DEBUGFUNC("e1000_configure_on_link_up"); 1240 1241 if (hw->phy.media_type == e1000_media_type_copper) { 1242 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed, 1243 &duplex); 1244 if (ret_val) 1245 return ret_val; 1246 1247 if (speed == SPEED_1000) 1248 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw); 1249 else 1250 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex); 1251 } 1252 1253 return ret_val; 1254 } 1255 1256 /** 1257 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation 1258 * @hw: pointer to the HW structure 1259 * @duplex: current duplex setting 1260 * 1261 * Configure the KMRN interface by applying last minute quirks for 1262 * 10/100 operation. 1263 **/ 1264 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) 1265 { 1266 s32 ret_val; 1267 u32 tipg; 1268 u32 i = 0; 1269 u16 reg_data, reg_data2; 1270 1271 DEBUGFUNC("e1000_configure_kmrn_for_10_100"); 1272 1273 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; 1274 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1275 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, 1276 reg_data); 1277 if (ret_val) 1278 return ret_val; 1279 1280 /* Configure Transmit Inter-Packet Gap */ 1281 tipg = E1000_READ_REG(hw, E1000_TIPG); 1282 tipg &= ~E1000_TIPG_IPGT_MASK; 1283 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; 1284 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1285 1286 do { 1287 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1288 ®_data); 1289 if (ret_val) 1290 return ret_val; 1291 1292 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1293 ®_data2); 1294 if (ret_val) 1295 return ret_val; 1296 i++; 1297 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1298 1299 if (duplex == HALF_DUPLEX) 1300 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; 1301 else 1302 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1303 1304 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1305 } 1306 1307 /** 1308 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation 1309 * @hw: pointer to the HW structure 1310 * 1311 * Configure the KMRN interface by applying last minute quirks for 1312 * gigabit operation. 1313 **/ 1314 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) 1315 { 1316 s32 ret_val; 1317 u16 reg_data, reg_data2; 1318 u32 tipg; 1319 u32 i = 0; 1320 1321 DEBUGFUNC("e1000_configure_kmrn_for_1000"); 1322 1323 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; 1324 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, 1325 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data); 1326 if (ret_val) 1327 return ret_val; 1328 1329 /* Configure Transmit Inter-Packet Gap */ 1330 tipg = E1000_READ_REG(hw, E1000_TIPG); 1331 tipg &= ~E1000_TIPG_IPGT_MASK; 1332 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; 1333 E1000_WRITE_REG(hw, E1000_TIPG, tipg); 1334 1335 do { 1336 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1337 ®_data); 1338 if (ret_val) 1339 return ret_val; 1340 1341 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, 1342 ®_data2); 1343 if (ret_val) 1344 return ret_val; 1345 i++; 1346 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); 1347 1348 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; 1349 1350 return hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); 1351 } 1352 1353 /** 1354 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register 1355 * @hw: pointer to the HW structure 1356 * @offset: register offset to be read 1357 * @data: pointer to the read data 1358 * 1359 * Acquire semaphore, then read the PHY register at offset 1360 * using the kumeran interface. The information retrieved is stored in data. 1361 * Release the semaphore before exiting. 1362 **/ 1363 static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1364 u16 *data) 1365 { 1366 u32 kmrnctrlsta; 1367 s32 ret_val; 1368 1369 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan"); 1370 1371 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1372 if (ret_val) 1373 return ret_val; 1374 1375 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1376 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 1377 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1378 E1000_WRITE_FLUSH(hw); 1379 1380 usec_delay(2); 1381 1382 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 1383 *data = (u16)kmrnctrlsta; 1384 1385 e1000_release_mac_csr_80003es2lan(hw); 1386 1387 return ret_val; 1388 } 1389 1390 /** 1391 * e1000_write_kmrn_reg_80003es2lan - Write kumeran register 1392 * @hw: pointer to the HW structure 1393 * @offset: register offset to write to 1394 * @data: data to write at register offset 1395 * 1396 * Acquire semaphore, then write the data to PHY register 1397 * at the offset using the kumeran interface. Release semaphore 1398 * before exiting. 1399 **/ 1400 static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset, 1401 u16 data) 1402 { 1403 u32 kmrnctrlsta; 1404 s32 ret_val; 1405 1406 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan"); 1407 1408 ret_val = e1000_acquire_mac_csr_80003es2lan(hw); 1409 if (ret_val) 1410 return ret_val; 1411 1412 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 1413 E1000_KMRNCTRLSTA_OFFSET) | data; 1414 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 1415 E1000_WRITE_FLUSH(hw); 1416 1417 usec_delay(2); 1418 1419 e1000_release_mac_csr_80003es2lan(hw); 1420 1421 return ret_val; 1422 } 1423 1424 /** 1425 * e1000_read_mac_addr_80003es2lan - Read device MAC address 1426 * @hw: pointer to the HW structure 1427 **/ 1428 static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw) 1429 { 1430 s32 ret_val; 1431 1432 DEBUGFUNC("e1000_read_mac_addr_80003es2lan"); 1433 1434 /* If there's an alternate MAC address place it in RAR0 1435 * so that it will override the Si installed default perm 1436 * address. 1437 */ 1438 ret_val = e1000_check_alt_mac_addr_generic(hw); 1439 if (ret_val) 1440 return ret_val; 1441 1442 return e1000_read_mac_addr_generic(hw); 1443 } 1444 1445 /** 1446 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down 1447 * @hw: pointer to the HW structure 1448 * 1449 * In the case of a PHY power down to save power, or to turn off link during a 1450 * driver unload, or wake on lan is not enabled, remove the link. 1451 **/ 1452 static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw) 1453 { 1454 /* If the management interface is not enabled, then power down */ 1455 if (!(hw->mac.ops.check_mng_mode(hw) || 1456 hw->phy.ops.check_reset_block(hw))) 1457 e1000_power_down_phy_copper(hw); 1458 1459 return; 1460 } 1461 1462 /** 1463 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters 1464 * @hw: pointer to the HW structure 1465 * 1466 * Clears the hardware counters by reading the counter registers. 1467 **/ 1468 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw) 1469 { 1470 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan"); 1471 1472 e1000_clear_hw_cntrs_base_generic(hw); 1473 1474 E1000_READ_REG(hw, E1000_PRC64); 1475 E1000_READ_REG(hw, E1000_PRC127); 1476 E1000_READ_REG(hw, E1000_PRC255); 1477 E1000_READ_REG(hw, E1000_PRC511); 1478 E1000_READ_REG(hw, E1000_PRC1023); 1479 E1000_READ_REG(hw, E1000_PRC1522); 1480 E1000_READ_REG(hw, E1000_PTC64); 1481 E1000_READ_REG(hw, E1000_PTC127); 1482 E1000_READ_REG(hw, E1000_PTC255); 1483 E1000_READ_REG(hw, E1000_PTC511); 1484 E1000_READ_REG(hw, E1000_PTC1023); 1485 E1000_READ_REG(hw, E1000_PTC1522); 1486 1487 E1000_READ_REG(hw, E1000_ALGNERRC); 1488 E1000_READ_REG(hw, E1000_RXERRC); 1489 E1000_READ_REG(hw, E1000_TNCRS); 1490 E1000_READ_REG(hw, E1000_CEXTERR); 1491 E1000_READ_REG(hw, E1000_TSCTC); 1492 E1000_READ_REG(hw, E1000_TSCTFC); 1493 1494 E1000_READ_REG(hw, E1000_MGTPRC); 1495 E1000_READ_REG(hw, E1000_MGTPDC); 1496 E1000_READ_REG(hw, E1000_MGTPTC); 1497 1498 E1000_READ_REG(hw, E1000_IAC); 1499 E1000_READ_REG(hw, E1000_ICRXOC); 1500 1501 E1000_READ_REG(hw, E1000_ICRXPTC); 1502 E1000_READ_REG(hw, E1000_ICRXATC); 1503 E1000_READ_REG(hw, E1000_ICTXPTC); 1504 E1000_READ_REG(hw, E1000_ICTXATC); 1505 E1000_READ_REG(hw, E1000_ICTXQEC); 1506 E1000_READ_REG(hw, E1000_ICTXQMTC); 1507 E1000_READ_REG(hw, E1000_ICRXDMTC); 1508 }
Cache object: 600f0f1a0b72d4062f35e59119f6a48d
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]