1 /******************************************************************************
2
3 Copyright (c) 2001-2012, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33 /*$FreeBSD:$*/
34
35 /* 82571EB Gigabit Ethernet Controller
36 * 82571EB Gigabit Ethernet Controller (Copper)
37 * 82571EB Gigabit Ethernet Controller (Fiber)
38 * 82571EB Dual Port Gigabit Mezzanine Adapter
39 * 82571EB Quad Port Gigabit Mezzanine Adapter
40 * 82571PT Gigabit PT Quad Port Server ExpressModule
41 * 82572EI Gigabit Ethernet Controller (Copper)
42 * 82572EI Gigabit Ethernet Controller (Fiber)
43 * 82572EI Gigabit Ethernet Controller
44 * 82573V Gigabit Ethernet Controller (Copper)
45 * 82573E Gigabit Ethernet Controller (Copper)
46 * 82573L Gigabit Ethernet Controller
47 * 82574L Gigabit Network Connection
48 * 82583V Gigabit Network Connection
49 */
50
51 #include "e1000_api.h"
52
53 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
54 static void e1000_release_nvm_82571(struct e1000_hw *hw);
55 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
58 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
59 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
60 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
61 bool active);
62 static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
63 static s32 e1000_init_hw_82571(struct e1000_hw *hw);
64 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
65 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
66 static s32 e1000_led_on_82574(struct e1000_hw *hw);
67 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
68 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
69 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
70 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
71 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
72 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
73 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
74 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
75 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
76 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
77 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
78 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
79 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
80 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
81 bool active);
82 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
83 bool active);
84 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
85 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
86 u16 words, u16 *data);
87 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
88 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
89
90 /**
91 * e1000_init_phy_params_82571 - Init PHY func ptrs.
92 * @hw: pointer to the HW structure
93 **/
94 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
95 {
96 struct e1000_phy_info *phy = &hw->phy;
97 s32 ret_val;
98
99 DEBUGFUNC("e1000_init_phy_params_82571");
100
101 if (hw->phy.media_type != e1000_media_type_copper) {
102 phy->type = e1000_phy_none;
103 return E1000_SUCCESS;
104 }
105
106 phy->addr = 1;
107 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
108 phy->reset_delay_us = 100;
109
110 phy->ops.check_reset_block = e1000_check_reset_block_generic;
111 phy->ops.reset = e1000_phy_hw_reset_generic;
112 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
113 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
114 phy->ops.power_up = e1000_power_up_phy_copper;
115 phy->ops.power_down = e1000_power_down_phy_copper_82571;
116
117 switch (hw->mac.type) {
118 case e1000_82571:
119 case e1000_82572:
120 phy->type = e1000_phy_igp_2;
121 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
122 phy->ops.get_info = e1000_get_phy_info_igp;
123 phy->ops.check_polarity = e1000_check_polarity_igp;
124 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
125 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
126 phy->ops.read_reg = e1000_read_phy_reg_igp;
127 phy->ops.write_reg = e1000_write_phy_reg_igp;
128 phy->ops.acquire = e1000_get_hw_semaphore_82571;
129 phy->ops.release = e1000_put_hw_semaphore_82571;
130 break;
131 case e1000_82573:
132 phy->type = e1000_phy_m88;
133 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
134 phy->ops.get_info = e1000_get_phy_info_m88;
135 phy->ops.check_polarity = e1000_check_polarity_m88;
136 phy->ops.commit = e1000_phy_sw_reset_generic;
137 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
138 phy->ops.get_cable_length = e1000_get_cable_length_m88;
139 phy->ops.read_reg = e1000_read_phy_reg_m88;
140 phy->ops.write_reg = e1000_write_phy_reg_m88;
141 phy->ops.acquire = e1000_get_hw_semaphore_82571;
142 phy->ops.release = e1000_put_hw_semaphore_82571;
143 break;
144 case e1000_82574:
145 case e1000_82583:
146 phy->type = e1000_phy_bm;
147 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
148 phy->ops.get_info = e1000_get_phy_info_m88;
149 phy->ops.check_polarity = e1000_check_polarity_m88;
150 phy->ops.commit = e1000_phy_sw_reset_generic;
151 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
152 phy->ops.get_cable_length = e1000_get_cable_length_m88;
153 phy->ops.read_reg = e1000_read_phy_reg_bm2;
154 phy->ops.write_reg = e1000_write_phy_reg_bm2;
155 phy->ops.acquire = e1000_get_hw_semaphore_82574;
156 phy->ops.release = e1000_put_hw_semaphore_82574;
157 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
158 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
159 break;
160 default:
161 return -E1000_ERR_PHY;
162 break;
163 }
164
165 /* This can only be done after all function pointers are setup. */
166 ret_val = e1000_get_phy_id_82571(hw);
167 if (ret_val) {
168 DEBUGOUT("Error getting PHY ID\n");
169 return ret_val;
170 }
171
172 /* Verify phy id */
173 switch (hw->mac.type) {
174 case e1000_82571:
175 case e1000_82572:
176 if (phy->id != IGP01E1000_I_PHY_ID)
177 ret_val = -E1000_ERR_PHY;
178 break;
179 case e1000_82573:
180 if (phy->id != M88E1111_I_PHY_ID)
181 ret_val = -E1000_ERR_PHY;
182 break;
183 case e1000_82574:
184 case e1000_82583:
185 if (phy->id != BME1000_E_PHY_ID_R2)
186 ret_val = -E1000_ERR_PHY;
187 break;
188 default:
189 ret_val = -E1000_ERR_PHY;
190 break;
191 }
192
193 if (ret_val)
194 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
195
196 return ret_val;
197 }
198
199 /**
200 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
201 * @hw: pointer to the HW structure
202 **/
203 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
204 {
205 struct e1000_nvm_info *nvm = &hw->nvm;
206 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
207 u16 size;
208
209 DEBUGFUNC("e1000_init_nvm_params_82571");
210
211 nvm->opcode_bits = 8;
212 nvm->delay_usec = 1;
213 switch (nvm->override) {
214 case e1000_nvm_override_spi_large:
215 nvm->page_size = 32;
216 nvm->address_bits = 16;
217 break;
218 case e1000_nvm_override_spi_small:
219 nvm->page_size = 8;
220 nvm->address_bits = 8;
221 break;
222 default:
223 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
224 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
225 break;
226 }
227
228 switch (hw->mac.type) {
229 case e1000_82573:
230 case e1000_82574:
231 case e1000_82583:
232 if (((eecd >> 15) & 0x3) == 0x3) {
233 nvm->type = e1000_nvm_flash_hw;
234 nvm->word_size = 2048;
235 /* Autonomous Flash update bit must be cleared due
236 * to Flash update issue.
237 */
238 eecd &= ~E1000_EECD_AUPDEN;
239 E1000_WRITE_REG(hw, E1000_EECD, eecd);
240 break;
241 }
242 /* Fall Through */
243 default:
244 nvm->type = e1000_nvm_eeprom_spi;
245 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
246 E1000_EECD_SIZE_EX_SHIFT);
247 /* Added to a constant, "size" becomes the left-shift value
248 * for setting word_size.
249 */
250 size += NVM_WORD_SIZE_BASE_SHIFT;
251
252 /* EEPROM access above 16k is unsupported */
253 if (size > 14)
254 size = 14;
255 nvm->word_size = 1 << size;
256 break;
257 }
258
259 /* Function Pointers */
260 switch (hw->mac.type) {
261 case e1000_82574:
262 case e1000_82583:
263 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
264 nvm->ops.release = e1000_put_hw_semaphore_82574;
265 break;
266 default:
267 nvm->ops.acquire = e1000_acquire_nvm_82571;
268 nvm->ops.release = e1000_release_nvm_82571;
269 break;
270 }
271 nvm->ops.read = e1000_read_nvm_eerd;
272 nvm->ops.update = e1000_update_nvm_checksum_82571;
273 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
274 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
275 nvm->ops.write = e1000_write_nvm_82571;
276
277 return E1000_SUCCESS;
278 }
279
280 /**
281 * e1000_init_mac_params_82571 - Init MAC func ptrs.
282 * @hw: pointer to the HW structure
283 **/
284 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
285 {
286 struct e1000_mac_info *mac = &hw->mac;
287 u32 swsm = 0;
288 u32 swsm2 = 0;
289 bool force_clear_smbi = FALSE;
290
291 DEBUGFUNC("e1000_init_mac_params_82571");
292
293 /* Set media type and media-dependent function pointers */
294 switch (hw->device_id) {
295 case E1000_DEV_ID_82571EB_FIBER:
296 case E1000_DEV_ID_82572EI_FIBER:
297 case E1000_DEV_ID_82571EB_QUAD_FIBER:
298 hw->phy.media_type = e1000_media_type_fiber;
299 mac->ops.setup_physical_interface =
300 e1000_setup_fiber_serdes_link_82571;
301 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
302 mac->ops.get_link_up_info =
303 e1000_get_speed_and_duplex_fiber_serdes_generic;
304 break;
305 case E1000_DEV_ID_82571EB_SERDES:
306 case E1000_DEV_ID_82571EB_SERDES_DUAL:
307 case E1000_DEV_ID_82571EB_SERDES_QUAD:
308 case E1000_DEV_ID_82572EI_SERDES:
309 hw->phy.media_type = e1000_media_type_internal_serdes;
310 mac->ops.setup_physical_interface =
311 e1000_setup_fiber_serdes_link_82571;
312 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
313 mac->ops.get_link_up_info =
314 e1000_get_speed_and_duplex_fiber_serdes_generic;
315 break;
316 default:
317 hw->phy.media_type = e1000_media_type_copper;
318 mac->ops.setup_physical_interface =
319 e1000_setup_copper_link_82571;
320 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
321 mac->ops.get_link_up_info =
322 e1000_get_speed_and_duplex_copper_generic;
323 break;
324 }
325
326 /* Set mta register count */
327 mac->mta_reg_count = 128;
328 /* Set rar entry count */
329 mac->rar_entry_count = E1000_RAR_ENTRIES;
330 /* Set if part includes ASF firmware */
331 mac->asf_firmware_present = TRUE;
332 /* Adaptive IFS supported */
333 mac->adaptive_ifs = TRUE;
334
335 /* Function pointers */
336
337 /* bus type/speed/width */
338 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
339 /* reset */
340 mac->ops.reset_hw = e1000_reset_hw_82571;
341 /* hw initialization */
342 mac->ops.init_hw = e1000_init_hw_82571;
343 /* link setup */
344 mac->ops.setup_link = e1000_setup_link_82571;
345 /* multicast address update */
346 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
347 /* writing VFTA */
348 mac->ops.write_vfta = e1000_write_vfta_generic;
349 /* clearing VFTA */
350 mac->ops.clear_vfta = e1000_clear_vfta_82571;
351 /* read mac address */
352 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
353 /* ID LED init */
354 mac->ops.id_led_init = e1000_id_led_init_generic;
355 /* setup LED */
356 mac->ops.setup_led = e1000_setup_led_generic;
357 /* cleanup LED */
358 mac->ops.cleanup_led = e1000_cleanup_led_generic;
359 /* turn off LED */
360 mac->ops.led_off = e1000_led_off_generic;
361 /* clear hardware counters */
362 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
363
364 /* MAC-specific function pointers */
365 switch (hw->mac.type) {
366 case e1000_82573:
367 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
368 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
369 mac->ops.led_on = e1000_led_on_generic;
370 mac->ops.blink_led = e1000_blink_led_generic;
371
372 /* FWSM register */
373 mac->has_fwsm = TRUE;
374 /* ARC supported; valid only if manageability features are
375 * enabled.
376 */
377 mac->arc_subsystem_valid = !!(E1000_READ_REG(hw, E1000_FWSM) &
378 E1000_FWSM_MODE_MASK);
379 break;
380 case e1000_82574:
381 case e1000_82583:
382 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
383 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
384 mac->ops.led_on = e1000_led_on_82574;
385 break;
386 default:
387 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
388 mac->ops.led_on = e1000_led_on_generic;
389 mac->ops.blink_led = e1000_blink_led_generic;
390
391 /* FWSM register */
392 mac->has_fwsm = TRUE;
393 break;
394 }
395
396 /* Ensure that the inter-port SWSM.SMBI lock bit is clear before
397 * first NVM or PHY acess. This should be done for single-port
398 * devices, and for one port only on dual-port devices so that
399 * for those devices we can still use the SMBI lock to synchronize
400 * inter-port accesses to the PHY & NVM.
401 */
402 switch (hw->mac.type) {
403 case e1000_82571:
404 case e1000_82572:
405 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
406
407 if (!(swsm2 & E1000_SWSM2_LOCK)) {
408 /* Only do this for the first interface on this card */
409 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
410 E1000_SWSM2_LOCK);
411 force_clear_smbi = TRUE;
412 } else {
413 force_clear_smbi = FALSE;
414 }
415 break;
416 default:
417 force_clear_smbi = TRUE;
418 break;
419 }
420
421 if (force_clear_smbi) {
422 /* Make sure SWSM.SMBI is clear */
423 swsm = E1000_READ_REG(hw, E1000_SWSM);
424 if (swsm & E1000_SWSM_SMBI) {
425 /* This bit should not be set on a first interface, and
426 * indicates that the bootagent or EFI code has
427 * improperly left this bit enabled
428 */
429 DEBUGOUT("Please update your 82571 Bootagent\n");
430 }
431 E1000_WRITE_REG(hw, E1000_SWSM, swsm & ~E1000_SWSM_SMBI);
432 }
433
434 /* Initialze device specific counter of SMBI acquisition timeouts. */
435 hw->dev_spec._82571.smb_counter = 0;
436
437 return E1000_SUCCESS;
438 }
439
440 /**
441 * e1000_init_function_pointers_82571 - Init func ptrs.
442 * @hw: pointer to the HW structure
443 *
444 * Called to initialize all function pointers and parameters.
445 **/
446 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
447 {
448 DEBUGFUNC("e1000_init_function_pointers_82571");
449
450 hw->mac.ops.init_params = e1000_init_mac_params_82571;
451 hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
452 hw->phy.ops.init_params = e1000_init_phy_params_82571;
453 }
454
455 /**
456 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
457 * @hw: pointer to the HW structure
458 *
459 * Reads the PHY registers and stores the PHY ID and possibly the PHY
460 * revision in the hardware structure.
461 **/
462 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
463 {
464 struct e1000_phy_info *phy = &hw->phy;
465 s32 ret_val;
466 u16 phy_id = 0;
467
468 DEBUGFUNC("e1000_get_phy_id_82571");
469
470 switch (hw->mac.type) {
471 case e1000_82571:
472 case e1000_82572:
473 /* The 82571 firmware may still be configuring the PHY.
474 * In this case, we cannot access the PHY until the
475 * configuration is done. So we explicitly set the
476 * PHY ID.
477 */
478 phy->id = IGP01E1000_I_PHY_ID;
479 break;
480 case e1000_82573:
481 return e1000_get_phy_id(hw);
482 break;
483 case e1000_82574:
484 case e1000_82583:
485 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
486 if (ret_val)
487 return ret_val;
488
489 phy->id = (u32)(phy_id << 16);
490 usec_delay(20);
491 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
492 if (ret_val)
493 return ret_val;
494
495 phy->id |= (u32)(phy_id);
496 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
497 break;
498 default:
499 return -E1000_ERR_PHY;
500 break;
501 }
502
503 return E1000_SUCCESS;
504 }
505
506 /**
507 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
508 * @hw: pointer to the HW structure
509 *
510 * Acquire the HW semaphore to access the PHY or NVM
511 **/
512 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
513 {
514 u32 swsm;
515 s32 sw_timeout = hw->nvm.word_size + 1;
516 s32 fw_timeout = hw->nvm.word_size + 1;
517 s32 i = 0;
518
519 DEBUGFUNC("e1000_get_hw_semaphore_82571");
520
521 /* If we have timedout 3 times on trying to acquire
522 * the inter-port SMBI semaphore, there is old code
523 * operating on the other port, and it is not
524 * releasing SMBI. Modify the number of times that
525 * we try for the semaphore to interwork with this
526 * older code.
527 */
528 if (hw->dev_spec._82571.smb_counter > 2)
529 sw_timeout = 1;
530
531 /* Get the SW semaphore */
532 while (i < sw_timeout) {
533 swsm = E1000_READ_REG(hw, E1000_SWSM);
534 if (!(swsm & E1000_SWSM_SMBI))
535 break;
536
537 usec_delay(50);
538 i++;
539 }
540
541 if (i == sw_timeout) {
542 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
543 hw->dev_spec._82571.smb_counter++;
544 }
545 /* Get the FW semaphore. */
546 for (i = 0; i < fw_timeout; i++) {
547 swsm = E1000_READ_REG(hw, E1000_SWSM);
548 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
549
550 /* Semaphore acquired if bit latched */
551 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
552 break;
553
554 usec_delay(50);
555 }
556
557 if (i == fw_timeout) {
558 /* Release semaphores */
559 e1000_put_hw_semaphore_82571(hw);
560 DEBUGOUT("Driver can't access the NVM\n");
561 return -E1000_ERR_NVM;
562 }
563
564 return E1000_SUCCESS;
565 }
566
567 /**
568 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
569 * @hw: pointer to the HW structure
570 *
571 * Release hardware semaphore used to access the PHY or NVM
572 **/
573 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
574 {
575 u32 swsm;
576
577 DEBUGFUNC("e1000_put_hw_semaphore_generic");
578
579 swsm = E1000_READ_REG(hw, E1000_SWSM);
580
581 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
582
583 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
584 }
585
586 /**
587 * e1000_get_hw_semaphore_82573 - Acquire hardware semaphore
588 * @hw: pointer to the HW structure
589 *
590 * Acquire the HW semaphore during reset.
591 *
592 **/
593 static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
594 {
595 u32 extcnf_ctrl;
596 s32 i = 0;
597
598 DEBUGFUNC("e1000_get_hw_semaphore_82573");
599
600 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
601 do {
602 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
603 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
604 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
605
606 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
607 break;
608
609 msec_delay(2);
610 i++;
611 } while (i < MDIO_OWNERSHIP_TIMEOUT);
612
613 if (i == MDIO_OWNERSHIP_TIMEOUT) {
614 /* Release semaphores */
615 e1000_put_hw_semaphore_82573(hw);
616 DEBUGOUT("Driver can't access the PHY\n");
617 return -E1000_ERR_PHY;
618 }
619
620 return E1000_SUCCESS;
621 }
622
623 /**
624 * e1000_put_hw_semaphore_82573 - Release hardware semaphore
625 * @hw: pointer to the HW structure
626 *
627 * Release hardware semaphore used during reset.
628 *
629 **/
630 static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
631 {
632 u32 extcnf_ctrl;
633
634 DEBUGFUNC("e1000_put_hw_semaphore_82573");
635
636 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
637 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
638 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
639 }
640
641 /**
642 * e1000_get_hw_semaphore_82574 - Acquire hardware semaphore
643 * @hw: pointer to the HW structure
644 *
645 * Acquire the HW semaphore to access the PHY or NVM.
646 *
647 **/
648 static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
649 {
650 s32 ret_val;
651
652 DEBUGFUNC("e1000_get_hw_semaphore_82574");
653
654 ret_val = e1000_get_hw_semaphore_82573(hw);
655 return ret_val;
656 }
657
658 /**
659 * e1000_put_hw_semaphore_82574 - Release hardware semaphore
660 * @hw: pointer to the HW structure
661 *
662 * Release hardware semaphore used to access the PHY or NVM
663 *
664 **/
665 static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
666 {
667 DEBUGFUNC("e1000_put_hw_semaphore_82574");
668
669 e1000_put_hw_semaphore_82573(hw);
670 }
671
672 /**
673 * e1000_set_d0_lplu_state_82574 - Set Low Power Linkup D0 state
674 * @hw: pointer to the HW structure
675 * @active: TRUE to enable LPLU, FALSE to disable
676 *
677 * Sets the LPLU D0 state according to the active flag.
678 * LPLU will not be activated unless the
679 * device autonegotiation advertisement meets standards of
680 * either 10 or 10/100 or 10/100/1000 at all duplexes.
681 * This is a function pointer entry point only called by
682 * PHY setup routines.
683 **/
684 static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
685 {
686 u32 data = E1000_READ_REG(hw, E1000_POEMB);
687
688 DEBUGFUNC("e1000_set_d0_lplu_state_82574");
689
690 if (active)
691 data |= E1000_PHY_CTRL_D0A_LPLU;
692 else
693 data &= ~E1000_PHY_CTRL_D0A_LPLU;
694
695 E1000_WRITE_REG(hw, E1000_POEMB, data);
696 return E1000_SUCCESS;
697 }
698
699 /**
700 * e1000_set_d3_lplu_state_82574 - Sets low power link up state for D3
701 * @hw: pointer to the HW structure
702 * @active: boolean used to enable/disable lplu
703 *
704 * The low power link up (lplu) state is set to the power management level D3
705 * when active is TRUE, else clear lplu for D3. LPLU
706 * is used during Dx states where the power conservation is most important.
707 * During driver activity, SmartSpeed should be enabled so performance is
708 * maintained.
709 **/
710 static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
711 {
712 u32 data = E1000_READ_REG(hw, E1000_POEMB);
713
714 DEBUGFUNC("e1000_set_d3_lplu_state_82574");
715
716 if (!active) {
717 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
718 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
719 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
720 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
721 data |= E1000_PHY_CTRL_NOND0A_LPLU;
722 }
723
724 E1000_WRITE_REG(hw, E1000_POEMB, data);
725 return E1000_SUCCESS;
726 }
727
728 /**
729 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
730 * @hw: pointer to the HW structure
731 *
732 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
733 * Then for non-82573 hardware, set the EEPROM access request bit and wait
734 * for EEPROM access grant bit. If the access grant bit is not set, release
735 * hardware semaphore.
736 **/
737 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
738 {
739 s32 ret_val;
740
741 DEBUGFUNC("e1000_acquire_nvm_82571");
742
743 ret_val = e1000_get_hw_semaphore_82571(hw);
744 if (ret_val)
745 return ret_val;
746
747 switch (hw->mac.type) {
748 case e1000_82573:
749 break;
750 default:
751 ret_val = e1000_acquire_nvm_generic(hw);
752 break;
753 }
754
755 if (ret_val)
756 e1000_put_hw_semaphore_82571(hw);
757
758 return ret_val;
759 }
760
761 /**
762 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
763 * @hw: pointer to the HW structure
764 *
765 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
766 **/
767 static void e1000_release_nvm_82571(struct e1000_hw *hw)
768 {
769 DEBUGFUNC("e1000_release_nvm_82571");
770
771 e1000_release_nvm_generic(hw);
772 e1000_put_hw_semaphore_82571(hw);
773 }
774
775 /**
776 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
777 * @hw: pointer to the HW structure
778 * @offset: offset within the EEPROM to be written to
779 * @words: number of words to write
780 * @data: 16 bit word(s) to be written to the EEPROM
781 *
782 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
783 *
784 * If e1000_update_nvm_checksum is not called after this function, the
785 * EEPROM will most likely contain an invalid checksum.
786 **/
787 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
788 u16 *data)
789 {
790 s32 ret_val;
791
792 DEBUGFUNC("e1000_write_nvm_82571");
793
794 switch (hw->mac.type) {
795 case e1000_82573:
796 case e1000_82574:
797 case e1000_82583:
798 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
799 break;
800 case e1000_82571:
801 case e1000_82572:
802 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
803 break;
804 default:
805 ret_val = -E1000_ERR_NVM;
806 break;
807 }
808
809 return ret_val;
810 }
811
812 /**
813 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
814 * @hw: pointer to the HW structure
815 *
816 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
817 * up to the checksum. Then calculates the EEPROM checksum and writes the
818 * value to the EEPROM.
819 **/
820 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
821 {
822 u32 eecd;
823 s32 ret_val;
824 u16 i;
825
826 DEBUGFUNC("e1000_update_nvm_checksum_82571");
827
828 ret_val = e1000_update_nvm_checksum_generic(hw);
829 if (ret_val)
830 return ret_val;
831
832 /* If our nvm is an EEPROM, then we're done
833 * otherwise, commit the checksum to the flash NVM.
834 */
835 if (hw->nvm.type != e1000_nvm_flash_hw)
836 return E1000_SUCCESS;
837
838 /* Check for pending operations. */
839 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
840 msec_delay(1);
841 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
842 break;
843 }
844
845 if (i == E1000_FLASH_UPDATES)
846 return -E1000_ERR_NVM;
847
848 /* Reset the firmware if using STM opcode. */
849 if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
850 /* The enabling of and the actual reset must be done
851 * in two write cycles.
852 */
853 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
854 E1000_WRITE_FLUSH(hw);
855 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
856 }
857
858 /* Commit the write to flash */
859 eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
860 E1000_WRITE_REG(hw, E1000_EECD, eecd);
861
862 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
863 msec_delay(1);
864 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD))
865 break;
866 }
867
868 if (i == E1000_FLASH_UPDATES)
869 return -E1000_ERR_NVM;
870
871 return E1000_SUCCESS;
872 }
873
874 /**
875 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
876 * @hw: pointer to the HW structure
877 *
878 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
879 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
880 **/
881 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
882 {
883 DEBUGFUNC("e1000_validate_nvm_checksum_82571");
884
885 if (hw->nvm.type == e1000_nvm_flash_hw)
886 e1000_fix_nvm_checksum_82571(hw);
887
888 return e1000_validate_nvm_checksum_generic(hw);
889 }
890
891 /**
892 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
893 * @hw: pointer to the HW structure
894 * @offset: offset within the EEPROM to be written to
895 * @words: number of words to write
896 * @data: 16 bit word(s) to be written to the EEPROM
897 *
898 * After checking for invalid values, poll the EEPROM to ensure the previous
899 * command has completed before trying to write the next word. After write
900 * poll for completion.
901 *
902 * If e1000_update_nvm_checksum is not called after this function, the
903 * EEPROM will most likely contain an invalid checksum.
904 **/
905 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
906 u16 words, u16 *data)
907 {
908 struct e1000_nvm_info *nvm = &hw->nvm;
909 u32 i, eewr = 0;
910 s32 ret_val = E1000_SUCCESS;
911
912 DEBUGFUNC("e1000_write_nvm_eewr_82571");
913
914 /* A check for invalid values: offset too large, too many words,
915 * and not enough words.
916 */
917 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
918 (words == 0)) {
919 DEBUGOUT("nvm parameter(s) out of bounds\n");
920 return -E1000_ERR_NVM;
921 }
922
923 for (i = 0; i < words; i++) {
924 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
925 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
926 E1000_NVM_RW_REG_START;
927
928 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
929 if (ret_val)
930 break;
931
932 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
933
934 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
935 if (ret_val)
936 break;
937 }
938
939 return ret_val;
940 }
941
942 /**
943 * e1000_get_cfg_done_82571 - Poll for configuration done
944 * @hw: pointer to the HW structure
945 *
946 * Reads the management control register for the config done bit to be set.
947 **/
948 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
949 {
950 s32 timeout = PHY_CFG_TIMEOUT;
951
952 DEBUGFUNC("e1000_get_cfg_done_82571");
953
954 while (timeout) {
955 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
956 E1000_NVM_CFG_DONE_PORT_0)
957 break;
958 msec_delay(1);
959 timeout--;
960 }
961 if (!timeout) {
962 DEBUGOUT("MNG configuration cycle has not completed.\n");
963 return -E1000_ERR_RESET;
964 }
965
966 return E1000_SUCCESS;
967 }
968
969 /**
970 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
971 * @hw: pointer to the HW structure
972 * @active: TRUE to enable LPLU, FALSE to disable
973 *
974 * Sets the LPLU D0 state according to the active flag. When activating LPLU
975 * this function also disables smart speed and vice versa. LPLU will not be
976 * activated unless the device autonegotiation advertisement meets standards
977 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
978 * pointer entry point only called by PHY setup routines.
979 **/
980 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
981 {
982 struct e1000_phy_info *phy = &hw->phy;
983 s32 ret_val;
984 u16 data;
985
986 DEBUGFUNC("e1000_set_d0_lplu_state_82571");
987
988 if (!(phy->ops.read_reg))
989 return E1000_SUCCESS;
990
991 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
992 if (ret_val)
993 return ret_val;
994
995 if (active) {
996 data |= IGP02E1000_PM_D0_LPLU;
997 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
998 data);
999 if (ret_val)
1000 return ret_val;
1001
1002 /* When LPLU is enabled, we should disable SmartSpeed */
1003 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1004 &data);
1005 if (ret_val)
1006 return ret_val;
1007 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1008 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1009 data);
1010 if (ret_val)
1011 return ret_val;
1012 } else {
1013 data &= ~IGP02E1000_PM_D0_LPLU;
1014 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1015 data);
1016 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1017 * during Dx states where the power conservation is most
1018 * important. During driver activity we should enable
1019 * SmartSpeed, so performance is maintained.
1020 */
1021 if (phy->smart_speed == e1000_smart_speed_on) {
1022 ret_val = phy->ops.read_reg(hw,
1023 IGP01E1000_PHY_PORT_CONFIG,
1024 &data);
1025 if (ret_val)
1026 return ret_val;
1027
1028 data |= IGP01E1000_PSCFR_SMART_SPEED;
1029 ret_val = phy->ops.write_reg(hw,
1030 IGP01E1000_PHY_PORT_CONFIG,
1031 data);
1032 if (ret_val)
1033 return ret_val;
1034 } else if (phy->smart_speed == e1000_smart_speed_off) {
1035 ret_val = phy->ops.read_reg(hw,
1036 IGP01E1000_PHY_PORT_CONFIG,
1037 &data);
1038 if (ret_val)
1039 return ret_val;
1040
1041 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1042 ret_val = phy->ops.write_reg(hw,
1043 IGP01E1000_PHY_PORT_CONFIG,
1044 data);
1045 if (ret_val)
1046 return ret_val;
1047 }
1048 }
1049
1050 return E1000_SUCCESS;
1051 }
1052
1053 /**
1054 * e1000_reset_hw_82571 - Reset hardware
1055 * @hw: pointer to the HW structure
1056 *
1057 * This resets the hardware into a known state.
1058 **/
1059 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
1060 {
1061 u32 ctrl, ctrl_ext, eecd, tctl;
1062 s32 ret_val;
1063
1064 DEBUGFUNC("e1000_reset_hw_82571");
1065
1066 /* Prevent the PCI-E bus from sticking if there is no TLP connection
1067 * on the last TLP read/write transaction when MAC is reset.
1068 */
1069 ret_val = e1000_disable_pcie_master_generic(hw);
1070 if (ret_val)
1071 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1072
1073 DEBUGOUT("Masking off all interrupts\n");
1074 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1075
1076 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1077 tctl = E1000_READ_REG(hw, E1000_TCTL);
1078 tctl &= ~E1000_TCTL_EN;
1079 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1080 E1000_WRITE_FLUSH(hw);
1081
1082 msec_delay(10);
1083
1084 /* Must acquire the MDIO ownership before MAC reset.
1085 * Ownership defaults to firmware after a reset.
1086 */
1087 switch (hw->mac.type) {
1088 case e1000_82573:
1089 ret_val = e1000_get_hw_semaphore_82573(hw);
1090 break;
1091 case e1000_82574:
1092 case e1000_82583:
1093 ret_val = e1000_get_hw_semaphore_82574(hw);
1094 break;
1095 default:
1096 break;
1097 }
1098 if (ret_val)
1099 DEBUGOUT("Cannot acquire MDIO ownership\n");
1100
1101 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1102
1103 DEBUGOUT("Issuing a global reset to MAC\n");
1104 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1105
1106 /* Must release MDIO ownership and mutex after MAC reset. */
1107 switch (hw->mac.type) {
1108 case e1000_82574:
1109 case e1000_82583:
1110 e1000_put_hw_semaphore_82574(hw);
1111 break;
1112 default:
1113 break;
1114 }
1115
1116 if (hw->nvm.type == e1000_nvm_flash_hw) {
1117 usec_delay(10);
1118 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1119 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1120 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1121 E1000_WRITE_FLUSH(hw);
1122 }
1123
1124 ret_val = e1000_get_auto_rd_done_generic(hw);
1125 if (ret_val)
1126 /* We don't want to continue accessing MAC registers. */
1127 return ret_val;
1128
1129 /* Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1130 * Need to wait for Phy configuration completion before accessing
1131 * NVM and Phy.
1132 */
1133
1134 switch (hw->mac.type) {
1135 case e1000_82571:
1136 case e1000_82572:
1137 /* REQ and GNT bits need to be cleared when using AUTO_RD
1138 * to access the EEPROM.
1139 */
1140 eecd = E1000_READ_REG(hw, E1000_EECD);
1141 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1142 E1000_WRITE_REG(hw, E1000_EECD, eecd);
1143 break;
1144 case e1000_82573:
1145 case e1000_82574:
1146 case e1000_82583:
1147 msec_delay(25);
1148 break;
1149 default:
1150 break;
1151 }
1152
1153 /* Clear any pending interrupt events. */
1154 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1155 E1000_READ_REG(hw, E1000_ICR);
1156
1157 if (hw->mac.type == e1000_82571) {
1158 /* Install any alternate MAC address into RAR0 */
1159 ret_val = e1000_check_alt_mac_addr_generic(hw);
1160 if (ret_val)
1161 return ret_val;
1162
1163 e1000_set_laa_state_82571(hw, TRUE);
1164 }
1165
1166 /* Reinitialize the 82571 serdes link state machine */
1167 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1168 hw->mac.serdes_link_state = e1000_serdes_link_down;
1169
1170 return E1000_SUCCESS;
1171 }
1172
1173 /**
1174 * e1000_init_hw_82571 - Initialize hardware
1175 * @hw: pointer to the HW structure
1176 *
1177 * This inits the hardware readying it for operation.
1178 **/
1179 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1180 {
1181 struct e1000_mac_info *mac = &hw->mac;
1182 u32 reg_data;
1183 s32 ret_val;
1184 u16 i, rar_count = mac->rar_entry_count;
1185
1186 DEBUGFUNC("e1000_init_hw_82571");
1187
1188 e1000_initialize_hw_bits_82571(hw);
1189
1190 /* Initialize identification LED */
1191 ret_val = mac->ops.id_led_init(hw);
1192 /* An error is not fatal and we should not stop init due to this */
1193 if (ret_val)
1194 DEBUGOUT("Error initializing identification LED\n");
1195
1196 /* Disabling VLAN filtering */
1197 DEBUGOUT("Initializing the IEEE VLAN\n");
1198 mac->ops.clear_vfta(hw);
1199
1200 /* Setup the receive address.
1201 * If, however, a locally administered address was assigned to the
1202 * 82571, we must reserve a RAR for it to work around an issue where
1203 * resetting one port will reload the MAC on the other port.
1204 */
1205 if (e1000_get_laa_state_82571(hw))
1206 rar_count--;
1207 e1000_init_rx_addrs_generic(hw, rar_count);
1208
1209 /* Zero out the Multicast HASH table */
1210 DEBUGOUT("Zeroing the MTA\n");
1211 for (i = 0; i < mac->mta_reg_count; i++)
1212 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1213
1214 /* Setup link and flow control */
1215 ret_val = mac->ops.setup_link(hw);
1216
1217 /* Set the transmit descriptor write-back policy */
1218 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1219 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1220 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
1221 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1222
1223 /* ...for both queues. */
1224 switch (mac->type) {
1225 case e1000_82573:
1226 e1000_enable_tx_pkt_filtering_generic(hw);
1227 /* fall through */
1228 case e1000_82574:
1229 case e1000_82583:
1230 reg_data = E1000_READ_REG(hw, E1000_GCR);
1231 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1232 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1233 break;
1234 default:
1235 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1236 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1237 E1000_TXDCTL_FULL_TX_DESC_WB |
1238 E1000_TXDCTL_COUNT_DESC;
1239 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1240 break;
1241 }
1242
1243 /* Clear all of the statistics registers (clear on read). It is
1244 * important that we do this after we have tried to establish link
1245 * because the symbol error count will increment wildly if there
1246 * is no link.
1247 */
1248 e1000_clear_hw_cntrs_82571(hw);
1249
1250 return ret_val;
1251 }
1252
1253 /**
1254 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1255 * @hw: pointer to the HW structure
1256 *
1257 * Initializes required hardware-dependent bits needed for normal operation.
1258 **/
1259 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1260 {
1261 u32 reg;
1262
1263 DEBUGFUNC("e1000_initialize_hw_bits_82571");
1264
1265 /* Transmit Descriptor Control 0 */
1266 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1267 reg |= (1 << 22);
1268 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1269
1270 /* Transmit Descriptor Control 1 */
1271 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1272 reg |= (1 << 22);
1273 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1274
1275 /* Transmit Arbitration Control 0 */
1276 reg = E1000_READ_REG(hw, E1000_TARC(0));
1277 reg &= ~(0xF << 27); /* 30:27 */
1278 switch (hw->mac.type) {
1279 case e1000_82571:
1280 case e1000_82572:
1281 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1282 break;
1283 case e1000_82574:
1284 case e1000_82583:
1285 reg |= (1 << 26);
1286 break;
1287 default:
1288 break;
1289 }
1290 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1291
1292 /* Transmit Arbitration Control 1 */
1293 reg = E1000_READ_REG(hw, E1000_TARC(1));
1294 switch (hw->mac.type) {
1295 case e1000_82571:
1296 case e1000_82572:
1297 reg &= ~((1 << 29) | (1 << 30));
1298 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1299 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1300 reg &= ~(1 << 28);
1301 else
1302 reg |= (1 << 28);
1303 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1304 break;
1305 default:
1306 break;
1307 }
1308
1309 /* Device Control */
1310 switch (hw->mac.type) {
1311 case e1000_82573:
1312 case e1000_82574:
1313 case e1000_82583:
1314 reg = E1000_READ_REG(hw, E1000_CTRL);
1315 reg &= ~(1 << 29);
1316 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1317 break;
1318 default:
1319 break;
1320 }
1321
1322 /* Extended Device Control */
1323 switch (hw->mac.type) {
1324 case e1000_82573:
1325 case e1000_82574:
1326 case e1000_82583:
1327 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1328 reg &= ~(1 << 23);
1329 reg |= (1 << 22);
1330 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1331 break;
1332 default:
1333 break;
1334 }
1335
1336 if (hw->mac.type == e1000_82571) {
1337 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1338 reg |= E1000_PBA_ECC_CORR_EN;
1339 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1340 }
1341
1342 /* Workaround for hardware errata.
1343 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1344 */
1345 if ((hw->mac.type == e1000_82571) ||
1346 (hw->mac.type == e1000_82572)) {
1347 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1348 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1349 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1350 }
1351
1352 /* Disable IPv6 extension header parsing because some malformed
1353 * IPv6 headers can hang the Rx.
1354 */
1355 if (hw->mac.type <= e1000_82573) {
1356 reg = E1000_READ_REG(hw, E1000_RFCTL);
1357 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1358 E1000_WRITE_REG(hw, E1000_RFCTL, reg);
1359 }
1360
1361 /* PCI-Ex Control Registers */
1362 switch (hw->mac.type) {
1363 case e1000_82574:
1364 case e1000_82583:
1365 reg = E1000_READ_REG(hw, E1000_GCR);
1366 reg |= (1 << 22);
1367 E1000_WRITE_REG(hw, E1000_GCR, reg);
1368
1369 /* Workaround for hardware errata.
1370 * apply workaround for hardware errata documented in errata
1371 * docs Fixes issue where some error prone or unreliable PCIe
1372 * completions are occurring, particularly with ASPM enabled.
1373 * Without fix, issue can cause Tx timeouts.
1374 */
1375 reg = E1000_READ_REG(hw, E1000_GCR2);
1376 reg |= 1;
1377 E1000_WRITE_REG(hw, E1000_GCR2, reg);
1378 break;
1379 default:
1380 break;
1381 }
1382
1383 return;
1384 }
1385
1386 /**
1387 * e1000_clear_vfta_82571 - Clear VLAN filter table
1388 * @hw: pointer to the HW structure
1389 *
1390 * Clears the register array which contains the VLAN filter table by
1391 * setting all the values to 0.
1392 **/
1393 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1394 {
1395 u32 offset;
1396 u32 vfta_value = 0;
1397 u32 vfta_offset = 0;
1398 u32 vfta_bit_in_reg = 0;
1399
1400 DEBUGFUNC("e1000_clear_vfta_82571");
1401
1402 switch (hw->mac.type) {
1403 case e1000_82573:
1404 case e1000_82574:
1405 case e1000_82583:
1406 if (hw->mng_cookie.vlan_id != 0) {
1407 /* The VFTA is a 4096b bit-field, each identifying
1408 * a single VLAN ID. The following operations
1409 * determine which 32b entry (i.e. offset) into the
1410 * array we want to set the VLAN ID (i.e. bit) of
1411 * the manageability unit.
1412 */
1413 vfta_offset = (hw->mng_cookie.vlan_id >>
1414 E1000_VFTA_ENTRY_SHIFT) &
1415 E1000_VFTA_ENTRY_MASK;
1416 vfta_bit_in_reg =
1417 1 << (hw->mng_cookie.vlan_id &
1418 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1419 }
1420 break;
1421 default:
1422 break;
1423 }
1424 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1425 /* If the offset we want to clear is the same offset of the
1426 * manageability VLAN ID, then clear all bits except that of
1427 * the manageability unit.
1428 */
1429 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1430 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1431 E1000_WRITE_FLUSH(hw);
1432 }
1433 }
1434
1435 /**
1436 * e1000_check_mng_mode_82574 - Check manageability is enabled
1437 * @hw: pointer to the HW structure
1438 *
1439 * Reads the NVM Initialization Control Word 2 and returns TRUE
1440 * (>0) if any manageability is enabled, else FALSE (0).
1441 **/
1442 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1443 {
1444 u16 data;
1445
1446 DEBUGFUNC("e1000_check_mng_mode_82574");
1447
1448 hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1449 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1450 }
1451
1452 /**
1453 * e1000_led_on_82574 - Turn LED on
1454 * @hw: pointer to the HW structure
1455 *
1456 * Turn LED on.
1457 **/
1458 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1459 {
1460 u32 ctrl;
1461 u32 i;
1462
1463 DEBUGFUNC("e1000_led_on_82574");
1464
1465 ctrl = hw->mac.ledctl_mode2;
1466 if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1467 /* If no link, then turn LED on by setting the invert bit
1468 * for each LED that's "on" (0x0E) in ledctl_mode2.
1469 */
1470 for (i = 0; i < 4; i++)
1471 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1472 E1000_LEDCTL_MODE_LED_ON)
1473 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1474 }
1475 E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1476
1477 return E1000_SUCCESS;
1478 }
1479
1480 /**
1481 * e1000_check_phy_82574 - check 82574 phy hung state
1482 * @hw: pointer to the HW structure
1483 *
1484 * Returns whether phy is hung or not
1485 **/
1486 bool e1000_check_phy_82574(struct e1000_hw *hw)
1487 {
1488 u16 status_1kbt = 0;
1489 u16 receive_errors = 0;
1490 s32 ret_val;
1491
1492 DEBUGFUNC("e1000_check_phy_82574");
1493
1494 /* Read PHY Receive Error counter first, if its is max - all F's then
1495 * read the Base1000T status register If both are max then PHY is hung.
1496 */
1497 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1498 &receive_errors);
1499 if (ret_val)
1500 return FALSE;
1501 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1502 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1503 &status_1kbt);
1504 if (ret_val)
1505 return FALSE;
1506 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1507 E1000_IDLE_ERROR_COUNT_MASK)
1508 return TRUE;
1509 }
1510
1511 return FALSE;
1512 }
1513
1514
1515 /**
1516 * e1000_setup_link_82571 - Setup flow control and link settings
1517 * @hw: pointer to the HW structure
1518 *
1519 * Determines which flow control settings to use, then configures flow
1520 * control. Calls the appropriate media-specific link configuration
1521 * function. Assuming the adapter has a valid link partner, a valid link
1522 * should be established. Assumes the hardware has previously been reset
1523 * and the transmitter and receiver are not enabled.
1524 **/
1525 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1526 {
1527 DEBUGFUNC("e1000_setup_link_82571");
1528
1529 /* 82573 does not have a word in the NVM to determine
1530 * the default flow control setting, so we explicitly
1531 * set it to full.
1532 */
1533 switch (hw->mac.type) {
1534 case e1000_82573:
1535 case e1000_82574:
1536 case e1000_82583:
1537 if (hw->fc.requested_mode == e1000_fc_default)
1538 hw->fc.requested_mode = e1000_fc_full;
1539 break;
1540 default:
1541 break;
1542 }
1543
1544 return e1000_setup_link_generic(hw);
1545 }
1546
1547 /**
1548 * e1000_setup_copper_link_82571 - Configure copper link settings
1549 * @hw: pointer to the HW structure
1550 *
1551 * Configures the link for auto-neg or forced speed and duplex. Then we check
1552 * for link, once link is established calls to configure collision distance
1553 * and flow control are called.
1554 **/
1555 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1556 {
1557 u32 ctrl;
1558 s32 ret_val;
1559
1560 DEBUGFUNC("e1000_setup_copper_link_82571");
1561
1562 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1563 ctrl |= E1000_CTRL_SLU;
1564 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1565 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1566
1567 switch (hw->phy.type) {
1568 case e1000_phy_m88:
1569 case e1000_phy_bm:
1570 ret_val = e1000_copper_link_setup_m88(hw);
1571 break;
1572 case e1000_phy_igp_2:
1573 ret_val = e1000_copper_link_setup_igp(hw);
1574 break;
1575 default:
1576 return -E1000_ERR_PHY;
1577 break;
1578 }
1579
1580 if (ret_val)
1581 return ret_val;
1582
1583 return e1000_setup_copper_link_generic(hw);
1584 }
1585
1586 /**
1587 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1588 * @hw: pointer to the HW structure
1589 *
1590 * Configures collision distance and flow control for fiber and serdes links.
1591 * Upon successful setup, poll for link.
1592 **/
1593 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1594 {
1595 DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1596
1597 switch (hw->mac.type) {
1598 case e1000_82571:
1599 case e1000_82572:
1600 /* If SerDes loopback mode is entered, there is no form
1601 * of reset to take the adapter out of that mode. So we
1602 * have to explicitly take the adapter out of loopback
1603 * mode. This prevents drivers from twiddling their thumbs
1604 * if another tool failed to take it out of loopback mode.
1605 */
1606 E1000_WRITE_REG(hw, E1000_SCTL,
1607 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1608 break;
1609 default:
1610 break;
1611 }
1612
1613 return e1000_setup_fiber_serdes_link_generic(hw);
1614 }
1615
1616 /**
1617 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1618 * @hw: pointer to the HW structure
1619 *
1620 * Reports the link state as up or down.
1621 *
1622 * If autonegotiation is supported by the link partner, the link state is
1623 * determined by the result of autonegotiation. This is the most likely case.
1624 * If autonegotiation is not supported by the link partner, and the link
1625 * has a valid signal, force the link up.
1626 *
1627 * The link state is represented internally here by 4 states:
1628 *
1629 * 1) down
1630 * 2) autoneg_progress
1631 * 3) autoneg_complete (the link successfully autonegotiated)
1632 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1633 *
1634 **/
1635 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1636 {
1637 struct e1000_mac_info *mac = &hw->mac;
1638 u32 rxcw;
1639 u32 ctrl;
1640 u32 status;
1641 u32 txcw;
1642 u32 i;
1643 s32 ret_val = E1000_SUCCESS;
1644
1645 DEBUGFUNC("e1000_check_for_serdes_link_82571");
1646
1647 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1648 status = E1000_READ_REG(hw, E1000_STATUS);
1649 E1000_READ_REG(hw, E1000_RXCW);
1650 /* SYNCH bit and IV bit are sticky */
1651 usec_delay(10);
1652 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1653
1654 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1655 /* Receiver is synchronized with no invalid bits. */
1656 switch (mac->serdes_link_state) {
1657 case e1000_serdes_link_autoneg_complete:
1658 if (!(status & E1000_STATUS_LU)) {
1659 /* We have lost link, retry autoneg before
1660 * reporting link failure
1661 */
1662 mac->serdes_link_state =
1663 e1000_serdes_link_autoneg_progress;
1664 mac->serdes_has_link = FALSE;
1665 DEBUGOUT("AN_UP -> AN_PROG\n");
1666 } else {
1667 mac->serdes_has_link = TRUE;
1668 }
1669 break;
1670
1671 case e1000_serdes_link_forced_up:
1672 /* If we are receiving /C/ ordered sets, re-enable
1673 * auto-negotiation in the TXCW register and disable
1674 * forced link in the Device Control register in an
1675 * attempt to auto-negotiate with our link partner.
1676 */
1677 if (rxcw & E1000_RXCW_C) {
1678 /* Enable autoneg, and unforce link up */
1679 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1680 E1000_WRITE_REG(hw, E1000_CTRL,
1681 (ctrl & ~E1000_CTRL_SLU));
1682 mac->serdes_link_state =
1683 e1000_serdes_link_autoneg_progress;
1684 mac->serdes_has_link = FALSE;
1685 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1686 } else {
1687 mac->serdes_has_link = TRUE;
1688 }
1689 break;
1690
1691 case e1000_serdes_link_autoneg_progress:
1692 if (rxcw & E1000_RXCW_C) {
1693 /* We received /C/ ordered sets, meaning the
1694 * link partner has autonegotiated, and we can
1695 * trust the Link Up (LU) status bit.
1696 */
1697 if (status & E1000_STATUS_LU) {
1698 mac->serdes_link_state =
1699 e1000_serdes_link_autoneg_complete;
1700 DEBUGOUT("AN_PROG -> AN_UP\n");
1701 mac->serdes_has_link = TRUE;
1702 } else {
1703 /* Autoneg completed, but failed. */
1704 mac->serdes_link_state =
1705 e1000_serdes_link_down;
1706 DEBUGOUT("AN_PROG -> DOWN\n");
1707 }
1708 } else {
1709 /* The link partner did not autoneg.
1710 * Force link up and full duplex, and change
1711 * state to forced.
1712 */
1713 E1000_WRITE_REG(hw, E1000_TXCW,
1714 (mac->txcw & ~E1000_TXCW_ANE));
1715 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1716 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1717
1718 /* Configure Flow Control after link up. */
1719 ret_val =
1720 e1000_config_fc_after_link_up_generic(hw);
1721 if (ret_val) {
1722 DEBUGOUT("Error config flow control\n");
1723 break;
1724 }
1725 mac->serdes_link_state =
1726 e1000_serdes_link_forced_up;
1727 mac->serdes_has_link = TRUE;
1728 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1729 }
1730 break;
1731
1732 case e1000_serdes_link_down:
1733 default:
1734 /* The link was down but the receiver has now gained
1735 * valid sync, so lets see if we can bring the link
1736 * up.
1737 */
1738 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1739 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1740 ~E1000_CTRL_SLU));
1741 mac->serdes_link_state =
1742 e1000_serdes_link_autoneg_progress;
1743 mac->serdes_has_link = FALSE;
1744 DEBUGOUT("DOWN -> AN_PROG\n");
1745 break;
1746 }
1747 } else {
1748 if (!(rxcw & E1000_RXCW_SYNCH)) {
1749 mac->serdes_has_link = FALSE;
1750 mac->serdes_link_state = e1000_serdes_link_down;
1751 DEBUGOUT("ANYSTATE -> DOWN\n");
1752 } else {
1753 /* Check several times, if SYNCH bit and CONFIG
1754 * bit both are consistently 1 then simply ignore
1755 * the IV bit and restart Autoneg
1756 */
1757 for (i = 0; i < AN_RETRY_COUNT; i++) {
1758 usec_delay(10);
1759 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1760 if ((rxcw & E1000_RXCW_SYNCH) &&
1761 (rxcw & E1000_RXCW_C))
1762 continue;
1763
1764 if (rxcw & E1000_RXCW_IV) {
1765 mac->serdes_has_link = FALSE;
1766 mac->serdes_link_state =
1767 e1000_serdes_link_down;
1768 DEBUGOUT("ANYSTATE -> DOWN\n");
1769 break;
1770 }
1771 }
1772
1773 if (i == AN_RETRY_COUNT) {
1774 txcw = E1000_READ_REG(hw, E1000_TXCW);
1775 txcw |= E1000_TXCW_ANE;
1776 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1777 mac->serdes_link_state =
1778 e1000_serdes_link_autoneg_progress;
1779 mac->serdes_has_link = FALSE;
1780 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1781 }
1782 }
1783 }
1784
1785 return ret_val;
1786 }
1787
1788 /**
1789 * e1000_valid_led_default_82571 - Verify a valid default LED config
1790 * @hw: pointer to the HW structure
1791 * @data: pointer to the NVM (EEPROM)
1792 *
1793 * Read the EEPROM for the current default LED configuration. If the
1794 * LED configuration is not valid, set to a valid LED configuration.
1795 **/
1796 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1797 {
1798 s32 ret_val;
1799
1800 DEBUGFUNC("e1000_valid_led_default_82571");
1801
1802 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1803 if (ret_val) {
1804 DEBUGOUT("NVM Read Error\n");
1805 return ret_val;
1806 }
1807
1808 switch (hw->mac.type) {
1809 case e1000_82573:
1810 case e1000_82574:
1811 case e1000_82583:
1812 if (*data == ID_LED_RESERVED_F746)
1813 *data = ID_LED_DEFAULT_82573;
1814 break;
1815 default:
1816 if (*data == ID_LED_RESERVED_0000 ||
1817 *data == ID_LED_RESERVED_FFFF)
1818 *data = ID_LED_DEFAULT;
1819 break;
1820 }
1821
1822 return E1000_SUCCESS;
1823 }
1824
1825 /**
1826 * e1000_get_laa_state_82571 - Get locally administered address state
1827 * @hw: pointer to the HW structure
1828 *
1829 * Retrieve and return the current locally administered address state.
1830 **/
1831 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1832 {
1833 DEBUGFUNC("e1000_get_laa_state_82571");
1834
1835 if (hw->mac.type != e1000_82571)
1836 return FALSE;
1837
1838 return hw->dev_spec._82571.laa_is_present;
1839 }
1840
1841 /**
1842 * e1000_set_laa_state_82571 - Set locally administered address state
1843 * @hw: pointer to the HW structure
1844 * @state: enable/disable locally administered address
1845 *
1846 * Enable/Disable the current locally administered address state.
1847 **/
1848 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1849 {
1850 DEBUGFUNC("e1000_set_laa_state_82571");
1851
1852 if (hw->mac.type != e1000_82571)
1853 return;
1854
1855 hw->dev_spec._82571.laa_is_present = state;
1856
1857 /* If workaround is activated... */
1858 if (state)
1859 /* Hold a copy of the LAA in RAR[14] This is done so that
1860 * between the time RAR[0] gets clobbered and the time it
1861 * gets fixed, the actual LAA is in one of the RARs and no
1862 * incoming packets directed to this port are dropped.
1863 * Eventually the LAA will be in RAR[0] and RAR[14].
1864 */
1865 hw->mac.ops.rar_set(hw, hw->mac.addr,
1866 hw->mac.rar_entry_count - 1);
1867 return;
1868 }
1869
1870 /**
1871 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1872 * @hw: pointer to the HW structure
1873 *
1874 * Verifies that the EEPROM has completed the update. After updating the
1875 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1876 * the checksum fix is not implemented, we need to set the bit and update
1877 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1878 * we need to return bad checksum.
1879 **/
1880 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1881 {
1882 struct e1000_nvm_info *nvm = &hw->nvm;
1883 s32 ret_val;
1884 u16 data;
1885
1886 DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1887
1888 if (nvm->type != e1000_nvm_flash_hw)
1889 return E1000_SUCCESS;
1890
1891 /* Check bit 4 of word 10h. If it is 0, firmware is done updating
1892 * 10h-12h. Checksum may need to be fixed.
1893 */
1894 ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1895 if (ret_val)
1896 return ret_val;
1897
1898 if (!(data & 0x10)) {
1899 /* Read 0x23 and check bit 15. This bit is a 1
1900 * when the checksum has already been fixed. If
1901 * the checksum is still wrong and this bit is a
1902 * 1, we need to return bad checksum. Otherwise,
1903 * we need to set this bit to a 1 and update the
1904 * checksum.
1905 */
1906 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1907 if (ret_val)
1908 return ret_val;
1909
1910 if (!(data & 0x8000)) {
1911 data |= 0x8000;
1912 ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1913 if (ret_val)
1914 return ret_val;
1915 ret_val = nvm->ops.update(hw);
1916 if (ret_val)
1917 return ret_val;
1918 }
1919 }
1920
1921 return E1000_SUCCESS;
1922 }
1923
1924
1925 /**
1926 * e1000_read_mac_addr_82571 - Read device MAC address
1927 * @hw: pointer to the HW structure
1928 **/
1929 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1930 {
1931 DEBUGFUNC("e1000_read_mac_addr_82571");
1932
1933 if (hw->mac.type == e1000_82571) {
1934 s32 ret_val;
1935
1936 /* If there's an alternate MAC address place it in RAR0
1937 * so that it will override the Si installed default perm
1938 * address.
1939 */
1940 ret_val = e1000_check_alt_mac_addr_generic(hw);
1941 if (ret_val)
1942 return ret_val;
1943 }
1944
1945 return e1000_read_mac_addr_generic(hw);
1946 }
1947
1948 /**
1949 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1950 * @hw: pointer to the HW structure
1951 *
1952 * In the case of a PHY power down to save power, or to turn off link during a
1953 * driver unload, or wake on lan is not enabled, remove the link.
1954 **/
1955 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1956 {
1957 struct e1000_phy_info *phy = &hw->phy;
1958 struct e1000_mac_info *mac = &hw->mac;
1959
1960 if (!phy->ops.check_reset_block)
1961 return;
1962
1963 /* If the management interface is not enabled, then power down */
1964 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1965 e1000_power_down_phy_copper(hw);
1966
1967 return;
1968 }
1969
1970 /**
1971 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1972 * @hw: pointer to the HW structure
1973 *
1974 * Clears the hardware counters by reading the counter registers.
1975 **/
1976 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1977 {
1978 DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1979
1980 e1000_clear_hw_cntrs_base_generic(hw);
1981
1982 E1000_READ_REG(hw, E1000_PRC64);
1983 E1000_READ_REG(hw, E1000_PRC127);
1984 E1000_READ_REG(hw, E1000_PRC255);
1985 E1000_READ_REG(hw, E1000_PRC511);
1986 E1000_READ_REG(hw, E1000_PRC1023);
1987 E1000_READ_REG(hw, E1000_PRC1522);
1988 E1000_READ_REG(hw, E1000_PTC64);
1989 E1000_READ_REG(hw, E1000_PTC127);
1990 E1000_READ_REG(hw, E1000_PTC255);
1991 E1000_READ_REG(hw, E1000_PTC511);
1992 E1000_READ_REG(hw, E1000_PTC1023);
1993 E1000_READ_REG(hw, E1000_PTC1522);
1994
1995 E1000_READ_REG(hw, E1000_ALGNERRC);
1996 E1000_READ_REG(hw, E1000_RXERRC);
1997 E1000_READ_REG(hw, E1000_TNCRS);
1998 E1000_READ_REG(hw, E1000_CEXTERR);
1999 E1000_READ_REG(hw, E1000_TSCTC);
2000 E1000_READ_REG(hw, E1000_TSCTFC);
2001
2002 E1000_READ_REG(hw, E1000_MGTPRC);
2003 E1000_READ_REG(hw, E1000_MGTPDC);
2004 E1000_READ_REG(hw, E1000_MGTPTC);
2005
2006 E1000_READ_REG(hw, E1000_IAC);
2007 E1000_READ_REG(hw, E1000_ICRXOC);
2008
2009 E1000_READ_REG(hw, E1000_ICRXPTC);
2010 E1000_READ_REG(hw, E1000_ICRXATC);
2011 E1000_READ_REG(hw, E1000_ICTXPTC);
2012 E1000_READ_REG(hw, E1000_ICTXATC);
2013 E1000_READ_REG(hw, E1000_ICTXQEC);
2014 E1000_READ_REG(hw, E1000_ICTXQMTC);
2015 E1000_READ_REG(hw, E1000_ICRXDMTC);
2016 }
Cache object: 6d18578145ee8fe039a1ff7f2eeba85c
|