1 /******************************************************************************
2
3 Copyright (c) 2001-2008, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ******************************************************************************/
33
34 #ifndef _DRAGONFLY_OS_H_
35 #define _DRAGONFLY_OS_H_
36
37 #include <sys/param.h>
38 #include <sys/bus.h>
39 #include <sys/kernel.h>
40 #include <sys/systm.h>
41
42 #include <bus/pci/pcivar.h>
43 #include <bus/pci/pcireg.h>
44
45 #define usec_delay(x) DELAY(x)
46 #define msec_delay(x) DELAY(1000*(x))
47 /* TODO: Should we be paranoid about delaying in interrupt context? */
48 #define msec_delay_irq(x) DELAY(1000*(x))
49
50 #define DEBUGFUNC(F) DEBUGOUT(F)
51 #define DEBUGOUT(S)
52 #define DEBUGOUT1(S,A)
53 #define DEBUGOUT2(S,A,B)
54 #define DEBUGOUT3(S,A,B,C)
55 #define DEBUGOUT7(S,A,B,C,D,E,F,G)
56
57 #define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
58 #define PCI_COMMAND_REGISTER PCIR_COMMAND
59
60 /*
61 * These typedefs are necessary due to the new
62 * shared code, they are native to Linux.
63 */
64 typedef uint64_t u64;
65 typedef uint32_t u32;
66 typedef uint16_t u16;
67 typedef uint8_t u8;
68 typedef int64_t s64;
69 typedef int32_t s32;
70 typedef int16_t s16;
71 typedef int8_t s8;
72 typedef boolean_t bool;
73
74 #define __le16 u16
75 #define __le32 u32
76 #define __le64 u64
77
78 struct e1000_osdep {
79 bus_space_tag_t mem_bus_space_tag;
80 bus_space_handle_t mem_bus_space_handle;
81 bus_space_tag_t io_bus_space_tag;
82 bus_space_handle_t io_bus_space_handle;
83 bus_space_tag_t flash_bus_space_tag;
84 bus_space_handle_t flash_bus_space_handle;
85 device_t dev;
86 };
87
88 #define E1000_REGISTER(hw, reg) (((hw)->mac.type >= e1000_82543) \
89 ? reg : e1000_translate_register_82542(reg))
90
91 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
92
93 /* Read from an absolute offset in the adapter's memory space */
94 #define E1000_READ_OFFSET(hw, offset) \
95 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
96 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset)
97
98 /* Write to an absolute offset in the adapter's memory space */
99 #define E1000_WRITE_OFFSET(hw, offset, value) \
100 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
101 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, offset, value)
102
103 /* Register READ/WRITE macros */
104
105 #define E1000_READ_REG(hw, reg) \
106 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
107 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
108 E1000_REGISTER(hw, reg))
109
110 #define E1000_WRITE_REG(hw, reg, value) \
111 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
112 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
113 E1000_REGISTER(hw, reg), value)
114
115 #define E1000_READ_REG_ARRAY(hw, reg, index) \
116 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
117 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
118 E1000_REGISTER(hw, reg) + ((index)<< 2))
119
120 #define E1000_WRITE_REG_ARRAY(hw, reg, index, value) \
121 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
122 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
123 E1000_REGISTER(hw, reg) + ((index)<< 2), value)
124
125 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
126 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
127
128 #define E1000_READ_REG_ARRAY_BYTE(hw, reg, index) \
129 bus_space_read_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
130 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
131 E1000_REGISTER(hw, reg) + index)
132
133 #define E1000_WRITE_REG_ARRAY_BYTE(hw, reg, index, value) \
134 bus_space_write_1(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
135 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
136 E1000_REGISTER(hw, reg) + index, value)
137
138 #define E1000_WRITE_REG_ARRAY_WORD(hw, reg, index, value) \
139 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->mem_bus_space_tag, \
140 ((struct e1000_osdep *)(hw)->back)->mem_bus_space_handle, \
141 E1000_REGISTER(hw, reg) + (index << 1), value)
142
143 #define E1000_WRITE_REG_IO(hw, reg, value) do {\
144 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \
145 ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \
146 (hw)->io_base, reg); \
147 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->io_bus_space_tag, \
148 ((struct e1000_osdep *)(hw)->back)->io_bus_space_handle, \
149 (hw)->io_base + 4, value); } while (0)
150
151 #define E1000_READ_FLASH_REG(hw, reg) \
152 bus_space_read_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
153 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)
154
155 #define E1000_READ_FLASH_REG16(hw, reg) \
156 bus_space_read_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
157 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg)
158
159 #define E1000_WRITE_FLASH_REG(hw, reg, value) \
160 bus_space_write_4(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
161 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)
162
163 #define E1000_WRITE_FLASH_REG16(hw, reg, value) \
164 bus_space_write_2(((struct e1000_osdep *)(hw)->back)->flash_bus_space_tag, \
165 ((struct e1000_osdep *)(hw)->back)->flash_bus_space_handle, reg, value)
166
167 #endif /* _DRAGONFLY_OS_H_ */
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